Micro-LED ISO vertical angle etching method

Abstract

The invention relates to the technical field of Micro-LED display, and discloses a Micro-LED ISO vertical angle etching method, which comprises the following steps: S1, epitaxial layer growth control: providing a sapphire substrate as a substrate, growing an epitaxial layer structure on the substrate, and growing silicon oxide with a certain thickness on the substrate through PECV equipment to serve as a protective layer, S2, photoetching patterning: selecting positive photoresist, and performing photoetching patterning on the positive photoresist to form an epitaxial layer; the method comprises the following steps: S1, coating the surface of a protective layer with a spin coater, and then carrying out photoetching and developing to manufacture a pattern, needing to be etched, of the ISO side wall, S3, carrying out metal coating and patterning, S4, carrying out dry etching epitaxy, and S5, removing the protective layer. The ISO side wall epitaxy with the angle approaching to be vertical is obtained by removing the epitaxial protection layer through wet etching or dry etching, the light-emitting area loss of the Micro-LED is reduced, the light emitting efficiency is improved, conditions are provided for Pitch reduction of a chip, meanwhile, chip breakage caused in the subsequent laser stripping process is reduced, and the yield and stability of chip manufacturing are improved.

Description

Technical Field

[0001] The present invention relates to the field of Micro-LED display technology, and in particular to a Micro-LED ISO vertical angle etching method. Background Art

[0002] In the rapid evolution of display technology, Micro-LED has attracted much attention due to its many advantages such as high brightness, high contrast, low power consumption and long life. In the manufacturing process chain of Micro-LED, the ISO sidewall etching process is an extremely critical link, which plays a decisive role in fully tapping the excellent performance of Micro-LED. It is directly related to the efficient extraction and precise control of light, the stability and optimization of electrical performance, the improvement of chip integration, and the miniaturization and high performance of the overall device.

[0003] However, in current technology, traditional etching processes mostly use resist as a barrier layer when processing epitaxial protective layers. After a fixed etching time, the ISO sidewall angle cannot reach near verticality, resulting in a reduction in the light-emitting area, limited chip integration, and problems with chip yield. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention provides a Micro-LED ISO vertical angle etching method to solve the problem that the ISO side wall angle is difficult to reach a near-vertical state when using a resist as a barrier layer.

[0005] To achieve the above objectives, the present invention is implemented by the following technical solutions: A Micro-LED ISO vertical angle etching method, comprising the following steps:

[0006] S1. Epitaxial layer growth control: Provide a sapphire substrate as a substrate, grow an epitaxial layer structure on the substrate, and simultaneously grow a certain thickness of silicon oxide as a protective layer on the substrate through a PECV device;

[0007] S2, photolithography patterning: Select positive photoresist and coat it on the surface of the protective layer through a coating machine, and then perform photolithography and development to produce the pattern that needs to be etched on the ISO sidewall;

[0008] S3, metal coating and patterning: Cr metal coating is performed through a metal evaporation table, the Cr metal is patterned through a gold peeling and debonding process, and then the protective layer is patterned by wet etching;

[0009] S4, dry etching epitaxy: using inductively coupled plasma etching equipment to dry etch the epitaxial part;

[0010] S5. Removing the protective layer: removing the protective layer on the epitaxial surface by wet etching or dry etching to obtain ISO sidewall epitaxy with an angle close to vertical.

[0011] Preferably, the epitaxial layer structure in S1 is gallium nitride, gallium phosphide or gallium indium arsenic phosphide, and a certain thickness of silicon oxide is grown on the substrate by PECV equipment as a protective layer with a thickness of 2000A for stripping the metal barrier layer.

[0012] Preferably, the pattern to be etched on the ISO sidewall in S2 is a Lift Off layer, and the thickness of the ISO sidewall etching is 4-4.3 microns.

[0013] Preferably, the Cr metal coating in S3 is a barrier layer, the selectivity of the metal Cr to etch gallium nitride is 1:17.1, and the thickness of the Cr metal coating is 2400-2500A.

[0014] Preferably, in the dry etching in S4, chlorine and argon are used as etching gases, the chlorine flow rate is set at 30-40 sccm, and the argon flow rate is set at 12-15 sccm.

[0015] Preferably, the wet etching in S5 uses a 6:1 BOE solution, and the etching time is 100 to 130 seconds.

[0016] The present invention provides a Micro-LED ISO vertical angle etching method. It has the following beneficial effects:

[0017] 1. The present invention removes the epitaxial protective layer by wet etching or dry etching to obtain ISO sidewall epitaxy with an angle close to vertical, thereby reducing the light emitting area loss of Micro-LED, improving the light emission efficiency, and providing conditions for reducing the Pitch of the chip. At the same time, it reduces chip breakage caused by the subsequent laser stripping process, and improves the yield and stability of chip manufacturing.

[0018] 2. The present invention precisely controls the selectivity of Cr metal, and the thickness of the metal barrier layer of the epitaxial height barrier layer of the same thickness is relatively low. When the barrier layer is reduced, the graphic bevel angle will increase, resulting in the side bevel of the ISO after etching close to 90°, thereby improving the process accuracy and ensuring the consistency of the quality of Micro-LED products. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the process of a Micro-LED ISO vertical angle etching method of the present invention;

[0020] Figure 2 A schematic diagram of epitaxial layer growth control steps of a Micro-LED ISO vertical angle etching method of the present invention;

[0021] Figure 3 A schematic diagram of photolithography patterning of a Micro-LED ISO vertical angle etching method of the present invention;

[0022] Figure 4 A schematic diagram of the metal coating and patterning steps of a Micro-LED ISO vertical angle etching method of the present invention;

[0023] Figure 5 A schematic diagram of the dry etching epitaxy step of a Micro-LED ISO vertical angle etching method of the present invention;

[0024] Figure 6 Schematic diagram of the protective layer removal step of a Micro-LED ISO vertical angle etching method of the present invention.

[0025] Among them, 1. Lift Off layer; 2. Protective layer; 3. Sapphire substrate; 4. Barrier layer. DETAILED DESCRIPTION

[0026] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] Please refer to the attached Figure 1 - Attachment Figure 6 , an embodiment of the present invention provides a Micro-LED ISO vertical angle etching method, comprising the following steps:

[0028] S1. Epitaxial layer growth control: providing a sapphire substrate 3 as a substrate, growing an epitaxial layer structure on the substrate, and at the same time growing a certain thickness of silicon oxide as a protective layer 2 on the substrate through a PECV device;

[0029] S2, photolithography patterning: select positive photoresist, apply it on the surface of protective layer 2 through a coating machine, and then perform photolithography and development to produce the pattern that needs to be etched on the ISO sidewall;

[0030] S3, metal coating and patterning: Cr metal coating is performed by a metal evaporation table, the Cr metal is patterned by a gold peeling and debonding process, and then the protective layer 2 is patterned by a wet etching method;

[0031] S4, dry etching epitaxy: using inductively coupled plasma etching equipment to dry etch the epitaxial part;

[0032] S5, removing the protective layer 2: removing the protective layer 2 on the epitaxial surface by wet etching or dry etching to obtain an ISO sidewall epitaxy with an angle close to vertical.

[0033] Specifically, the sapphire in S1 has high hardness and mechanical stability, and can provide a solid and flat support surface for the growth of the epitaxial layer, ensuring that the epitaxial layer will not produce defects due to deformation or unevenness of the substrate during the growth process. At the same time, the protective layer 2 provides effective protection for the epitaxial layer, and in subsequent processes, it can avoid damage caused by chemical erosion and physical etching, thereby accurately controlling the etching process and limiting the transition effect of the etchant on the epitaxial layer, which not only greatly improves the yield of the device and reduces the device failure caused by damage to the epitaxial layer, but also enhances the accuracy of etching, achieves more precise and accurate graphics and structures, and ensures the consistency and stability of device performance;

[0034] In S2, a positive photoresist is selected and coated on the surface of the protective layer 2 by a coating machine, and then photolithography and development are performed to produce the pattern to be etched on the ISO sidewall, so as to accurately define the etching area for the subsequent etching process, and then the required etching pattern can be accurately planned, thereby improving the accuracy and consistency of etching, helping to manufacture fine structures that meet the design requirements and improving the performance and quality of the device;

[0035] In S3, Cr metal is plated on a metal evaporation table, and the Cr metal is patterned using a gold peeling and debonding process, and then the protective layer 2 is patterned by wet etching, so that a specific metal and protective layer 2 pattern can be formed, which provides a template and protection for the subsequent precise etching of the epitaxial layer, accurately controls the boundary of the etching area, reduces the etching error, and ensures the accuracy and consistency of the etching. At the same time, the Cr metal film can block the erosion of the epitaxial layer or other key structures by certain chemicals or etchants, plays a protective role, and helps to manufacture high-quality, high-precision device structures that meet design requirements, and improve the performance and reliability of the device;

[0036] The precise ISO sidewall angle formed by dry etching in S4, and the use of inductively coupled plasma etching equipment to dry-etch the epitaxial part, can accurately remove specific areas of the epitaxial layer to shape the structure and shape that meet the design requirements. The effects achieved include high-precision, anisotropic etching, precise control of etching depth and profile, and obtaining steep and clear sidewall boundaries. At the same time, the damage to the surrounding materials is small, and the quality and performance of the epitaxial layer can be better maintained. The etching process is highly controllable, and the etching rate and effect can be accurately controlled by adjusting the parameters, and the repeatability is high, which is conducive to large-scale stable production;

[0037] In S5, the protective layer 2 on the epitaxial surface is removed by wet etching or dry etching to obtain an ISO sidewall epitaxial with an angle close to vertical, which can eliminate the potential impact of the protective layer 2 on the device performance, help improve the light extraction efficiency and electrical performance of the device, and can accurately control the degree of removal of the protective layer 2 to avoid unnecessary damage to the epitaxial structure. At the same time, the vertical ISO sidewall helps to achieve tighter device integration and provide conditions for chip pitch reduction, thereby improving the overall performance and reliability of the device, providing a good foundation for subsequent process steps and device applications, and reducing the area of ​​thin epitaxy at the bottom of the chip to reduce the effect of chip cracking caused by the laser stripping process.

[0038] The epitaxial layer structure in S1 is gallium nitride, gallium phosphide or gallium indium arsenic phosphide. A certain thickness of silicon oxide is grown on the substrate through PECV equipment as a protective layer 2 with a thickness of 2000A, which is used to strip off the metal barrier layer 4.

[0039] Specifically, gallium nitride is a wide-bandgap semiconductor material. In LED and Micro-LED manufacturing, gallium nitride, as an epitaxial layer, can effectively convert electrical energy into light energy. At the same time, gallium nitride-based LEDs have higher luminous efficiency, longer service life and better stability;

[0040] Gallium phosphide can emit red and green light, and its specific adjustability makes it widely used in fields such as color display screens;

[0041] The band gap of the GaInAsP epitaxial layer is adjustable, and it can emit light from the infrared to the red light band. In the field of optical communications, the infrared light it emits can well match the low-loss window of the optical fiber, achieving long-distance, high-speed optical signal transmission and providing stable light emission function for optical fiber communications;

[0042] The silicon oxide layer as a protective layer 2 can ensure sufficient strength to withstand the operations of subsequent processes, and can effectively separate the metal barrier layer 4 from the substrate and the epitaxial layer through a suitable stripping method when necessary, while preventing the etchant from further corroding the epitaxial layer and the substrate to a certain extent, thereby achieving clean stripping of the metal barrier layer 4.

[0043] The pattern that needs to be etched on the ISO sidewall in S2 is the Lift Off layer 1, and the thickness of the ISO sidewall etching is 4-4.3 microns.

[0044] Specifically, by etching the Lift-Off layer on the ISO sidewall, the pre-designed pattern can be accurately transferred to the ISO sidewall, thereby determining the boundary of the light-emitting area in the Micro-LED chip.

[0045] In S3, the Cr metal coating is the barrier layer 4, the selectivity ratio of metal Cr to gallium nitride etching is 1:17.1, and the coating thickness of the Cr metal is 2400-2500A.

[0046] Specifically, the Cr metal coating is used as a barrier layer 4 to prevent the damage to important epitaxial layers such as gallium nitride caused by impurity diffusion or chemical reactions that may occur in subsequent processes. In the subsequent etching process, the barrier layer 4 can prevent the entry of foreign substances, isolate and protect the gallium nitride epitaxial layer, and maintain the stability of its electrical and optical properties. In addition, by utilizing the etching selectivity ratio of Cr metal to gallium nitride, the thickness of the metal barrier layer 4 is relatively low when etching an epitaxial layer of the same thickness. When the barrier layer 4 is reduced, the angle of the patterned bevel will increase, resulting in the side bevel of the ISO after etching being close to 90°. The etching shape and depth of gallium nitride can be accurately controlled, thereby improving the functional integration and performance of the device.

[0047] In S4, chlorine and argon are used as etching gases for dry etching, the chlorine flow rate is set at 30-40 sccm, and the argon flow rate is set at 12-15 sccm.

[0048] Specifically, chlorine and argon are used as dry etching gases. Chlorine is used as the main etchant to chemically react with the material to be etched to remove the material. Argon assists through physical bombardment to remove the reaction products and enhance the etching anisotropy. The synergistic effect of the two can achieve precise etching of the target material, ensure good etching directionality, obtain vertical side walls and a flat surface, stabilize the etching process, improve process repeatability and product consistency, optimize the quality of the etched surface, reduce roughness, and provide a good foundation for subsequent processes such as material deposition, which will strongly promote the manufacture of high-quality and high-performance semiconductor devices.

[0049] In S5, the wet etching uses a 6:1 BOE solution, and the etching time is 100 to 130 seconds.

[0050] Specifically, the use of a 6:1 BOE solution for wet etching can accurately remove silicon oxide while causing minimal damage to other key material layers, thereby further optimizing the device structure, improving the fineness and flatness of the structure, reducing defects, and improving the overall performance and reliability of semiconductor devices. It also ensures that the Micro-LED product manufacturing process achieves nearly vertical ISO epitaxy, reduces the loss of the Micro-LED's light-emitting area, increases luminous efficacy, and improves light emission efficiency.

[0051] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A Micro-LED ISO vertical angle etching method, characterized in that: The following steps are involved: S1. Epitaxial layer growth control: Provide a sapphire substrate as a substrate, grow an epitaxial layer structure on the substrate, and simultaneously grow a certain thickness of silicon oxide as a protective layer on the substrate through a PECV device; S2, photolithography patterning: Select positive photoresist and coat it on the surface of the protective layer through a coating machine, and then perform photolithography and development to produce the pattern that needs to be etched on the ISO sidewall; S3, metal coating and patterning: Cr metal coating is performed through a metal evaporation table, the Cr metal is patterned through a gold peeling and debonding process, and then the protective layer is patterned by wet etching; S4, dry etching epitaxy: using inductively coupled plasma etching equipment to dry etch the epitaxial part; S5. Removing the protective layer: removing the protective layer on the epitaxial surface by wet etching or dry etching to obtain ISO sidewall epitaxy with an angle close to vertical.

2. A Micro-LED ISO vertical angle etching method according to claim 1, characterized in that: The epitaxial layer structure in S1 is gallium nitride, gallium phosphide or gallium indium arsenic phosphide. A certain thickness of silicon oxide is grown on the substrate by PECV equipment as a protective layer with a thickness of 2000A for stripping the metal barrier layer.

3. A Micro-LED ISO vertical angle etching method according to claim 1, characterized in that: The pattern to be etched on the ISO sidewall in S2 is the Lift Off layer, and the thickness of the ISO sidewall etching is 4-4.3 microns.

4. The Micro-LED ISO vertical angle etching method according to claim 1, characterized in that: The Cr metal coating in S3 is a barrier layer, the selectivity of the metal Cr for etching gallium nitride is 1:17.1, and the thickness of the Cr metal coating is 2400-2500A.

5. The Micro-LED ISO vertical angle etching method according to claim 1, characterized in that: In the dry etching in S4, chlorine and argon are used as etching gases.

6. A Micro-LED ISO vertical angle etching method according to claim 5, characterized in that: The chlorine gas flow rate was set at 30-40 sccm, and the argon gas flow rate was set at 12-15 sccm.

7. The Micro-LED ISO vertical angle etching method according to claim 1, characterized in that: The wet etching in S5 uses a 6:1 BOE solution.

8. The Micro-LED ISO vertical angle etching method according to claim 7, characterized in that: The etching time is between 100 and 130 seconds.

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