Preparation method of quantum chip, quantum chip and quantum computing equipment

Abstract

The invention discloses a preparation method of a quantum chip, the quantum chip and quantum computing equipment. The preparation method of the quantum chip comprises the following steps: preparing a chip circuit layer on a chip substrate; the chip circuit layer comprises two structural subcomponents of a first structural element and a second structural element; the two structural sub-components are located on the two sides of the first structural element respectively; preparing a shielding structure spanning the first structural element above the first structural element on the inner sides of the two structural sub-components; and preparing a connecting part for connecting the two structural sub-components in the second structural element, wherein the connecting part is positioned above the shielding structure. According to the quantum bit extension architecture, the quantum bit extension architecture is realized on a single chip, meanwhile, the effect of shielding two structural elements with an intersection area is well achieved, the problems of coupling and signal crosstalk generated between the two structural elements with the intersection area are avoided or reduced, and the service life of the quantum bit is guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of quantum information technology, and in particular to a method for preparing a quantum chip, a quantum chip and a quantum computing device. Background Art

[0002] Superconducting quantum chips are considered a powerful tool for quantum computing due to their low noise, high speed and low power consumption. Although research is still in its early stages, as scientists continue to optimize quantum bit design, improve error correction technology and control strategies, some leading institutions and companies have successfully produced multi-bit superconducting quantum systems in the laboratory.

[0003] Multi-bit superconducting quantum systems can perform complex problems that are difficult for classical computers to solve, such as large-scale optimization problems, quantum simulations, etc. In addition, these chips can also be used to realize quantum technologies such as quantum communications and high-precision sensing, opening up new possibilities for scientific research and industrial applications.

[0004] The core component of a superconducting quantum chip is a superconducting qubit. More qubits mean more powerful computing power. Each qubit requires one or more signal lines to control or read out. As the number of bits continues to increase, how to more reasonably utilize limited space for wiring has become a difficulty in the expansion of multiple bits. Summary of the invention

[0005] In view of the above problems, the present invention is proposed to provide a method for preparing a quantum chip, a quantum chip and a quantum computing device that overcome the above problems or at least partially solve the above problems.

[0006] In a first aspect, an embodiment of the present invention provides a method for preparing a quantum chip, wherein the quantum chip comprises a first structural element, a second structural element and a shielding structure, wherein in a height direction, there is at least one overlapping region between the first structural element, the second structural element and the shielding structure, and within the overlapping region, the shielding structure is at least partially located between the first structural element and the second structural element, and the preparation method comprises the following steps:

[0007] A chip circuit layer is prepared on a chip substrate; the chip circuit layer comprises two structural subcomponents of a first structural element and a second structural element; the two structural subcomponents are respectively located on two sides of the first structural element;

[0008] On the inner sides of the two structural subcomponents, a shielding structure is prepared above the first structural element and spans the first structural element;

[0009] A connecting portion in the second structural element for connecting the two structural subcomponents is prepared and is located above the shielding structure.

[0010] In one embodiment, the width of the shielding structure is greater than or equal to the width of the connecting portion.

[0011] In one embodiment, the chip circuit layer further includes: a ground located inside the two structural subcomponents and respectively located on both sides of the first structural element;

[0012] A shielding structure is prepared on the inner side of the two structural subcomponents and spanning the first structural element above the first structural element, comprising:

[0013] A shielding structure spanning the first structural element is prepared between the grounds located inside the two structural subcomponents and respectively located on both sides of the first structural element, and two ends of the shielding structure are respectively connected to the grounds.

[0014] In one embodiment, the step of preparing a shielding structure spanning the first structural element comprises:

[0015] A shielding layer having a bridge-like structure spanning the first structural element is prepared.

[0016] In one embodiment, preparing a shielding layer having a bridge-like structure spanning the first structural element comprises:

[0017] Preparing a shielding layer support on the chip substrate and the chip circuit layer; the shielding layer support is made of non-conductive material;

[0018] In a corresponding area of ​​the ground, removing at least a portion of the shielding layer support so that at least a portion of the ground plane is exposed;

[0019] Removing the oxide layer of the exposed part and preparing a superconducting metal layer of a preset thickness on the chip;

[0020] A photoresist is coated on the surface of the superconducting metal layer, and a non-shielding layer area is defined. The superconducting metal layer in the non-shielding layer area is removed by exposure and etching, and the superconducting metal layer in the shielding layer area is retained to form the shielding layer.

[0021] In one embodiment, the shielding layer support includes one or more of a photoresist, a silicon oxide dielectric layer, and a silicon nitride dielectric layer.

[0022] In one embodiment, when the support is made of photoresist, a shielding layer support is prepared on the chip substrate and the chip circuit layer accordingly, and in the corresponding area of ​​the ground, at least part of the shielding layer support is removed to expose at least part of the ground plane, including:

[0023] Coating a layer of photoresist on the chip substrate and the chip circuit layer;

[0024] In a corresponding area of ​​the ground, denaturing a portion of the photoresist in the corresponding area through an exposure process;

[0025] The denatured region of the photoresist is developed using a developer to expose the developed ground plane.

[0026] In one embodiment, after the step of developing the denatured region of the photoresist with a developer to expose the developed ground plane, and before the step of removing the oxide layer of the exposed portion of the ground to prepare a superconducting metal layer of a preset thickness, the method further includes:

[0027] The photoresist is baked to form the photoresist into a preset arch shape.

[0028] In one embodiment, after the step of removing the superconducting metal layer in the non-shielding layer area and retaining the superconducting metal layer in the shielding layer area, the method further comprises:

[0029] The remaining photoresist is removed, wherein the remaining photoresist includes the photoresist between the shielding layer and the first structural element, and the photoresist covering other areas outside the shielding layer.

[0030] In one embodiment, the step of preparing the connecting portion of the second structural element comprises:

[0031] preparing a connection support again on the chip, wherein the connection support is made of a non-conductive material;

[0032] Removing the connection support at the preset positions on the two structural subcomponents to expose the chip circuit layer at the preset positions;

[0033] Removing the oxide layer of the exposed chip circuit layer, and preparing a superconducting metal layer of a preset thickness on the chip again;

[0034] A photoresist is coated on the surface of the superconducting metal layer to define a non-connecting region. The superconducting metal layer in the non-connecting region is removed by exposure and etching, and the superconducting metal layer in the connecting region is retained to form the connecting portion.

[0035] In one embodiment, the superconducting metal layer of preset thickness is prepared by an evaporation process.

[0036] In one embodiment, the connection portion support is one or more of a photoresist, a silicon oxide dielectric layer, and a silicon nitride dielectric layer.

[0037] In one embodiment, when the support of the connection part is made of photoresist, accordingly, after the step of removing the support of the connection part at the preset position on the two structural subcomponents to expose the chip circuit layer at the preset position, before the step of removing the oxide layer of the exposed chip circuit layer and preparing a superconducting metal layer of a preset thickness on the chip again, the method further includes:

[0038] The photoresist serving as a support for the connection portion is baked to change the photoresist into a preset arch shape.

[0039] In one embodiment, after the step of removing the superconducting metal layer in the non-connecting part area and retaining the superconducting metal layer in the connecting part area to form the connecting part, the step further includes:

[0040] Remaining supports are removed, wherein the remaining supports include supports between the second structural element and the shielding layer, and supports on other areas outside the connecting portion.

[0041] In one embodiment, the superconducting metal material used to prepare the chip circuit layer, the shielding layer and the connecting portion includes any one or more of the following:

[0042] Metal aluminum Al, metal niobium Nb and metal tantalum Ta.

[0043] In one embodiment, the prepared quantum chip is a single chip.

[0044] In one embodiment, in the width direction, both sides of the shielding structure extend beyond the connecting portion.

[0045] In a second aspect, an embodiment of the present invention provides a quantum chip, which is prepared by the method for preparing a quantum chip as described above.

[0046] In a third aspect, an embodiment of the present invention provides a quantum computing device, wherein the quantum computing device comprises the quantum chip as described above.

[0047] The beneficial effects of the above technical solution provided by the embodiment of the present invention include at least:

[0048] In order to achieve the expansion of quantum bits and avoid the above-mentioned problems at the same time, the inventors of the present application, through design and conception, first prepare a shielding structure when preparing a structural element with an intersection area, and then prepare a connecting portion located on the shielding structure, so that there is at least the same overlapping area between the first structural element, the second structural element and the shielding structure finally generated, and in the height direction, within the overlapping area, the shielding structure is at least partially located between the two structural elements. While realizing the expansion architecture of quantum bits on a single chip, it can also play a good role in shielding the two structural elements, avoiding or reducing the coupling and signal crosstalk problems generated between the two structural elements with the intersection area, thereby ensuring the service life of the quantum bits and improving the reliability of the use of quantum chips.

[0049] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0050] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0052] Figure 1 This is the first implementation of the quantum bit expansion solution in the prior art;

[0053] Figure 2 This is the second implementation method of the quantum bit expansion solution in the prior art;

[0054] Figure 3 is a flow chart of a method for preparing a quantum chip in an embodiment of the present invention;

[0055] Figure 4 This is a schematic diagram of the relevant structure of the chip circuit layer in the quantum chip in an embodiment of the present invention;

[0056] Figure 5 It is a schematic diagram of the chip structure after the shielding layer support is prepared in an embodiment of the present invention;

[0057] Figure 6 A schematic diagram of a chip structure coated with photoresist and with a developed ground plane exposed in an embodiment of the present invention;

[0058] Figure 7A schematic diagram showing that the photoresist becomes an arch during the preparation of the shielding layer in an embodiment of the present invention;

[0059] Figure 8 This is a schematic structural diagram of a superconducting metal layer on a photoresist during the process of preparing a shielding layer in an embodiment of the present invention;

[0060] Fig. 9 It is a schematic structural diagram of coating a photoresist on the surface of a superconducting metal layer in the process of preparing a shielding layer in an embodiment of the present invention;

[0061] Fig.10 It is a schematic diagram of a chip structure after the superconducting metal layer in the shielding layer area is removed in an embodiment of the present invention;

[0062] Fig.11 This is a schematic diagram of a chip in which the photoresist is removed after the shielding layer is prepared in an embodiment of the present invention;

[0063] Fig.12 Schematic diagram of the chip structure after preparing the connection part support (such as photoresist) in an embodiment of the present invention;

[0064] Fig.13 This is a schematic diagram of the chip structure after photoresist baking in the process of preparing the connection part in an embodiment of the present invention;

[0065] Fig.14 This is a cross-sectional schematic diagram of the fabricated quantum chip;

[0066] Fig.15 This is a top view of the completed quantum chip. DETAILED DESCRIPTION

[0067] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0068] In the description of the invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, which are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In the description of the invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a connection between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the invention can be understood according to specific circumstances.

[0069] Regarding the solution for expanding the existing quantum bits, the inventors of the present application have found that there are two common processing methods in the prior art for rationally utilizing spatial wiring to realize more quantum bits in a limited space:

[0070] In the first solution, all components and signal lines of the chip are set on a single chip (Die), and a large number of crossovers occur between the signal lines. Figure 1 As shown in the enlarged schematic diagram in the lower right corner, in this case, the air bridge process is used to achieve line crossing and avoid line collision. This technical solution is simple and can be prepared without the use of complex multi-layer chip processes and expensive multi-layer process equipment.

[0071] However, this approach may cause the lifetime of quantum bits to be drastically shortened because of the use of air bridges across components.

[0072] For example, if the air bridge connecting the signal line is placed directly above the qubit, that is, there is a crossover or overlap between the air bridge and the qubit in the height direction, a capacitive coupling will be generated between the air bridge and the qubit. The more air bridges there are, the capacitive coupling between the qubit and the outside world will increase exponentially, and the energy of the qubit will leak to the outside world through this undesirable capacitive coupling. Among them, the qubit is one of the many components in the quantum chip.

[0073] Reference Figure 2 As shown, the second solution is to prepare the components and signal lines of the chip on multiple chips (Die), for example Figure 2The Readout / interconnect tier, TSV tier and Qubit tier are then pressed together to achieve multi-bit integration. The advantage of this solution is that different signal lines and components are set on different chips, and there will be no crossover. At the same time, the crosstalk and coupling between signal lines will be very small. However, the disadvantage is that a large number of complex multi-layer chip processes such as through silicon via technology (TSV) and flip chip technology are required. Because of the high process level and the need for more complex and high-end equipment, the cost is relatively high.

[0074] In order to achieve the expansion of quantum bits and avoid the above problems at the same time, the inventor of the present application, through design and conception, first prepares a shielding structure above one of the structural elements when preparing a quantum chip, and then prepares the connecting part of another structural element on the shielding structure, so that in the final quantum chip, there is at least one overlapping area between the two structural elements with cross-regions and the shielding structure, and in the height direction, in the overlapping area, the shielding structure is at least partially located between the two structural elements. Such a design can not only realize the expansion architecture of quantum bits on a single chip, but also play a good role in shielding the two structural elements, avoiding or reducing the coupling and signal crosstalk problems between the two structural elements with overlapping regions, ensuring the service life of the quantum bits, and improving the reliability of the use of quantum chips.

[0075] The present invention provides a method for preparing a quantum chip. Figure 3 As shown, the following steps are included:

[0076] S31, preparing a chip circuit layer on a chip substrate; wherein the chip circuit layer comprises two structural subcomponents of a first structural element and a second structural element; the two structural subcomponents are respectively located on two sides of the first structural element;

[0077] In this step S31, for example, micro-nano processing technology may be used to prepare the chip circuit layer.

[0078] The chip circuit layer contains multiple structural elements, all of which are conductive.

[0079] The structural elements include: a first structural element, and two structural subcomponents of a second structural element;

[0080] The first structural element is an integral structure, and the second structural element is a structure of multiple components connected, including two structural subcomponents and a connecting portion. The connecting portion spans the first structural element and is used to connect the two structural subcomponents.

[0081] After the first structural element is completely prepared, the first structural element and the second structural element intersect each other, that is, there is an intersection region between the two. A shielding structure is arranged in the intersection region of the first structural element and the second structural element, and in the vertical direction, the shielding structure is located between the first structural element and the second structural element.

[0082] In the embodiment of the present invention, the specific form and angle of intersection between the structural elements are not limited.

[0083] S32, preparing a shielding structure spanning the first structural element above the first structural element on the inner sides of the two structural subcomponents;

[0084] S33, preparing a connecting portion in the second structural element for connecting two structural subcomponents, and the connecting portion is located above the shielding structure.

[0085] The quantum chip obtained through the preparation process of the above steps S31-S33 includes a first structural element, a second structural element and a shielding structure. In the height direction, there is at least the same overlapping area between the first structural element, the second structural element and the shielding structure, and the shielding structure is at least partially located between the first structural element and the second structural element.

[0086] Those skilled in the art can imagine that in the prepared quantum chip, the shielding structure can be completely located in the intersection area of ​​the first structural element and the second structural element, or only partially located in the above-mentioned intersection area, and the rest can extend out of the intersection area.

[0087] In an embodiment of the present invention, the shielding structure is prepared before the connecting portion of the second structural element.

[0088] The two structural elements (the first structural element and the second structural element) having the intersection region may include the following situations, for example:

[0089] Two signal lines crossing each other; or

[0090] Two components crossing each other; or

[0091] Signal lines and components that cross signal lines.

[0092] The above-mentioned components can be any components used in quantum chips, including but not limited to electronic components such as quantum bits, resonators, tunable couplers, etc.

[0093] The signal lines include, for example, DC signal lines, microwave signal lines, and the like.

[0094] In step S32 and step S33, the shielding structure may be prepared using the same material as the first structural element and the second structural element, such as various superconducting materials, such as metal aluminum Al, metal niobium Nb, and metal tantalum Ta.

[0095] In another embodiment, the shielding structure may be made of a material different from the first structural element and the second structural element.

[0096] The shielding structure may also be prepared using non-superconducting metal materials, such as copper, etc., which is not limited in the embodiment of the present invention.

[0097] By using the above-mentioned method for preparing a quantum chip, for two first structural elements and second structural elements having an intersection area, a shielding structure is first prepared in the intersection area, and then a connecting portion located above the shielding structure for connecting two structural sub-components of the second structural element is prepared, so as to form a structural form in which one of the two structural elements is on top and the other is on the bottom in the height direction, and there is at least one same overlapping area among the first structural element, the second structural element and the shielding structure, and in the overlapping area of ​​the three, the shielding structure is at least partially located between the first structural element and the second structural element, and the shielding structure can play a better shielding role, so that the two structural elements will not generate capacitive coupling or at least can reduce unnecessary capacitive coupling, thereby reducing crosstalk on the chip and ensuring the life of the quantum bit.

[0098] In one embodiment, referring to Figure 4 As shown, the chip circuit layer also includes: a ground located inside the two structural subcomponents and respectively located on both sides of the first structural element.

[0099] Accordingly, in the above step S32, a shielding structure spanning the first structural element is prepared on the inner side of the two structural subcomponents and above the first structural element, which can be specifically achieved in the following manner:

[0100] A shielding structure spanning the first structural element is prepared between grounds located inside the two structural subcomponents and respectively located on both sides of the first structural element, wherein both ends of the shielding structure are respectively connected to the grounds.

[0101] In the embodiment of the present invention, the width of the prepared shielding structure is greater than or equal to the width of the connecting portion, and the length of the prepared shielding structure is greater than the width of the first structural element it crosses.

[0102] In one embodiment, in the above preparation method, the shielding structure can be in the form of a shielding layer, and the shielding layer adopts an arched structure, for example, a shielding layer of a bridge structure spanning the first structural element is prepared. However, in other embodiments, the shielding structure can also be a structure of other suitable shapes, and is not limited to the shielding layer of the arched structure herein.

[0103] Inside the two structural subcomponents of the second structural element, a shielding layer of a bridge-like structure spanning the first structural element is prepared on the ground arranged on both sides of the first structural element.

[0104] After the shielding layer is prepared, a connecting portion for connecting two structural subcomponents in the second structural element is prepared, and the connecting portion is located above the shielding layer in a vertical direction. The preparation method is similar to that of the shielding layer.

[0105] The following is an example of a specific process to illustrate the method for preparing a quantum chip provided by an embodiment of the present invention. The method includes the following steps:

[0106] 1.1 Prepare the chip circuit layer on the chip substrate;

[0107] For example, the quantum chip circuit layer can be prepared on the chip substrate through micro-nano processing technology.

[0108] The chip structure of the prepared chip circuit layer is detailed in Figure 4 As shown, the chip circuit layer includes two structural sub-components including a first structural element, a ground and a second structural element.

[0109] 1.2 Prepare a shielding layer support on the chip substrate and the chip circuit layer;

[0110] The shielding layer support may be made of non-conductive material; the shielding layer support includes one or more of photoresist, silicon oxide dielectric layer, and silicon nitride dielectric layer.

[0111] A layer of photoresist is spin-coated on the chip as a shielding layer support, and then in the area where the ground is located, at the position where the shielding layer needs to be prepared, the photoresist in the corresponding area is denatured through an exposure process.

[0112] The chip structure after this step is as follows Figure 5 shown.

[0113] 1.3 In the corresponding area of ​​the ground, remove at least part of the shielding layer support to expose at least part of the ground plane;

[0114] Reference Figure 6 As shown, for example, when the shielding layer support is made of photoresist, a layer of photoresist is first coated on the chip substrate and the chip circuit layer;

[0115] In a corresponding area of ​​the ground, a portion of the photoresist in the corresponding area is denatured by an exposure process;

[0116] The denatured area of ​​the photoresist is developed using a developer to expose the developed ground plane.

[0117] Bake the photoresist to make it into a preset arch shape. Figure 7 As shown, the photoresist becomes an arch shape after being baked.

[0118] The purpose of making the photoresist into a preset arch shape is to prepare for the subsequent preparation of a bridge-shaped shielding layer.

[0119] 1.4 Remove the oxide layer of the exposed part and evaporate a superconducting metal layer of preset thickness on the chip;

[0120] Reference Figure 8 As shown, there is a superconducting metal layer on the photoresist.

[0121] For example, ion beam etching (IBE) bombardment and other operations can be used to remove the oxide layer of the exposed part of the ground. Removing the oxide layer can ensure good conductivity between the subsequent evaporated superconducting metal layer and the ground.

[0122] The material used for the superconducting metal layer may include, for example, Al, Nb, and Ta.

[0123] 1.5 Coat photoresist on the surface of the superconducting metal layer and define the non-shielding layer area on the chip. Through exposure and etching steps, remove the superconducting metal layer in the non-shielding layer area and retain the superconducting metal layer in the shielding layer area to form a shielding layer.

[0124] Reference Fig. 9 As shown, a layer of photoresist is coated on the surface of the superconducting metal layer. Fig.10 What is shown is the chip structure after the superconducting metal layer in the shielding layer area is removed.

[0125] Optionally, after the shielding layer is prepared, the remaining photoresist may be removed, where the remaining photoresist includes the photoresist between the shielding layer and the first structural element, and the photoresist covering the outside of the shielding layer.

[0126] The remaining photoresist can be removed using an organic solvent or a special degumming solution, such as NMP (N-methylpyrrolidone), acetone, etc.

[0127] After preparing the shielding layer and then removing the photoresist chip, please refer to Fig.11 shown.

[0128] After the shielding layer is prepared, it is necessary to continue preparing the connecting portion of the second structural element. The process of preparing the connecting portion is similar to the process of preparing the shielding layer. For details, refer to the description of the following steps 1.6-1.10.

[0129] 1.6 Preparing a connection support again on the chip, wherein the connection support is made of a non-conductive material;

[0130] Similar to step 1.2, the connection support can also be prepared by using one or more of a photoresist, a silicon oxide dielectric layer, and a silicon nitride dielectric layer.

[0131] The chip structure after preparing the connection support (such as photoresist) can be seen in Fig.12 shown.

[0132] 1.7 Remove the connection support at the preset position on the two structural sub-components to expose the chip circuit layer at the preset position;

[0133] The connecting part is connected to the two structural sub-components, so some supports need to be removed in this step. The removal method can adopt different processes according to the material of the supports. For example, for photoresist, the supports in the corresponding area are removed through an exposure process or an etching process.

[0134] When the support is a photoresist, high-temperature baking is required for a certain period of time, and the photoresist is deformed into an arch shape after high-temperature baking.

[0135] Chip structure reference after photoresist baking Fig.13 shown.

[0136] 1.8 Remove the oxide layer of the exposed chip circuit layer, and evaporate a superconducting metal layer of preset thickness on the chip again;

[0137] The steps are similar to those in 1.4 above.

[0138] 1.9 Coat the surface of the superconducting metal layer with photoresist and define the non-connecting area. Remove the superconducting metal layer in the non-connecting area through exposure and etching, and retain the superconducting metal layer in the connecting area to form a connecting part.

[0139] 1.10 Remove the remaining supports;

[0140] In this step, the remaining supports include supports (photoresist, etc.) between the second structural element and the shielding layer, and supports on other areas outside the connecting portion.

[0141] After this step, the second structural element is prepared. The specific chip structure can be referred to Fig.14 shown.

[0142] Reference Fig.15As shown, Fig.15 It is a top view of the prepared quantum chip. In the direction where the shielding layer 3 crosses the first structural element 1, the length of the shielding layer 3 is greater than the width of the first structural element 1 at the crossing point.

[0143] In another direction perpendicular to the direction in which the shielding layer 3 crosses the first structural element 1 , the width x2 of the shielding layer 3 is greater than or equal to the width x1 of the connecting portion 23 .

[0144] In the width direction, both sides of the shielding layer 3 extend beyond the connecting portion 23 .

[0145] The above steps 1.1 to 1.10 are examples of a specific process of the method for preparing the quantum chip of the present invention. However, it is clear to those skilled in the art that other specific processes can also be used to manufacture the shielding structure and the like. Therefore, as long as the technical solution of manufacturing the shielding structure in the intersection area of ​​the first structural element and the second structural element is used, it should fall within the protection scope of the present invention.

[0146] An embodiment of the present invention further provides a quantum chip, which is prepared by the method for preparing the quantum chip as described above.

[0147] An embodiment of the present invention further provides a quantum computing device, which includes the quantum chip as described above.

[0148] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0149] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for preparing a quantum chip, characterized in that: The quantum chip comprises a first structural element, a second structural element and a shielding structure, in the height direction, there is at least one overlapping region between the first structural element, the second structural element and the shielding structure, and in the overlapping region, the shielding structure is at least partially located between the first structural element and the second structural element, and the preparation method comprises the following steps: A chip circuit layer is prepared on a chip substrate; the chip circuit layer comprises two structural subcomponents of a first structural element and a second structural element; the two structural subcomponents are respectively located on two sides of the first structural element; On the inner sides of the two structural subcomponents, a shielding structure is prepared above the first structural element and spans the first structural element; A connecting portion in the second structural element for connecting the two structural subcomponents is prepared and is located above the shielding structure.

2. The method according to claim 1, characterized in that The chip circuit layer further includes: a ground located inside the two structural subcomponents and respectively located on both sides of the first structural element; A shielding structure is prepared on the inner side of the two structural subcomponents and spanning the first structural element above the first structural element, comprising: A shielding structure spanning the first structural element is prepared between the grounds located inside the two structural subcomponents and respectively located on both sides of the first structural element, and two ends of the shielding structure are respectively connected to the grounds.

3. The method according to claim 2, characterized in that The width of the shielding structure is greater than or equal to the width of the connecting portion.

4. The method according to claim 2, characterized in that The step of preparing a shielding structure spanning the first structural element comprises: A shielding layer having a bridge-like structure spanning the first structural element is prepared.

5. The method according to claim 4, characterized in that Preparing a shielding layer having a bridge-like structure spanning the first structural element, comprising: Preparing a shielding layer support on the chip substrate and the chip circuit layer; the shielding layer support is made of non-conductive material; In a corresponding area of ​​the ground, removing at least a portion of the shielding layer support so that at least a portion of the ground plane is exposed; Removing the oxide layer of the exposed part and preparing a superconducting metal layer of a preset thickness on the chip; A photoresist is coated on the surface of the superconducting metal layer, and a non-shielding layer area is defined. The superconducting metal layer in the non-shielding layer area is removed by exposure and etching, and the superconducting metal layer in the shielding layer area is retained to form the shielding layer.

6. The method according to claim 5, characterized in that The shielding layer support includes one or more of a photoresist, a silicon oxide dielectric layer, and a silicon nitride dielectric layer.

7. The method according to claim 5, characterized in that When the support is made of photoresist, accordingly, a shielding layer support is prepared on the chip substrate and the chip circuit layer, and in the corresponding area of ​​the ground, at least part of the shielding layer support is removed to expose at least part of the ground plane, including: Coating a layer of photoresist on the chip substrate and the chip circuit layer; In a corresponding area of ​​the ground, denaturing a portion of the photoresist in the corresponding area through an exposure process; The denatured region of the photoresist is developed using a developer to expose the developed ground plane.

8. The method according to claim 7, characterized in that After the step of developing the denatured region of the photoresist with a developer to expose the developed ground plane, and before the step of removing the oxide layer of the exposed portion of the ground to prepare a superconducting metal layer of a preset thickness, the method further includes: The photoresist is baked to form the photoresist into a preset arch shape.

9. The method according to claim 5, characterized in that After the step of removing the superconducting metal layer in the non-shielding layer area and retaining the superconducting metal layer in the shielding layer area, the method further includes: The remaining photoresist is removed, wherein the remaining photoresist includes the photoresist between the shielding layer and the first structural element, and the photoresist covering the outside of the shielding layer.

10. The method according to claim 1, characterized in that The step of preparing the connecting portion of the second structural element comprises: preparing a connection support again on the chip, wherein the connection support is made of a non-conductive material; Removing the connection support at the preset positions on the two structural subcomponents to expose the chip circuit layer at the preset positions; Removing the oxide layer of the exposed chip circuit layer, and preparing a superconducting metal layer of a preset thickness on the chip again; A photoresist is coated on the surface of the superconducting metal layer to define a non-connecting region. The superconducting metal layer in the non-connecting region is removed by exposure and etching, and the superconducting metal layer in the connecting region is retained to form the connecting portion.

11. The method according to claim 5 or 9, characterized in that: The superconducting metal layer of preset thickness is prepared by an evaporation process.

12. The method according to claim 10, characterized in that The connecting part support is one or more of a photoresist, a silicon oxide dielectric layer, and a silicon nitride dielectric layer.

13. The method according to claim 11, characterized in that In the case where the support of the connection part is made of photoresist, accordingly, after the step of removing the support of the connection part at the preset position on the two structural subcomponents to expose the chip circuit layer at the preset position, and before the step of removing the oxide layer of the exposed chip circuit layer and preparing a superconducting metal layer of a preset thickness on the chip again, the method further includes: The photoresist serving as a support for the connection portion is baked to change the photoresist into a preset arch shape.

14. The method according to claim 10, characterized in that After the step of removing the superconducting metal layer in the non-connecting part area and retaining the superconducting metal layer in the connecting part area to form the connecting part, the method further includes: Remaining supports are removed, wherein the remaining supports include supports between the second structural element and the shielding layer, and supports outside the connecting portion.

15. The method according to any one of claims 1 to 14, characterized in that: The superconducting metal materials used to prepare the chip circuit layer, the shielding layer and the connecting portion include any one or more of the following: Metal aluminum Al, metal niobium Nb and metal tantalum Ta.

16. The method according to any one of claims 1 to 14, characterized in that: The prepared quantum chip is a single chip.

17. The method according to claim 3, characterized in that In the width direction, both sides of the shielding structure exceed the connecting portion.

18. A quantum chip, characterized in that: The quantum chip is prepared by the method for preparing a quantum chip according to any one of claims 1 to 17.

19. A quantum computing device, characterized in that: The quantum computing device comprises the quantum chip as claimed in claim 18.

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