MRAM integrated with self-aligned direct backside contact

Abstract

A backside contact structure is provided that directly connects a first electrode (52) of the MRAM located at the backside of the wafer to a source / drain structure (36) of the transistor. The backside contact is self-aligned with a source / drain structure (36) of the transistor and a first electrode (52) of the MRAM. The close proximity between the MRAM and the source / drain structure (36) increases the speed of the device. The MRAM yield is not compromised because re-sputtering of the back side contact metal onto the MRAM does not occur.

Description

Background Art

[0001] The present invention relates to semiconductor technology, and more particularly to a semiconductor structure including a magnetoresistive random access memory (MRAM) on the back side of a wafer and a method for forming the same.

[0002] MRAM is an available memory option for standalone and embedded applications, such as the Internet of Things (IoT), automotive or artificial intelligence (AI). MRAM is a non-volatile random access memory technology in which data is stored by magnetic storage elements. These elements are usually formed of two ferromagnetic plates, each of which can maintain a magnetization, separated by a thin dielectric layer, the tunnel barrier layer. One of the two plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match the magnetization of the external field storing the memory. MRAM is usually formed in the back-end of the line (BEOL) area of ​​the semiconductor structure, so there is a large distance between the source / drain area of ​​the field effect transistor (FET) and the MRAM. Summary of the invention

[0003] A backside contact structure is provided that directly connects a first electrode of an MRAM located on the backside of a wafer to a source / drain structure of a transistor. The backside contact is self-aligned with the source / drain structure of the transistor and the first electrode of the MRAM. The close proximity between the MRAM and the source / drain structure increases the speed of the device. The MRAM yield is not compromised because re-sputtering of the backside contact metal onto the MRAM does not occur.

[0004] In one aspect of the present application, a semiconductor structure is provided. In one embodiment, the semiconductor structure includes an MRAM located in an MRAM device region and in a back side of a wafer. The MRAM includes a first electrode, an MRAM stack, and a second electrode. There is a first back side source / drain contact structure that directly connects the first electrode of the MRAM to a first source / drain structure of a first transistor that is present in a front side of the wafer and in the MRAM device region.

[0005] In some embodiments of the present application, the first backside source / drain contact structure has an outermost wall that is substantially vertically aligned with the outermost wall of the first electrode. The term "substantially" when used with the phrase "vertically aligned" means that the outermost wall of one structure is within ±5.0% of the outermost wall of the other structure; in some cases, perfect vertical alignment is achieved. In some embodiments of the present application, the outermost wall of the first backside source / drain contact structure is substantially vertically aligned with the outermost wall of the first source / drain structure of the first transistor. This "vertical alignment" provides reduced overlay error in the device.

[0006] In some embodiments of the present application, the first transistor includes a vertical stack of semiconductor channel material nanosheets and a functional gate structure surrounding each of the semiconductor channel material nanosheets. Such a transistor may be referred to as a nanosheet field effect transistor. In other embodiments, the first transistor is a planar transistor, a finFET transistor, or a nanowire transistor.

[0007] In some embodiments of the present application, the structure further includes a bottom dielectric isolation layer located on a surface of the first transistor, the bottom dielectric isolation layer having a sidewall in direct physical contact with an outermost sidewall of the first backside source / drain contact structure.

[0008] In some embodiments of the present application, particularly when a nanosheet field effect transistor is used as the first transistor, the inner spacer is positioned laterally adjacent to a functional gate structure of the transistor.

[0009] In some embodiments of the present application, the structure further includes a second source / drain structure located on a second side of the functional gate structure of the first transistor, the second side being opposite to the first side of the functional gate structure of the first transistor. In such embodiments, the structure may further include a first front side source / drain contact structure connecting the second source / drain structure of the first transistor to a front side back end of line (BEOL) structure. In embodiments of the present application, a carrier wafer is located on a surface of the front side BEOL structure.

[0010] In some embodiments of the present invention, the structure further comprises an MRAM spacer positioned laterally adjacent to and in direct physical contact with the MRAM stack and the second electrode, wherein the MRAM spacer is positioned laterally adjacent to but spaced apart from the first electrode. In such embodiments, the MRAM spacer has a bottom-most surface located between a bottom-most surface and a top-most surface of the first electrode.

[0011] In some embodiments of the present application, a backside interlayer dielectric (ILD) material layer stack laterally surrounds the MRAM and an upper portion of the first backside source / drain contact structure.

[0012] In some embodiments of the present application, the second electrode is in electrical contact with the backside interconnect structure. In such embodiments, the structure further includes a contact via structure extending vertically through the second electrode, the contact via structure having a first surface in direct contact with the MRAM stack and a second surface opposite to the first surface, the second surface in direct contact with the backside interconnect structure.

[0013] In some embodiments of the present application, the structure also includes a second transistor located in the front side of the wafer and in a logic device area positioned adjacent to the MRAM device area, wherein the second transistor has a first source / drain structure located on a first side of a functional gate structure of the second transistor, and a second source / drain structure located on a second side of the functional gate structure of the second transistor opposite to the first side of the functional gate structure of the second transistor.

[0014] In some embodiments of the present application, the second backside source / drain contact structure is located in the logic device region and connects the first source / drain structure of the second transistor to the backside power rail.

[0015] In some embodiments of the present application, the backside power rail is in electrical contact with the backside interconnect structure. In an embodiment, the via contact structure is located between the backside interconnect structure and the backside power rail.

[0016] In some embodiments of the present application, the structure further comprises a front side source / drain contact structure in the logic device region, which connects the second source / drain structure of the second transistor to the front side BEOL structure. In some embodiments of the present application, a carrier wafer is located on the surface of the front side BEOL structure.

[0017] In some embodiments of the present application, the second backside source / drain contact structure present in the logic device region has a topmost surface located below a bottommost surface of an MRAM spacer surrounding the MRAM device.

[0018] In another embodiment of the present invention, a semiconductor structure includes an MRAM device region, the MRAM device region includes an MRAM, the MRAM includes a first electrode, an MRAM stack, and a second electrode, and the MRAM device region is located on the back side of the wafer. The MRAM device region also includes a first transistor having a first source / drain structure, and a first backside source / drain contact structure that directly connects the first electrode of the MRAM to the first source / drain structure of the first transistor. In the present application, the first backside source / drain contact structure has an outermost wall that is substantially vertically aligned with the outermost walls of both the first source / drain structure and the first electrode of the first transistor. The structure also includes a logic device region positioned adjacent to the MRAM device region, wherein the logic device region includes a second transistor located in the front side of the wafer, and has a first source / drain structure located on a first side of a functional gate structure of the second transistor, and a second backside source / drain contact structure that directly connects the first source / drain structure of the functional gate structure of the second transistor to the backside power rail.

[0019] In some embodiments, the second backside source / drain contact structure has a topmost surface that is below a bottommost surface of an MRAM spacer surrounding the MRAM device.

[0020] In some embodiments, the MRAM spacer has a bottommost surface located between a bottommost surface and a topmost surface of the first electrode.

[0021] In some embodiments, the backside power rail is in electrical contact with a backside interconnect structure on top of the backside power rail, and the second electrode of the MRAM is in electrical contact with the backside interconnect structure on top of the MRAM.

[0022] In another aspect of the present application, a method for forming a semiconductor structure is provided, which will become more clear with reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1A and Figure 1B The exemplary structures are cross-sectional views in the logic device region and the MRAM device region, respectively, the exemplary structure comprising at least one stack containing nanosheets on a semiconductor substrate, the semiconductor substrate comprising a first semiconductor material layer, an etch stop layer, a second semiconductor material layer, a sacrificial gate structure on the at least one stack containing nanosheets, and a hard mask cap on the sacrificial gate structure, wherein at least one stack containing nanosheets comprises alternating recessed sacrificial semiconductor material nanosheets and semiconductor channel material nanosheets.

[0024] Figure 2A and Figure 2B After forming openings into the semiconductor substrate in the logic device region and the MRAM device region, respectively, Figure 1A and Figure 1B A cross-sectional view of an exemplary structure shown in FIG.

[0025] Figure 3A and Figure 3B After forming a blocking mask in the logic device region but not in the MRAM device region and extending the opening depth in the MRAM device region, Figure 2A and Figure 2B A cross-sectional view of an exemplary structure shown in FIG.

[0026] Figure 4A and Figure 4B After removing the blocking mask and forming sacrificial placeholder materials in the openings in the logic device area and in the extended depth openings in the MRAM device area, respectively Figure 3A and Figure 3B A cross-sectional view of an exemplary structure shown in FIG.

[0027] Figure 5A and Figure 5BAfter the sacrificial placeholder material in both the logic device region and the MRAM device region is recessed to provide a logic device region sacrificial placeholder material structure in the logic device region and an MRAM device region sacrificial placeholder material structure in the MRAM device region, respectively. Figure 4A and Figure 4B A cross-sectional view of an exemplary structure shown in FIG.

[0028] Fig. 6A and Figure 6B After forming a source / drain structure and a first interlayer dielectric (ILD) material layer in the logic device region and the MRAM device region, respectively, Figure 5A and Figure 5B A cross-sectional view of an exemplary structure shown in FIG.

[0029] Fig. 7A and Figure 7B After removing the hard mask, sacrificial gate structure and each recessed sacrificial semiconductor material nanosheet of at least one nanosheet-containing material stack in the logic device region and the MRAM device region, forming a functional gate structure surrounding each semiconductor channel material nanosheet of at least one nanosheet-containing stack, forming a second ILD material, forming a front side source / drain contact structure, forming a front side BEOL structure and forming a carrier wafer, Fig. 6A and Figure 6B A cross-sectional view of an exemplary structure shown in FIG.

[0030] Fig. 8A and Figure 8B After the exemplary structure is flipped 180° and the second semiconductor material layer of the semiconductor substrate is removed, Fig. 7A and Figure 7B Cross-sectional view of an exemplary structure shown where removal stops on an etch stop layer of a semiconductor substrate; after flipping, the front side of the wafer is now below the back side of the wafer.

[0031] Fig. 9A and Fig. 9B After removing the etching stop layer and the first semiconductor material layer of the semiconductor substrate to expose a portion of the logic device region sacrificial placeholder material structure in the logic device region and a portion of the MRAM device region sacrificial placeholder material structure in the MRAM device region, respectively, Fig. 8A and Figure 8B A cross-sectional view of an exemplary structure shown in FIG.

[0032] Fig. 10A and Fig. 10B After forming the first backside ILD material layer, Fig. 9A and Fig. 9B A cross-sectional view of an exemplary structure shown in FIG.

[0033] Fig.11A and Fig. 11B After removing the MRAM device region sacrificial placeholder material structure in the MRAM device region to provide an opening that physically exposes the surface of the source / drain structure present in the MRAM device region, respectively, Fig. 10A and Fig. 10B A cross-sectional view of an exemplary structure shown in FIG.

[0034] Fig. 12A and Fig. 12B After forming a precursor MRAM backside source / drain contact structure in the opening existing in the first backside ILD material layer in the MRAM device region, respectively, Fig.11A and Fig. 11B A cross-sectional view of an exemplary structure shown in FIG.

[0035] Fig.13A and Fig. 13B respectively after recessing the precursor MRAM backside source / drain contact structure to provide the MRAM backside source / drain contact structure in a lower portion of the opening in the first backside ILD material layer present in the MRAM device region, Fig. 12A and Fig. 12B A cross-sectional view of an exemplary structure shown in FIG.

[0036] Fig.14A and Fig. 14B After forming a first electrode in an upper portion of an opening existing in a first backside ILD material layer in an MRAM device region and on an MRAM backside source / drain contact structure, respectively, Fig.13A and Fig. 13B A cross-sectional view of an exemplary structure shown in FIG.

[0037] Fig.15A and Fig. 15B After forming the MRAM layered stack in the logic device area and the MRAM device area, Fig.14A and Fig. 14B A cross-sectional view of an exemplary structure shown in FIG.

[0038] Fig.16A and Fig. 16B respectively after patterning the MRAM layered stack using the second electrode formed on the top of the MRAM layered stack in the MRAM device region as an etching mask to provide the MRAM stack in the MRAM device region, Fig.15A and Fig. 15B A cross-sectional view of an exemplary structure in FIG.

[0039] Fig.17A and Fig. 17B After showing the sacrificial placeholder material structure in the logic device area and forming the MRAM spacer laterally adjacent to the second electrode and the MRAM stack Fig.16A and Fig. 16B A cross-sectional view of an exemplary structure is shown.

[0040] Fig.18A and Fig.18B After removing the sacrificial placeholder material structure in the logic device area to expose the source / drain structure in the logic device area, Fig.17A and Fig. 17B A cross-sectional view of an exemplary structure shown in FIG.

[0041] Fig.19A and Fig.19B After forming the logic device backside source / drain contacts on the exposed source / drain structures in the logic device region, Fig.18A and Fig.18B A cross-sectional view of an exemplary structure shown in FIG.

[0042] Fig. 20A and Fig. 20B After forming a backside power rail in the logic device area, forming a second backside ILD material layer in the logic device area and the MRAM device area, forming a contact through hole structure in the logic device area and the MRAM device area, and forming a backside interconnect structure in the logic device area and the MRAM device area. Fig.19A and Fig.19B A cross-sectional view of an exemplary structure shown in FIG. DETAILED DESCRIPTION

[0043] The present application will now be described in more detail by reference to the following discussion and the drawings of the present application. Note that the drawings of the present application are for illustrative purposes only and therefore the drawings are not drawn to scale. It should also be noted that identical and corresponding elements are represented by similar reference numerals.

[0044] In the following description, many specific details, such as specific structures, components, materials, dimensions, processing steps and techniques are set forth to provide an understanding of the various embodiments of the present application. However, it will be appreciated by those of ordinary skill in the art that the various embodiments of the present application can be practiced without these specific details. In other cases, in order to avoid obscuring the present application, well-known structures or processing steps are not described in detail.

[0045] It should be understood that when an element as a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there can be intervening elements. In contrast, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "below" or "under" another element, it can be directly below or under the other element, or there can be intervening elements. In contrast, when an element is referred to as being "directly below" or "directly under" another element, there are no intervening elements.

[0046] First reference Figure 1A and Figure 1B , respectively show exemplary structures in the logic device region 100 and the MRAM device region 102. In the exemplary structure, the logic device region 100 and the MRAM device region 102 are located adjacent to each other and exist at the same level. Figure 1A and Figure 1B The exemplary structure shown in includes at least one stack containing nanosheets located on a semiconductor substrate. The number of stacks containing nanosheets present in both the logic device area 100 and the MRAM device area 102 can vary, and is not limited to three stacks containing nanosheets in each of those device areas. Moreover, the number of stacks containing nanosheets in the logic device area 100 can be equal to, greater than, or less than the number of stacks containing nanosheets present in the MRAM device area 102. Although the present application describes and illustrates the logic device area 100, the present application contemplates embodiments in which the analog device area replaces the logic device area 100 or is used in combination with it. Moreover, although the present application describes the formation of nanosheet field effect transistors (FETs) in two device areas, the present application contemplates embodiments in which the nanosheet FET is replaced by other types of FETs, including but not limited to planar FETs, FinFETs, or semiconductor nanowire FETs.

[0047] The semiconductor substrate present in the logic device region 100 and the MRAM device region 102 includes a first semiconductor material layer 10, an etch stop layer 12, and a second semiconductor material layer 14. There is also a sacrificial gate structure 22 located on at least one stack containing nanosheets, and a hard mask cap 24 located on the sacrificial gate structure 22. At least one stack containing nanosheets contains alternating recessed sacrificial semiconductor material nanosheets 18 and semiconductor channel material nanosheets 20. Figure 1A and Figure 1BThe exemplary structure shown in also includes a bottom dielectric isolation layer 16 located between the second semiconductor material layer 14 of the semiconductor substrate and at least one nanosheet-containing stack in the logic device region 100 and the MRAM device region 102. Moreover, a dielectric spacer 26 is located at a position laterally adjacent to the sacrificial gate structure 22 and the hard mask cap 24 and on top of the at least one nanosheet-containing stack, and an inner spacer 28 is located at a position laterally adjacent to each recessed sacrificial semiconductor material nanosheet 20. The inner spacer 28 has a first sidewall in direct physical contact with the sidewall of the laterally adjacent recessed sacrificial semiconductor material nanosheet 18 and a second sidewall opposite the first sidewall, the second sidewall being substantially vertically aligned to the outermost wall of each semiconductor channel material nanosheet 20 and the outermost wall of the dielectric spacer 26.

[0048] The first semiconductor material layer 10 of the semiconductor substrate is composed of a first semiconductor material having semiconductor properties. Examples of the first semiconductor material that can be used to provide the first semiconductor material layer 10 include, but are not limited to, silicon (Si), silicon germanium (SiGe) alloys, silicon germanium carbide (SiGeC) alloys, germanium (Ge), III / V compound semiconductors, or II / VI compound semiconductors. The second semiconductor material layer 14 is composed of a second semiconductor material. The second semiconductor material providing the second semiconductor material layer 14 may be the same or different in composition from the first semiconductor material providing the first semiconductor material layer 10. In some embodiments of the present application, the etch stop layer 12 may be composed of a dielectric material, such as silicon dioxide and / or boron nitride. In other embodiments of the present application, the etch stop layer 12 is composed of a semiconductor material that is different in composition from the semiconductor material that provides both the first semiconductor material layer 10 and the second semiconductor material layer 14.

[0049] In one example, the first semiconductor material layer 10 is composed of silicon, the etch stop layer 12 is composed of silicon dioxide, and the second semiconductor material layer 14 is composed of silicon. Such a semiconductor substrate including silicon / silicon dioxide / silicon may be referred to as a silicon-on-insulator (SOI) substrate. In another example, the first semiconductor material layer 10 is composed of silicon, the etch stop layer 12 is composed of silicon germanium, and the second semiconductor material layer 14 is composed of silicon. Such a semiconductor substrate including silicon / silicon germanium / silicon may be referred to as a bulk semiconductor substrate.

[0050] As described above, at least one nanosheet-containing stack includes alternating recessed sacrificial semiconductor material nanosheets 18 and semiconductor channel material nanosheets 20. At least one nanosheet-containing stack includes "n" semiconductor channel material nanosheets 20 and "n or n+1" recessed sacrificial semiconductor material nanosheets 18; the "n+1" embodiment is not shown. In the illustrated embodiment, at least one nanosheet-containing stack includes "n" recessed sacrificial semiconductor material nanosheets 18 and "n" semiconductor channel material nanosheets 20. As an example, at least one nanosheet-containing stack includes three semiconductor channel material nanosheets 20 and three recessed sacrificial semiconductor material nanosheets 18.

[0051] Each recessed sacrificial semiconductor material nanosheet 18 is composed of a third semiconductor material, and each semiconductor channel material nanosheet 20 is composed of a fourth semiconductor material having a composition different from the third semiconductor material. In some embodiments, the semiconductor channel material nanosheet 20 is composed of a fourth semiconductor material capable of providing a high channel mobility for an NFET device. In other embodiments, the semiconductor channel material nanosheet 20 is composed of a fourth semiconductor material capable of providing a high channel mobility for a PFET device.

[0052] The third semiconductor material providing each recessed sacrificial semiconductor material nanosheet 18 and the fourth semiconductor material providing each semiconductor channel material nanosheet 20 may include one of the semiconductor materials described above for the first semiconductor material layer 10. In one example, the third semiconductor material providing each recessed sacrificial semiconductor material nanosheet 18 is composed of a silicon-germanium alloy, and the fourth semiconductor material providing each semiconductor channel material nanosheet 20 is composed of silicon.

[0053] Each recessed sacrificial semiconductor material nanosheet 18 has a first width, and each semiconductor channel material nanosheet 20 has a second width greater than the first width. In one example, the first width is 10nm to 100nm, and the second width is 20nm to 130nm. Each recessed sacrificial semiconductor material nanosheet 18 and each semiconductor channel material nanosheet 20 have the same length. In one example, the length of each recessed sacrificial semiconductor material nanosheet 18 and each semiconductor channel material nanosheet 20 is 10nm to 130nm. The vertical height of each recessed sacrificial semiconductor material nanosheet 18 and semiconductor channel material nanosheet 20 is in the range of 4nm to 20nm. The vertical height of each recessed sacrificial semiconductor material nanosheet 18 can be equal to, greater than, or less than the vertical height of each semiconductor channel material nanosheet 20.

[0054] The sacrificial gate structure 22 includes at least a sacrificial gate material. In some embodiments, the sacrificial gate structure 22 may include a sacrificial gate dielectric material. The sacrificial gate dielectric material may be composed of a dielectric material such as silicon dioxide. The sacrificial gate material may include, but is not limited to, polycrystalline silicon, amorphous silicon, amorphous silicon germanium, tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, platinum, or alloys of these metals.

[0055] The hard mask cap 24 may be formed of a hard mask material, such as silicon dioxide, silicon nitride, silicon oxynitride, or any multi-layer combination thereof. In some embodiments, the hard mask cap 24 may also be omitted.

[0056] The dielectric spacer 26 is composed of a gate spacer dielectric material. Examples of gate spacer dielectric materials that may be used to provide the dielectric spacer 26 include, but are not limited to, SiN, SiBCN, SiOCN, or SiOC.

[0057] The bottom dielectric spacer 16 is composed of one of the gate spacer dielectric materials described above for the dielectric spacer 26. The bottom dielectric spacer 16 and the dielectric spacer 26 are formed simultaneously, so they are composed of the same composition of the gate spacer dielectric material. The bottom dielectric spacer 16 can have a thickness from 5 nm to 50 nm; although other thicknesses of the bottom dielectric spacer 16 are contemplated and can be used as the thickness of the bottom dielectric spacer 16.

[0058] The inner spacer 28 is composed of one of the gate spacer dielectric materials described above for the dielectric spacer 26. The gate spacer dielectric material providing the inner spacer 28 may be the same as or different in composition from the gate dielectric spacer material providing the dielectric spacer 26.

[0059] Figure 1A and Figure 1B The exemplary structure shown in can be formed using conventional nanosheet stacking processes well known to those skilled in the art. In one example, Figure 1A and Figure 1BThe exemplary structure shown in can be formed by first forming a sacrificial placeholder material layer (not shown) on the surface of the second semiconductor material layer 14 of the semiconductor substrate, which also includes the etch stop layer 12 and the first semiconductor material layer 10. The sacrificial placeholder material layer can include a semiconductor material that is different in composition from the second semiconductor material providing the second semiconductor material layer 14, the third semiconductor material providing each recessed sacrificial semiconductor material nanosheet 18, and the fourth semiconductor material providing each semiconductor channel material nanosheet 20. The formation of the placeholder material layer can include an epitaxial growth process or any other deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or evaporation. After forming the placeholder material layer, a material stack of alternating layers of the third and fourth semiconductor material layers is formed by epitaxial growth or one of the deposition processes described above for forming the placeholder material. Then, photolithography and etching can be used to pattern the material stack and the placeholder material layer into a multilayer material structure, which includes the remaining portion of the placeholder material layer and the remaining portion of the material stack.

[0060] The term "epitaxial growth" or "epitaxial growth" refers to the growth of a second semiconductor material on the growth surface of a first semiconductor material, wherein the grown second semiconductor material has the same crystal properties as the first semiconductor material. In the epitaxial deposition process, the chemical reactants provided by the source gas are controlled and the system parameters are set so that the deposited atoms arrive at the growth surface of the first semiconductor material with sufficient energy to move back and forth on the growth surface and orient themselves to the crystal arrangement of the atoms on the growth surface. Examples of various epitaxial growth process equipment that can be used in the present application include, for example, rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD) and molecular beam epitaxy (MBE). The temperature used for epitaxial deposition is generally in the range of 550°C to 900°C. Although higher temperatures generally result in faster deposition, faster deposition may result in crystal defects and film rupture.

[0061] A sacrificial gate structure 22 and a hard mask 24 are then formed on the multilayer material by depositing a sacrificial gate dielectric material (if present), a capping layer of a sacrificial gate material, and a dielectric hard mask material. The deposition of the dielectric hard mask material, the sacrificial gate material, and the capping layer of the sacrificial gate dielectric material (if present) includes, but is not limited to, CVD, PECVD, PVD, ALD, or any combination of these deposition processes. After forming these capping layers, a patterning process (including photolithography and etching) is used to convert the capping layer of the hard mask material into a hard mask 24, and the capping layer of the sacrificial gate dielectric material (if present) and the capping layer of the sacrificial gate dielectric material into a sacrificial gate structure 22. Etching may include dry etching and / or wet chemical etching. Dry etching may include reactive ion etching (RIE), plasma etching, or ion beam etching (IBE). Multiple such sacrificial gate structures 22 covered with a hard mask cap 24 may be formed in each of the logic device area 100 and the MRAM device area 102.

[0062] Next, the placeholder material layer present in the multilayer material stack is removed using an etching process that is selective in removing the placeholder material layer. A space (or gap) is formed between the bottommost sacrificial semiconductor material layer and the second semiconductor material layer 14 of the multilayer material stack. The structure is not free floating, but is held in place by the sacrificial gate structure 22. Next, a dielectric spacer 26 and a bottom dielectric isolation layer 16 are formed simultaneously. It is noteworthy that the dielectric spacer 26 and the bottom dielectric isolation layer 16 are formed by depositing a gate dielectric spacer material and then performing a spacer etching. The deposit fills the gap and forms the bottom dielectric isolation layer 16. In an embodiment, the dielectric spacer 26 can be I-shaped and have a top surface that is coplanar with the top surface of the hard mask cap 24.

[0063] After forming the dielectric spacers 22 and the bottom dielectric isolation layer 16, the multilayer material stack including alternating layers of the third and fourth semiconductor materials is etched, wherein the hard mask cap 24 / gate structure 22 and the dielectric spacers 26 serve as an etching mask. The etching stops on the bottom dielectric isolation layer 16. In the present application, the unetched (i.e., remaining) portion of each sacrificial semiconductor material layer is referred to as a sacrificial semiconductor material nanosheet, and the unetched (i.e., remaining) portion of each semiconductor channel material layer is referred to as a semiconductor channel material nanosheet 20.

[0064] Next, inner spacers 28 are formed. The inner spacers 28 are formed by first recessing each sacrificial semiconductor material nanosheet to form an inner spacer gap adjacent to the end of each recessed sacrificial semiconductor material nanosheet 18. After this recessing step, the remaining (i.e., recessed) sacrificial semiconductor material nanosheet 18 has a lateral width that is reduced compared to the width of the original sacrificial semiconductor material nanosheet. The recessing includes a lateral etching process that selectively removes the sacrificial semiconductor material nanosheet relative to the semiconductor channel material nanosheet 20. Next, the inner spacers 28 are formed in the inner spacer gaps by conformal deposition of a spacer dielectric material followed by isotropic etching.

[0065] Reference now Figure 2A and Figure 2B , respectively, show the openings 32 after forming the openings 32 into the semiconductor substrate in the logic device region 100 and the MRAM device region 102. Figure 1A and Figure 1B The openings 32 formed in the logic device region 100 and the MRAM device region 102 may be formed by photolithography and etching. The photolithography step may include forming a patterned mask layer 30 having an opening therein that physically exposes a surface of the bottom dielectric isolation layer 16 in a region between two adjacent nanosheet stacks, such as Figure 2A and Figure 2B As shown. The patterned mask layer 30 may include an organic planarization layer (OPL). Etching may include dry etching and / or chemical etching. Physically exposed portions of the dielectric isolation layer 16 are removed and stopped within the sub-surface of the second dielectric material layer 14. The term "sub-surface" refers to the surface of a structure located between the topmost surface and the bottommost surface of the same structure. At this point in the present application, the opening 32 formed in each of the logic device area 100 and the MRAM device area 102 extends a first depth D1 below the topmost surface of the second dielectric material layer 14. After forming the opening 32 having the first depth D1, the patterned mask layer 30 is removed from the structure using one or more material removal processes.

[0066] Reference now Figure 3A and Figure 3B , respectively, show the block mask 31 formed in the logic device region 100 instead of the MRAM device region 102, and the depth of the opening 32 in the MRAM device region 102 is extended. Figure 2A and Figure 2BThe exemplary structure shown in . Extending the depth of the opening 32 in the MRAM device area 102 provides an extended depth opening 32E in the MRAM device area 102. The blocking mask 31 may include an OPL formed by deposition and photolithographic patterning. Extending the depth of the opening 32 in the MRAM device area 102 includes an etching process to form the opening 32 as described above. The extended depth opening 32E extends a second depth D2, located below the topmost surface of the second dielectric material layer 14 in the MRAM device area 102. In the present application, D2 is greater than D1. In one example, D2 is approximately 90nm and D1 is approximately 50nm; here, the term "approximately" means ±10% of the value.

[0067] Reference now Figure 4A and Figure 4B , respectively, after removing the blocking mask 31 and forming a sacrificial placeholder material 34 in the opening 32 in the logic device region 100 and in the extended depth opening 32E in the MRAM device region 102 Figure 3A and Figure 3B The exemplary structure shown in . The block mask 31 is removed from the logic device area 100 using one or more material removal processes. The sacrificial placeholder material 34 includes a metal oxide, such as TiOx or AlOx; a metal nitride, such as TiN or TaN; or a dielectric material, such as SiCO or SiC or a combination of a SiN liner and a SiO2 filler. The sacrificial placeholder material 34 can be formed by a deposition process, such as CVD, PECVD, ALD, PVD, or spin coating. The sacrificial placeholder material 34 fills the opening 32 in the logic device area 100 and the extended depth opening 32E in the MRAM device area 102, and is formed on top of each of the hard mask-covered sacrificial gate structures present in both the logic device area 100 and the MRAM device area 102.

[0068] Reference now Figure 5A and Figure 5B , respectively, after the sacrificial placeholder material 34 in the logic device region 100 and the MRAM device region 102 is recessed to provide a logic device region sacrificial placeholder material structure 34S in the logic device region 100 and an MRAM device region sacrificial placeholder material structure 35S in the MRAM device region 102 Figure 4A and Figure 4B The exemplary structure shown in FIG. The recessing of the sacrificial placeholder material 34 in the logic device region 100 and the MRAM device region 102 includes an etch-back process that is selective when removing the sacrificial placeholder material 34. Figure 5BAs shown, the MRAM device region sacrificial placeholder material structure 35S extends deeper into the second semiconductor material layer 14 than the logic device region sacrificial placeholder material structure 34S. It is noteworthy that the MRAM device region sacrificial placeholder material structure 35S extends a second depth D2 below the topmost surface of the second dielectric material layer 14 in the MRAM device region 102, while the logic device region sacrificial placeholder material structure 34S extends a first depth D1 below the topmost surface of the second dielectric material layer 14 in the logic device region 100.

[0069] Reference now Fig. 6A and Figure 6B , respectively, after forming a source / drain structure 36 and a first interlayer dielectric (ILD) material layer 38 in the logic device region 100 and the MRAM device region 102. Figure 5A and Figure 5B . As used herein, a "source / drain or S / D" structure can be a source region or a drain region, depending on the subsequent wiring and the voltage application during the operation of the field effect transistor (FET). Each source / drain structure 36 is composed of a semiconductor material and a dopant. The semiconductor material providing the source / drain structure 36 may include one of the semiconductor materials described above for the first semiconductor material layer 10. The semiconductor material providing the source / drain structure 36 may be the same or different in composition from each semiconductor channel material nanosheet 20. However, the semiconductor material providing the source / drain structure 36 is different in composition from each recessed sacrificial semiconductor material nanosheet 18. The dopant present in the source / drain structure 36 may be a p-type dopant or an n-type dopant. The term "p-type" refers to the addition of impurities to an intrinsic semiconductor, resulting in a lack of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, phosphorus, and indium. "N-type" refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus. In one example, the source / drain structure 36 may have a 4×10 20 Atom / cm 3 Up to 3×10 21 Atom / cm 3 In one example, the bottom source / drain structure 36 is composed of silicon doped with phosphorus.

[0070] The source / drain structure 36 may be formed by an epitaxial growth process and formed on both sides of at least one nanosheet-containing material stack. The source / drain structure 36 grows outward from the physically exposed sidewalls of each semiconductor channel material nanosheet 20. In the logic device region 100, and as Fig. 6AAs shown, one of the source / drain structures 36 is grown on top of the logic device region sacrificial placeholder material structure 34S, while the other source / drain structure 26 is grown on top of the bottom dielectric isolation layer 16. In the MRAM device region 102, and as shown in FIG. Figure 6B As shown, one of the source / drain structures 36 is grown on top of the MRAM device region sacrificial placeholder material structure 35S, while the other source / drain structure 26 is grown on top of the bottom dielectric isolation layer 16. The dopants as defined above are typically present by implantation during or after the epitaxial growth process. A recess etch may be used to reduce the height of the source / drain structure 36 so that it does not extend above the sacrificial gate structure 22.

[0071] The ILD material layer 38 may be made of a dielectric material, including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. The term "low-k" used throughout this application means a dielectric material having a dielectric constant less than 4.0 (unless otherwise specified, all dielectric constants mentioned herein are relative to vacuum). Although not shown, the ILD material layer 38 may include a multilayer structure including at least two different dielectric materials, one of which is stacked on top of another, such as silicon nitride and silicon dioxide. The ILD material layer 38 may be formed by a deposition process, such as CVD, PECVD, or spin coating. A planarization process (including, for example, chemical mechanical polishing (CMP)) is typically performed after the deposition of the dielectric material providing the ILD material layer 38. The planarization process removes the upper portions of the hard mask cap 24 and the dielectric spacer 26 and provides structures in the logic device region 100 and the MRAM device region 102 where the ILD material layer 38 has a top surface coplanar with the top surface of the sacrificial gate structure 22. As shown, the ILD material layer 38 is located on top of each source / drain structure 36.

[0072] Reference now Fig. 7A and Figure 7B , respectively, after removing the sacrificial gate structure 22 of at least one nanosheet-containing material stack and each recessed sacrificial semiconductor material nanosheet 18 in the logic device region 100 and the MRAM device region 102, forming a functional gate structure 40 surrounding each semiconductor channel material nanosheet 20 of at least one nanosheet-containing stack, forming a second ILD material layer, forming a front side source / drain contact structure 44, forming a front side BEOL structure 46, and forming a carrier wafer 48, Fig. 6A and Figure 6BIn the present application, the combination of the first ILD material layer 38 and the second ILD material layer may be referred to as a front-side ILD material layer 42 .

[0073] The sacrificial gate structure 22 and the recessed sacrificial semiconductor material nanosheet 18 are removed by utilizing a first etching process that selectively removes the sacrificial gate structure 22 and a second etching process that selectively removes the recessed sacrificial semiconductor material nanosheet 18 relative to the semiconductor channel material nanosheet 20. For example, the second etching can be used to selectively remove SiGe sacrificial semiconductor material nanosheets relative to Si semiconductor channel material nanosheets. The removal of the recessed sacrificial semiconductor material nanosheet 18 provides a suspended semiconductor channel material nanosheet 20 in each nanosheet-containing material stack. The removal of the sacrificial gate structure 22 and the recessed sacrificial semiconductor material nanosheet 18 provides gate openings above and below each suspended semiconductor channel material nanosheet 20 of the nanosheet-containing material stack.

[0074] A functional gate structure 40 is then formed in each gate opening. A source / drain structure 36 is located on each side of the functional gate structure 40. The functional gate structure 40 includes at least a gate dielectric material layer and a gate electrode; the gate dielectric material layer and the gate electrode are not shown separately in the drawings of the present application. The functional gate structure 40 surrounds the semiconductor channel material nanosheet 20, such as Fig. 7A and Figure 7B As is known, the gate dielectric material layer of the functional gate structure 40 is in direct contact with the physically exposed portion of each semiconductor channel material nanosheet 20, and the gate electrode is located on the gate dielectric material layer. In some embodiments, the gate structure includes a work function metal (WFM) layer (not shown) located between the gate dielectric material layer and the gate electrode. In some embodiments, an optional gate cap (also not shown) can be formed on top of the functional gate structure 40.

[0075] The formation of the functional gate structure 40 includes forming a continuous layer of gate dielectric material and a gate electrode material inside the gate opening. The continuous layer of gate dielectric material may include silicon oxide or a dielectric material having a dielectric constant greater than 4.0 (such dielectric materials may be referred to as high-k gate dielectric materials). Illustrative examples of high-k gate dielectric materials include metal oxides such as hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), zirconium silicon oxynitride (ZrSiOxNy), tantalum oxide (TaOx), titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc, Ta)O3) and / or lead zinc niobium (Pb(Zn, Nb)O). The high-k gate dielectric material may also include dopants such as lanthanum (La), aluminum (Al) and / or magnesium (Mg). The continuous layer of gate dielectric material may be formed using a deposition process such as ALD, CVD, PECVD or PVD. The continuous layer of gate dielectric material is a conformal layer and may have a thickness ranging from 1 nm to 10 nm.

[0076] The gate electrode material may include a conductive metal-containing material, including but not limited to tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), zirconium (Zr), cobalt (Co), copper (Cu), aluminum (Al), lead (Pb), platinum (Pt), tin (Sn), silver (Ag) or gold (Au), tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaCX), titanium carbide (TiC), titanium aluminum carbide, tungsten silicide (WSi2), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide or nickel silicide. The gate electrode material may be formed using a deposition process such as ALD, CVD, PECVD, PVD, electroplating or sputtering. In some embodiments of the present application, after the conductive metal-containing material deposition has been performed, a reflow annealing or a silicide annealing may be used.

[0077] In some embodiments, a WFM (work function metal) layer may be formed on the continuous layer of gate dielectric material before forming the gate electrode material. In other embodiments, the gate electrode is composed only of WFM. The WFM layer can be used to set the threshold voltage of the FET to a desired value. In some embodiments, the WFM layer can be selected to achieve an n-type threshold voltage shift. As used herein, "n-type threshold voltage shift" means the shift of the effective work function of the work function metal-containing material toward the conduction band of silicon in the silicon-containing material. In one embodiment, the work function of the n-type work function metal is 4.1eV-4.3eV. Examples of such materials that can achieve an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or a combination thereof. In other embodiments, the WFM layer can be selected to achieve a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal is in the range of 4.9eV to 5.2eV. As used herein, "threshold voltage" is the lowest achievable gate voltage that will turn on a semiconductor device (e.g., a transistor) by turning on the channel of the device. As used herein, the term "p-type threshold voltage shift" refers to a shift of the effective work function of a material containing a work function metal toward the valence band of silicon in a silicon-containing material. Examples of such materials that can achieve a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof. The WFM layer is a conformal layer that can be formed by a conformal deposition process such as ALD, CVD, or PECVD. The layer of the WFM layer can have a thickness in the range of 1 nm to 20 nm, although other thicknesses above or below this range can be used as required for a specific application.

[0078] After forming the continuous layer of gate dielectric material, the optional WFM layer, and the gate electrode material, the continuous layer of gate dielectric material, the optional WFM layer, and the gate electrode material are removed from outside the gate opening using a planarization process such as chemical mechanical polishing (CMP). The remaining continuous layer of gate dielectric material present inside the gate opening can be referred to as a gate dielectric material layer, the remaining optional layer of WFM present inside the gate opening can be referred to as a WFM layer, and the remaining gate electrode material present inside the gate opening provides a gate electrode of the functional gate structure 40.

[0079] When present, the gate cap may be composed of a hard mask material, such as silicon dioxide or silicon nitride with or without an air gap, or the gate cap may be composed of an air gap only. The gate cap may be formed by a deposition process followed by a planarization process. In embodiments employing a gate cap, the topmost portion of the functional gate structure 40 may be recessed prior to forming the gate cap. In the present application, the top surface of the functional gate structure 40 or the gate cap (if present) is coplanar with the top surface of the first ILD material layer 38.

[0080] A second ILD material layer is formed on top of the first ILD material layer 38 and on top of the topmost surface of each functional gate structure 40. The second ILD material layer may include one of the dielectric materials described above for the first ILD material layer 38. The dielectric material providing the second ILD material layer may be the same or different in composition from the dielectric material providing the first ILD material layer 38. Likewise, the combination of the first ILD material layer 38 and the second ILD material layer provides Fig. 7A and Figure 7B The front side ILD material layer 42 is shown in FIG. The second ILD material layer may be formed using one of the deposition processes described above for forming the first ILD material layer 38 .

[0081] A front side source / drain contact structure 44 is then formed in each of the logic device region 100 and the MRAM device region 102. Fig. 7A As shown, the front side source / drain contact structure 44 in the logic device region 100 extends completely through the front side ILD material layer 42 and directly contacts the surface of one of the source / drain structures 36 located on top of the bottom dielectric isolation layer 16. Figure 7B As shown, the front side source / drain contact structure 44 in the MRAM device area 102 extends completely through the front side ILD material layer 42 and directly contacts the surface of one of the source / drain structures 36 located on the top of the bottom dielectric isolation layer 16. Each front side source / drain contact structure 44 may include a contact conductor material of the same or different composition. The contact conductor material may include a conductive metal, such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh or an alloy thereof. In an embodiment, each front side source / drain contact structure 44 may also include a silicide liner such as TiSi, NiSi, NiPtSi, etc. and an adhesion metal liner such as TiN. The contact conductor material may be formed by any suitable deposition method, such as ALD, CVD, PVD or electroplating. Each front side source / drain contact structure may be formed by forming a trench in the front side ILD material layer 42, which physically exposes the surface of the source / drain structure 36 located on the top of the bottom dielectric isolation layer 16. Each trench is then filled with a contact conductor material and then planarized to remove any contact conductor material located outside the trench.

[0082] In some embodiments (not shown), a metal semiconductor alloy region may be formed in each trench that physically exposes the source / drain structure 36 located on top of the bottom dielectric isolation layer 16. The metal semiconductor alloy region may be composed of silicide or germanide. In one or more embodiments of the present application, the metal semiconductor alloy region may be formed by first depositing a metal layer (not shown) in the trench. The metal layer may include a metal, such as Ni, Co, Pt, W, Ti, Ta, a rare earth metal (e.g., Er, Yt, La), an alloy thereof, or any combination thereof. The metal layer may be deposited by ALD, CVD, PVD, or ALD. The thickness of the metal layer may be 2nm to 10nm, although a smaller or larger thickness may also be used. Then, a diffusion barrier layer (not shown), such as TiN or TaN, may be formed on the metal layer. An annealing process may then be performed at an elevated temperature to cause a reaction of the semiconductor material of the source / drain structure 26, thereby providing a metal semiconductor alloy region. Then, the unreacted portion of the metal layer is removed, for example, by an etching process (or multiple etching processes), and the diffusion barrier layer is removed if present. In one embodiment, the etching process may be a wet etch that selectively removes metal in the metal layer relative to the metal semiconductor alloy in the metal semiconductor alloy region.

[0083] Each front side source / drain contact structure 44 may include one or more source / drain contact liners (not shown) formed along the sidewalls of the trench before forming the front side source / drain contact structure 44. In one or more embodiments, the contact liner (not shown) may include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. The contact liner may be formed using a conformal deposition process including CVD or ALD. The formed contact liner may have a thickness ranging from 1 nm to 5 nm, but a smaller or larger thickness may also be used.

[0084] The front side BEOL structure 46 includes one or more interconnect dielectric material layers contacting one or more wiring regions embedded thereon. The front side BEOL structure 46 can be formed using BEOL processing techniques well known to those skilled in the art. The carrier wafer 48 can include one of the semiconductor materials described above for the first semiconductor material layer 10. In the present application, the carrier wafer 48 is typically bonded to the front side BEOL structure 46 after the front side BEOL structure 46 has been formed on the front side ILD material layer 42. Fig. 7A and Figure 7BAs shown, each front side source / drain contact structure 44 has a first surface directly contacting a surface of the front side BEOL structure 46 and a second surface opposite the first surface directly contacting the source / drain structure 36 located on top of the bottom dielectric isolation layer 16 .

[0085] Reference now Fig. 8A and Figure 8B , respectively show the structure after the exemplary structure is flipped 180° and the second semiconductor material layer 14 of the semiconductor substrate is removed. Fig. 7A and Figure 7B , where the removal stops on the etch stop layer 12 of the semiconductor substrate. The flipping of the structure can be performed by hand or by using a mechanical device such as a robot arm. The removal of the second semiconductor material layer 14 can be performed using any material removal process, such as etching that is selective when removing the first semiconductor material layer 14.

[0086] Reference now Fig. 9A and Fig. 9B , respectively, after removing the etching stop layer 12 and the first semiconductor material layer 10 of the semiconductor substrate to expose a portion of the logic device region sacrificial placeholder material structure 34S in the logic device region 100 and a portion of the MRAM device region sacrificial placeholder material structure 35S in the MRAM device region 102 Fig. 8A and Figure 8B The exemplary structure shown in . The removal of the etch stop layer 12 and the first semiconductor material layer 10 can be performed using one or more material removal processes that selectively remove the etch stop layer 12 and the first semiconductor material layer 10 relative to the logic device area sacrificial placeholder material structure 34S, the MRAM device area sacrificial placeholder material structure 35S, and the bottom dielectric isolation layer 16. In one example, the etch stop layer 12 is removed using a first etch, and the first semiconductor material layer 10 is removed using a second etch different from the first etch.

[0087] Reference now Fig. 10A and Fig. 10B , respectively show the first backside ILD material layer 50 after forming Fig. 9A and Fig. 9B The exemplary structure shown in FIG. The backside ILD material layer 50 includes one of the dielectric materials mentioned above for the first ILD material layer 38. The backside ILD material layer 50 can be formed using one of the deposition processes for forming the first ILD material layer 38 described above. The planarization process can be performed after the deposition process to expose the MRAM device region sacrificial placeholder material structure 35S in the MRAM device region 102, see FIG. Fig. 10B .like Fig. 10AAs shown, no portion of the logic device area sacrificial placeholder material structure 34S is exposed.

[0088] Reference now Fig.11A and Fig. 11B , respectively, show the MRAM device region sacrificial placeholder material structure 35S in the MRAM device region 102 after removing it to provide the opening 52 Fig. 10A and Fig. 10B , the opening physically exposes the surface of the source / drain structure 36 present in the MRAM device region 102. The physically exposed source / drain structure 36 is located on a side of the functional gate structure 40 that is opposite to the side of the functional gate structure 40 that includes the source / drain structure 36 connected to the front side source / drain contact structure 44. In other words, the opening 52 physically exposes the source / drain structure 36 on the opposite side of the side of the material stack containing the nanosheet that includes the source / drain contact structure 44 that contacts the source / drain structure 36 on the side of the material stack containing the nanosheet. The removal of the MRAM device region sacrificial placeholder material structure 35S in the MRAM device region 102 includes an etching process, such as reactive ion etching, which is selective in removing the MRAM device region sacrificial placeholder material structure 35S in the MRAM device region 102.

[0089] Reference now Fig. 12A and Fig. 12B , respectively, show the formation of a precursor MRAM backside source / drain contact structure 54 in the opening 52 present in the first backside ILD material layer 50 in the MRAM device region 102 Fig.11A and Fig. 11B The precursor MRAM backside source / drain contact structure 54 is composed of the materials used for the frontside source / drain contact structure 44 as described above, and the precursor MRAM backside source / drain contact structure 54 can be formed using the above-mentioned process in forming the frontside source / drain contact structure 44. The precursor MRAM backside source / drain contact structure 54 has an uppermost surface that is coplanar with the uppermost surface of the first backside ILD material layer 50.

[0090] Reference now Fig.13A and Fig. 13B , respectively, after the precursor MRAM backside source / drain contact structure 54 is recessed to provide an MRAM backside source / drain contact structure 54S in a lower portion of the opening 52 present in the first backside ILD material layer 50 in the MRAM device region 102, Fig. 12A and Fig. 12B. The recessing of the precursor MRAM backside source / drain contact structure 54 includes any recess etching process that has selectivity when removing the material that provides the precursor MRAM backside source / drain contact structure 54. The MRAM backside source / drain contact structure 54S has a first surface that extends below the bottom dielectric isolation layer 16 and contacts the surface of the source / drain region 36, and a second surface opposite the first surface that is located between the bottommost surface and the topmost surface of the first backside ILD material layer 50.

[0091] Reference now Fig.14A and Fig. 14B , respectively showing the upper portion of the opening 52 existing in the first backside ILD material layer 50 in the MRAM device region 102, and after the first electrode 56 is formed on the MRAM backside source / drain contact structure 54. Fig.13A and Fig. 13B . The first electrode 56 has a top surface coplanar with the top surface of the first backside ILD material layer 50. The first electrode 56 has an outermost wall substantially aligned with the outermost wall of the MRAM backside source / drain contact structure 54S and the source / drain structure 36 directly below the MRAM backside source / drain contact structure 54S. It is noteworthy that the first electrode 52, the MRAM backside source / drain contact structure 54S and the source / drain structure 36 directly below the MRAM backside source / drain contact structure 54S are self-aligned. The first electrode 56 is composed of a conductive material, such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN or any combination thereof. The first electrode 56 can be formed by deposition of a conductive material (including but not limited to CVD, PECVD or ALD), followed by a planarization process. The first electrode 56 will serve as one of the electrodes of the MRAM formed in the MRAM device region 102.

[0092] Reference now Fig.15A and Fig. 15B , respectively, after forming the MRAM layered stack 58 in both the logic device region 100 and the MRAM device region 102 Fig.14A and Fig. 14B . The MRAM layered stack 58 includes at least a magnetic reference layer, a tunnel barrier layer, and a magnetic free layer. In some embodiments, the MRAM layered stack 58 includes a magnetic reference layer, a tunnel barrier layer, and a magnetic free layer from bottom to top. In other embodiments, the MRAM layered stack 58 includes a magnetic reference layer, a tunnel barrier layer, and a magnetic free layer from bottom to top. Other known MRAM material layers may be formed in the MRAM layered stack 58.

[0093] The magnetic reference layer has a fixed magnetization. The magnetic reference layer may be composed of a metal or metal alloy (or a stack thereof) including one or more metals exhibiting high spin polarization. In alternative embodiments, exemplary metals for forming the magnetic reference layer include iron, nickel, cobalt, chromium, boron, or manganese. Exemplary metal alloys may include the metals exemplified above. In another embodiment, the magnetic reference layer may be a multilayer arrangement having (1) a high spin polarization region formed by metals and / or metal alloys using the above metals, and (2) a region constructed of one or more materials exhibiting strong perpendicular magnetic anisotropy (strong PMA). Exemplary materials with strong PMA that can be used include metals such as cobalt, nickel, platinum, palladium, iridium, or ruthenium, and may be arranged as alternating layers. Strong PMA regions may also include alloys exhibiting strong PMA, exemplary alloys including cobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum, cobalt-platinum, cobalt-palladium, iron-platinum, and / or iron-palladium. The alloys may be arranged as alternating layers. In one embodiment, combinations of these materials and regions may also be used. The thickness of the magnetic reference layer will depend on the material selected. In one example, the magnetic reference layer may have a thickness from 0.3 nm to 3 nm.

[0094] The tunnel barrier layer is composed of an insulator material and is formed with a thickness that provides an appropriate tunnel resistance. Exemplary materials for the tunnel barrier layer include magnesium oxide, aluminum oxide, and titanium oxide, or a material with a higher electrical tunnel conductance, such as a semiconductor or a low bandgap insulator. The thickness of the tunnel barrier layer will depend on the material selected. In one example, the tunnel barrier layer can have a thickness from 0.5 nm to 1.5 nm.

[0095] The magnetic free layer can be composed of a magnetic material (or a stack of magnetic materials) having a magnetization that can change its orientation relative to the magnetization orientation of the magnetic reference layer. Exemplary magnetic materials for the magnetic free layer include alloys and / or multilayers of cobalt, iron, cobalt-iron alloys, nickel, nickel-iron alloys, and cobalt-iron-boron alloys. The thickness of the magnetic free layer will depend on the material selected. In one example, the magnetic free layer can have a thickness from 0.3 nm to 3 nm.

[0096] The MRAM layer stack 58 may be formed using one or more deposition processes, such as electroplating, sputtering, plasma enhanced atomic layer deposition (PEALD), plasma enhanced chemical vapor deposition (PECVD), or PVD.

[0097] Reference now Fig.16A and Fig. 16B, respectively illustrate that after the MRAM layered stack 58 is patterned using the second electrode 60 formed on the top of the MRAM layered stack 58 in the MRAM device region 102 as an etching mask to provide the MRAM stack 58S in the MRAM device region 102, Fig.15A and Fig. 15B The first electrode 56, the MRAM stack 58S, and the top electrode 60 together provide the MRAM. In some embodiments, as Fig. 16B As shown, the width of the top electrode 60 and the MRAM stack 58S is greater than the width of the first electrode 56. Fig. 16B As further shown, a portion of the MRAM stack 56 extends beyond the width of the bottom electrode 56, and the extended portion of the MRAM stack 56 is located on the mesa region of the first backside ILD material layer 50. The second electrode 60 has an outermost sidewall substantially vertically aligned with the outermost edge of the MRAM stack 58S.

[0098] The patterning of the MRAM layered stack 58 includes: forming a capping layer for the bottom electrode 56 composed of one of the above conductive materials on the MRAM layered stack 58 through a deposition process. After forming the capping layer for the bottom electrode 56 composed of one of the above conductive materials, the capping layer can be patterned into the second electrode 60 using photolithography and etching. The second electrode 60 only exists in the MRAM device region 102; Fig.16A As shown, the capping layer formed in the logic device area 100 is completely removed. The patterned resist used to pattern the second electrode 60 can be removed by ashing, and then pattern transfer etching (e.g., plasma etching or ion beam etching) is used to pattern the MRAM layered stack 58. During the pattern transfer etching, the portion of the MRAM layered stack 58 that is not protected by the second electrode 60 is removed. Moreover, the pattern transfer etching can remove a portion of the first backside ILD material layer 50; in the MRAM device area, the pattern transfer etching can form a mesa region in the first backside ILD material layer 50, such as Fig. 16B Note that no re-sputtering of metal ions occurs in the MRAM device region 102 because the first electrode 56 and the MRAM backside source / drain contact structure 54S remain embedded in the first backside ILD material layer 50. Also, no re-sputtering of metal ions occurs from the sacrificial placeholder material structure 34S in the logic device region 100 because the sacrificial placeholder material structure 34S remains embedded in the first backside ILD material layer 50.

[0099] Reference now Fig.17A and Fig. 17B , respectively, show the exposure of the logic device region sacrificial placeholder material structure 34S and the formation of the MRAM spacer 62 laterally adjacent to the second electrode 60 and the MRAM stack 62. Fig.16A and Fig. 16B The exposure of the logic device region sacrificial placeholder material structure 34S includes etching, such as reactive ion etching, which removes the upper portion of the first backside ILD material layer 50. This etching occurs in the logic device region 100 and the MRAM device region 102. In the MRAM device region 102, the etching creates a step in the first backside ILD material layer 50, such as Fig. 17B As shown. The MRAM spacer 62 is composed of a dielectric material. In one example, the MRAM spacer 62 is composed of silicon nitride. In another example, the MRAM spacer 62 may be composed of a dielectric material containing silicon, carbon, and hydrogen atoms. In some embodiments, in addition to carbon atoms and hydrogen atoms, the dielectric material providing the MRAM spacer 62 may include at least one of nitrogen atoms and oxygen atoms. In other embodiments, in addition to silicon, nitrogen, carbon, and hydrogen atoms, the dielectric material providing the MRAM spacer 62 may include boron atoms. In one example, the MRAM spacer 62 may be composed of an nBLOK dielectric material containing silicon, carbon, hydrogen, nitrogen, and oxygen atoms. In another embodiment, the MRAM spacer 62 may be composed of a SiBCN dielectric material containing silicon, boron, carbon, hydrogen, and nitrogen atoms.

[0100] The MRAM spacer 62 can be formed using a deposition process, such as PECVD, PVD or PEALD, followed by spacer etching. The MRAM spacer 62 can have a thickness of 10nm to 200nm. Other thicknesses are also possible and can be used as the thickness of the MRAM spacer 62. As shown, the MRAM spacer 62 has a bottom surface formed on the step region in the first backside ILD material layer 50 and a top surface coplanar with the second electrode 60.

[0101] Reference now Fig.18A and Fig.18B , respectively, show the logic device region sacrificial placeholder material structure 34S in the logic device region 100 after it is removed to expose the source / drain structure 36 present in the logic device region 100 on the side of the material stack including the nanosheets that does not include the front side source / drain contact 44, Fig.17A and Fig. 17B The exemplary structure shown in FIG. The removal of the logic device region sacrificial placeholder material structure 34S includes an etch that selectively removes the logic device region sacrificial placeholder material structure 34S.

[0102] Reference now Fig.19A and Fig.19B , respectively, show the logic device backside source / drain contact structure 64 after forming the exposed source / drain structure 36 in the logic device region 100. Fig.18A and Fig.18BThe logic device back side source / drain contact structure 64 includes the materials described above for the front side source / drain contact structure 44. The logic device back side source / drain contact structure 64 may be formed by deposition, and after deposition, an etch back process may be performed to provide the logic device back side source / drain contact structure 64, such as Fig.19A The logic device backside source / drain contact structure 64 has an outermost sidewall that can be substantially vertically aligned with the outermost surface of the source / drain region 36 in physical contact therewith. According to the present application, the logic device backside source / drain contact structure 64 has a topmost surface located below the bottommost surface of the MRAM spacer 62.

[0103] Reference now Fig. 20A and Fig. 20B , respectively showing the backside power rail 66 formed in the logic device region 100, the second backside ILD material layer formed in the logic device region 100 and the MRAM device region 102, the contact via structure 67 formed in the logic device region 100 and the MRAM device region 100, and the backside interconnect structure 70 formed in the logic device region 100 and the MRAM device region 102. Fig.19A and Fig.19B The exemplary structure shown in .

[0104] The backside power rail 66 is made of a power rail conductive material. Exemplary power rail conductive materials that may be used to provide include, but are not limited to, tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), copper (Cu), platinum (Pt), rhodium (Rh), or palladium (Pd), wherein a thin metal adhesion layer (such as TiN, TaN) is typically formed prior to the deposition of the conductive metal; for clarity, the metal adhesion layer is not separately shown in the drawings of the present application. The backside power rail 66 may be formed by first forming a blocking mask (not shown) in the MRAM device region 102. With the blocking mask in place, the backside power rail 66 is then formed in the logic device region 100 by a deposition process such as CVD, PECVD, PVD, sputtering, or electroplating. The blocking mask is removed after the deposition process. As shown, the logic device backside source / drain contact structure 64 has a first surface in physical contact with the logic device backside source / drain contact 64 and a second surface opposite to the first surface in physical contact with the backside power rail 66.

[0105] A second backside ILD material layer is then formed in the logic device region 100 and the MRAM device region 102. In the logic device region 100, the second backside ILD material layer may be referred to as another ILD material layer 68 because it is spaced apart from the first backside ILD material layer 50. In the MRAM device region, the second backside ILD material layer is formed on the first backside ILD material layer 50 to form an MRAM backside ILD material layer stack 69. The MRAM backside ILD material layer stack 69 extends over the second electrode 60, as shown in FIG. Fig. 20B The second backside ILD material layer may include one of the dielectric materials described above for the first ILD material layer 38 , and it may be formed by the deposition process for providing the first ILD material layer 38 as described above.

[0106] Then, a contact via structure 67 is formed in the logic device area 100 and the MRAM device area 102. Each contact via structure 67 is composed of a conductive metal or a conductive metal alloy. Exemplary conductive materials that can be used to provide the contact via structure 67 include, but are not limited to, copper (Cu), aluminum (Al), tungsten (W), or a Cu-Al alloy. Each contact via structure 67 can be formed by first providing a contact via opening in another ILD material layer 68 and in the MRAM backside ILD material layer stack 69. In the logic device area 100, the contact via opening extends downward through another ILD material layer 68 and physically exposes the surface of the backside power rail 66. In the MRAM device area 102, the contact via opening extends downward through the MRAM backside ILD material layer stack 69 and the upper portion of the second electrode 60 and physically exposes the top surface of the MRAM stack 58S. Next, a conductive material is formed in each contact via opening using a deposition process. A planarization process may be performed after the deposition process. In some embodiments, a diffusion barrier material layer (eg, Ti or Ta) is deposited along the sidewalls of each contact via opening, followed by deposition of a conductive material, and then a planarization process is performed.

[0107] Then, a backside interconnect structure 70 is formed in the logic device area 100 and the MRAM device area 102. The backside interconnect structure 70 includes materials as mentioned above for the front side BEOL structure 46. The backside interconnect structure 70 can be formed using techniques well known in the art. In the logic device area 100, the contact via structure 67 electrically connects the back power rail 66 to the backside interconnect structure 70, while in the logic device area, the contact via structure 67 electrically connects the MRAM to the backside interconnect structure.

[0108] It is worth noting that Fig. 20BA semiconductor structure including an MRAM (first electrode 56, MRAM stack 58S, and second electrode 60) located at an MRAM device region 102 and the back side of the wafer is shown. The structure includes a first back side source / drain contact structure (i.e., an MRAM back side source / drain contact structure 54S) that directly connects the first electrode 56 of the MRAM to the first source / drain structure 36 of the first transistor present in the MRAM device region 102 (i.e., a functional gate structure 40 surrounding a semiconductor channel material nanosheet 20). The logic device region 100 may be positioned laterally adjacent to the MRAM device level and at the same level as the MRAM device region 102.

[0109] Although the present application has been specifically shown and described with reference to the preferred embodiments of the present application, it should be understood by those skilled in the art that the foregoing and other changes may be made in form and detail without departing from the spirit and scope of the present application. Therefore, the present application should not be limited to the exact form and details described and shown, but fall within the scope of the appended claims.

Claims

1. A semiconductor structure comprising: a magnetoresistive random access memory (MRAM) located in a device region and in a back side of a wafer, the MRAM comprising a first electrode, an MRAM stack, and a second electrode; as well as A first backside source / drain contact structure directly connects the first electrode of the MRAM to a first source / drain structure of a first transistor present in the front side of the wafer and in the MRAM device region. 2 . The semiconductor structure of claim 1 , wherein the first backside source / drain contact structure has an outermost wall that is substantially vertically aligned with an outermost wall of the first electrode. 3 . The semiconductor structure of claim 2 , wherein an outermost wall of the first backside source / drain contact structure is substantially vertically aligned with an outermost wall of the first source / drain structure of the first transistor.

4. The semiconductor structure according to claim 1, wherein: The first transistor includes a vertical stack of semiconductor channel material nanosheets and a functional gate structure surrounding each semiconductor channel material nanosheet in the vertical stack of semiconductor channel material nanosheets.

5. The semiconductor structure of claim 4, further comprising a bottom dielectric spacer layer on a surface of the first transistor, the bottom dielectric spacer layer having sidewalls in direct physical contact with outermost sidewalls of the first backside source / drain contact structure. 6 . The semiconductor structure of claim 4 , further comprising an inner spacer positioned laterally adjacent to the functional gate structure.

7. The semiconductor structure of claim 1, further comprising a second source / drain structure located on a second side of the functional gate structure of the first transistor, the second side being opposite to the first side of the functional gate structure of the first transistor.

8. The semiconductor structure of claim 7, further comprising a first front side source / drain contact structure connecting the second source / drain structure of the first transistor to a front side back end of line (BEOL) structure.

9. The semiconductor structure of claim 8, further comprising a carrier wafer located on a surface of the front side BEOL structure.

10. The semiconductor structure of claim 1, further comprising an MRAM spacer positioned laterally adjacent to and in direct physical contact with the MRAM stack and the second electrode, wherein the MRAM spacer is positioned laterally adjacent to but spaced apart from the first electrode. 11 . The semiconductor structure of claim 10 , wherein the MRAM spacer has a bottommost surface located between a bottommost surface and an uppermost surface of the first electrode. 12 . The semiconductor structure of claim 1 , further comprising a backside interlayer dielectric (ILD) material layer stack laterally surrounding the MRAM and an upper portion of the first backside source / drain contact structure.

13. The semiconductor structure of claim 1, wherein the second electrode is in electrical contact with a backside interconnect structure.

14. The semiconductor structure of claim 13, further comprising a contact via structure extending vertically through the second electrode, the contact via structure having a first surface directly contacting the MRAM stack and a second surface opposite to the first surface, the second surface directly contacting the backside interconnect structure.

15. The semiconductor structure according to claim 1 further includes a second transistor located in the front side of the wafer and in a logic device area positioned adjacent to the MRAM device area, wherein the second transistor has a first source / drain structure located on a first side of a functional gate structure of the second transistor, and a second source / drain structure located on a second side of the functional gate structure of the second transistor opposite to the first side of the functional gate structure of the second transistor.

16. The semiconductor structure of claim 15, further comprising a second backside source / drain contact structure located in the logic device region and connecting the first source / drain structure of the second transistor to a backside power rail.

17. The semiconductor structure of claim 16, wherein the backside power rail is in electrical contact with a backside interconnect structure.

18. The semiconductor structure of claim 17, further comprising a via contact structure between the backside interconnect structure and the backside power rail.

19. The semiconductor structure of claim 15, further comprising a front side source / drain contact structure in the logic device region, the front side source / drain contact structure connecting the second source / drain structure of the second transistor to a front side BEOL structure.

20. The semiconductor structure of claim 19, further comprising a carrier wafer located on a surface of the front side BEOL structure.

21. The semiconductor structure of claim 16, wherein: The second backside source / drain contact structure has an uppermost surface located below a bottommost surface of an MRAM spacer surrounding the MRAM device.

22. A semiconductor structure comprising: A magnetoresistive random access memory (MRAM) device region, comprising an MRAM, the MRAM comprising a first electrode, an MRAM stack, and a second electrode, and being located in a backside of a wafer, a first transistor having a first source / drain structure located below the MRAM, and a first backside source / drain contact structure directly connecting the first electrode of the MRAM to the first source / drain structure of the first transistor, wherein the first backside source / drain contact structure has an outermost wall substantially vertically aligned with outermost walls of both the first source / drain structure and the first electrode of the first transistor; as well as a logic device region positioned adjacent to the MRAM device region, wherein the logic device region includes a second transistor located in the front side of the wafer and having a first source / drain structure located on a first side of a functional gate structure of the second transistor and a second backside source / drain contact structure directly connecting the first source / drain structure of the functional gate structure of the second transistor to a backside power rail.

23. The semiconductor structure of claim 22, wherein: The second backside source / drain contact structure has an uppermost surface located below a bottommost surface of an MRAM spacer surrounding the MRAM device.

24. The semiconductor structure of claim 23, wherein the MRAM spacer has a bottommost surface located between a bottommost surface and an uppermost surface of the first electrode.

25. The semiconductor structure of claim 22, wherein the backside power rail is in electrical contact with a backside interconnect structure on top of the backside power rail, and the second electrode of the MRAM is in electrical contact with the backside interconnect structure on top of the MRAM.

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