RISC-V DSP chip test waveform automatic generation method and system, and storage medium

Abstract

The invention provides an RISC-V DSP chip test waveform automatic generation method and system and a storage medium, and the method comprises the steps: determining first voltage information according to a first configuration parameter of a first configuration module and a chip power supply state; secondly, determining first clock information according to a second configuration parameter of a second configuration module and a clock source connection state; then, determining an output waveform mode according to a third configuration parameter of the first function module; and finally, according to the first voltage information or the first clock information, according to a corresponding output waveform mode, a waveform parameter is searched according to a preset operation script, and the waveform parameter is used for automatically generating a test waveform. The test waveform is automatically generated according to the running script according to the configuration parameters of the function test, manual modification operation of testers is reduced, and the efficiency and accuracy of test waveform generation are improved.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and more specifically, to a method, system and storage medium for automatically generating a RISC-V DSP chip test waveform. Background Art

[0002] When the RISC-V DSP chip is tested at the functional level ATE (Automatic Test Equipment), a specific test program is usually required for each function that needs to be tested. The test program is simulated in the RTL simulation environment to generate a test waveform passing through the JTAG / CJTAG pin of the chip. This waveform completes the function of loading the current test program into the RAM of the chip under test and controlling the chip to run this test program.

[0003] For each function that needs to be tested, there are several configuration modules, such as power supply module, clock module, etc., and at least one functional module, which needs parameter configuration. At present, chip functional level ATE testers usually organize the procedures of each functional test by manual summary; then manually modify the test waveform according to the configuration of the module, which has low test efficiency and the risk of manual error. Therefore, there is an urgent need for a RISC-V DSP chip test waveform automatic generation technology that improves test efficiency and accuracy. Summary of the invention

[0004] In view of the above problems, the purpose of the present invention is to provide a RISC-V DSP chip test waveform automatic generation method, system and storage medium. First, according to the configuration parameters of the power supply module, the first voltage information is determined; secondly, according to the configuration parameters of the clock module, the first clock information is determined; then, according to the configuration parameters of the functional module to be tested, the output waveform mode is determined; finally, according to the first voltage information or the first clock information, according to the corresponding output waveform mode, the test waveform is automatically generated through a preset running script; the manual modification operations of the test personnel are reduced, and the efficiency and accuracy of the test waveform generation are improved.

[0005] A first aspect of the present invention provides a method for automatically generating a RISC-V DSP chip test waveform, the method comprising:

[0006] Obtaining a first configuration parameter of a first configuration module;

[0007] Determining first voltage information according to the first configuration parameter;

[0008] Obtaining a second configuration parameter of a second configuration module;

[0009] Determining first clock information according to the second configuration parameter;

[0010] Obtaining a third configuration parameter of the first functional module;

[0011] Determining an output waveform mode according to the third configuration parameter;

[0012] A test waveform is generated according to the first voltage information or the first clock information and in accordance with a corresponding output waveform mode.

[0013] In this solution, the first voltage information is determined according to the first configuration parameter, specifically:

[0014] Determining a first voltage range according to the first configuration parameter;

[0015] Acquiring second voltage information;

[0016] determining whether the second voltage information is within the first voltage range;

[0017] If yes, determining the first voltage information according to the first configuration parameter and the second voltage information;

[0018] If not, the first voltage information is set to a preset second voltage threshold, and a first abnormal instruction is sent.

[0019] In this solution, determining the first clock information according to the second configuration parameter is specifically:

[0020] According to the second configuration parameter, a clock source flag is obtained;

[0021] Determine whether the clock source flag indicates an external clock;

[0022] If yes, obtaining external clock information, and setting second clock information according to the external clock information;

[0023] If not, obtaining an internal clock flag bit according to the second configuration parameter;

[0024] Determining second clock information according to the internal clock flag bit;

[0025] According to the second configuration parameter, a clock frequency division flag is obtained;

[0026] The first clock information is determined according to the second clock information and the clock frequency division flag.

[0027] In this solution, the test waveform is generated according to the first voltage information or the first clock information and the corresponding output waveform mode, specifically:

[0028] When it is determined that the output waveform mode is a digital output mode,

[0029] According to the third configuration parameter, a first duty cycle sequence is obtained by searching according to a preset operation script;

[0030] Determine first frequency information according to the third configuration parameter and the first clock information;

[0031] A test waveform is generated according to the first duty cycle sequence and the first frequency information.

[0032] In this solution, the test waveform is generated according to the first voltage information or the first clock information and the corresponding output waveform mode, specifically:

[0033] When it is determined that the output waveform mode is the analog output mode,

[0034] According to the third configuration parameter, a first ratio sequence is obtained by searching according to a preset operation script;

[0035] Determining third voltage information according to the third configuration parameter and the first voltage information;

[0036] A test waveform is generated according to the third voltage information and the first ratio sequence.

[0037] This plan also includes:

[0038] Determine whether the test waveform is verified;

[0039] If yes, obtaining a fourth configuration parameter according to a preset parameter list or parameter script;

[0040] The third configuration parameters are updated according to the fourth configuration parameters to regenerate a test waveform.

[0041] A second aspect of the present invention provides a RISC-V DSP chip test waveform automatic generation system, including a RISC-V DSP chip test waveform automatic generation method program, and when the RISC-V DSP chip test waveform automatic generation method program is executed by the processor, the following steps are implemented:

[0042] Obtaining a first configuration parameter of a first configuration module;

[0043] Determining first voltage information according to the first configuration parameter;

[0044] Obtaining a second configuration parameter of a second configuration module;

[0045] Determining first clock information according to the second configuration parameter;

[0046] Obtaining a third configuration parameter of the first functional module;

[0047] Determining an output waveform mode according to the third configuration parameter;

[0048] A test waveform is generated according to the first voltage information or the first clock information and in accordance with a corresponding output waveform mode.

[0049] In this solution, the test waveform is generated according to the first voltage information or the first clock information and the corresponding output waveform mode, specifically:

[0050] When it is determined that the output waveform mode is a digital output mode,

[0051] According to the third configuration parameter, a first duty cycle sequence is obtained by searching according to a preset operation script;

[0052] Determine first frequency information according to the third configuration parameter and the first clock information;

[0053] A test waveform is generated according to the first duty cycle sequence and the first frequency information.

[0054] In this solution, the test waveform is generated according to the first voltage information or the first clock information and the corresponding output waveform mode, specifically:

[0055] When it is determined that the output waveform mode is the analog output mode,

[0056] According to the third configuration parameter, a first ratio sequence is obtained by searching according to a preset operation script;

[0057] Determining third voltage information according to the third configuration parameter and the first voltage information;

[0058] A test waveform is generated according to the third voltage information and the first ratio sequence.

[0059] A third aspect of the present invention provides a computer-readable storage medium, which includes a RISC-V DSP chip test waveform automatic generation method program. When the RISC-V DSP chip test waveform automatic generation method program is executed by a processor, the steps of the RISC-V DSP chip test waveform automatic generation method as described in any one of the above items are implemented.

[0060] The present invention provides a RISC-V DSP chip test waveform automatic generation method, system and storage medium. First, first voltage information is determined according to a first configuration parameter of a first configuration module and a chip power supply state; secondly, first clock information is determined according to a second configuration parameter of a second configuration module and a clock source connection state; then, an output waveform mode is determined according to a third configuration parameter of a first functional module; finally, waveform parameters are searched according to a preset running script according to the first voltage information or the first clock information and the corresponding output waveform mode, so as to automatically generate a test waveform. The present invention automatically generates a test waveform according to a running script according to the configuration parameters of a functional test, thereby reducing manual modification operations of test personnel and improving the efficiency and accuracy of test waveform generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and should not be regarded as limiting the scope.

[0062] Figure 1 A flow chart of a method for automatically generating a RISC-V DSP chip test waveform according to the present invention is shown;

[0063] Figure 2 A flow chart of generating a test waveform in a digital output mode provided by an embodiment of the present invention is shown;

[0064] Figure 3 A flow chart of generating a test waveform in an analog output mode provided by an embodiment of the present invention is shown;

[0065] Figure 4 A block diagram of a RISC-V DSP chip test waveform automatic generation system of the present invention is shown. DETAILED DESCRIPTION

[0066] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0067] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present invention have the same meanings as commonly understood by those of ordinary skill in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless the embodiments of the present invention are clearly defined in this way.

[0068] The words "first", "second" and similar words used in the embodiments of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "one", "an" or "the" and similar words do not indicate a quantity limitation, but indicate the existence of at least one. Similarly, words such as "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The steps before or after the method of the embodiment of the present invention are not necessarily carried out in order. On the contrary, various steps can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or a step or several steps can be removed from these processes.

[0069] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0070] Figure 1 A flow chart of a method for automatically generating a RISC-V DSP chip test waveform according to the present invention is shown.

[0071] like Figure 1 As shown, the first aspect of the present invention discloses a method for automatically generating a RISC-V DSP chip test waveform, the method comprising:

[0072] S102, obtaining a first configuration parameter of a first configuration module;

[0073] S104, determining first voltage information according to the first configuration parameter;

[0074] S106, obtaining a second configuration parameter of a second configuration module;

[0075] S108, determining first clock information according to the second configuration parameter;

[0076] S110, obtaining a third configuration parameter of the first functional module;

[0077] S112, determining an output waveform mode according to the third configuration parameter;

[0078] S114, generating a test waveform according to the first voltage information or the first clock information and a corresponding output waveform mode.

[0079] It should be noted that the first configuration module is the power supply module of the chip; the first configuration parameter is the parameter for configuring the power supply module, such as the data for configuring the power supply register; the first voltage information is the power supply voltage value of the chip operation; the second configuration module is the clock module of the chip, the second configuration parameter is the parameter for configuring the module, such as the data for configuring the clock register; the first clock information is the system clock of the chip operation. The first functional module is the chip functional module to be tested; the third configuration parameter is the parameter for configuring the chip functional module, such as the data for configuring the output register.

[0080] In this embodiment, first, according to the first configuration parameter of the chip power supply module, the input voltage range required for the normal operation of the chip is obtained; then, according to the chip input voltage, it is determined whether the normal operation of the chip can be supported. If so, the operating voltage of the chip is determined according to the first configuration parameter and the input voltage. Secondly, according to the second configuration parameter of the clock module, the clock source of the chip is determined; when it is determined that the internal clock of the chip is used, the high-speed clock or the low-speed clock is selected according to the second configuration parameter to obtain the system clock frequency. When it is determined that the external clock is used, the system clock frequency is obtained according to the external clock. Then, according to the third configuration parameter of the first functional module, the pin and mode of the output waveform are determined; wherein the output mode includes a digital output mode and an analog output mode, and a digital signal is output through the output pin when in the digital output mode, and an analog signal is output through the output pin when in the analog output mode. Finally, according to the corresponding output waveform mode, the first voltage information or the first clock information is passed into the running script, and the corresponding output waveform is found through the script as a test waveform. This embodiment automatically generates a test waveform according to the running script according to the configuration parameters of the functional test, thereby reducing the manual modification operation of the tester and improving the efficiency and accuracy of the test waveform generation.

[0081] According to an embodiment of the present invention, determining the first voltage information according to the first configuration parameter is specifically:

[0082] Determining a first voltage range according to the first configuration parameter;

[0083] Acquiring second voltage information;

[0084] determining whether the second voltage information is within the first voltage range;

[0085] If yes, determining the first voltage information according to the first configuration parameter and the second voltage information;

[0086] If not, the first voltage information is set to a preset second voltage threshold, and a first abnormal instruction is sent.

[0087] It should be noted that the first voltage range threshold is the range of input voltage required for the chip to maintain stable operation according to the set power configuration parameters; the second voltage information is the power supply voltage value of the chip; the first abnormal instruction is an instruction used to feedback to the test background to indicate that the input voltage is abnormal. In this embodiment, first, according to the first configuration parameter of the chip power supply module, the input voltage range required for the normal operation of the chip, that is, the first voltage range information, is obtained. Then, the voltage value of the input power supply is obtained to determine whether the input voltage is within the first voltage range; if so, it means that the input voltage meets the normal working requirements of the chip. At this time, the chip operating voltage value is determined according to the first configuration parameter and the input voltage value; if not, it means that insufficient input voltage will cause the chip to fail to power on normally, or the input voltage is too high and there is a risk of burning the chip. At this time, the chip operating voltage value is set according to the preset second voltage threshold to send the first abnormal instruction, thereby improving the efficiency of abnormal problem handling during the test process.

[0088] According to an embodiment of the present invention, determining the first clock information according to the second configuration parameter is specifically:

[0089] According to the second configuration parameter, a clock source flag is obtained;

[0090] Determine whether the clock source flag indicates an external clock;

[0091] If yes, obtaining external clock information, and setting second clock information according to the external clock information;

[0092] If not, obtaining an internal clock flag bit according to the second configuration parameter;

[0093] Determining second clock information according to the internal clock flag bit;

[0094] According to the second configuration parameter, a clock frequency division flag is obtained;

[0095] The first clock information is determined according to the second clock information and the clock frequency division flag.

[0096] It should be noted that the clock source flag is the flag data for configuring the chip clock source in the second configuration parameter, and the clock source includes an external clock and an internal clock; the internal clock flag is the flag data for configuring the chip internal clock source in the second configuration parameter, and the internal clock includes at least a high-speed internal clock and a low-speed internal clock; the second clock information is the reference clock source of the chip; the clock frequency division flag is the clock frequency division coefficient in the second configuration parameter, which is used to obtain the system clock of the chip operation in combination with the reference clock source. In this embodiment, first, according to the clock source flag of the second configuration parameter of the clock module, it is determined whether the clock source of the chip is an internal clock or an external clock. When it is determined that the clock source of the chip is an external clock, the clock frequency of the external clock is obtained from the input interface of the external clock frequency, such as the data input interface of the test equipment. When it is determined that the clock source of the chip is an internal clock, according to the internal clock flag information, it is determined that the clock source of the chip is an internal high-speed clock or an internal low-speed clock, and the clock frequency is determined according to the internal clock. Finally, according to the frequency division flag of the second configuration parameter, according to the frequency division rule of the chip, the first clock information, that is, the system clock of the chip operation, is obtained.

[0097] Figure 2 A flow chart of generating a test waveform in a digital output mode provided by an embodiment of the present invention is shown.

[0098] According to an embodiment of the present invention, Figure 2 As shown, the test waveform is generated according to the first voltage information or the first clock information and the corresponding output waveform mode, specifically:

[0099] S202, when it is determined that the output waveform mode is a digital output mode,

[0100] S204, searching and obtaining a first duty cycle sequence according to the third configuration parameter and a preset operation script;

[0101] S206, determining first frequency information according to the third configuration parameter and the first clock information;

[0102] S208: Generate a test waveform according to the first duty cycle sequence and the first frequency information.

[0103] It should be noted that, in this embodiment, when the output waveform mode is a digital output mode, the script is first run to find the first duty cycle sequence according to the third configuration parameter of the output module. In practical applications, the digital signals that can be set by the duty cycle parameters include high level, low level and pulse level. When the duty cycle is 100%, it can represent a high level, when the duty cycle is 0%, it can represent a low level, and when the duty cycle is between 0% and 100%, it can represent a pulse level in combination with the output frequency information. Then, according to the third configuration parameter and the system clock frequency of the chip, the frequency of the output waveform, that is, the first frequency information, is determined. Finally, according to the first duty cycle sequence, the time of the high level and the low level of the waveform in each cycle is adjusted according to the first frequency information to obtain a digital test waveform.

[0104] Figure 3 A flow chart of generating a test waveform in an analog output mode provided by an embodiment of the present invention is shown;

[0105] According to an embodiment of the present invention, Figure 3 As shown, the test waveform is generated according to the first voltage information or the first clock information and the corresponding output waveform mode, specifically:

[0106] S302, when it is determined that the output waveform mode is an analog output mode,

[0107] S304, searching and obtaining a first ratio sequence according to the third configuration parameter and a preset running script;

[0108] S306, determining third voltage information according to the third configuration parameter and the first voltage information;

[0109] S308: Generate a test waveform according to the third voltage information and the first ratio sequence.

[0110] It should be noted that, in this embodiment, when the output waveform mode is the analog output mode, first, the script is run to find the first ratio sequence according to the third configuration parameter of the output module. In practical applications, the ratio parameter is the ratio of the output voltage amplitude to the output reference voltage; then, according to the ratio sequence, output voltages of different amplitudes can be obtained, and combined with the system clock, the output waveform can specify the set voltage amplitude within the set time. Then, according to the third configuration parameter and the system power supply voltage of the chip, the output reference voltage of the output waveform, that is, the third voltage information, is determined. Finally, according to the third voltage information and the first ratio sequence, the analog test waveform is obtained according to the set output time.

[0111] According to an embodiment of the present invention, it also includes:

[0112] Determine whether the test waveform is verified;

[0113] If yes, obtaining a fourth configuration parameter according to a preset parameter list or parameter script;

[0114] The third configuration parameters are updated according to the fourth configuration parameters to regenerate a test waveform.

[0115] It should be noted that, in this embodiment, after completing the waveform output and verification under the third configuration parameter of the current functional module, the waveform output and verification of the next set of functional configuration parameters are performed. At this time, according to the list of functional configuration parameters, or the set parameter script, the configuration parameters of the next set of tests, i.e., the fourth configuration parameters, are obtained. The third configuration parameters are replaced by the fourth configuration parameters for the next round of waveform output. This embodiment reduces the manual operation items of the tester and improves the efficiency of chip testing by automatically updating the configuration parameters of the functional module.

[0116] It is worth mentioning that it also includes:

[0117] When it is determined that the output waveform mode is a digital output mode,

[0118] Obtaining a first duty cycle sequence;

[0119] Obtaining first duty cycle information according to the first duty cycle sequence;

[0120] Determining whether the first duty cycle information exceeds a preset duty cycle threshold;

[0121] If yes, it means the digital logic information is logic 1;

[0122] If not, it means that the digital logic information is logic 0;

[0123] According to the digital logic, a first digital logic sequence is obtained;

[0124] According to the first digital logic sequence and the preset number of data bits, communication data is obtained.

[0125] It should be noted that in this embodiment, digital logic information is obtained by analyzing the duty cycle of the test waveform, and then the communication data is composed according to the preset number of digital logic information. For example, when the duty cycle of a pulse is higher than 50%, it indicates that the digital logic information is logic 1; when the duty cycle of a pulse is lower than 50%, it indicates that the digital logic information is logic 0; that is, each pulse can represent a binary number. According to the preset bit length, such as 8 bits, 16 bits, and 32 bits, the digital logic information of a set number of pulses can be composed of data; this data can be used for data communication.

[0126] It is worth mentioning that it also includes:

[0127] Obtaining the serial number information of the first functional module;

[0128] The numbering information is input to the first neural network model to obtain a third configuration parameter and a corresponding duty cycle sequence or ratio sequence.

[0129] It should be noted that, due to the limitation of memory capacity, the function test information saved in the running script cannot cover all situations. When the memory lacks the waveform information of the function to be tested, the module number of the function module to be tested is input into the first neural network model. Through the first neural network model, the third configuration parameter of the current function module and the duty cycle sequence or ratio sequence corresponding to the configuration parameter are obtained.

[0130] Figure 4 A block diagram of a RISC-V DSP chip test waveform automatic generation system of the present invention is shown.

[0131] like Figure 4 As shown, the second aspect of the present invention discloses a RISC-V DSP chip test waveform automatic generation system 4, including a memory 41 and a processor 42, wherein the memory includes a RISC-V DSP chip test waveform automatic generation method program, and when the RISC-V DSP chip test waveform automatic generation method program is executed by the processor, the following steps are implemented:

[0132] Obtaining a first configuration parameter of a first configuration module;

[0133] Determining first voltage information according to the first configuration parameter;

[0134] Obtaining a second configuration parameter of a second configuration module;

[0135] Determining first clock information according to the second configuration parameter;

[0136] Obtaining a third configuration parameter of the first functional module;

[0137] Determining an output waveform mode according to the third configuration parameter;

[0138] A test waveform is generated according to the first voltage information or the first clock information and in accordance with a corresponding output waveform mode.

[0139] It should be noted that the first configuration module is the power supply module of the chip; the first configuration parameter is the parameter for configuring the power supply module, such as the data for configuring the power supply register; the first voltage information is the power supply voltage value of the chip operation; the second configuration module is the clock module of the chip, the second configuration parameter is the parameter for configuring the module, such as the data for configuring the clock register; the first clock information is the system clock of the chip operation. The first functional module is the chip functional module to be tested; the third configuration parameter is the parameter for configuring the chip functional module, such as the data for configuring the output register.

[0140] In this embodiment, first, according to the first configuration parameter of the chip power supply module, the input voltage range required for the normal operation of the chip is obtained; then, according to the chip input voltage, it is determined whether the normal operation of the chip can be supported. If so, the operating voltage of the chip is determined according to the first configuration parameter and the input voltage. Secondly, according to the second configuration parameter of the clock module, the clock source of the chip is determined; when it is determined that the internal clock of the chip is used, the high-speed clock or the low-speed clock is selected according to the second configuration parameter to obtain the system clock frequency. When it is determined that the external clock is used, the system clock frequency is obtained according to the external clock. Then, according to the third configuration parameter of the first functional module, the pin and mode of the output waveform are determined; wherein the output mode includes a digital output mode and an analog output mode, and a digital signal is output through the output pin when in the digital output mode, and an analog signal is output through the output pin when in the analog output mode. Finally, according to the corresponding output waveform mode, the first voltage information or the first clock information is passed into the running script, and the corresponding output waveform is found through the script as a test waveform. This embodiment automatically generates a test waveform according to the running script according to the configuration parameters of the functional test, thereby reducing the manual modification operation of the tester and improving the efficiency and accuracy of the test waveform generation.

[0141] According to an embodiment of the present invention, determining the first voltage information according to the first configuration parameter is specifically:

[0142] Determining a first voltage range according to the first configuration parameter;

[0143] Acquiring second voltage information;

[0144] determining whether the second voltage information is within the first voltage range;

[0145] If yes, determining the first voltage information according to the first configuration parameter and the second voltage information;

[0146] If not, the first voltage information is set to a preset second voltage threshold, and a first abnormal instruction is sent.

[0147] It should be noted that the first voltage range threshold is the range of input voltage required for the chip to maintain stable operation according to the set power configuration parameters; the second voltage information is the power supply voltage value of the chip; the first abnormal instruction is an instruction used to feedback to the test background to indicate that the input voltage is abnormal. In this embodiment, first, according to the first configuration parameter of the chip power supply module, the input voltage range required for the normal operation of the chip, that is, the first voltage range information, is obtained. Then, the voltage value of the input power supply is obtained to determine whether the input voltage is within the first voltage range; if so, it means that the input voltage meets the normal working requirements of the chip. At this time, the chip operating voltage value is determined according to the first configuration parameter and the input voltage value; if not, it means that insufficient input voltage will cause the chip to fail to power on normally, or the input voltage is too high and there is a risk of burning the chip. At this time, the chip operating voltage value is set according to the preset second voltage threshold to send the first abnormal instruction, thereby improving the efficiency of abnormal problem handling during the test process.

[0148] According to an embodiment of the present invention, determining the first clock information according to the second configuration parameter is specifically:

[0149] According to the second configuration parameter, a clock source flag is obtained;

[0150] Determine whether the clock source flag indicates an external clock;

[0151] If yes, obtaining external clock information, and setting second clock information according to the external clock information;

[0152] If not, obtaining an internal clock flag bit according to the second configuration parameter;

[0153] Determining second clock information according to the internal clock flag bit;

[0154] According to the second configuration parameter, a clock frequency division flag is obtained;

[0155] The first clock information is determined according to the second clock information and the clock frequency division flag.

[0156] It should be noted that the clock source flag is the flag data for configuring the chip clock source in the second configuration parameter, and the clock source includes an external clock and an internal clock; the internal clock flag is the flag data for configuring the chip internal clock source in the second configuration parameter, and the internal clock includes at least a high-speed internal clock and a low-speed internal clock; the second clock information is the reference clock source of the chip; the clock frequency division flag is the clock frequency division coefficient in the second configuration parameter, which is used to obtain the system clock of the chip operation in combination with the reference clock source. In this embodiment, first, according to the clock source flag of the second configuration parameter of the clock module, it is determined whether the clock source of the chip is an internal clock or an external clock. When it is determined that the clock source of the chip is an external clock, the clock frequency of the external clock is obtained from the input interface of the external clock frequency, such as the data input interface of the test equipment. When it is determined that the clock source of the chip is an internal clock, according to the internal clock flag information, it is determined that the clock source of the chip is an internal high-speed clock or an internal low-speed clock, and the clock frequency is determined according to the internal clock. Finally, according to the frequency division flag of the second configuration parameter, according to the frequency division rule of the chip, the first clock information, that is, the system clock of the chip operation, is obtained.

[0157] According to an embodiment of the present invention, generating a test waveform according to the first voltage information or the first clock information and the corresponding output waveform mode is specifically:

[0158] When it is determined that the output waveform mode is a digital output mode,

[0159] According to the third configuration parameter, a first duty cycle sequence is obtained by searching according to a preset operation script;

[0160] Determine first frequency information according to the third configuration parameter and the first clock information;

[0161] A test waveform is generated according to the first duty cycle sequence and the first frequency information.

[0162] It should be noted that, in this embodiment, when the output waveform mode is a digital output mode, the script is first run to find the first duty cycle sequence according to the third configuration parameter of the output module. In practical applications, the digital signals that can be set by the duty cycle parameters include high level, low level and pulse level. When the duty cycle is 100%, it can represent a high level, when the duty cycle is 0%, it can represent a low level, and when the duty cycle is between 0% and 100%, it can represent a pulse level in combination with the output frequency information. Then, according to the third configuration parameter and the system clock frequency of the chip, the frequency of the output waveform, that is, the first frequency information, is determined. Finally, according to the first duty cycle sequence, the time of the high level and the low level of the waveform in each cycle is adjusted according to the first frequency information to obtain a digital test waveform.

[0163] According to an embodiment of the present invention, generating a test waveform according to the first voltage information or the first clock information and the corresponding output waveform mode is specifically:

[0164] When it is determined that the output waveform mode is the analog output mode,

[0165] According to the third configuration parameter, a first ratio sequence is obtained by searching according to a preset operation script;

[0166] Determining third voltage information according to the third configuration parameter and the first voltage information;

[0167] A test waveform is generated according to the third voltage information and the first ratio sequence.

[0168] It should be noted that, in this embodiment, when the output waveform mode is the analog output mode, first, the script is run to find the first ratio sequence according to the third configuration parameter of the output module. In practical applications, the ratio parameter is the ratio of the output voltage amplitude to the output reference voltage; then, according to the ratio sequence, output voltages of different amplitudes can be obtained, and combined with the system clock, the output waveform can specify the set voltage amplitude within the set time. Then, according to the third configuration parameter and the system power supply voltage of the chip, the output reference voltage of the output waveform, that is, the third voltage information, is determined. Finally, according to the third voltage information and the first ratio sequence, the analog test waveform is obtained according to the set output time.

[0169] According to an embodiment of the present invention, it also includes:

[0170] Determine whether the test waveform is verified;

[0171] If yes, obtaining a fourth configuration parameter according to a preset parameter list or parameter script;

[0172] The third configuration parameters are updated according to the fourth configuration parameters to regenerate a test waveform.

[0173] It should be noted that, in this embodiment, after completing the waveform output and verification under the third configuration parameter of the current functional module, the waveform output and verification of the next set of functional configuration parameters are performed. At this time, according to the list of functional configuration parameters, or the set parameter script, the configuration parameters of the next set of tests, i.e., the fourth configuration parameters, are obtained. The third configuration parameters are replaced by the fourth configuration parameters for the next round of waveform output. This embodiment reduces the manual operation items of the tester and improves the efficiency of chip testing by automatically updating the configuration parameters of the functional module.

[0174] It is worth mentioning that it also includes:

[0175] When it is determined that the output waveform mode is a digital output mode,

[0176] Obtaining a first duty cycle sequence;

[0177] Obtaining first duty cycle information according to the first duty cycle sequence;

[0178] Determining whether the first duty cycle information exceeds a preset duty cycle threshold;

[0179] If yes, it means the digital logic information is logic 1;

[0180] If not, it means that the digital logic information is logic 0;

[0181] According to the digital logic, a first digital logic sequence is obtained;

[0182] According to the first digital logic sequence and the preset number of data bits, communication data is obtained.

[0183] It should be noted that in this embodiment, digital logic information is obtained by analyzing the duty cycle of the test waveform, and then the communication data is composed according to the preset number of digital logic information. For example, when the duty cycle of a pulse is higher than 50%, it indicates that the digital logic information is logic 1; when the duty cycle of a pulse is lower than 50%, it indicates that the digital logic information is logic 0; that is, each pulse can represent a binary number. According to the preset bit length, such as 8 bits, 16 bits, and 32 bits, the digital logic information of a set number of pulses can be composed of data; this data can be used for data communication.

[0184] It is worth mentioning that it also includes:

[0185] Obtaining the serial number information of the first functional module;

[0186] The numbering information is input to the first neural network model to obtain a third configuration parameter and a corresponding duty cycle sequence or ratio sequence.

[0187] It should be noted that, due to the limitation of memory capacity, the function test information saved in the running script cannot cover all situations. When the memory lacks the waveform information of the function to be tested, the module number of the function module to be tested is input into the first neural network model. Through the first neural network model, the third configuration parameter of the current function module and the duty cycle sequence or ratio sequence corresponding to the configuration parameter are obtained.

[0188] A third aspect of the present invention provides a computer-readable storage medium, which includes a RISC-V DSP chip test waveform automatic generation method program. When the RISC-V DSP chip test waveform automatic generation method program is executed by a processor, the steps of the RISC-V DSP chip test waveform automatic generation method as described in any one of the above items are implemented.

[0189] The present invention provides a RISC-V DSP chip test waveform automatic generation method, system and storage medium. First, first voltage information is determined according to a first configuration parameter of a first configuration module and a chip power supply state; secondly, first clock information is determined according to a second configuration parameter of a second configuration module and a clock source connection state; then, an output waveform mode is determined according to a third configuration parameter of a first functional module; finally, waveform parameters are searched according to a preset running script according to the first voltage information or the first clock information and the corresponding output waveform mode, so as to automatically generate a test waveform. The present invention automatically generates a test waveform according to a running script according to the configuration parameters of a functional test, thereby reducing manual modification operations of test personnel and improving the efficiency and accuracy of test waveform generation.

[0190] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0191] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for automatically generating a RISC-V DSP chip test waveform, characterized in that: The method comprises: Obtaining a first configuration parameter of a first configuration module; Determining first voltage information according to the first configuration parameter; Obtaining a second configuration parameter of a second configuration module; Determining first clock information according to the second configuration parameter; Obtaining a third configuration parameter of the first functional module; Determining an output waveform mode according to the third configuration parameter; A test waveform is generated according to the first voltage information or the first clock information and in accordance with a corresponding output waveform mode.

2. A RISC-V DSP chip test waveform automatic generation method according to claim 1, characterized in that: The determining the first voltage information according to the first configuration parameter is specifically: Determining a first voltage range according to the first configuration parameter; Acquiring second voltage information; determining whether the second voltage information is within the first voltage range; If yes, determining the first voltage information according to the first configuration parameter and the second voltage information; If not, the first voltage information is set to a preset second voltage threshold, and a first abnormal instruction is sent.

3. A RISC-V DSP chip test waveform automatic generation method according to claim 1, characterized in that: The determining the first clock information according to the second configuration parameter is specifically: According to the second configuration parameter, a clock source flag is obtained; Determine whether the clock source flag indicates an external clock; If yes, obtaining external clock information, and setting second clock information according to the external clock information; If not, obtaining an internal clock flag bit according to the second configuration parameter; Determining second clock information according to the internal clock flag bit; According to the second configuration parameter, a clock frequency division flag is obtained; The first clock information is determined according to the second clock information and the clock frequency division flag.

4. A RISC-V DSP chip test waveform automatic generation method according to claim 1, characterized in that: The generating of the test waveform according to the first voltage information or the first clock information and the corresponding output waveform mode is specifically: When it is determined that the output waveform mode is a digital output mode, According to the third configuration parameter, a first duty cycle sequence is obtained by searching according to a preset operation script; Determine first frequency information according to the third configuration parameter and the first clock information; A test waveform is generated according to the first duty cycle sequence and the first frequency information.

5. A RISC-V DSP chip test waveform automatic generation method according to claim 1, characterized in that: The generating of the test waveform according to the first voltage information or the first clock information and the corresponding output waveform mode is specifically: When it is determined that the output waveform mode is the analog output mode, According to the third configuration parameter, a first ratio sequence is obtained by searching according to a preset operation script; Determining third voltage information according to the third configuration parameter and the first voltage information; A test waveform is generated according to the third voltage information and the first ratio sequence.

6. A RISC-V DSP chip test waveform automatic generation method according to claim 1, characterized in that: Also includes: Determine whether the test waveform is verified; If yes, obtaining a fourth configuration parameter according to a preset parameter list or parameter script; The third configuration parameters are updated according to the fourth configuration parameters to regenerate a test waveform.

7. A RISC-V DSP chip test waveform automatic generation system, characterized in that: The system includes a memory and a processor, wherein the memory includes a RISC-V DSP chip test waveform automatic generation method program, and when the RISC-V DSP chip test waveform automatic generation method program is executed by the processor, the following steps are implemented: Obtaining a first configuration parameter of a first configuration module; Determining first voltage information according to the first configuration parameter; Obtaining a second configuration parameter of a second configuration module; Determining first clock information according to the second configuration parameter; Obtaining a third configuration parameter of the first functional module; Determining an output waveform mode according to the third configuration parameter; A test waveform is generated according to the first voltage information or the first clock information and in accordance with a corresponding output waveform mode.

8. A RISC-V DSP chip test waveform automatic generation system according to claim 7, characterized in that: The generating of the test waveform according to the first voltage information or the first clock information and the corresponding output waveform mode is specifically: When it is determined that the output waveform mode is a digital output mode, According to the third configuration parameter, a first duty cycle sequence is obtained by searching according to a preset operation script; Determine first frequency information according to the third configuration parameter and the first clock information; A test waveform is generated according to the first duty cycle sequence and the first frequency information.

9. A RISC-V DSP chip test waveform automatic generation system according to claim 7, characterized in that: The generating of the test waveform according to the first voltage information or the first clock information and the corresponding output waveform mode is specifically: When it is determined that the output waveform mode is the analog output mode, According to the third configuration parameter, a first ratio sequence is obtained by searching according to a preset operation script; Determining third voltage information according to the third configuration parameter and the first voltage information; A test waveform is generated according to the third voltage information and the first ratio sequence.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: The computer-readable storage medium includes a RISC-V DSP chip test waveform automatic generation method program. When the RISC-V DSP chip test waveform automatic generation method program is executed by a processor, the steps of the RISC-V DSP chip test waveform automatic generation method as described in any one of claims 1 to 6 are implemented.

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