Predictive power management

Abstract

The application is directed to predictive power management. A correlation may be identified between a set of commands executed at a memory device and an oscillating voltage pattern or a resonant frequency, or both. A voltage may be monitored by the memory device and compared to the identified voltage pattern to mitigate unwanted oscillating voltages and resonant frequencies.

Description

[0001] Divisional Application Information

[0002] This application is a divisional application of the invention patent application with application date of March 11, 2020, application number 202080025692.9, and invention name “Predictive Power Management”.

[0003] Cross Reference

[0004] This patent application claims priority to PCT Application No. PCT / US2020 / 022042, entitled “PREDICTIVE POWER MANAGEMENT,” filed by Badrieh et al. on March 11, 2020, which claims priority to U.S. Patent Application No. 16 / 369,804, entitled “PREDICTIVE POWER MANAGEMENT,” filed by Badrieh et al. on March 29, 2019, each of which is assigned to the present assignee and each of which is expressly incorporated by reference in its entirety.

[0005] The technical field relates to predictive power management. Background Art

[0006] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, often represented by a logical 1 or a logical 0. In other devices, more than two states may be stored. To access the stored information, a component of the device may read or sense at least one stored state in the memory device. To store information, a component of the device may write or program a state in the memory device.

[0007] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time, even when no external power source is present. Volatile memory devices, such as DRAM, may lose their stored state when disconnected from an external power source.

[0008] The power delivery network may provide power to the memory device, and in doing so, may need to consider different factors and elements, including feedback, circuit elements, time dependencies, frequency dependencies, etc. When the power delivery network operates close to or outside of an acceptable range for the memory device, the memory device may perform suboptimally with increased latency when executing commands or experience reliability issues. Summary of the invention

[0009] A method is described. The method may include: monitoring one or more voltages of a power delivery network associated with a memory die; comparing the one or more voltages to a set of voltages of the power delivery network indicating that the power delivery network operates at a first frequency; determining whether the one or more voltages of the power delivery network satisfy a condition based at least in part on comparing the one or more voltages to the set of voltages; and adjusting timing of at least one command associated with the memory die based at least in part on determining whether the one or more voltages satisfy the condition.

[0010] Another method is described. The method may include: receiving, at a host device, one or more voltages of a power delivery network associated with a memory die; comparing the one or more voltages to a set of voltages of the power delivery network indicating that the power delivery network operates at a first frequency; determining whether the one or more voltages of the power delivery network satisfy a condition based at least in part on comparing the one or more voltages to the set of voltages; determining timing of at least one command associated with the memory die based at least in part on determining whether the one or more voltages satisfy the condition; and transmitting the timing of at least one command associated with the memory die to the memory die based at least in part on determining the timing of at least one command.

[0011] Another method is described. The method may include: receiving, at a host device, an indication that one or more voltages of a power delivery network on a memory die are configured to cause the power delivery network to operate at a resonant frequency for a duration; determining a timing of at least one command based at least in part on the receiving the indication; and transmitting the timing of the at least one command.

[0012] An apparatus is described. The apparatus may include: a memory die including one or more memory cells; a power delivery network coupled to the memory die; and a controller. The power delivery network may be configured to power one or more operations of the memory die. The sensor may be configured to sense one or more voltages of the power delivery network associated with the memory die. The controller may be configured to cause the apparatus to: compare the one or more voltages with a set of voltages of the power delivery network indicating that the power delivery network operates at a first frequency; determine whether the one or more voltages of the power delivery network associated with the memory die meet a condition based at least in part on comparing the one or more voltages with the set of voltages; and adjust the timing of at least one command associated with the memory die based at least in part on determining whether the one or more voltages of the power delivery network meet the condition. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 An example of a system supporting predictive power management according to examples as disclosed herein is described.

[0014] Figure 2 An example of a memory die supporting predictive power management according to examples as disclosed herein is illustrated.

[0015] Figure 3 An example of a power delivery network supporting predictive power management according to examples as disclosed herein is illustrated.

[0016] Figure 4 An example of a graph supporting predictive power management according to examples as disclosed herein is illustrated.

[0017] Figure 5 An example of a process flow supporting predictive power management according to examples as disclosed herein is described.

[0018] Figure 6 An example of a process flow supporting predictive power management according to examples as disclosed herein is described.

[0019] Figure 7 An example of a memory device supporting predictive power management according to examples as disclosed herein is illustrated.

[0020] Figure 8 A block diagram of a host device supporting predictive power management according to aspects of the present disclosure is shown.

[0021] Figures 9 to 12 A flow chart is shown illustrating one or more methods of supporting predictive power management according to examples as disclosed herein. DETAILED DESCRIPTION

[0022] The memory device may receive commands from a host device and may execute the commands accordingly. The memory device may draw current from the power delivery network when executing the commands. In some examples, the current demand may cause a voltage drop, cause the voltage to drop below the specification range of the memory device, cause the power delivery network to operate at a resonant frequency, cause the voltage or current of the power delivery network to oscillate, or a combination thereof. In some examples, the memory device may receive a set of commands or command timings corresponding to specific current demands that produce an undesirable voltage oscillation pattern, a voltage drop, and in some cases a resonant frequency. Correlations between different command sets and undesirable oscillation patterns may be identified, and therefore, the memory device may be able to predict upcoming command sequences that may trigger a voltage drop and / or a resonant frequency.

[0023] Some memory devices may include transistors (e.g., DRAM transistors) that may have impedances associated therewith. Impedances may be frequency dependent, and frequency dependent elements may tend to behave differently for different temporal stimuli. In some examples of power delivery networks, high impedance at or near a frequency or frequency range may cause undesirable oscillation modes or resonant frequencies, which may cause different parameters (e.g., voltages) to be outside of the specification range for the device and / or network.

[0024] In some examples, by identifying an impedance distribution and a frequency range where a resonant frequency may occur, a voltage response to the impedance distribution and frequency range may be established. Furthermore, the voltage response of the memory device may be monitored for unacceptable behavior (e.g., voltage drop, operation at a resonant frequency, etc.), which may be a result of command timing. Additionally or alternatively, the voltage response of the memory device may be monitored for an oscillation pattern that may be an indicator of a trend toward a resonant frequency. Upon identifying any of these conditions, the timing of commands communicated to the memory device may be adjusted so that these conditions are mitigated or do not occur.

[0025] In some cases, one or more voltages of a power delivery network associated with a memory die may be monitored. The one or more voltages may be compared to a set of voltages of the power delivery network that may indicate that the power delivery network is operating at a particular frequency. A memory device or a host device may determine whether the one or more voltages satisfy a condition. Command timing associated with the memory die may be adjusted based on determining that the one or more voltages satisfy the condition.

[0026] First, in reference Figure 1 and 2 Features of the present disclosure are described in the context of the memory system described. Figures 3 to 6Features of the present disclosure are described in the context of a power delivery network and process flow for a memory device as described herein. Figures 7 to 10 These and other features of the present disclosure are illustrated by and described with reference to the apparatus diagrams and flow diagrams described for predictive power management of memory devices.

[0027] Figure 1 An example of a system 100 utilizing one or more memory devices according to examples as disclosed herein is illustrated. The system 100 may include an external memory controller 105, a memory device 110, and a plurality of channels 115 coupling the external memory controller 105 with the memory device 110. The system 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110.

[0028] System 100 may include a portion of an electronic device such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, a laptop, a tablet, a smart phone, a cellular phone, a wearable device, an Internet-connected device, and the like. Memory device 110 may be a component of the system configured to store data for one or more other components of system 100. In some examples, system 100 is capable of machine type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0029] At least some portions of the system 100 may be instances of host devices. Such host devices may be instances of devices that use memory to perform processes, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, computers, laptop computers, tablet computers, smart phones, cellular phones, wearable devices, Internet-connected devices, some other fixed or portable electronic devices, and the like. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof that implements the functions of the external memory controller 105. In some cases, the external memory controller 105 may be referred to as a host or host device. In some examples, the system 100 is a graphics card. In some examples, the host device may identify a set of voltages that may indicate that the memory device is operating at or near a resonant frequency. The set of voltages may be a set of oscillating voltages that establish a periodic pattern trend toward a falling voltage, which may cause the memory device to operate suboptimally.

[0030] In some cases, memory device 110 may be a standalone device or component configured to communicate with other components of system 100 and provide physical memory addresses or other space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to cooperate with at least one or more different types of systems 100. Signaling between components of system 100 and memory device 110 may be used to support modulation schemes for modulating signals, different pin designs for communicating signals, different packaging of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions, and / or other factors.

[0031] The memory device 110 may be configured to store data for components of the system 100. In some cases, the memory device 110 may act as a slave device of the system 100 (e.g., responding to and executing commands provided by the system 100 through the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) that support a desired or specified capacity for data storage. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0032] System 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may electronically communicate with each other using a bus 140.

[0033] Processor 120 may be configured to control at least a portion of system 100. Processor 120 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. In such cases, processor 120 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a system on a chip (SoC), among other examples.

[0034] BIOS component 125 may be a software component including a BIOS operating as firmware that may initialize and run the various hardware components of system 100. BIOS component 125 may also manage the flow of data between processor 120 and various components of system 100, such as peripheral components 130, I / O controller 135, etc. BIOS component 125 may include a program or software stored in a read-only memory (ROM), flash memory, or any other non-volatile memory.

[0035] Peripheral component 130 may be any input device or output device, or an interface for such a device, that may be integrated into or with system 100. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a peripheral component interconnect (PCI) or a dedicated graphics port. Peripheral component 130 may be other components that are understood by those skilled in the art to be peripheral devices.

[0036] I / O controller 135 may manage data communications between processor 120 and peripheral components 130, input device 145, or output device 150. I / O controller 135 may manage peripheral devices that are not integrated into or with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0037] Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface or an interface with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0038] Output 150 may represent a device or signal external to system 100 that is configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, an audio speaker, a printing device, or another processor on a printed circuit board, etc. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0039] The components of system 100 may be composed of general or special purpose circuitry designed to perform their functions. This may include various circuit elements configured to perform the functions described herein, such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements. In some examples, an on-die monitoring component (e.g., an on-die oscilloscope) may dynamically calculate the spectrum of the memory device signal on the fly. The on-die component may be able to read the instantaneous waveform that can provide spectrum information. This spectrum information can be compared to a predetermined lookup table and used to identify the resonant frequency before it occurs.

[0040] The memory device 110 may include a device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). The memory array 170 may be a collection (e.g., a grid) of memory cells, each of which is configured to store at least one bit of digital data. Figure 2 Features of memory array 170 and / or memory cells are described in greater detail.

[0041] The memory device 110 may be an example of a two-dimensional (2D) memory cell array or may be an example of a three-dimensional (3D) memory cell array. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, multiple memory dies 160-N may be stacked on top of each other or next to each other. In some cases, the memory dies 160-N in a 3D memory device may be referred to as a stack, a tier, a layer, or a die. A 3D memory device may include any number of stacked memory dies 160-N (e.g., two high stacked memory dies, three high stacked memory dies, four high stacked memory dies, five high stacked memory dies, six high stacked memory dies, seven high stacked memory dies, eight high stacked memory dies). This can increase the number of memory cells that can be positioned on a substrate compared to a single 2D memory device, which in turn can reduce production costs or increase performance of the memory array, or both. In some 3D memory devices, different stacks can share at least one common access line, such that some stacks can share at least one of a word line, a digit line, and / or a plate line.

[0042] The device memory controller 155 may include circuits or components configured to control the operation of the memory device 110. Thus, the device memory controller 155 may include hardware, firmware, and software that enables the memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information regarding the memory device 110. The device memory controller 155 may be configured to communicate with an external memory controller 105, one or more memory dies 160, or a processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105. For example, the memory device 110 may receive a write command indicating that the memory device 110 is to store certain data on behalf of a component of the system 100 (e.g., the processor 120), or receive a read command indicating that the memory device 110 is to provide certain data stored in the memory die 160 to a component of the system 100 (e.g., the processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating and transmitting signals to the external memory controller 105, logic, decoders, amplifiers, filters, etc. In some examples, the memory device controller may identify a periodic pattern or oscillating voltage that may be trending toward a falling voltage. The controller may then request new command signaling that may change the current demand, thus preventing undesirable voltage oscillations and resonant frequencies.

[0043] A local memory controller 165 (e.g., local to the memory die 160) may be configured to control the operation of the memory die 160. Moreover, the local memory controller 165 may be configured to communicate with the device memory controller 155 (e.g., receive and transmit data and / or commands). The local memory controller 165 may support the device memory controller 155 to control the operation of the memory device 110 as described herein. In some cases, the memory device 110 does not include a device memory controller 155, and the local memory controller 165 or the external memory controller 105 may perform the various functions described herein. Thus, the local memory controller 165 may be configured to communicate with the device memory controller 155, to communicate with other local memory controllers 165, or to communicate directly with the external memory controller 105 or the processor 120.

[0044] The external memory controller 105 may be configured to enable communication of information, data, and / or commands between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 may act as a liaison between the components of the system 100 and the memory device 110, so that the components of the system 100 may not need to know the operating details of the memory device. The components of the system 100 may present requests (e.g., read commands or write commands) to the external memory controller 105 for the external memory controller 105 to satisfy. The external memory controller 105 may convert or translate communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0045] In some cases, the external memory controller 105 or other components of the system 100, or the functions thereof described herein, may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 120 or other components of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or the functions thereof described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110, such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Likewise, in some cases, one or more functions attributed herein to device memory controller 155 or local memory controller 165 may in some cases be performed by external memory controller 105 (separate from or included in processor 120 ).

[0046] Components of system 100 may exchange information with memory device 110 using a plurality of channels 115. In some examples, channels 115 may enable communication between external memory controller 105 and memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 may include a first terminal including one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be configured to function as part of a channel.

[0047] In some cases, the pins or pads of the terminals may be part of a signal path of channel 115. Additional signal paths may be coupled with the terminals of the channel for routing signals within components of system 100. For example, memory device 110 may include signal paths (e.g., internal to memory device 110 or a component thereof, such as a signal path internal to memory die 160) that route signals from the terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0048] Channel 115 (and associated signal paths and terminals) may be dedicated to conveying a specific type of information. In some cases, channel 115 may be an aggregate channel and may therefore include multiple individual channels. For example, data channel 190 may be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), etc. Signals conveyed via the channel may use double data rate (DDR) signaling. For example, some symbols of the signal may be recorded on the rising edge of the clock signal, and other symbols of the signal may be recorded on the falling edge of the clock signal. Signals conveyed via the channel may use single data rate (SDR) signaling. For example, one symbol of the signal may be recorded for each clock cycle.

[0049] In some cases, channels 115 may include one or more command and address (CA) channels 186. CA channels 186 may be configured to communicate commands between external memory controller 105 and memory device 110, including control information associated with the commands (e.g., address information). For example, CA channels 186 may include a read command regarding the address of the desired data. In some cases, CA channels 186 may register on a rising clock signal edge and / or a falling clock signal edge. In some cases, CA channels 186 may include any number of signal paths to decode address and command data (e.g., eight or nine signal paths).

[0050] In some cases, the channel 115 may include one or more clock signal (CK) channels 188. The CK channel 188 may be configured to communicate one or more common clock signals between the external memory controller 105 and the memory device 110. Each clock signal may be configured to oscillate between a high state and a low state and coordinate the actions of the external memory controller 105 and the memory device 110. In some cases, the clock signal may be a differential output (e.g., a CK_t signal and a CK_c signal) and the signal path of the CK channel 188 may be configured accordingly. In some cases, the clock signal may be single-ended. The CK channel 188 may include any number of signal paths. In some cases, the clock signal CK (e.g., the CK_t signal and the CK_c signal) may provide a timing reference for command and addressing operations of the memory device 110 or other system-wide operations of the memory device 110. The clock signal CK may therefore be variously referred to as a control clock signal CK, a command clock signal CK, or a system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0051] In some cases, channels 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to communicate data and / or control information between external memory controller 105 and memory device 110. For example, data channels 190 may communicate (e.g., bidirectionally) information to be written to memory device 110 or information to be read from memory device 110.

[0052] In some cases, channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may include any number of signal paths.

[0053] In some cases, other channels 192 may include one or more write clock signal (WCK) channels. Although the 'W' in WCK may nominally stand for "write", the write clock signal WCK (e.g., WCK_t signal and WCK_c signal) may provide a timing reference generally used for access operations of the memory device 110 (e.g., a timing reference for both read and write operations). Therefore, the write clock signal WCK may also be referred to as the data clock signal WCK. The WCK channel may be configured to communicate a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write operations or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., WCK_t signal and WCK_c signal), and the signal path of the WCK channel may be configured accordingly. The WCK channel may include any number of signal paths. The data clock signal WCK may be generated by a data clock, which may include one or more hardware components (eg, oscillators, crystals, logic gates, transistors, etc.).

[0054] The channel 115 may use a variety of different architectures to couple the external memory controller 105 with the memory device 110. Examples of various architectures may include a bus, a point-to-point connection, a crossbar switch, a high-density interposer such as a silicon interposer, or a channel formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer such as a silicon interposer or a glass interposer.

[0055] A variety of different modulation schemes may be used to modulate the signals communicated over the channel 115. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate the signals communicated between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme with M equal to two. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., a symbol may represent a logical 1 or a logical 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return to zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and the like.

[0056] In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals communicated between the external memory controller 105 and the memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one bit of digital data (e.g., a symbol may represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM4, PAM8, etc., quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), etc. A multi-symbol signal or PAM4 signal may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one bit of information. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or high-order modulation schemes and symbols.

[0057] Figure 2 An example of a memory die 200 according to an example disclosed herein is illustrated. The memory die 200 may be a reference Figure 1 1. An example of a memory die 160 is described. In some cases, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, the memory cell 205 may be configured to store one bit of digital logic (e.g., logic 0 and logic 1) at a time. In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of digital logic (e.g., logic 00, logic 01, logic 10, or logic 11) at a time.

[0058] The memory cell 205 can store a charge representing a programmable state in a capacitor. A DRAM architecture can include a capacitor that includes dielectric material to store a charge representing a programmable state. In other memory architectures, other storage devices and components are also possible. For example, a nonlinear dielectric material can be used.

[0059] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting access lines such as word line 210 and / or digit line 215. In some cases, digit line 215 may also be referred to as a bit line. References to access lines, word lines, and digit lines, or the like, may be interchangeable without affecting understanding or operation. Activating or selecting word line 210 or digit line 215 may include applying a voltage to the corresponding line.

[0060] The memory die 200 may include access lines (e.g., word lines 210 and digit lines 215) arranged in a grid-like pattern. Memory cells 205 may be positioned at the intersections of the word lines 210 and digit lines 215. By biasing the word lines 210 and digit lines 215 (e.g., applying a voltage to the word lines 210 or the digit lines 215), a single memory cell 205 may be accessed at their intersections.

[0061] Access to the memory cell 205 may be controlled by a row decoder 220 or a column decoder 225. For example, the row decoder 220 may receive a row address from the local memory controller 260 and activate the word line 210 based on the received row address. The column decoder 225 may receive a column address from the local memory controller 260 and may activate the digit line 215 based on the received column address. For example, the memory die 200 may include a plurality of word lines 210 labeled WL_1 to WL_M and a plurality of digit lines 215 labeled DL_1 to DL_N, where M and N depend on the size of the memory array. Thus, by activating a word line 210 and a digit line 215, such as WL_1 and DL_3, a memory cell 205 at the intersection thereof may be accessed. The intersection of a word line 210 and a digit line 215 in a two-dimensional or three-dimensional configuration may be referred to as the address of the memory cell 205.

[0062] Memory cell 205 may include a logic storage component, such as capacitor 230 and switching component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled to switching component 235, and a second node of capacitor 230 may be coupled to voltage source 240. In some cases, voltage source 240 may be a cell plate reference voltage, such as Vpl, or may be grounded, such as Vss. In some cases, voltage source 240 may be an example of a plate line coupled to a plate line driver. Switching component 235 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between two components.

[0063] Selecting or deselecting the memory cell 205 can be achieved by activating or deactivating the switching component 235. The capacitor 230 can be in electronic communication with the digital line 215 using the switching component 235. For example, when the switching component 235 is deactivated, the capacitor 230 can be isolated from the digital line 215, and when the switching component 235 is activated, the capacitor 230 can be coupled to the digital line 215. In some cases, the switching component 235 is a transistor, and its operation can be controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source can be greater than or less than the threshold voltage of the transistor. In some cases, the switching component 235 can be a p-type transistor or an n-type transistor. The word line 210 can be in electronic communication with the gate of the switching component 235, and the switching component 235 can be activated / deactivated based on the voltage applied to the word line 210.

[0064] The word line 210 can be a conductive line in electronic communication with the memory cell 205 for performing access operations on the memory cell 205. In some architectures, the word line 210 can be in electronic communication with a gate of a switching element 235 of the memory cell 205 and can be configured to control the switching element 235 of the memory cell. In some architectures, the word line 210 can be in electronic communication with a node of a capacitor of the memory cell 205, and the memory cell 205 may not include a switching element.

[0065] The digit line 215 can be a conductive line connecting the memory cell 205 and the sensing component 245. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during portions of an access operation. For example, the word line 210 and the switching component 235 of the memory cell 205 can be configured to couple and / or isolate the capacitor 230 of the memory cell 205 and the digit line 215. In some architectures, the memory cell 205 can be in electronic communication (e.g., constant) with the digit line 215.

[0066] The sensing component 245 may be configured to detect a state (e.g., charge) stored on the capacitor 230 of the memory cell 205, and determine the logic state of the memory cell 205 based on the stored state. In some cases, the charge stored by the memory cell 205 may be very small. Therefore, the sensing component 245 may include one or more sense amplifiers to amplify the signal output by the memory cell 205. The sense amplifier may detect a small change in the charge of the digit line 215 during a read operation, and may generate a signal corresponding to a logic state 0 or a logic state 1 based on the detected charge. During a read operation, the capacitor 230 of the memory cell 205 may output a signal (e.g., release charge) to its corresponding digit line 215. The signal may cause the voltage of the digit line 215 to change. The sensing component 245 may be configured to compare the signal received from the memory cell 205 across the digit line 215 with a reference signal 250 (e.g., a reference voltage). The sensing component 245 may determine the stored state of the memory cell 205 based on the comparison. For example, in binary signaling, if the digit line 215 has a higher voltage than the reference signal 250, the sensing component 245 can determine that the storage state of the memory cell 205 is a logic 1, and if the digit line 215 has a lower voltage than the reference signal 250, the sensing component 245 can determine that the storage state of the memory cell 205 is a logic 0. The sensing component 245 can include various transistors or amplifiers to detect and amplify the difference in signals. The detected logic state of the memory cell 205 can be provided as an output of the sensing component 245 (e.g., provided to the input / output 255), and the detected logic state can be indicated to another component of the memory device 110 including the memory die 200, such as the device memory controller 155 (e.g., directly or using the local memory controller 260).

[0067] The local memory controller 260 may control the operation of the memory cell 205 through various components (eg, the row decoder 220, the column decoder 225, and the sensing component 245). The local memory controller 260 may be a reference Figure 1 105 . In some cases, one or more of the row decoder 220, the column decoder 225, and the sensing component 245 can be co-located with the local memory controller 260. The local memory controller 260 can be configured to receive data from the external memory controller 105 (or reference Figure 1The local memory controller 260 may receive commands and / or data, translate the commands and / or data into information that the memory die 200 may use, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the external memory controller 105 (or the device memory controller 155) in response to performing one or more operations. The local memory controller 260 may generate row signals and column address signals to activate the target word lines 210 and the target digital lines 215. The local memory controller 260 may also generate and control various voltages or currents used during the operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltage or current described herein may be adjusted or varied, and may be different for the various operations described in the process of operating the memory die 200. In some examples, the memory device controller may identify a periodic pattern or oscillating voltage that may tend to drop in voltage. The controller may then request new command signaling that may change the current demand, thus preventing undesirable voltage oscillations and resonant frequencies.

[0068] In some cases, the local memory controller 260 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 may identify a target memory cell 205 on which a write operation is to be performed. The local memory controller 260 may identify a target word line 210 and a target digit line 215 in electronic communication with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. Local memory controller 260 may apply a specific signal (eg, voltage) to digit line 215 during a write operation to store a specific state (eg, charge) in capacitor 230 of memory cell 205 that may indicate a desired logic state.

[0069] In some cases, the local memory controller 260 may be configured to perform a read operation (e.g., a sensing operation) on one or more memory cells 205 of the memory die 200. During the read operation, the logic state stored in the memory cell 205 of the memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 260 may identify the target memory cell 205 on which the read operation is to be performed. The local memory controller 260 may identify the target word line 210 and the target digit line 215 in electronic communication with the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 may activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The target memory cell 205 may pass a signal to the sensing component 245 in response to the biased access line. The sensing component 245 may amplify the signal. The local memory controller 260 may trigger the sensing component 245 (e.g., latch the sensing component), thereby comparing the signal received from the memory cell 205 to the reference signal 250. Based on the comparison, the sensing component 245 may determine the logic state stored on the memory cell 205. As part of the read operation, the local memory controller 260 may communicate the logic state stored on the memory cell 205 to the external memory controller 105 (or the device memory controller 155).

[0070] In some memory architectures, accessing the memory cell 205 may degrade or destroy the logical state stored in the memory cell 205. For example, a read operation performed in a DRAM architecture may partially or completely discharge the capacitor of the target memory cell. The local memory controller 260 may perform a rewrite operation or a refresh operation to return the memory cell to its original logical state. The local memory controller 260 may rewrite the logical state to the target memory cell after the read operation. In some cases, the rewrite operation may be considered part of the read operation. In addition, activating a single access line (e.g., word line 210) may disturb the state stored in some memory cells that are in electronic communication with the access line. Therefore, a rewrite operation or a refresh operation may be performed on one or more memory cells that may not have been accessed.

[0071] Figure 3An example of a power delivery network 300 supporting predictive power management for a memory device according to examples as disclosed herein is illustrated. The system 300 may include a printed circuit board (PCB) regulator 305, a sensing point 310, a representative impedance 315 associated with a PCB capacitor, a representative impedance 320 associated with a package impedance, a representative impedance 325 associated with a die, and a die current 330. The representative impedance 325 for the die and the memory die current 330 may be a representative model of a memory die (not shown), which may be as described in reference to FIG. Figure 1 and 2 An example of a memory die 200 is depicted.

[0072] The power delivery network 300 may be an impedance model of a physical power delivery network and may include representative memory device elements. The power delivery network 300 may include elements such as, but not limited to, voltage regulators, PCBs, interposers, packages encapsulating memory dies, memory dies, etc. In some examples, the power delivery network may include one or more voltage rails that are coupled to the memory cell array and configured to deliver power to the memory cell array. These physical elements of the power delivery network 300 may be modeled with current sources and some general and substantially equivalent impedance elements, such as Figure 3 As described in . Figure 3 The equivalent impedance elements of are shown as regulators, resistors, inductors, capacitors, etc., and are examples of relevant losses of the physical power delivery network.

[0073] Capacitors may be located on the PCB to stabilize voltages associated with the voltage regulator 305, and to keep such voltages associated with the voltage regulator 305 stable. In some cases, the PCB capacitors may have parasitics associated with them (which may be modeled by capacitors, inductors, and resistors), and the PCB may additionally have parasitics associated with it (which may also be modeled by capacitors, inductors, and resistors). Additionally, the package encapsulated memory die may have impedances associated with it that may be attributable to metal and vias and may be modeled using inductors, capacitors, and resistors.

[0074] The PCB capacitor parasitics 315 can be illustrated and modeled as representative parasitic elements. The representative parasitic elements can indicate the impedance of the PCB capacitor parasitics and can be Figure 3 3. The package impedance 320 can be modeled with inductors and resistors, and the impedance 325 of the die can be modeled with capacitors and resistors. Figure 3 The elements representing the impedance of the power delivery network 300 illustrated in are not limiting, and the impedance of the power delivery network 300 may be modeled using any suitable elements.

[0075] The voltage regulator 305 may be supplied with a voltage and may increase and decrease the voltage depending on the power required. The voltage regulator 305 may be a voltage controlled source having an output impedance and may be monitored at the sensing point 310. In some examples, the PCB capacitor may discharge (e.g., when the voltage rail contracts), and the power delivery network may react with a voltage drop or rebound depending on the direction of the current. In this example, the voltage regulator 305 may track the sensing point 310 and may adjust the output voltage to compensate for the voltage drop or rebound. The voltage drop or rebound may cause the operating voltage of the memory die to drop below or exceed the memory die voltage range, which may cause latency in memory operation and in some cases memory errors.

[0076] Figure 4 An example of a graph 400 is illustrated to support predictive power management for a memory device according to examples as disclosed herein. Graph 400 may be an example of an impedance curve from a voltage regulator to a memory device and illustrates die side impedance. The representative impedance may include an impedance model of a memory die ( Figure 4 Not shown), which may be as shown in reference Figure 2 An example of a memory die 200 is depicted.

[0077] The power delivery network can be designed to minimize impedance to obtain frequency independent impedance, and maintain a steady state frequency so that the voltage drop between the ideal case and the memory die can be close to zero or a fixed number. In some cases, for a physical power delivery network, the impedance can vary depending on the frequency. Graph 400 illustrates one example of the frequency dependent behavior of the impedance, and any suitable curve can be used to illustrate the frequency dependent behavior of the impedance. In addition, the inflection point, magnitude, and slope / ratio can vary and can depend on the design of the power delivery network.

[0078] At lower frequencies and at 405, the impedance may be minimal because the voltage regulator may be able to address a significant portion of the DC power demand. As the frequency increases, at 410, the gain in voltage regulator performance may degrade and produce a higher effective impedance. Depending on the voltage regulator design, regulation may become inefficient and the PCB capacitor may address the impedance at 415, so the impedance may begin to decrease even as the frequency increases. The impedance of the capacitor may be expressed as 1 / 2πfC, where 2πf or ω may be the frequency and C may be the capacitance. As a result, the impedance of the PCB capacitor may decrease impedance with frequency. However, capacitors are not ideal, so the impedance may not decrease to zero. In general, capacitors may have intrinsic resistors and inductors associated with them due to their location on the PCB, so the impedance may decrease at 415, flatten, and then begin to increase at 420 due to the inductive effects of the PCB capacitor and the package.

[0079] At 420, the impedance curve may increase or rise due in part to the parasitic and inductive effects of the PCB capacitors and also due to the package inductance and resistance. At 425, the impedance begins to decrease due to the memory die capacitors, which address the impedance in the higher frequencies in the range of tens to hundreds of MHz and above. In practical applications, the memory die capacitors may not be ideal capacitors, so there may be parasitic equivalent series resistance (ESR) and equivalent series inductance (ESL) associated with the memory die capacitors. ESR and ESL may be typical parasitics associated with power delivery networks.

[0080] In general, higher impedance may not be desirable because it may cause voltage drops in the power delivery on the integrated circuit. Figure 4 In an example, it may be necessary to mitigate resonances around range 430, which may be in the approximate range of and around tens of MHz (e.g., 20 MHz). In one example, the impedance may be reduced by adding more memory die capacitors or increasing the size of the capacitors on the memory die itself, but this may use more physical area on the PCB and may not be practical without any additional mitigation factors.

[0081] Higher impedance can increase current demand, which can cause voltage droop. When the voltage drops below the voltage specification of the memory die or above the voltage specification of the memory die, it can cause the memory die to operate at suboptimal levels, which can introduce latency into memory operations or, in some cases, memory errors.

[0082] In some instances, various command signaling from a host device may induce different current demands. The voltage may respond to different current demands by oscillating between high and low voltages. Identifying the voltage response and correlating it to the current demand, and in some cases, to the command signaling, may help mitigate voltage sag issues before they occur. In some instances, the periodic demand for current may cause the voltage to oscillate, which may cause issues with jitter and / or timing requirements of the memory die, which may be problematic. Therefore, minimizing the oscillations may ensure that commands can be executed by the memory die at the correct timing.

[0083] In some examples, problems can be identified by monitoring resonance over a duration or period of time. Additionally, the amount of periodic oscillations that occur over a certain duration can be another indicator of a voltage drop problem, and it can be used to identify problematic voltage oscillations before reaching the resonant frequency.

[0084] In some examples, correlations can be determined by taking a Fourier transform of the signal to identify patterns and identify peaks in the spectrum. As the voltage continues to oscillate, the peaks in the spectrum can indicate that the voltage will drop below the desired operating voltage range. By identifying patterns and / or spectrum peaks, corrective actions can be taken to mitigate the voltage drop before it drops below the voltage specification range.

[0085] In some instances, a sensing element or sensor may sense the voltage on the die, and then the spectrum of the signal may be dynamically calculated on the fly. In some instances, an on-die oscilloscope capable of reading instantaneous waveforms may provide spectrum information. A predetermined lookup table may be utilized to identify and compare the calculated spectrum with a predetermined spectrum (e.g., a resonant frequency) that may cause a problem. In some instances, if the spectrum has a certain minimum amount of frequency modulation in a region, or if the frequency modulation may exceed a predetermined value, corrective actions may be performed to mitigate the problem before it occurs. In some instances, a sensor may be positioned as close as possible to the memory die to monitor the voltage on the die.

[0086] In some instances, corrective actions to space out the operations, either through spectrum analysis or through a feedback mechanism (e.g., monitoring voltage), can mitigate the problem. Additionally, any appropriate corrective action that can break the oscillation mode and / or manipulate current demand, or any combination of appropriate corrective actions, can be used. In some instances, additional capacitors can be dynamically enabled to mitigate resonance.

[0087] Figure 5 An example of a process flow 500 for supporting predictive power management for a memory device according to examples as disclosed herein is illustrated. The process flow 500 may illustrate the functionality of and communication between a host device 505 and a memory device 510. In some examples, the memory device 510 may be a reference Figure 1 and 2 An example of a memory device 110 or memory die 200 is depicted. Process flow 500 illustrates an on-die implementation that supports predictive power management.

[0088] In some examples, at 515, host device 505 may transmit command signaling to memory device 510. The command signaling may be a function such as, but not limited to, a read or sense command, a write command, a refresh command, the like, and any combination thereof.

[0089] At 520, the memory device 510 can receive command signaling from the host device 505, and the memory device 510 can process the received command signaling. The memory device can process the command by performing appropriate functions (e.g., executing a read command). The current demand can be used to execute the received command. Therefore, the resulting voltage can be used to execute the command to the memory device 510.

[0090] At 525, memory device 510 can monitor one or more voltages of a power delivery network associated with the memory die and / or memory device 510. The one or more voltages can be monitored using a sensing element or sensor that can be positioned as close to the memory die as possible.

[0091] At 530, the one or more voltages may be compared to a set of voltages for the power delivery network. The set of voltages may indicate that the power delivery network is operating at a first frequency, which may be an undesirable resonant frequency in some examples. In some examples, the set of voltages for the power delivery network may be identified before the memory device 510 receives a command from the host device 505. The set of voltages may indicate that the power delivery network is operating at a first frequency, which may be a resonant frequency. The set of voltages may be compared to a set of voltages for the power delivery network. The set of voltages may indicate that the power delivery network is operating at a first frequency, which may be a resonant frequency. Figure 3 and 4 Modeling the power delivery network to identify the set of voltages is described. By identifying the set of voltages that indicates operation at a resonant frequency, command signaling can be changed before the power delivery network reaches the resonant frequency.

[0092] At 535, the memory device 510 may determine whether one or more voltages of the power delivery network satisfy a condition. In some examples, the condition may be whether the one or more voltages establish a predetermined pattern indicating operation at a resonant frequency or operation at or near a resonant frequency for a certain duration. In some examples, the condition may be whether the one or more voltages are below a predetermined or threshold voltage, which may be a dropped voltage that exceeds an operating voltage specification range of the memory die. In some examples, the determination may be made based at least in part on comparing the one or more voltages to the set of voltages. In some examples, determining whether the one or more voltages satisfy a condition may occur before the power delivery network operates at the resonant frequency.

[0093] In addition, in some examples, it can be determined whether the one or more voltages meet the condition by monitoring the instantaneous waveform through an on-die component. The on-die component can be an oscilloscope and can provide spectrum information for identifying a resonant frequency. In some examples, it can be determined whether the one or more voltages meet the condition by monitoring the spectrum information associated with the one or more voltages using one or more instantaneous waveforms. In some examples, the on-die component can provide spectrum information for identifying a resonant frequency. In addition, in some examples, it can be determined whether the one or more voltages meet the condition by identifying the number of oscillation cycles associated with the one or more voltages. The number of oscillations indicating a resonant frequency can be determined, and therefore, by identifying the voltage oscillation cycle, the resonant frequency of the power delivery network can be mitigated before it occurs.

[0094] In some examples, when it is determined that a condition is met, one or more additional capacitors on the PCB may be enabled to change and reduce the impedance associated with the memory die. The one or more capacitors may be coupled to the power delivery network based on whether the condition is met. By enabling the additional capacitors, the first frequency or resonant frequency of the power delivery network may be mitigated before the first frequency or resonant frequency occurs. In some examples, the condition may be one or more of: operating at the resonant frequency for a certain duration, a falling threshold associated with the one or more voltages, or a set of predetermined voltages associated with the operating resonant frequency, or any combination thereof.

[0095] At 540, signaling or an indication indicating that a condition is satisfied may be transmitted from the memory device 510 to the host device 505. At 545, the timing of at least one command associated with the memory device 510 and / or the memory die may be adjusted at or by the host device 505. By adjusting the timing of the commands, the commands may be spaced apart so that the current demand may produce an undesirable oscillating voltage that may be at a resonant frequency. At 550, a new timing of the command may be transmitted from the host device 505 to the memory device 510. The new timing of the command may be received from the host device 505 and may be control information including the timing of the command. The timing of the command may be different from the previous timing associated with the command. If the previous timing is executed, it may cause a current demand that may cause an undesirable voltage oscillation that causes a voltage drop. In contrast, the new timing may alleviate the current demand, voltage oscillation, or voltage drop, or a combination thereof.

[0096] In some examples, the timing of commands that may cause the power delivery network to operate at a first frequency, which may be a resonant frequency, may be identified. Identification of the undesirable timing of commands may be performed before the resonant frequency occurs, such that the timing of commands may be identified and mitigated before the power delivery network operates at the resonant frequency. Further, a number of oscillation cycles may be identified, wherein a different minimum value associated with each of the oscillation cycles corresponds to a voltage approaching the condition for each oscillation cycle. By identifying the number of oscillation cycles, voltage trends toward undesirable conditions may be identified before they occur, and corrective action may be performed.

[0097] Figure 6 An example of a process flow 600 for supporting predictive power management for a memory device according to examples as disclosed herein is illustrated. The process flow 600 may illustrate the functionality of and communication between a host device 605 and a memory device 610. In some examples, the memory device 610 may be a reference Figure 1 and 2 An example of a memory device 110 or memory die 200 is depicted. Process flow 600 illustrates a host device implementation that supports predictive power management.

[0098] like Figure 6 , at 615, the host device 605 can identify a set of voltages that can indicate that the memory device 610 is operating at or near a first frequency, which can be a resonant frequency. Additionally, the set of voltages can be a set of oscillating voltages that establish a periodic pattern trend toward a decreasing voltage, which can cause the memory device 610 to operate suboptimally.

[0099] In some examples, at 620, the host device 605 may transmit command signaling to the memory device 610. The command signaling may be a function such as, but not limited to, a read or sense command, a write command, a refresh command, the like, and any combination thereof.

[0100] The memory device 610 may receive command signaling from the host device 605, and at 625, the memory device 610 may process the received command signaling. At 625, the memory device 610 may process the command by performing an appropriate function (e.g., executing a read command). The current demand may be used to execute the received command. Thus, the resulting voltage may be used to execute the command to the memory device 610.

[0101] At 630, one or more voltages may be monitored at the memory die. The voltages may be monitored by sensing elements and / or sensors, and the sensors may be located as close to the memory die as practicable. At 635, the monitored voltages may be transmitted from the memory device 610. Thus, the host device 605 may receive one or more voltages of the power delivery network associated with the memory die.

[0102] The one or more voltages may be compared to a set of voltages of the power delivery network at 640. The set of voltages may indicate that the power delivery network is operating at a first frequency, which in some examples may be an undesirable resonant frequency.

[0103] At 645, the host device 605 may determine whether one or more voltages of the power delivery network meet a condition. In some examples, the condition may be whether the one or more voltages establish a predetermined pattern indicating operation at a resonant frequency. In some examples, the condition may be whether the one or more voltages are below a predetermined voltage, which may be a dropped voltage that exceeds an operating voltage specification range. In some examples, the determination may be made based at least in part on comparing the monitored one or more voltages to the set of voltages. In some examples, the condition may be one or more of: operating at a resonant frequency for a certain duration, a dropped threshold associated with the one or more voltages, or a set of predetermined voltages associated with an operating resonant frequency, or any combination thereof.

[0104] At 650, the timing of at least one command associated with the memory device 610 and / or the memory die may be determined at the host device 605. By determining and adjusting the timing of the commands, the commands may be spaced apart so that the current demand may produce an undesirable oscillating voltage that may be at a resonant frequency. At 655, the new timing of the command may be transmitted from the host device 605 to the memory device 610. Additionally, the timing of the command may be based on whether one or more voltages meet a condition as described herein. In some examples, a correlation may be identified between a previous timing of the command and the received indication, wherein the determination of the timing may be based at least in part on identifying this correlation.

[0105] Figure 7 A block diagram 700 is shown of a memory device 705 supporting predictive power management according to examples as disclosed herein. The memory device 705 may be a memory device as described in reference Figures 1 to 6 Memory device 705 may include a voltage monitoring component 710, a comparison component 715, a determination component 720, a timing component 725, a coupling component 730, a spectrum monitoring component 735, and a communication component 740. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0106] Voltage monitoring component 710 can monitor one or more voltages of a power delivery network associated with a memory die. In some cases, the power delivery network includes one or more voltage rails coupled to and configured to deliver power to the memory cell array.

[0107] The comparison component 715 can compare the one or more voltages to a set of voltages of the power delivery network that indicates the power delivery network operates at a first frequency. In some examples, the comparison component 715 can identify a set of voltages of the power delivery network that indicates the power delivery network operates at the first frequency, wherein comparing the one or more voltages to the set of voltages is based on identifying the set of voltages. In some examples, determining whether the one or more voltages satisfy a condition occurs before the power delivery network operates at a resonant frequency, wherein the first frequency comprises a resonant frequency.

[0108] In some examples, the comparison component 715 can determine that a voltage in the one or more voltages drops below a threshold, wherein the adjustment timing is based on determining that the voltage drops below the threshold. In some examples, the condition includes operating at the resonant frequency for a certain duration, a drop threshold associated with the one or more voltages, or a set of predetermined voltages associated with the operating resonant frequency, or a combination thereof.

[0109] The determining component 720 can determine whether one or more voltages of the power delivery network meet a condition based on comparing the one or more voltages to the set of voltages. In some examples, determining whether the power delivery network operates at a resonant frequency for a certain duration can be based on the one or more voltages, wherein the first frequency includes the resonant frequency. In some examples, the determining component 720 can identify a number of oscillation cycles associated with the one or more voltages.

[0110] The timing component 725 can adjust the timing of at least one command associated with the memory die based on determining whether the one or more voltages satisfy the condition. In some examples, the timing component 725 can identify the timing of the command that causes the power delivery network to operate at a first frequency, wherein determining that the one or more voltages satisfy the condition is based on identifying the timing of the command.

[0111] Coupling component 730 can couple at least one additional capacitor to the power delivery network based on determining whether the one or more voltages satisfy a condition.

[0112] The spectrum monitoring component 735 can monitor spectrum information associated with the one or more voltages using one or more transient waveforms.

[0113] The communication component 740 may receive control information including timing of at least one command from the host device that is different from a previous timing associated with the at least one command, wherein adjusting the timing is based on receiving the control information. In some examples, the communication component 740 may transmit an indication that the one or more voltages satisfy a condition to the host device. In some examples, the communication component 740 may receive control information including timing of at least one command from the host device based on transmitting the indication, wherein adjusting the timing is based on receiving the control information.

[0114] Figure 8 A block diagram 800 is shown of a host device 805 supporting predictive power management according to examples as disclosed herein. The host device 805 may be a Figures 1 to 6 An example of aspects of the described host device. Host device 805 can include a communication component 810, a comparison component 815, a determination component 820, and a timing component 825. Each of these modules can communicate with each other directly or indirectly (eg, via one or more buses).

[0115] The communication component 810 can receive one or more voltages of a power delivery network associated with the memory die at the host device. In some examples, the communication component 810 can transmit the timing of at least one command associated with the memory die to the memory die based on determining the timing of the at least one command.

[0116] In some examples, the communication component 810 may receive an indication at a host device that one or more voltages of a power delivery network on a memory die are configured to cause the power delivery network to operate at a resonant frequency for a duration. In some examples, the communication component 810 may transmit a timing of at least one command. In some examples, the communication component 810 may transmit at least one command with a timing determined based on receiving the indication.

[0117] The comparison component 815 can compare the one or more voltages to a set of voltages of the power delivery network that indicate the power delivery network is operating at a first frequency. In some examples, the comparison component 815 can identify a set of voltages of the power delivery network that indicate the power delivery network is operating at a first frequency, wherein comparing the one or more voltages to the set of voltages is based on identifying the set of voltages. In some examples, the comparison component 815 can determine that a voltage of the one or more voltages drops below a threshold, wherein adjusting the timing is based on determining that the voltage drops below the threshold.

[0118] The determining component 820 can determine whether one or more voltages of the power delivery network meet a condition based on comparing the one or more voltages to the set of voltages. In some examples, the determining component 820 can determine a timing of at least one command based on receiving the indication. In some examples, it is determined based on the one or more voltages whether the power delivery network operates at a resonant frequency for a certain duration, wherein the first frequency includes the resonant frequency.

[0119] The timing component 825 can determine the timing of at least one command associated with the memory die based on determining whether the one or more voltages satisfy the condition. In some examples, the timing component 825 can identify the timing of the command that causes the power delivery network to operate at a first frequency, wherein determining that the one or more voltages satisfy the condition is based on identifying the timing of the command.

[0120] In some examples, the timing component 825 can identify a previous timing of the at least one command based on determining whether the one or more voltages satisfy a condition, wherein the timing is different from the previous timing. In some examples, the timing component 825 can identify a correlation between a previous timing of the at least one command and receiving the indication, wherein determining the timing is based on identifying the correlation.

[0121] Fig. 9 A flow chart is shown that illustrates one or more methods 900 for supporting predictive power management according to aspects of the present disclosure. The operations of the method 900 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 900 may be implemented by a memory device or components thereof as described herein. Figure 7The memory device described herein performs. In some examples, the memory device may execute an instruction set to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0122] At 905, the memory device may monitor one or more voltages of a power delivery network associated with the memory die. The operations of 905 may be performed according to the methods described herein. In some examples, aspects of the operations of 905 may be described by reference to Figure 7 The voltage monitoring component described is implemented.

[0123] At 910, the memory device may compare the one or more voltages to a set of voltages of the power delivery network indicating that the power delivery network operates at a first frequency. The operations of 910 may be performed according to the methods described herein. In some examples, aspects of the operations of 910 may be described as in reference to Figure 7 The described comparison component performs.

[0124] At 915, the memory device may determine whether one or more voltages of the power delivery network meet a condition based on comparing the one or more voltages to the voltage set. The operations of 915 may be performed according to the methods described herein. In some examples, aspects of the operations of 915 may be described as in reference to Figure 7 The described determining components execute.

[0125] At 920, the memory device may adjust the timing of at least one command associated with the memory die based on determining whether the one or more voltages satisfy the condition. The operations of 920 may be performed according to the methods described herein. In some examples, aspects of the operations of 920 may be described as in reference to Figure 7 The described timing components are executed.

[0126] In some examples, an apparatus as described herein may perform one or more methods, such as method 900. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for monitoring one or more voltages of a power delivery network associated with a memory die; comparing the one or more voltages to a set of voltages of a power delivery network indicating that the power delivery network operates at a first frequency; determining whether the one or more voltages of the power delivery network satisfy a condition based on comparing the one or more voltages to the set of voltages; and adjusting timing of at least one command associated with the memory die based on determining whether the one or more voltages satisfy the condition.

[0127] Some examples of the method 900 and apparatus described herein may further include operations, features, means, or instructions for identifying a set of voltages of the power delivery network that indicates the power delivery network operates at a first frequency, wherein comparing the one or more voltages to the set of voltages may be based on identifying the set of voltages.

[0128] Some examples of the method 900 and apparatus described herein may further include operations, features, means, or instructions for coupling at least one additional capacitor to the power delivery network based on determining whether the one or more voltages satisfy a condition.

[0129] Some examples of the method 900 and apparatus described herein may further include operations, features, means, or instructions for determining whether the one or more voltages satisfy a condition prior to operating the power delivery network at a resonant frequency, wherein the first frequency includes the resonant frequency.

[0130] In some examples of the method 900 and apparatus described herein, determining whether the one or more voltages satisfy the condition may further include operations, features, means, or instructions for monitoring spectral information associated with the one or more voltages using one or more transient waveforms.

[0131] Some examples of the method 900 and apparatus described herein may further include operations, features, means, or instructions for determining that a voltage of the one or more voltages drops below a threshold, where adjusting the timing may be based on determining that the voltage drops below the threshold.

[0132] In some examples of the methods 900 and apparatus described herein, determining whether the one or more voltages satisfy a condition may further include operations, features, means, or instructions for determining whether the power delivery network operates at a resonant frequency for a duration based on the one or more voltages, wherein the first frequency includes the resonant frequency.

[0133] Some instances of the method 900 and apparatus described herein may further include operations, features, components, or instructions for receiving, from a host device, control information including a timing of at least one command, the timing being different from a previous timing associated with the at least one command, wherein adjusting the timing may be based on receiving the control information.

[0134] Some instances of the method 900 and apparatus described herein may further include operations, features, components, or instructions for: transmitting an indication that one or more voltages satisfy a condition to a host device; and receiving control information including the timing of at least one command from the host device based on transmitting the indication, wherein adjusting the timing may be based on receiving the control information.

[0135] Some examples of the method 900 and apparatus described herein may further include operations, features, means, or instructions for identifying a timing of a command to cause the power delivery network to operate at a first frequency, wherein determining the one or more voltage satisfaction conditions may be based on identifying the timing of the command.

[0136] In some examples of the method 900 and apparatus described herein, determining whether the one or more voltages satisfy the condition may further include operations, features, means, or instructions for identifying a number of oscillation cycles associated with the one or more voltages.

[0137]

[0096] In some examples of the method 900 and apparatus described herein, the power delivery network includes one or more voltage rails coupled to the memory cell array and configured to deliver power to the memory cell array.

[0138] In some examples of the method 900 and apparatus described herein, the condition includes operating at the resonant frequency for a duration, a falling threshold associated with one or more voltages, or a set of predetermined voltages associated with the operating resonant frequency, or a combination thereof.

[0139] Fig.10 A flow chart is shown that illustrates one or more methods 1000 of supporting predictive power management according to aspects of the present disclosure. The operations of the method 1000 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 1000 may be implemented by a memory device or components thereof as described herein. Figure 7 The memory device described herein performs. In some examples, the memory device may execute an instruction set to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0140] At 1005, the memory device may monitor one or more voltages of a power delivery network associated with the memory die. The operations of 1005 may be performed according to the methods described herein. In some examples, aspects of the operations of 1005 may be described by reference to Figure 7 The voltage monitoring component described is implemented.

[0141] At 1010, the memory device may identify a set of voltages of the power delivery network that indicates the power delivery network is operating at a first frequency based on monitoring the one or more voltages. The operations of 1010 may be performed according to the methods described herein. In some examples, aspects of the operations of 1010 may be described as in reference to Figure 7 The described comparison component performs.

[0142] At 1015, the memory device may compare the one or more voltages to the set of voltages based on identifying a set of voltages of the power delivery network that indicates the power delivery network operates at the first frequency. The operations of 1015 may be performed according to the methods described herein. In some examples, aspects of the operations of 1015 may be described as in reference to Figure 7 The described comparison component performs.

[0143] At 1020, the memory device may determine whether one or more voltages of the power delivery network meet a condition based on comparing the one or more voltages to the voltage set. The operations of 1020 may be performed according to the methods described herein. In some examples, aspects of the operations of 1020 may be described as in reference to Figure 7 The described determining components execute.

[0144] At 1025, the memory device may adjust the timing of at least one command associated with the memory die based on determining whether the one or more voltages satisfy the condition. The operations of 1025 may be performed according to the methods described herein. In some examples, aspects of the operations of 1025 may be described as in reference to Figure 7 The described timing components are executed.

[0145] Fig.11 A flow chart is shown that illustrates one or more methods 1100 for supporting predictive power management according to aspects of the present disclosure. The operations of the method 1100 may be implemented by a host device or components thereof as described herein. For example, the operations of the method 1100 may be implemented by a host device or components thereof as described herein. Figure 8 The host device described herein performs. In some examples, the host device may execute a set of instructions to control functional elements of the host device to perform the described functions. Additionally or alternatively, the host device may use dedicated hardware to perform various aspects of the described functions.

[0146] At 1105, the host device may receive one or more voltages of a power delivery network associated with the memory die at the host device. The operations of 1105 may be performed according to the methods described herein. In some examples, aspects of the operations of 1105 may be described as described with reference to Figure 8 The described communication components perform.

[0147] At 1110, the host device may compare the one or more voltages to a set of voltages of the power delivery network indicating that the power delivery network is operating at a first frequency. The operations of 1110 may be performed according to the methods described herein. In some examples, aspects of the operations of 1110 may be described as in reference to Figure 8 The described comparison component performs.

[0148] At 1115, the host device may determine whether one or more voltages of the power delivery network meet a condition based on comparing the one or more voltages to the set of voltages. The operations of 1115 may be performed according to the methods described herein. In some examples, aspects of the operations of 1115 may be described as in reference to Figure 8 The described determining components execute.

[0149] At 1120, the host device may determine the timing of at least one command associated with the memory die based on determining whether the one or more voltages satisfy the condition. The operations of 1120 may be performed according to the methods described herein. In some examples, aspects of the operations of 1120 may be described as in reference to Figure 8 The described timing components are executed.

[0150] At 1125, the host device may transmit the timing of at least one command associated with the memory die to the memory die based on determining the timing of the at least one command. The operations of 1125 may be performed according to the methods described herein. In some examples, aspects of the operations of 1125 may be described as in reference to Figure 8 The described communication components perform.

[0151] In some examples, an apparatus as described herein may perform one or more methods such as method 1100. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving, at a host device, one or more voltages of a power delivery network associated with a memory die; comparing the one or more voltages to a set of voltages of a power delivery network indicating that the power delivery network operates at a first frequency; determining whether the one or more voltages of the power delivery network satisfy a condition based on comparing the one or more voltages to the set of voltages; determining a timing of at least one command associated with the memory die based on determining whether the one or more voltages satisfy the condition; and transmitting the timing of at least one command associated with the memory die to the memory die based on determining the timing of the at least one command.

[0152] Some examples of the method 1100 and apparatus described herein may further include operations, features, means, or instructions for identifying a set of voltages of the power delivery network that indicates the power delivery network operates at a first frequency, wherein comparing the one or more voltages to the set of voltages may be based on identifying the set of voltages.

[0153] Some examples of the method 1100 and apparatus described herein may further include operations, features, means, or instructions for determining that a voltage of the one or more voltages drops below a threshold, where adjusting the timing may be based on determining that the voltage drops below the threshold.

[0154] In some examples of the methods 1100 and apparatus described herein, determining whether the one or more voltages satisfy a condition may further include operations, features, means, or instructions for determining whether the power delivery network operates at a resonant frequency for a certain duration based on the one or more voltages, wherein the first frequency includes the resonant frequency.

[0155] Some examples of the method 1100 and apparatus described herein may further include operations, features, means, or instructions for identifying a timing of a command to cause the power delivery network to operate at a first frequency, wherein determining the one or more voltage satisfaction conditions may be based on identifying the timing of the command.

[0156] Some examples of the method 1100 and apparatus described herein may further include operations, features, means, or instructions for identifying a previous timing of at least one command based on determining whether the one or more voltages satisfy a condition, wherein the timing may be different from the previous timing.

[0157] Fig.12 A flow chart is shown that illustrates one or more methods 1200 for supporting predictive power management according to aspects of the present disclosure. The operations of the method 1200 may be implemented by a host device or components thereof as described herein. For example, the operations of the method 1200 may be implemented by reference to Figure 8 The host device described herein performs. In some examples, the host device may execute a set of instructions to control functional elements of the host device to perform the described functions. Additionally or alternatively, the host device may use dedicated hardware to perform various aspects of the described functions.

[0158] At 1205, the host device may receive at the host device an indication that one or more voltages of the power delivery network on the memory die are configured to cause the power delivery network to operate at a resonant frequency for a certain duration. The operations of 1205 may be performed according to the methods described herein. In some examples, aspects of the operations of 1205 may be described as in reference to Figure 8 The described communication components perform.

[0159] At 1210, the host device may determine the timing of at least one command based on receiving the indication. The operations of 1210 may be performed according to the methods described herein. In some examples, aspects of the operations of 1210 may be described as in reference to Figure 8 The described determining components execute.

[0160] At 1215, the host device may transmit the timing of the at least one command. The operations of 1215 may be performed according to the methods described herein. In some examples, aspects of the operations of 1215 may be described as in reference to Figure 8 The described communication components perform.

[0161] In some examples, an apparatus as described herein may perform one or more methods such as method 1200. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving, at a host device, an indication that one or more voltages of a power delivery network on a memory die are configured to cause the power delivery network to operate at a resonant frequency for a duration; determining a timing of at least one command based on receiving the indication; and transmitting the timing of the at least one command.

[0162] Some examples of the method 1200 and apparatus described herein may further include operations, features, means, or instructions for identifying a correlation between a previous timing of at least one command and receiving an indication, wherein determining the timing may be based on identifying the correlation.

[0163] In some examples of the method 1200 and apparatus described herein, transmitting at least one command may further include operations, features, means, or instructions for transmitting at least one command having a timing determined based on receiving the indication.

[0164] It should be noted that the methods described herein describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and other embodiments are possible. In addition, portions from two or more of the methods may be combined.

[0165] An apparatus is described. The apparatus may include: a memory die including one or more memory cells; a power delivery network coupled to the memory die and configured to power one or more operations of the memory die; a sensor configured to sense one or more voltages of the power delivery network associated with the memory die; and a controller configured to cause the apparatus to compare the one or more voltages to a set of voltages of the power delivery network indicating that the power delivery network operates at a first frequency; determine whether the one or more voltages of the power delivery network associated with the memory die satisfy a condition based at least in part on comparing the one or more voltages to the set of voltages; and adjust timing of at least one command associated with the memory die based at least in part on determining whether the one or more voltages of the power delivery network satisfy the condition.

[0166] Some examples may further include determining that a voltage in the one or more voltages drops below a threshold, wherein adjusting the timing may be based on determining that the voltage drops below the threshold. Some examples may further include identifying a timing of a command to cause the power delivery network to operate at a first frequency, wherein determining that the one or more voltages satisfy a condition may be based on identifying the timing of the command.

[0167] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate signaling as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a bus of signals, where the bus may have various bit widths.

[0168] As used herein, the term "virtual ground" refers to a circuit node that is maintained at a voltage of approximately zero volts (0V) without being directly coupled to ground. Thus, the voltage of the virtual ground may fluctuate over time and return to approximately 0V in a steady state. Virtual ground may be implemented using various electronic circuit elements such as a voltage divider consisting of an operational amplifier and a resistor. Other implementations are also possible. "Virtual ground" or "virtual ground" means connecting to approximately 0V.

[0169] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact with each other, or connected or coupled) may be open or closed based on the operation of the device that includes the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some cases, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0170] As used herein, the term "substantially" means that the modified characteristic (such as a verb or adjective modified by the term substantially) is not necessarily absolute but is close enough to obtain the advantage of the characteristic.

[0171] The devices described herein including memory arrays may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0172] The switching components or transistors described herein may represent field effect transistors (FETs) and include a three-terminal device including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (e.g., most of the carriers are signals), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "started". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "de-started".

[0173] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferable" or "advantageous" over other examples. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0174] In the drawings, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0175] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0176] The various illustrative blocks and modules described in connection with the present disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0177] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hard wiring, or any combination of these. The features of the implementation functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations. Moreover, as used herein, included in the claims, the "or" used in the list of items (e.g., a list of items starting with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as referring to a closed set of conditions. For example, without departing from the scope of the present disclosure, the exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on."

[0178] Computer-readable media include both non-transitory computer storage media and communication media including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. As an example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage or other magnetic storage device device, or any other non-transitory media that can be used to carry or store the desired program code device in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor. Moreover, any connection can be appropriately referred to as computer-readable media. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave is used to transmit software from a website, server or other remote source, the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology such as infrared, radio and microwave are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0179] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: monitoring one or more voltages associated with the memory die via a power delivery network; determining whether the one or more voltages satisfy a condition for a duration based at least in part on monitoring the one or more voltages; transmitting, to a host device, an indication that the one or more voltages satisfy the condition based at least in part on determining that the one or more voltages satisfy the condition for the duration; receiving control information from a host device based at least in part on transmitting the indication, wherein the control information relates to an adjusted timing of at least one command associated with the memory die; as well as A voltage output to the memory die is adjusted over a power delivery network based at least in part on the control information related to the adjusted timing of the at least one command.

2. The method according to claim 1, further comprising: Based at least in part on determining that the one or more voltages satisfy the condition for the duration, the voltage output to the memory die is adjusted through the power delivery network.

3. The method of claim 2, wherein adjusting the voltage output to the memory die further comprises: Based at least in part on determining that the one or more voltages satisfy the condition for the duration, one or more regulators of the power delivery network are deactivated.

4. The method according to claim 1, further comprising: A determination is made that a voltage of the one or more voltages drops below a threshold, wherein determining whether the one or more voltages satisfy the condition is based at least in part on determining that the voltage drops below the threshold.

5. The method according to claim 1, further comprising: A determination is made that a voltage of the one or more voltages has increased above a threshold, wherein determining whether the one or more voltages satisfy the condition is based at least in part on determining that the voltage has increased above the threshold.

6. The method according to claim 1, further comprising: Determining the one or more voltages across the power delivery network indicates that the power delivery network satisfies the condition, wherein determining whether the one or more voltages satisfies the condition is based at least in part on determining the one or more voltages.

7. The method according to claim 1, further comprising: Based at least in part on determining whether the one or more voltages satisfy the condition and the control information, a timing of at least one command associated with the memory die is adjusted from a previous timing to a second timing different from the previous timing.

8. The method according to claim 1, wherein: The power delivery network includes one or more regulators coupled to the memory die, the one or more regulators configured to output power to the memory die; as well as Monitoring one or more voltages associated with the memory die through the power delivery network further includes monitoring one or more signals output by the one or more regulators through the power delivery network.

9. The method of claim 1, wherein the power delivery network is separate from the memory die.

10. A device comprising: Memory die; Electricity transmission networks; as well as A controller configured to cause the device to: monitoring one or more voltages associated with the memory die via a power delivery network; determining whether the one or more voltages satisfy a condition for a duration based at least in part on monitoring the one or more voltages; transmitting, to a host device, an indication that the one or more voltages satisfy the condition based at least in part on determining that the one or more voltages satisfy the condition for the duration; receiving control information from the host device based at least in part on transmitting the indication, wherein the control information relates to an adjusted timing of at least one command associated with the memory die; as well as A voltage output to the memory die is adjusted via the power delivery network based at least in part on the control information related to an adjusted timing of the at least one command.

11. The apparatus of claim 10, wherein the controller is further configured to cause the apparatus to: Based at least in part on determining that the one or more voltages satisfy the condition for the duration, the voltage output to the memory die is adjusted through the power delivery network.

12. The apparatus of claim 11, wherein the controller is further configured to cause the apparatus to: Based at least in part on determining that the one or more voltages satisfy the condition for the duration, one or more regulators of the power delivery network are deactivated.

13. The apparatus of claim 10, wherein the controller is further configured to cause the apparatus to: A determination is made that a voltage of the one or more voltages drops below a threshold, wherein determining whether the one or more voltages satisfy the condition is based at least in part on determining that the voltage drops below the threshold.

14. The apparatus of claim 10, wherein the controller is further configured to cause the apparatus to: A determination is made that a voltage of the one or more voltages has increased above a threshold, wherein determining whether the one or more voltages satisfy the condition is based at least in part on determining that the voltage has increased above the threshold.

15. The apparatus of claim 10, wherein the power delivery network comprises one or more regulators coupled to the memory die, the one or more regulators configured to output power to the memory die; and The controller is further configured to cause the device to monitor one or more signals output by the one or more regulators through the power delivery network.

16. A non-transitory computer readable medium storing code including instructions, wherein the code, when executed by one or more processors of an electronic device, causes the electronic device to: monitoring one or more voltages associated with the memory die via a power delivery network; determining whether the one or more voltages satisfy a condition for a duration based at least in part on monitoring the one or more voltages; transmitting, to a host device, an indication that the one or more voltages satisfy the condition based at least in part on determining that the one or more voltages satisfy the condition for the duration; receiving control information from a host device based at least in part on transmitting the indication, wherein the control information relates to an adjusted timing of at least one command associated with the memory die; as well as A voltage output to the memory die is adjusted through the power delivery network based at least in part on the control information related to the adjusted timing of the at least one command.

Images