FPGA (Field Programmable Gate Array) power operation system based on serial-parallel combined architecture
By adopting the serial-parallel architecture design in the FPGA power computing system, the problem of excessive resource consumption in the existing system is solved, and more efficient clock usage and resource optimization are achieved.
Patent Information
- Application Number
- CN202411633532.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-15
- Publication Date
- 2025-03-21
AI Technical Summary
When performing multi-channel power parameter calculation, the existing FPGA power computing system consumes too much resources, resulting in the lack of sufficient available resources for other modules, which seriously squeezes out the resources of other modules.
The FPGA power computing system based on the serial-parallel architecture is adopted, and through the computing state control module, the input data preprocessing module, the power computing module, the intermediate data cache module, the calculation result cache module, the output state control module and the calculation result frame packaging module, the overall pipeline serial and local parallel computing architecture is optimized.
It significantly improves the clock usage efficiency of various resources, reduces hardware resource consumption, improves the clock usage rate of DSP units, and optimizes FPGA resource consumption.
Smart Images
Figure CN119668396A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of electronic measurement, and more specifically, relates to an FPGA power calculation system based on a serial-parallel combination architecture. Background Art
[0002] Power parameter calculation is one of the core functions of various power analyzers. In electricity, the basic formula for power calculation (instantaneous power) is p(t) = u(t)i(t), where u(t) represents voltage and i(t) represents current. In actual use, the average value of the integral of the instantaneous power emitted or consumed by the load in a cycle is used as the main power reference indicator, namely active power. The calculation formula for active power is:
[0003]
[0004] Where T represents the signal length.
[0005] The corresponding discrete calculation formula used in the computer is:
[0006]
[0007] Where N represents the number of sampling points, u n 、i n Represent the voltage and current of the nth sampling point respectively.
[0008] In the actual calculation process, the cumulative term Frequent multiplication and accumulation operations must be performed on each set of newly collected voltage and current within a certain period of time. At the same time, there is usually more than one multiplication and accumulation item that needs to be calculated simultaneously.
[0009] Figure 1 The following is a diagram showing the structure of a power oscilloscope analyzer. Figure 1 As shown, the power oscilloscope analyzer supports up to 7 acquisition cards, each of which contains two acquisition bands (wideband and narrowband), totaling 14 bands. Therefore, in terms of the multi-channel power parameter calculation items involved in the instrument, according to the acquisition card, wide and narrow band, calculation time interval, and different sub-items of specific calculation items, it is necessary to calculate 7 (7 acquisition cards) * 2 (wideband, narrowband) * 4 (4 different calculation intervals) * 8 (8 different calculation items) at the same time, totaling 448 multiplication and accumulation items. Such complex calculations cannot be completed by the CPU within a limited time, so FPGA will be selected for collaborative calculations. The internal structure of FPGA can build a corresponding number of pipelines according to the number of data packet steps. Different pipelines process different data packets to realize pipeline parallelism and data parallelism. However, any module built on the FPGA side needs to consume the corresponding FPGA underlying hardware resources.
[0010] Figure 2This is the structural diagram of the existing 7-card FPGA power computing module with pure parallel architecture. Figure 2 As shown in the figure, the 14 channels of data (distinguishing between wide and narrow bands) collected by the 7 acquisition cards and their corresponding control signals, address signals, etc. enter the input data preprocessing module. After the corresponding data preprocessing, the 14 channels of data enter the multi-channel power calculation module Multi_Card_CALC module in parallel for calculation. The Multi_Card_CALC module contains 14 single-channel power calculation modules CALC, each of which contains 32 groups of multiplication and accumulation calculation units MUL_AND_ADD_V4. A total of 448 groups of multiplication and accumulation calculation units perform power calculation under the control of the timestamp trigger signal timestamp_trigger. After the calculation of a time period is completed, the calculation module outputs the 448 calculation results of the current time period in parallel to the calculation result cache module, and then starts the calculation of the new time period. After receiving the calculation results, the calculation result cache module temporarily caches the results internally, and then performs a parallel-to-serial conversion operation to output the 448 groups of calculation results one by one to the calculation result frame encapsulation module. The calculation result frame encapsulation module encapsulates the calculation results into a specific data frame format for output.
[0011] It can be seen that when using a purely parallel power calculation structure, 448 calculation modules and supporting calculation control modules and data mixed storage modules need to be built simultaneously. The data, control, and calculation link designs of the entire power calculation module are relatively simple, and the main resource consumption is located in the 448-way multiplication and accumulation calculation units and the 448-way parallel data cache modules. Large-scale parallel computing causes each resource consumption in the multiplication and accumulation calculation module to be magnified hundreds of times, resulting in the overall resource consumption of the power calculation module being out of control. Moreover, the available resources inside an FPGA chip are limited. If the power parameter calculation module consumes too many resources, other modules will not have enough available resources, thereby severely squeezing the number of available resources of the remaining modules. Summary of the invention
[0012] The purpose of the present invention is to overcome the shortcomings of the prior art and provide an FPGA power calculation system based on a serial-parallel combination architecture, which fully considers the characteristics of the clock rate difference between the acquisition end (ADC) and the processing end (FPGA) of the power analyzer (generally speaking, the sampling frequency is much lower than the clock frequency of the FPGA end), and optimizes the traditional pure parallel power calculation architecture into an overall pipeline serial and local parallel calculation architecture, greatly improving the clock utilization efficiency of each part of the resources and significantly reducing the consumption of hardware resources.
[0013] In order to achieve the above-mentioned object, the FPGA power calculation system based on the serial-parallel combination architecture of the present invention includes a calculation state control module CALC_STATE_control, an input data preprocessing module input_data_arbitrator, a power calculation module CALC, an intermediate data cache module temp_data_RAM_group, a calculation result cache module output_data_RAM_gtoup, an output state control module OUTPUT_STATE_control and a calculation result frame encapsulation module data_pacling, wherein:
[0014] The calculation state control module CALC_STATE_control is used to schedule and control the power calculation process. The specific scheduling process is as follows:
[0015] After detecting the arrival of the external input update time trigger signal timestamp_trigger, the calculation state control module CALC_STATE_control ends the existing interval calculation, sets the calculation completion signal CALC_state to be valid for one clock, and starts a new interval calculation at the same time, sends a reset signal to the intermediate data cache module temp_data_RAM_group, sets the state indication signal r_calc_state signal to invalid and writes it into the intermediate data cache module temp_data_RAM_group, and then the calculation state control module CALC_STATE_control sets the read address read_addr and write address write_addr of the intermediate data cache module temp_data_RAM_group to the storage address ADDR of each input data channel in the module according to the predetermined interval clock. n , set the write address output_RAM_write_addry in the calculation result cache module output_data_RAM_gtoup to the storage address OUT_ADDR of the corresponding channel in the module n , n=1,2,…,N, N represents the number of channels of input data; after the operation state control module CALC_STATE_control detects the arrival of the full cycle signal i_SW of the sampling data, it sets the state indication signal r_calc_state to be valid and writes it into the corresponding address of the intermediate data cache module temp_data_RAM_group;
[0016] The intermediate data cache module temp_data_RAM_group is a RAM array composed of multiple RAM blocks, which is used to cache the state indication signal r_calc_state set by the calculation state control module CALC_STATE_control and the intermediate value data MED calculated by the power calculation module CALC n and cache, the intermediate value data MED of each channel n Includes the intermediate calculation results MED of the M calculation units in the power calculation module CALC n [m], m = 1, 2, ..., M, each intermediate value data MED n Exclusive use of a fixed address space, the storage address is ADDR n After receiving the reset signal from the calculation state control module CALC_STATE_control, the intermediate data cache module temp_data_RAM_group will store the intermediate value data MED of all channels. n All are reset to 0, and the state indication signal r_calc_state is set to invalid; the intermediate data cache module temp_data_RAM_group reads the intermediate value data of the corresponding address according to the read address read_addr, and outputs the state indication signal r_calc_state as the previous round state indication signal i_calc_state together with the intermediate value data to the input data preprocessing module input_data_arbitrator, and overwrites the intermediate value data sent by the power calculation module CALC to the write address write_addr;
[0017] The input data preprocessing module input_data_arbitrator receives the input data and the full cycle signal i_SW sent by the data acquisition card, and parses to obtain the input data DATA of N channels. n Whenever the intermediate value data and the previous state indication signal i_calc_state are received from the intermediate data cache module temp_data_RAM_group, the input data preprocessing module input_data_arbitrator will receive the input data DATA of the corresponding channel. n , median data MED n , the previous round state indication signal i_calc_state and the whole cycle signal i_SW are sent together to the power calculation module CALC;
[0018] The power calculation module CALC includes M calculation units MUL_AND_ADD_V4_m, m = 1, 2, ..., M, the number of calculation units M and the calculation items are set according to actual needs. When receiving the input data DATA from the input data preprocessing module input_data_arbitrator n , median data MED n , the previous state indication signal i_calc_state and the whole cycle signal i_SW, each calculation unit MUL_AND_ADD_V4_m respectively according to the input data DATA n and median data MED n [m] Calculate the new intermediate value data MED n [m], M intermediate value data MED n [m] constitutes the intermediate value data MED n ; Determine whether the previous round of state indication signal i_calc_state is valid, if not, the intermediate value data MED n Set to 0 and send to the intermediate data cache module temp_data_RAM_group. If valid, the intermediate value data MED n Send it to the intermediate data cache module temp_data_RAM_group; then delay the full cycle signal i_SW by a single channel calculation time as the delayed full cycle signal o_SW, together with the intermediate value data MED n Send them together to the calculation result cache module output_data_RAM_gtoup;
[0019] The calculation result cache module output_data_RAM_gtoup is a RAM array composed of multiple RAM blocks, which is used to cache the calculation results that need to be output externally. The output calculation result of each channel in the calculation result cache module output_data_RAM_gtoup has an address of OUT_ADDR n The cache method is: after receiving the delayed full cycle signal o_SW and the intermediate value data MED n After that, when the delay full cycle signal o_SW is invalid, no operation is performed. When the delay full cycle signal o_SW is valid, the currently received intermediate value data MED n Overwrite the write address output_RAM_write_addr; the calculation result cache module output_data_RAM_gtoup reads the intermediate value data of the corresponding address according to the read address output_RAM_read_addr set by the output state control module OUTPUT_STATE_control and outputs it to the calculation result frame encapsulation module data_pacling;
[0020] The output state control module OUTPUT_STATE_control is used to schedule and control the output process of the calculation results. The specific scheduling process is: when the output state control module OUTPUT_STATE_control detects that the calculation completion signal CALC_state is valid, the output calculation results of each channel are stored in the address OUT_ADDR of the calculation result cache module output_data_RAM_gtoup. n Set the read address output_RAM_read_addr of the calculation result cache module output_data_RAM_gtoup;
[0021] The data frame packaging module data_pacling is used to receive the data sent by the calculation result cache module output_data_RAM_group, encapsulate it according to the pre-set standard data frame format and output it to the outside.
[0022] The present invention is based on an FPGA power calculation system of a serial-parallel combination architecture, comprising an operation state control module, an input data preprocessing module, a power calculation module, an intermediate data cache module, a calculation result cache module, an output state control module and a calculation result frame encapsulation module. In the power calculation module, multiple calculation units are used to perform parallel calculations under the control of the operation state control module, the calculation results are cached by the intermediate data cache module and the calculation result cache module, and then the calculation result frame encapsulation module is used to package and output them under the control of the output state control module, thereby improving the traditional pure parallel power calculation architecture into an overall pipeline serial and local parallel calculation architecture, greatly improving the clock utilization efficiency of each part of the resources, and significantly reducing the hardware resource consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 This is a diagram showing an example of the structure of a power oscilloscope analyzer;
[0024] Figure 2 This is the structural diagram of the existing 7-card FPGA power computing module with pure parallel architecture;
[0025] Figure 3 It is a structural diagram of a specific implementation of an FPGA power computing system based on a serial-parallel combination architecture of the present invention;
[0026] Figure 4 It is a schematic diagram of the actual effective calculation period in the present invention;
[0027] Figure 5 It is a structural diagram of a 7-card FPGA power computing module based on a serial-parallel combination architecture in this embodiment. DETAILED DESCRIPTION
[0028] The specific implementation of the present invention is described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.
[0029] Example
[0030] Figure 3 FIG. 1 is a structural diagram of a specific implementation of an FPGA power computing system based on a serial-parallel combination architecture of the present invention. Figure 3 As shown, the FPGA power calculation system based on the serial-parallel combination architecture of the present invention includes a calculation state control module CALC_STATE_control, an input data preprocessing module input_data_arbitrator, a power calculation module CALC, an intermediate data cache module temp_data_RAM_group, a calculation result cache module output_data_RAM_gtoup, an output state control module OUTPUT_STATE_control and a calculation result frame encapsulation module data_pacling, and each module is described in detail below.
[0031] The calculation state control module CALC_STATE_control is used to schedule and control the power calculation process. In the present invention, according to the external input update time trigger signal timestamp_trigger and the valid signal input_data_valid of the sampling data (a signal to indicate that each acquisition card has new sampling data), the entire calculation process is divided into a large calculation interval and a small calculation cycle, wherein the large calculation interval is determined by the external input update time trigger signal timestamp_trigger. For example, if the update time trigger signal interval is set to 100ms, that is, the large calculation interval is 100ms, the calculation state control needs to perform relevant calculations on all input data of the entire cycle within 100ms. The small single-round calculation cycle is determined by the input sampling data. Assuming that the front-end sampling rate is 5Mhz and the back-end clock frequency is 100Mhz, the small single-round calculation cycle is 20 clocks. In this case, the power calculation module needs to process all data within 20 clocks.
[0032] In addition, the signals measured by power oscilloscope analyzers are usually periodic, such as common AC signals. A full cycle is a complete cycle of a signal, which is used to identify the signal from one zero crossing point to the next zero crossing point. If the current input data is a full cycle zero crossing point, the full cycle signal i_SW will be pulled high. Then the actual effective calculation interval is the interval from the first signal full cycle zero crossing point to the last signal full cycle zero crossing point within the calculation interval determined by the update time trigger signal timestamp_trigger. Figure 3 It is a schematic diagram of the actual effective calculation period in the present invention. Figure 3 As shown, in order to control the actual effective calculation, the present invention sets a state indication signal r_calc_state and a previous round state indication signal i_calc_statet. When the update time trigger signal timestamp_trigger signal arrives, a new calculation interval begins. The state indication signal r_calc_state signal will be pulled low until the first full cycle signal i_SW signal arrives and it will be pulled high, and then it will enter the actual effective calculation interval. At this time, the result calculated by the power operation module CALC will be written into the intermediate data cache module temp_data_RAM_group, otherwise it will only be written as 0. The state indication signal r_calc_state will also be written into the intermediate data cache module temp_data_RAM_group for caching. During power calculation, it will be read out together with the intermediate value data as the previous round state indication signal i_calc_statet, and sent to the power operation module CALC together with the new input data of the corresponding channel. By detecting the previous round state indication signal i_calc_state, the power operation module CALC can know whether the current calculation is in the actual effective calculation interval.
[0033] According to the above analysis, the specific scheduling process of the calculation state control module CALC_STATE_control in the present invention is as follows:
[0034] After detecting the arrival of the external input update time trigger signal timestamp_trigger, the calculation state control module CALC_STATE_control ends the existing interval calculation, sends a calculation completion signal to the output state control module OUTPUT_STATE_control, and starts a new interval calculation at the same time, sends a reset signal to the intermediate data cache module temp_data_RAM_group, sets the state indication signal r_calc_state signal to invalid and writes it into the intermediate data cache module temp_data_RAM_group, and then the calculation state control module CALC_STATE_control sets the read address read_addr and write address write_addr of the intermediate data cache module temp_data_RAM_group to the storage address ADDR of each input data channel in the module according to the predetermined interval clock (determined according to the single-channel calculation duration of the power calculation module CALC) cyclically. n , set the write address output_RAM_write_addry in the calculation result cache module output_data_RAM_gtoup to the storage address OUT_ADDR of the corresponding channel in the module n , n=1,2,…,N, N represents the number of channels of input data. After the operation state control module CALC_STATE_control detects the arrival of the full cycle signal i_SW of the sampling data, it sets the state indication signal r_calc_state to be valid and writes it into the corresponding address of the intermediate data cache module temp_data_RAM_group.
[0035] The intermediate data cache module temp_data_RAM_group is a RAM array composed of multiple RAM blocks, which is used to cache the state indication signal r_calc_state set by the calculation state control module CALC_STATE_control and the intermediate value data MED calculated by the power calculation module CALC n and cache, the intermediate value data MED of each channel n Includes the intermediate calculation results MED of the M calculation units in the power calculation module CALC n [m], m = 1, 2, ..., M, each intermediate value data MED n Exclusive use of a fixed address space, the storage address is ADDR nFor example, the calculation result of channel 1 is cached at address 0, the calculation result of channel 2 is cached at address 1, and so on. After receiving the reset signal from the calculation state control module CALC_STATE_control, the intermediate data cache module temp_data_RAM_group caches the intermediate value data MED of all channels. n All are reset to 0, and the state indication signal r_calc_state is set to invalid. The intermediate data cache module temp_data_RAM_group reads the intermediate value data of the corresponding address according to the read address read_addr, and outputs the state indication signal r_calc_state as the previous round state indication signal i_calc_state together with the intermediate value data to the input data preprocessing module input_data_arbitrator, and overwrites the intermediate value data sent by the power calculation module CALC to the write address write_addr.
[0036] It can be seen that the write data of the intermediate data cache module temp_data_RAM_group comes from the power calculation module CALC (that is, after each calculation is completed, the new intermediate calculation result is written to the corresponding storage address), read by the input data preprocessing module input_data_arbitrator and input into the power calculation module CALC together with the new input data to start a new round of calculation (that is, each time a new calculation starts, the new input data of each channel is input into the power calculation module CALC together with the previous round of calculation results of the channel), thereby completing the accumulation.
[0037] The input data preprocessing module input_data_arbitrator receives the input data and the full cycle signal i_SW sent by the data acquisition card, and parses to obtain the input data DATA of N channels. n Whenever the intermediate value data and the previous state indication signal i_calc_state are received from the intermediate data cache module temp_data_RAM_group, the input data preprocessing module input_data_arbitrator will receive the input data DATA of the corresponding channel. n , median data MED n , the previous round state indication signal i_calc_state and the whole cycle signal i_SW are sent to the power calculation module CALC.
[0038] The power calculation module CALC includes M calculation units MUL_AND_ADD_V4_m, m = 1, 2, ..., M, the number of calculation units M and the calculation items are set according to actual needs. When receiving the input data DATA from the input data preprocessing module input_data_arbitrator n , median data MED n , the previous state indication signal i_calc_state and the whole cycle signal i_SW, each calculation unit MUL_AND_ADD_V4_m respectively according to the input data DATA n and median data MED n [m] Calculate the new intermediate value data MED n [m], M intermediate value data MED n [m] constitutes the intermediate value data MED n . Determine whether the previous round state indication signal i_calc_state is valid. If not, the intermediate value data MED n Set to 0 and send to the intermediate data cache module temp_data_RAM_group. If valid, the intermediate value data MED n It is sent to the intermediate data cache module temp_data_RAM_group. Then the full cycle signal i_SW is delayed by a single channel calculation time as the delayed full cycle signal o_SW, together with the intermediate value data MED n Sent together to the calculation result cache module output_data_RAM_gtoup.
[0039] Similar to the intermediate data cache module temp_data_RAM_group, the calculation result cache module output_data_RAM_gtoup is a RAM array composed of multiple RAM blocks, which is used to cache the calculation results that need to be output externally. The output calculation result of each channel in the calculation result cache module output_data_RAM_gtoup has an address of OUT_ADDR n Unlike the intermediate calculation data cache module temp_data_RAM_group, which caches the intermediate value data obtained in each round of calculation, the calculation result cache module output_data_RAM_group only caches the calculation results of the entire cycle. That is, after receiving the delayed full cycle signal o_SW and the intermediate value data MED n After that, when the delay full cycle signal o_SW is invalid, no operation is performed. When the delay full cycle signal o_SW is valid, the currently received intermediate value data MED nOverwrite the write address output_RAM_write_addr. It can be seen that the write operation of the calculation result cache module output_data_RAM_group is controlled by the delayed full cycle signal o_SW and the calculation state control module CALC_STATE_control. The read operation of the calculation result cache module output_data_RAM_group is controlled by the output state control module OUTPUT_STATE_control, that is, according to the read address output_RAM_read_addr set by the output state control module OUTPUT_STATE_control, the intermediate value data of the corresponding address is read and output to the calculation result frame encapsulation module data_pacling.
[0040] In order to prevent the calculation result data from being overwritten before being accurately read out, the calculation result cache module output_data_RAM_gtoup in this embodiment adopts a dual cache partition setting, and the two cache partitions alternately write and read data in different calculation intervals. For example, if the first calculation interval uses cache partition 1 to cache data, then the second calculation interval uses cache partition 2 to cache data and reads data from cache partition 1, and then the next time, cache partition 1 is used again to cache data and read data from cache partition 2, and so on.
[0041] The output state control module OUTPUT_STATE_control has similar functions to the calculation state control module CALC_STATE_control, and is used to schedule and control the output process of the calculation results. The specific scheduling process is as follows: when the output state control module OUTPUT_STATE_control detects that the calculation completion signal CALC_state is valid, the output calculation results of each channel are stored in the address OUT_ADDR of the calculation result cache module output_data_RAM_gtoup. n Set the read address output_RAM_read_addr of the calculation result cache module output_data_RAM_gtoup.
[0042] The data frame packaging module data_pacling is used to receive the data sent by the calculation result cache module output_data_RAM_group, encapsulate it according to the pre-set standard data frame format and output it to the outside.
[0043] In order to better illustrate the technical effect of the present invention, a 7-card FPGA power operation module is taken as an example to describe its serial-parallel combination architecture in detail.
[0044] Figure 5: is a structural diagram of a 7-card FPGA power computing module based on a serial-parallel combination architecture in this embodiment. Figure 5 As shown, in this embodiment, each acquisition card data contains two channels, broadband and narrowband, respectively, so the input data has a total of 14 channels. In this embodiment, 32 calculation units are set, and the calculation items include SW0 (entire update time), SW1 (hardware voltage square wave), SW2 (hardware current square wave), SW3 (to be determined) channels, and each channel has 8 items (RMS_U, RMS_I, ABS_U, ABS_I, POSI_WAVE_U, POSI_WAVE_I, PWR, POSI_PWR).
[0045] contrast Figure 2 and Figure 5 It can be seen that the 7-channel FPGA power calculation module with pure parallel architecture has the disadvantages of insufficient DSP clock utilization and excessive resource overhead when it is in large-scale parallel operation. Although the 7-channel FPGA power calculation module based on the serial-parallel combination architecture adds more and more complex control logic and increases the use of RAM resources for caching temporary data, the serial-parallel combination architecture makes full use of DSP resources and uses a single CALC module (containing 32 MUL_AND_ADD_V4 modules) to complete the calculation of a total of 448 calculation items in 7 cards and 14 bands, which is far less than the 14 CALC modules of the pure parallel solution (containing a total of 448 MUL_AND_ADD_V4 modules). At the same time, it reduces the large-scale result cache module calc_data_cache originally constructed using the register array, greatly reducing resource usage.
[0046] The final comprehensive results show that the 7-card FPGA power computing module based on the serial-parallel combination architecture significantly improves the clock utilization rate of the DSP unit (from 5% of the existing pure parallel architecture to 70%), greatly optimizes the FPGA resource consumption, and reduces the module resource consumption by 82.87% (in terms of LUT) to 95.67% (in terms of Slice Reg). The resource usage share of this module in the entire project has dropped from 58.05% to 23.70% (in terms of LUT).
[0047] Although the above describes the illustrative specific embodiments of the present invention to facilitate those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations using the concept of the present invention are protected.
Claims
1. An FPGA power computing system based on a serial-parallel combination architecture, characterized in that: It includes a calculation state control module CALC_STATE_control, an input data preprocessing module input_data_arbitrator, a power calculation module CALC, an intermediate data cache module temp_data_RAM_group, a calculation result cache module output_data_RAM_gtoup, an output state control module OUTPUT_STATE_control and a calculation result frame packaging module data_pacling, wherein: The calculation state control module CALC_STATE_control is used to schedule and control the power calculation process. The specific scheduling process is as follows: After detecting the arrival of the external input update time trigger signal timestamp_trigger, the calculation state control module CALC_STATE_control ends the existing interval calculation, sets the calculation completion signal CALC_state to be valid for one clock, and starts a new interval calculation at the same time, sends a reset signal to the intermediate data cache module temp_data_RAM_group, sets the state indication signal r_calc_state signal to invalid and writes it into the intermediate data cache module temp_data_RAM_group, and then the calculation state control module CALC_STATE_control sets the read address read_addr and write address write_addr of the intermediate data cache module temp_data_RAM_group to the storage address ADDR of each input data channel in the module according to the predetermined interval clock. n , set the write address output_RAM_write_addry in the calculation result cache module output_data_RAM_gtoup to the storage address OUT_ADDR of the corresponding channel in the module n , n=1,2,…,N, N represents the number of channels of input data; after the operation state control module CALC_STATE_control detects the arrival of the full cycle signal i_SW of the sampling data, it sets the state indication signal r_calc_state to be valid and writes it into the corresponding address of the intermediate data cache module temp_data_RAM_group; The intermediate data cache module temp_data_RAM_group is a RAM array composed of multiple RAM blocks, which is used to cache the state indication signal r_calc_state set by the calculation state control module CALC_STATE_control and the intermediate value data MED calculated by the power calculation module CALC n and cache, the intermediate value data MED of each channel n Includes the intermediate calculation results MED of the M calculation units in the power calculation module CALC n [m], m = 1, 2, ..., M, each intermediate value data MED n Exclusive use of a fixed address space, the storage address is ADDR n After receiving the reset signal from the calculation state control module CALC_STATE_control, the intermediate data cache module temp_data_RAM_group will store the intermediate value data MED of all channels. n All are reset to 0, and the state indication signal r_calc_state is set to invalid; the intermediate data cache module temp_data_RAM_group reads the intermediate value data of the corresponding address according to the read address read_addr, and outputs the state indication signal r_calc_state as the previous round state indication signal i_calc_state together with the intermediate value data to the input data preprocessing module input_data_arbitrator, and overwrites the intermediate value data sent by the power calculation module CALC into the write address write_addr; The input data preprocessing module input_data_arbitrator receives the input data and the full cycle signal i_SW sent by the data acquisition card, and parses to obtain the input data DATA of N channels. n Whenever the intermediate value data and the previous state indication signal i_calc_state are received from the intermediate data cache module temp_data_RAM_group, the input data preprocessing module input_data_arbitrator will receive the input data DATA of the corresponding channel. n , median data MED n , the previous round state indication signal i_calc_state and the whole cycle signal i_SW are sent together to the power calculation module CALC; The power calculation module CALC includes M calculation units MUL_AND_ADD_V4_m, m = 1, 2, ..., M, the number of calculation units M and the calculation items are set according to actual needs. When receiving the input data DATA from the input data preprocessing module input_data_arbitrator n , median data MED n , the previous state indication signal i_calc_state and the whole cycle signal i_SW, each calculation unit MUL_AND_ADD_V4_m respectively according to the input data DATA n and median data MED n [m] Calculate the new intermediate value data MED n [m], M intermediate value data MED n [m] constitutes the intermediate value data MED n ; Determine whether the previous state indication signal i_calc_state is valid. If not, the intermediate value data MED n Set to 0 and send to the intermediate data cache module temp_data_RAM_group. If valid, the intermediate value data MED n Send it to the intermediate data cache module temp_data_RAM_group; then delay the full cycle signal i_SW by a single channel calculation time as the delayed full cycle signal o_SW, together with the intermediate value data MED n Send them together to the calculation result cache module output_data_RAM_gtoup; The calculation result cache module output_data_RAM_gtoup is a RAM array composed of multiple RAM blocks, which is used to cache the calculation results that need to be output externally. The output calculation result of each channel in the calculation result cache module output_data_RAM_gtoup has an address of OUT_ADDR n The cache method is: after receiving the delayed full cycle signal o_SW and the intermediate value data MED n After that, when the delay full cycle signal o_SW is invalid, no operation is performed. When the delay full cycle signal o_SW is valid, the currently received intermediate value data MED n Overwrite the write address output_RAM_write_addr; the calculation result cache module output_data_RAM_gtoup reads the intermediate value data of the corresponding address according to the read address output_RAM_read_addr set by the output state control module OUTPUT_STATE_control and outputs it to the calculation result frame encapsulation module data_pacling; The output state control module OUTPUT_STATE_control is used to schedule and control the output process of the calculation results. The specific scheduling process is: when the output state control module OUTPUT_STATE_control detects that the calculation completion signal CALC_state is valid, the output calculation results of each channel are stored in the address OUT_ADDR of the calculation result cache module output_data_RAM_gtoup. n Set the read address output_RAM_read_addr of the calculation result cache module output_data_RAM_gtoup; The data frame packaging module data_pacling is used to receive the data sent by the calculation result cache module output_data_RAM_group, encapsulate it according to the pre-set standard data frame format and output it to the outside.
2. The FPGA power computing system according to claim 1, characterized in that: The calculation result cache module output_data_RAM_gtoup adopts a dual cache partition setting, and the two cache partitions alternately write and read data in different calculation intervals.