Temperature environment construction method and system for chip test calibration

Abstract

The invention discloses a temperature environment construction method and system for chip test calibration, and relates to the technical field of chip test processing, and the method comprises the steps: S1, test memory bank statistics, S2, chip prior test data preprocessing, S3, test environment construction temperature interval acquisition, and S4, temperature environment cooperative adjustment construction. According to the invention, pertinent analysis of prior data is carried out on the to-be-tested memory bank, and the test environment of the to-be-tested memory bank is obtained to construct the temperature interval, so that the problem that the temperature environment setting is too one-sidedness when the memory bank is tested at present is effectively solved; according to the method, the characteristic of inconsistency of the actual application performance of the memory bank can be fully considered, so that the situation that whether the temperature of the memory bank reaches a set value or not is singly sensed and judged is avoided, complex temperature environment conditions can be accurately simulated, and powerful data support guarantee is provided for the accuracy of a test result.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a method and system for constructing a temperature environment for chip testing and calibration. Background Art

[0002] The performance of the memory stick directly affects the overall performance of the computer system. Quality problems of the memory stick may cause serious consequences such as system crash and data loss. Therefore, testing can timely discover and solve potential quality problems, thereby ensuring the stable operation of the system. Since memory chips have different performance at different temperatures, the temperature of the test environment needs to be controlled when testing the memory stick.

[0003] The prior art, such as the invention patent with announcement number: CN112965866B, is a method for automatically screening the temperature resistance range of memory sticks, and classifying memory sticks according to the temperature resistance range, including: BMC starts the memory stick shutdown temperature control module, confirms that the temperature of the memory stick reaches the set temperature, starts the X86 system and turns on the POST counter, starts the memory stick startup temperature control module, and determines whether the BMC receives a clear POST counter instruction within a specified time. If so, it determines whether the BMC receives a clear OS counter instruction within a specified time. If not, it determines whether this operation is the lowest over-temperature temperature; if the clear OS counter instruction is received, the current temperature is recorded as the maximum operable temperature of this memory stick. If not, it determines whether this operation is the lowest over-temperature temperature; if it is confirmed that this operation is the lowest over-temperature temperature, it is determined that this memory stick cannot be over-heated. If not, the BMC forcibly shuts down the X86 system and reduces the test temperature by one level, waiting for the next test cycle.

[0004] Based on the above scheme, the present applicant has found that the current temperature setting test for memory sticks has the problem of overly one-sided temperature environment setting. Due to the inconsistency in the actual application performance of the memory sticks, there are differences in the testing requirements for the temperature environment. The current single perception and judgment of whether the temperature of the memory stick reaches the set value cannot simulate complex temperature environment conditions, resulting in a phenomenon that the test results are inconsistent with actual usage, and it is also impossible to reveal the true performance of the memory stick under temperature environment fluctuations, thereby affecting the credibility of the test results. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention provides a method and system for establishing a temperature environment for chip testing and calibration, which can effectively solve the problems involved in the above-mentioned background technology.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solutions: First, a method for constructing a temperature environment for chip testing and calibration is provided, including: a temperature chamber controller receives a memory chip test request calibration signal triggered by a port, and counts the test memory sticks currently placed in the test mainboard in the temperature chamber, marking them as memory sticks to be tested.

[0007] The chip type of the memory bar to be tested is obtained, and the chip priori test data of the memory bar to be tested is obtained based on the chip type matching and imported into the cloud computing center of the temperature chamber controller for preprocessing to obtain the chip priori test aggregation index of the memory bar to be tested.

[0008] The preset adjustable environment building temperature range of the test motherboard in the temperature chamber is obtained, and the preset adjustable environment building temperature range is pre-corrected based on the chip prior test aggregation index of the memory bar to be tested, so as to obtain the test environment building temperature range of the memory bar to be tested.

[0009] Based on the test environment construction temperature range of the memory stick to be tested, the test environment construction temperature of each fixed point of the memory stick to be tested is obtained through re-correction processing, and transmitted to the temperature box controller for coordinated adjustment and construction of the temperature environment.

[0010] As a preferred technical solution, the chip prior test data of the memory stick to be tested is obtained based on chip type matching. The specific matching process includes: matching the chip prior test data corresponding to the sample memory sticks of each chip type stored in the incubator data register according to the chip type of the memory stick to be tested, obtaining the chip prior test data corresponding to the sample memory stick that is consistent with the chip type of the memory stick to be tested, and marking it as the chip prior test data of the memory stick to be tested.

[0011] As a preferred technical solution, the chip a priori test data of the memory stick to be tested, wherein the chip a priori test data specifically includes first a priori test data and second a priori test data.

[0012] The first a priori test data includes an average read / write speed, an average read / write delay, a single-bit error rate, and a multi-bit error rate of each a priori measured memory chip.

[0013] The second a priori test data includes various electrical parameter perception curves of each a priori measured memory chip.

[0014] As an optimal technical solution, the chip prior test data of the memory bar to be tested obtained by matching is imported into the cloud computing center of the temperature chamber controller for preprocessing. The specific preprocessing process is: each prior determined memory chip is integrated and marked as a prior memory chip array.

[0015] Based on the average read and write speed, average read and write delay, single-bit error rate and multi-bit error rate of each priori measured memory chip, the average read and write speed, average read and write delay, average single-bit error rate and average multi-bit error rate of the priori memory chip array are obtained through truncated mean processing, and then the first aggregation factor of the priori memory chip array is obtained through convergent analysis processing. The first aggregation factor is used to characterize the comprehensive measured read and write performance of the priori memory chip array.

[0016] The balanced values ​​of various electrical parameters of the memory stick to be tested are extracted from the temperature chamber data register, and the various electrical parameter baselines are simultaneously mapped and constructed in the various electrical parameter perception curves of each priori measured memory chip. The cumulative coverage area and the cumulative total duration of the various electrical parameter perception curves exceeding the corresponding electrical parameter baseline are recorded as the cumulative coverage area of ​​the curve measurement drift and the cumulative total duration of the curve measurement drift, respectively. The cumulative coverage area of ​​the curve measurement drift and the cumulative total duration of the curve measurement drift corresponding to the various electrical parameters of each priori measured memory chip are statistically calculated, and the oscillation frequency and the highest oscillation time span of the various electrical parameter perception curves of each priori measured memory chip are statistically calculated. The second aggregation factor of the priori memory chip array is obtained through convergent analysis and processing, and the second aggregation factor is used to characterize the comprehensive measurement electrical performance of the priori memory chip array.

[0017] As a preferred technical solution, the chip a priori test aggregation index of the memory bar to be tested is obtained by the following specific process: based on the first aggregation factor of the a priori memory chip array and the second aggregation factor of the a priori memory chip array, the chip a priori test aggregation index of the memory bar to be tested is obtained through weighted processing. The chip a priori test aggregation index of the memory bar to be tested is a numerical result obtained by data aggregation and analysis of the a priori memory chip array, which is used to characterize the comprehensive measurement performance of the a priori memory chip array and serves as a constraint basic condition for constructing a temperature environment for the memory bar to be tested.

[0018] As a preferred technical solution, the preset adjustable environment construction temperature interval is pre-corrected based on the chip prior test aggregation index of the memory bar to be tested to obtain the test environment construction temperature interval of the memory bar to be tested. The specific process includes: based on the chip prior test aggregation index of the memory bar to be tested, and compared with the chip prior test aggregation index threshold in the temperature box data register, the test environment construction adjustment temperature is obtained through pre-correction processing. The specific correction processing conditions are: ; in, Indicates that the test environment builds the adjustment temperature. Indicates the chip priori test aggregation index of the memory module to be tested. Indicates the chip prior test aggregation index threshold, Indicates the adjusted temperature value corresponding to the chip prior test aggregate unit deviation index defined in the temperature chamber data register; The temperature range is built based on the preset adjustable environment of the test motherboard in the incubator and marked as , and the test environment construction adjustment temperature is processed to obtain the test environment construction temperature range of the memory module to be tested. The numerical expression is: .

[0019] As an optimal technical solution, the fixed-point test environment construction temperatures of the memory stick to be tested are obtained through re-correction processing. The specific correction processing process includes: extracting the test environment construction temperature range value of the memory stick to be tested according to the test environment construction temperature interval of the memory stick to be tested, and importing it into the temperature range division ratio linear model pre-defined in the temperature box data register, and extracting the first corrected division ratio of the test environment temperature corresponding to the memory stick to be tested.

[0020] According to the chip priori test aggregation index of the memory bar to be tested, a mapping match is performed with the second corrected segmentation ratio of the test environment temperature corresponding to each priori test aggregation index interval pre-defined by the temperature chamber data register to obtain the second corrected segmentation ratio of the test environment temperature corresponding to the memory bar to be tested.

[0021] As a preferred technical solution, the method of obtaining the fixed-point test environment construction temperatures of the memory stick to be tested through re-correction processing also includes: accumulating the first corrected segmentation ratio of the test environment temperature and the second corrected segmentation ratio of the test environment temperature corresponding to the memory stick to be tested and synchronously performing average processing to obtain the comprehensive corrected segmentation ratio of the test environment temperature corresponding to the memory stick to be tested, and dividing the test environment construction temperature range value of the memory stick to be tested based on the comprehensive corrected segmentation ratio of the test environment temperature to obtain the fixed-point test environment construction temperatures of the memory stick to be tested.

[0022] As a preferred technical solution, the chip of the memory stick to be tested is priori tested for aggregation index, and the specific execution conditions are: ; in, Indicates the chip priori test aggregation index of the memory module to be tested. represents the first aggregation factor of the a priori memory chip array, represents the second aggregation factor of the a priori memory chip array, Indicates the first aggregation factor check value defined in the oven data register, Indicates the second aggregation factor check value defined in the oven data register, represents the weight coefficient of the first aggregation factor, represents the weight coefficient of the second aggregation factor, and e is a natural constant.

[0023] Secondly, a temperature environment construction system for chip testing and calibration is provided, including: a test memory bar statistics module, which is used to receive a memory chip test request calibration signal triggered by a temperature chamber controller port, and count the test memory bars currently placed in the test motherboard in the temperature chamber, marking them as memory bars to be tested.

[0024] The chip prior test data preprocessing module is used to obtain the chip type of the memory stick to be tested, and obtain the chip prior test data of the memory stick to be tested based on the chip type matching, and import it into the cloud computing center of the temperature chamber controller for preprocessing to obtain the chip prior test aggregation index of the memory stick to be tested.

[0025] The test environment construction temperature range acquisition module is used to obtain the preset adjustable environment construction temperature range of the test motherboard in the temperature chamber, and pre-correct the preset adjustable environment construction temperature range based on the chip prior test aggregation index of the memory stick to be tested, so as to obtain the test environment construction temperature range of the memory stick to be tested.

[0026] The temperature environment coordinated adjustment construction module is used to construct a temperature range based on the test environment of the memory stick to be tested, obtain the temperature of each fixed-point test environment construction of the memory stick to be tested through re-correction processing, and transmit it to the temperature box controller for temperature environment coordinated adjustment construction.

[0027] Compared with the prior art, the embodiments of the present invention have at least the following beneficial effects: (1) The present invention provides a method and system for establishing a temperature environment for chip testing and calibration. By conducting a targeted analysis of the prior data of a memory stick to be tested and obtaining a test environment construction temperature range for the memory stick to be tested, the present invention effectively solves the problem of overly one-sided temperature environment setting when testing a memory stick. The present invention can fully consider the inconsistency of the actual application performance of the memory stick, thereby avoiding the single perception and judgment of whether the temperature of the memory stick reaches the set value. The present invention can accurately simulate complex temperature environment conditions, providing strong data support and guarantee for the accuracy of the test results.

[0028] (2) The present invention obtains chip priori test data of the memory stick to be tested by matching, and processes and obtains chip priori test aggregation indicators of the memory stick to be tested, thereby achieving normalization and quantification of the chip priori test data. The priori test data can be used as a reference to further reflect the actual test performance of the chip of the memory stick to be tested, thereby providing an early numerical constraint basis for the analysis and acquisition of the temperature range for the test environment. This can not only help determine the most representative test temperature range and ensure that the temperature test conditions are more in line with the actual performance of the chip of the memory stick to be tested, but also promote the improvement of the accuracy and credibility of the test results.

[0029] (3) The present invention obtains the temperature of each fixed-point test environment construction of the memory stick to be tested through re-correction processing. By performing fixed-point tests at different temperature points, it can more accurately locate the chip problems that may exist in the memory stick to be tested at a specific temperature. At the same time, it can realize targeted testing, reduce unnecessary test steps, improve the efficiency of the overall test process, fully ensure the effective allocation and utilization of time and resources, and is also conducive to revealing the true performance of the memory stick to be tested under temperature environment fluctuations, promoting better evaluation and verification of the chip reliability and durability of the memory stick to be tested, and improving the credibility of the test results.

[0030] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the method flow of the present invention.

[0032] Figure 2 It is a schematic diagram of the system module of the present invention.

[0033] Figure 3 It is a schematic diagram of a current parameter sensing curve involved in an embodiment of the present invention.

[0034] Figure 4 It is a schematic diagram of a temperature range partitioning proportional linear model involved in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] In the description of the present invention, it should be understood that the terms "opening", "upper", "lower", "thickness", "top", "middle", "length", "inside", "all around" and the like indicating orientation or positional relationship are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the components or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0037] See also Figure 1 As shown, in the first aspect of an embodiment of the present invention, a method for constructing a temperature environment for chip testing and calibration is provided, including: S1, test memory bar statistics: a temperature chamber controller receives a memory chip test request calibration signal triggered by a port, and counts the test memory bars currently placed in a test mainboard in the temperature chamber, marking them as memory bars to be tested.

[0038] The thermostat controller is an embedded system specifically used for managing and controlling the temperature of the thermostat. It is responsible for processing data from the temperature sensor, controlling the heating and cooling devices, and communicating with external devices.

[0039] The port refers to the communication interface between the temperature chamber controller and an external device (such as a test master control computer). The port can be a physical interface (such as a USB interface) or a wireless communication interface (such as Wi-Fi or Bluetooth, etc.).

[0040] It should be noted that the memory chip test request calibration signal is a specific signal used to trigger the temperature box controller to perform a temperature calibration and adjustment process. After receiving the calibration signal, the temperature box controller starts the temperature calibration program.

[0041] It should also be noted that the test memory stick currently placed in the test mainboard in the incubator, wherein the incubator is a test device for simulating different temperature environments. During the test, the memory stick generally needs to be placed in a cavity that can control the ambient temperature. This device that can control the ambient temperature in the cavity is the incubator. The test mainboard is a specially designed hardware platform for testing and verifying the performance of the memory stick. In this embodiment, the test mainboard is equipped with multiple memory slots arranged side by side, and multiple memory sticks can be tested at the same time. Heat sinks are arranged on both sides of the memory slots. The heat sinks are composed of a heat sink PCB (a heat sink PCB is a specially designed printed circuit board with a heating element integrated inside, which is used to provide a specific area The PCB is composed of a PI electric heating film (electric heating film with a polyimide substrate) and a heat sink. The PI electric heating films are respectively pasted on both sides of the heating sheet PCB, and a heat sink is pasted on the outer side of the PI electric heating film. One or more temperature sensors are arranged on the heating sheet PCB. The temperature sensors are used to detect the ambient temperature of the memory stick and serve as feedback values ​​for temperature control. The heating sheet PCB is also provided with one or more pairs of electric heating film power supply pads for electrically connecting the heating wire of the PI electric heating film. The PI electric heating film is composed of a PI film and a heating wire. The heating wire is evenly arranged on the PI film, and both ends of the heating wire are pads. By arranging two or more heating wires in zones, the zoned temperature control of the heating sheet can be achieved.

[0042] It should be understood that the description of the lateral directions involved in this embodiment, such as the two sides of the memory slot, the two sides of the heating plate PCB, and the outside of the PI heating film, all refer to one or two lateral directions corresponding to the maximum side area of ​​the corresponding component.

[0043] S2. Preprocessing of chip prior test data: Obtain the chip type of the memory stick to be tested, and obtain the chip prior test data of the memory stick to be tested based on chip type matching, and import it into the cloud computing center of the temperature chamber controller for preprocessing to obtain the chip prior test aggregation index of the memory stick to be tested.

[0044] Exemplarily, the chip types include, but are not limited to, SRAM (static random access memory), SDRAM (synchronous dynamic random access memory), FRAM (ferroelectric random access memory), MRAM (magnetic random access memory), and the like.

[0045] The cloud computing center is a data processing center responsible for collecting, storing and analyzing data from the thermostat controllers. Through the cloud computing center, multiple thermostat controllers can be remotely monitored and controlled to adjust the temperature, record data and process data in real time.

[0046] Specifically, the chip prior test data of the memory stick to be tested is obtained based on chip type matching, and the specific matching process includes: matching the chip prior test data corresponding to the sample memory sticks of each chip type stored in the incubator data register according to the chip type of the memory stick to be tested, obtaining the chip prior test data corresponding to the sample memory stick that is consistent with the chip type of the memory stick to be tested, and marking it as the chip prior test data of the memory stick to be tested, wherein the chip prior test data is reference data that has been measured historically and stored in the incubator data register.

[0047] In this embodiment, the temperature box data register is a register used to store and manage temperature-related monitoring data or status information in the temperature box control system.

[0048] Specifically, the chip a priori test data of the memory stick to be tested, wherein the chip a priori test data specifically includes first a priori test data and second a priori test data.

[0049] The first a priori test data includes an average read and write speed (in megabytes per second, MB / s), an average read and write latency (in nanoseconds, ns), a single-bit error rate, and a multi-bit error rate of each a priori measured memory chip.

[0050] It should be understood that the average read and write speed refers to the amount of data that the memory chip can transmit per second when performing data read and write operations. The average read and write latency refers to the time required for the memory chip to receive the read and write instructions and actually complete the data reading and writing. The single-bit error rate refers to the probability of a single bit error occurring when each bit of data is transmitted during the reading and writing process of the memory chip. The multi-bit error rate refers to the probability of multiple bit errors occurring in a read and write operation.

[0051] The second a priori test data includes various electrical parameter perception curves of each a priori measured memory chip, wherein the electrical parameters include but are not limited to current, voltage, etc., and the various electrical parameter perception curves are constructed with time as the horizontal axis.

[0052] Furthermore, the chip a priori test data of the memory bar to be tested obtained by matching is imported into the cloud computing center of the temperature chamber controller for preprocessing. The specific preprocessing process is: each a priori measured memory chip is integrated and marked as a priori memory chip array.

[0053] Based on the average read and write speed, average read and write delay, single-bit error rate and multi-bit error rate of each priori measured memory chip, the average read and write speed, average read and write delay, average single-bit error rate and average multi-bit error rate of the priori memory chip array are obtained through truncated mean processing, and then the first aggregation factor of the priori memory chip array is obtained through convergent analysis processing. The first aggregation factor is used to characterize the comprehensive measured read and write performance of the priori memory chip array.

[0054] Exemplarily, the method of obtaining the average read and write speed of the a priori memory chip array through truncated mean processing is as follows: according to the average read and write speeds of each a priori measured memory chip, the a priori measured memory chips corresponding to the highest average read and write speed and the lowest average read and write speed are removed, and the average read and write speeds of the remaining a priori measured memory chips are summed and averaged to obtain the average read and write speed of the a priori memory chip array. In this truncated mean processing method, the average read and write delay, single-bit error rate and multi-bit error rate of the a priori memory chip array can be obtained one by one, which will not be repeated here.

[0055] In this embodiment, the first aggregation factor of the a priori memory chip array is executed under the following conditions: ; in, represents the first aggregation factor of the a priori memory chip array, V g represents the average read and write speed of memory chip g determined a priori, T g represents the a priori determination of the read and write delay of memory chip g, C g represents the single bit error rate of memory chip g determined a priori, D g represents the multi-bit error rate of memory chip g determined a priori, represents the average read and write speed of the prior memory chip array, represents the mean read and write latency of the prior memory chip array, represents the single-bit error rate mean of the prior memory chip array, represents the multi-bit error rate mean of the a priori memory chip array, θ1, θ2, θ3, θ4 represent the read / write speed weight, read / write delay weight, single-bit error rate weight, and multi-bit error rate weight, respectively, g is the number of each a priori measured memory chip, g=1,2,…,z, z is the total number of a priori measured memory chips.

[0056] It should be noted that the read / write speed weights, read / write delay weights, single-bit error rate weights, and multi-bit error rate weights all have a value range between 0 and 1. In an embodiment, a preset value can be directly extracted from a temperature chamber data register, or a mapping comparison set of first a priori test data and corresponding weights can be obtained by sampling first a priori test data of multiple groups of memory bars and fitting them. In an application, by importing each independent parameter in the first a priori test data collected this time into the corresponding mapping comparison set, for example, the average read / write speed of each a priori measured memory chip collected in this embodiment is input into the mapping comparison set of average read / write speed and weight, the average read / write speed weight of each a priori measured memory chip can be extracted, and finally the average read / write speed weight of each a priori measured memory chip is averaged to obtain the read / write speed weight. In this way, the read / write delay weights, single-bit error rate weights, and multi-bit error rate weights can be obtained one by one, and brought into the execution conditions for analysis to obtain the first aggregation factor of the a priori memory chip array.

[0057] The various electrical parameter equilibrium values ​​of the memory bar to be tested are extracted from the temperature chamber data register, wherein the various electrical parameter equilibrium values ​​refer to the ideal values ​​or target values ​​of the memory bar design and operation under normal operating conditions.

[0058] According to the balanced values ​​of various electrical parameters of the memory stick to be tested, various electrical parameter baselines are simultaneously mapped and constructed in various electrical parameter perception curves of each priori measured memory chip, and the cumulative coverage area and the cumulative total duration of various electrical parameter perception curves exceeding the corresponding electrical parameter baseline are recorded as the cumulative coverage area of ​​curve measurement drift and the cumulative total duration of curve measurement drift, respectively. Thus, the cumulative coverage area of ​​curve measurement drift and the cumulative total duration of curve measurement drift corresponding to various electrical parameters of each priori measured memory chip are counted, and the oscillation frequency and the highest oscillation time span of various electrical parameter perception curves of each priori measured memory chip are counted, thereby obtaining the second aggregation factor of the priori memory chip array through convergent analysis and processing, and the second aggregation factor is used to characterize the comprehensive measurement electrical performance of the priori memory chip array.

[0059] like Figure 3As shown, it is a schematic diagram of the current parameter perception curve of a priori measured memory chip involved in an embodiment of the present invention. In the figure, time is the horizontal axis and the vertical axis is the current. In this embodiment, the current parameter equilibrium value of the memory stick to be tested is 1.5A, that is, the dotted line constructed at the 1.5A scale on the vertical axis in the figure represents the current parameter baseline. Therefore, it can be seen from the figure that the current parameter perception curve fluctuates with the time displacement. When it is higher than the current parameter baseline, it means that the measured current of this priori measured memory chip exceeds the equilibrium standard. Therefore, the cumulative coverage area and the cumulative total duration exceeding the current parameter baseline can be extracted. The cumulative coverage area and the total duration reflect the severity and frequency of current fluctuations. By monitoring and analyzing these indicators, the operating stability of the memory stick to be tested can be indirectly reflected and evaluated.

[0060] The oscillation frequency and the maximum oscillation time span of the electrical parameter perception curve, wherein the oscillation frequency refers to the frequency of the oscillation phenomenon on the electrical parameter perception curve, that is, the number of oscillations per second, and the maximum oscillation time span refers to the longest time from the beginning of oscillation to the significant reduction or disappearance of the oscillation amplitude on the electrical parameter perception curve. The oscillation frequency and the maximum oscillation time span in the electrical parameter perception curve of the memory stick are important indicators for evaluating the stability of the chip. Accurate evaluation of these parameters can fully reflect the overall reliability and performance of the memory stick.

[0061] In this embodiment, the second aggregation factor of the a priori memory chip array is specifically processed as follows: based on the various electrical parameter perception curves of each a priori measured memory chip, the total coverage area of ​​the various electrical parameter perception curves of each a priori measured memory chip and the total measurement time of various electrical parameters of each a priori measured memory chip are extracted, and the following analysis conditions are introduced for comprehensive processing to obtain the second aggregation factor of the a priori memory chip array, specifically: ; in, represents the second aggregation factor of the prior memory chip array, S gi The curve corresponding to the i-th type of electrical parameters of the memory chip g measured a priori measures the cumulative coverage area of ​​the drift, t gi represents the total cumulative drift time of the curve corresponding to the i-th type of electrical parameters of memory chip g measured a priori, P gi represents the oscillation frequency of the i-th type electrical parameter perception curve of memory chip g determined a priori, k gi represents the highest oscillation time span of the i-th type electrical parameter perception curve of memory chip g determined a priori, represents the total coverage area of ​​the i-th type electrical parameter perception curve of memory chip g determined a priori, represents the total measurement time of the i-th type electrical parameter of memory chip g, They represent the weight of the area covered by the curve measurement drift, the weight of the curve measurement drift duration, the weight of the oscillation frequency, and the weight of the oscillation time span respectively. g is the number of each prior measurement memory chip, g=1,2,…,z, z is the total number of prior measurement memory chips, i is the number of each type of electrical parameters, i=1,2,…,q, q is the total number of electrical parameters.

[0062] It should be explained that the weight of the area covered by the drift measured by the curve, the weight of the drift time measured by the curve, the weight of the oscillation frequency, and the weight of the oscillation time span are all in the range of 0 to 1. The preset value can be directly extracted from the temperature chamber data register, or a mapping comparison set of each curve-related parameter and weight can be constructed by collecting multiple groups of a priori electrical parameter perception curves in the memory bar, such as a mapping comparison set of the area covered by the drift measured by the curve and the weight, a mapping comparison set of the drift time measured by the curve and the weight, etc. In the embodiment, the accumulated coverage area of ​​the drift measured by the curve corresponding to each type of electrical parameter is extracted in turn, and inputted one by one into the mapping comparison set of the drift coverage area of ​​the curve and the weight, so as to obtain the weight of the drift coverage area of ​​the curve corresponding to each type of electrical parameter, and the weight of the drift coverage area of ​​the curve corresponding to each type of electrical parameter is averaged, so as to obtain the weight of the drift coverage area of ​​the curve measured involved in the analysis condition of the final embodiment, and in this way, the drift time weight, the oscillation frequency weight, and the oscillation time span weight are obtained one by one.

[0063] Furthermore, the chip a priori test aggregation index of the memory bar to be tested is obtained by the following specific process: based on the first aggregation factor of the a priori memory chip array and the second aggregation factor of the a priori memory chip array, the chip a priori test aggregation index of the memory bar to be tested is obtained through weighted processing. The chip a priori test aggregation index of the memory bar to be tested is a numerical result obtained by data aggregation and analysis of the a priori memory chip array, which is used to characterize the comprehensive measurement performance of the a priori memory chip array, and serves as a constraint basic condition for constructing a temperature environment for the memory bar to be tested.

[0064] It should be added that the chip priori test aggregation index of the memory stick to be tested has the following specific execution conditions: ; in, Indicates the chip priori test aggregation index of the memory module to be tested. represents the first aggregation factor of the a priori memory chip array, represents the second aggregation factor of the a priori memory chip array, Indicates the first aggregation factor check value defined in the oven data register, Indicates the second aggregation factor check value defined in the oven data register, represents the weight coefficient of the first aggregation factor, represents the weight coefficient of the second aggregation factor, and e is a natural constant.

[0065] In this embodiment, the first aggregation factor weight coefficient and the second aggregation factor weight coefficient both have a value range between 0 and 1. The preset value can be directly extracted from the temperature chamber data register, or a comparison set of the first aggregation factor and the weight coefficient and a comparison set of the second aggregation factor and the weight coefficient can be constructed by collecting multiple groups of historical data. In the embodiment, the first aggregation factor of the prior memory chip array and the second aggregation factor of the prior memory chip array are input into the corresponding comparison set to extract the first aggregation factor weight coefficient and the second aggregation factor weight coefficient.

[0066] Taking the six groups of memory sticks to be tested involved in this embodiment as an example, on the basis of assigning fixed values ​​of 0.4 and 0.6 to the first aggregation factor weight coefficient and the second aggregation factor weight coefficient respectively, the chip priori test aggregation index finally outputted is specifically as follows: Table 1 Example of chip prior test aggregation indicators

[0067] Combined with the above table, it can be seen that on the basis of the first aggregation factor check value and the second aggregation factor check value being a unified fixed value, the chip prior test aggregation index of the memory stick to be tested numbered 6 is the highest, which indicates that the prior memory chip array of the same type as the memory stick to be tested 6 has a higher instability in the historical measurement process, and the high instability means that the performance of this type of memory chip fluctuates greatly under different conditions, and there may be manufacturing defects, design defects or other potential problems. Therefore, when testing the memory stick to be tested 6, it is necessary to set up a more rigorous temperature test environment to help collect detailed performance data and fault information to ensure the product quality and reliability of the memory stick to be tested.

[0068] In an embodiment, the present invention obtains chip prior test data of the memory stick to be tested by matching, and processes to obtain chip prior test aggregation indicators of the memory stick to be tested, thereby achieving normalization and quantification of the chip prior test data. The prior test data can be used as a reference to further reflect the actual test performance of the chip of the memory stick to be tested, thereby providing an early numerical constraint basis for the analysis and acquisition of temperature ranges for the test environment, which can not only help determine the most representative test temperature range and ensure that the temperature test conditions are more in line with the actual performance of the chip of the memory stick to be tested, but also promote the improvement of the accuracy and credibility of the test results.

[0069] S3. Acquisition of the test environment construction temperature range: Acquire the preset adjustable environment construction temperature range of the test motherboard in the temperature chamber, and pre-correct the preset adjustable environment construction temperature range based on the chip prior test aggregation index of the memory stick to be tested to obtain the test environment construction temperature range of the memory stick to be tested.

[0070] It should be understood that the preset adjustable environment builds a temperature range, which refers to a controllable temperature range that can be adjusted by default for the test motherboard in the temperature chamber. This range usually covers the core temperature measurement range required by most memory sticks. The preset adjustable environment builds a temperature range that is mostly pre-set by the corresponding installation management personnel when the test motherboard is installed and calibrated.

[0071] Specifically: the preset adjustable environment construction temperature interval is pre-corrected based on the chip prior test aggregation index of the memory bar to be tested, and the test environment construction temperature interval of the memory bar to be tested is obtained. The specific process includes: based on the chip prior test aggregation index of the memory bar to be tested, and compared with the chip prior test aggregation index threshold in the temperature box data register, the test environment construction adjustment temperature is obtained through pre-correction processing, and the specific correction processing conditions are: ; in, Indicates that the test environment builds the adjustment temperature. Indicates the chip priori test aggregation index of the memory module to be tested. Indicates the chip prior test aggregation index threshold, Indicates the adjusted temperature value corresponding to the chip prior test aggregate unit deviation index defined in the temperature chamber data register; The temperature range is built based on the preset adjustable environment of the test motherboard in the incubator and marked as , and the test environment construction adjustment temperature is processed to obtain the test environment construction temperature range of the memory module to be tested. The numerical expression is: .

[0072] It should be specially noted here that the memory stick to be tested has an upper and lower limit rating of a temperature test stored in the temperature box data register. If in the embodiment, the upper limit value in the temperature interval of the test environment construction of the memory stick to be tested is lower than the upper limit rated value, then the upper limit value in the temperature interval of the test environment construction of the memory stick to be tested is directly defined as the upper limit rated value. Similarly, if the lower limit value in the temperature interval of the test environment construction of the memory stick to be tested is higher than the lower limit rated value, then the lower limit value in the temperature interval of the test environment construction of the memory stick to be tested is directly defined as the lower limit rated value, thereby ensuring that the test environment of the memory stick to be tested meets the rated temperature test standard.

[0073] S4, temperature environment coordinated regulation and construction: based on the test environment construction temperature range of the memory stick to be tested, the temperature of each fixed-point test environment construction of the memory stick to be tested is obtained through re-correction processing, and transmitted to the temperature box controller for temperature environment coordinated regulation and construction.

[0074] In the embodiment, the temperature environment coordinated regulation is constructed, and the specific construction process is as follows: the temperature control circuits on the test mainboard are all powered on and connected to the temperature sensor and the PI electric heating film. When the expected temperature is given, the temperature control circuit supplies power to the PI electric heating film to make it heat up. The temperature sensor feeds back the temperature data of the surrounding area of ​​the memory stick in real time. When the temperature around the memory stick reaches the expected temperature, the temperature control circuit stops supplying power to the PI electric heating film, and then the temperature control circuit adjusts the opening and closing or power of the PI electric heating film according to the temperature value fed back by the temperature sensor, so as to stabilize the temperature at the expected temperature. When multiple memory sticks are tested at the same time, the temperature control circuit can independently control the PI electric heating films on both sides of each memory stick according to the real-time temperature data fed back by the temperature sensors on both sides of each memory stick, so as to realize independent temperature control of each memory stick. When the PI electric heating film has two or more heating zones, the temperature control circuit can independently control the temperature of the corresponding heating zone according to the data fed back by the temperature sensors of each heating zone, so as to realize precise temperature control of each area of ​​the memory stick, wherein the expected temperature is the temperature of each fixed-point test environment construction.

[0075] Specifically, the fixed-point test environment construction temperatures of the memory stick to be tested are obtained through re-correction processing, and the specific correction processing process includes: extracting the test environment construction temperature range value of the memory stick to be tested according to the test environment construction temperature interval of the memory stick to be tested, wherein the test environment construction temperature range value refers to the maximum temperature difference range in the test environment construction temperature interval, for example, the test environment construction temperature interval of the memory stick to be tested is [-20℃, 60℃], then the test environment construction temperature range value is 80℃.

[0076] A temperature range value is constructed according to the test environment of the memory bar to be tested, and is imported into a temperature range segmentation ratio linear model predefined in a temperature chamber data register to extract a first corrected segmentation ratio of the test environment temperature corresponding to the memory bar to be tested.

[0077] like Figure 4As shown, it is a schematic diagram of the linear model of the temperature range segmentation ratio involved in the embodiment of the present invention. The horizontal axis in the figure is the test environment construction temperature range value, and the vertical axis is the test environment temperature first correction segmentation ratio. Referring to the first data point in the figure, it can be seen that when the test environment construction temperature range value is 0, the test environment temperature first correction segmentation ratio is 0, which means that no segmentation operation is performed. Secondly, the second data point in the figure represents the test environment construction temperature range value of the memory bar to be tested involved in this embodiment and the corresponding test environment temperature first correction segmentation ratio. In this embodiment, the test environment construction temperature range value of the memory bar to be tested is 125°C. The first correction segmentation ratio of the test environment temperature located in the figure is 6, that is, 6 temperature test points need to be segmented. Through the temperature range segmentation ratio linear model, the correction segmentation ratio under different temperature conditions can be intuitively understood and located, thereby enhancing the reliability and accuracy of data processing.

[0078] According to the chip priori test aggregation index of the memory bar to be tested, a mapping match is performed with the second corrected segmentation ratio of the test environment temperature corresponding to each priori test aggregation index interval pre-defined by the temperature chamber data register to obtain the second corrected segmentation ratio of the test environment temperature corresponding to the memory bar to be tested.

[0079] Furthermore, the method of obtaining the fixed-point test environment construction temperatures of the memory bar to be tested through re-correction processing also includes: accumulating and synchronously averaging the first corrected segmentation ratio of the test environment temperature and the second corrected segmentation ratio of the test environment temperature corresponding to the memory bar to be tested, obtaining the comprehensive corrected segmentation ratio of the test environment temperature corresponding to the memory bar to be tested, and dividing the test environment construction temperature range value of the memory bar to be tested based on the comprehensive corrected segmentation ratio of the test environment temperature to obtain the fixed-point test environment construction temperatures of the memory bar to be tested.

[0080] For ease of understanding, the first corrected split ratio of the test environment temperature corresponding to the memory stick to be tested and the second corrected split ratio of the test environment temperature corresponding to the memory stick to be tested are accumulated and synchronously averaged to obtain the comprehensive corrected split ratio of the test environment temperature corresponding to the memory stick to be tested, and the numerical form is: ; Wherein, X0 represents the comprehensive correction split ratio of the test environment temperature corresponding to the memory bar under test, X1 represents the first correction split ratio of the test environment temperature corresponding to the memory bar under test, and X2 represents the second correction split ratio of the test environment temperature corresponding to the memory bar under test.

[0081] It should be noted that the test environment temperature construction range value of the memory bar to be tested is divided based on the comprehensive correction division ratio of the test environment temperature, and the starting point of the division is the upper limit value in the test environment temperature range of the memory bar to be tested. By dividing the test environment temperature construction range value of the memory bar to be tested according to the comprehensive correction division ratio of the test environment temperature, the test environment construction temperatures of each fixed point of the memory bar to be tested can be obtained. For example, the comprehensive correction division ratio of the test environment temperature in this embodiment is 8 to 1, that is, 8 temperature test points need to be obtained by division. At the same time, the test environment construction temperature range of the memory bar to be tested in this embodiment is [-40℃, 85℃], and the test environment construction temperature range value is 125℃. The test environment construction temperatures of each fixed point obtained by division are: -40℃, -22℃, -4℃, 12℃, 30℃, 48℃, 66℃, 85℃, wherein except for the upper limit value and the lower limit value of the test environment construction temperature range, the other fixed-point test environment construction temperatures follow the rounding principle.

[0082] In an embodiment, the present invention obtains the temperature of each fixed-point test environment construction of the memory stick to be tested through re-correction processing. By performing fixed-point tests at different temperature points, it is possible to more accurately locate chip problems that may exist in the memory stick to be tested at a specific temperature. At the same time, it is possible to perform targeted testing, reduce unnecessary testing steps, improve the efficiency of the overall testing process, fully ensure the effective allocation and utilization of time and resources, and is also conducive to revealing the true performance of the memory stick to be tested under temperature environment fluctuations, promote better evaluation and verification of the chip reliability and durability of the memory stick to be tested, and improve the credibility of the test results.

[0083] See also Figure 2 As shown, the second aspect of an embodiment of the present invention provides a temperature environment construction system for chip testing and calibration, including: a test memory bar statistics module, which is used to receive a memory chip test request calibration signal triggered by a temperature chamber controller port, and to count the test memory bars currently placed in the test mainboard in the temperature chamber, marking them as memory bars to be tested.

[0084] The chip prior test data preprocessing module is used to obtain the chip type of the memory stick to be tested, and obtain the chip prior test data of the memory stick to be tested based on the chip type matching, and import it into the cloud computing center of the temperature chamber controller for preprocessing to obtain the chip prior test aggregation index of the memory stick to be tested.

[0085] The test environment construction temperature range acquisition module is used to obtain the preset adjustable environment construction temperature range of the test motherboard in the temperature chamber, and pre-correct the preset adjustable environment construction temperature range based on the chip prior test aggregation index of the memory stick to be tested, so as to obtain the test environment construction temperature range of the memory stick to be tested.

[0086] The temperature environment coordinated adjustment construction module is used to construct a temperature range based on the test environment of the memory stick to be tested, obtain the temperature of each fixed-point test environment construction of the memory stick to be tested through re-correction processing, and transmit it to the temperature box controller for temperature environment coordinated adjustment construction.

[0087] In this embodiment, the temperature environment construction system for chip testing and calibration also uses an incubator data register, which is used to store various reference indicator data, such as chip prior test data corresponding to sample memory bars of each chip type and the first aggregation factor verification value, the second aggregation factor verification value, etc. The various reference indicator data are collected and verified by personnel during the test and calibration phase and stored in the incubator data register.

[0088] In an embodiment, the present invention provides a method and system for establishing a temperature environment for chip testing and calibration. By conducting a targeted analysis of the prior data of the memory stick to be tested and obtaining a test environment construction temperature range for the memory stick to be tested, the problem of overly one-sided temperature environment settings currently existing in testing the memory stick is effectively solved. The present invention can fully consider the inconsistency characteristics of the actual application performance of the memory stick, thereby avoiding only a single perception and judgment of whether the temperature of the memory stick has reached the set value, and can accurately simulate complex temperature environment conditions, providing strong data support and guarantee for the accuracy of the test results.

[0089] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0090] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that technicians in the relevant technical field can understand and use the present invention well. As long as they do not deviate from the structure of the present invention or exceed the scope defined by the present invention, they should all belong to the protection scope of the present invention.

Claims

1. A method for constructing a temperature environment for chip testing and calibration, characterized in that: include: The temperature chamber controller receives the memory chip test request calibration signal triggered by the port, and counts the test memory bars currently placed in the test mainboard in the temperature chamber, marking them as memory bars to be tested; Obtain the chip type of the memory bar to be tested, and obtain the chip priori test data of the memory bar to be tested based on the chip type matching, and import it into the cloud computing center of the temperature chamber controller for preprocessing to obtain the chip priori test aggregation index of the memory bar to be tested; Obtaining a preset adjustable environment building temperature range of the test motherboard in the temperature chamber, and pre-correcting the preset adjustable environment building temperature range based on a priori test aggregation indicators of the chip of the memory stick to be tested, to obtain a test environment building temperature range of the memory stick to be tested; Based on the test environment construction temperature range of the memory stick to be tested, the test environment construction temperature of each fixed point of the memory stick to be tested is obtained through re-correction processing, and transmitted to the temperature box controller for coordinated adjustment and construction of the temperature environment.

2. The method for establishing a temperature environment for chip testing and calibration according to claim 1, characterized in that: The chip priori test data of the memory stick to be tested is obtained based on the chip type matching, and the specific matching process includes: According to the chip type of the memory stick to be tested, the chip priori test data corresponding to the sample memory sticks of each chip type stored in the incubator data register is matched, and the chip priori test data corresponding to the sample memory stick consistent with the chip type of the memory stick to be tested is obtained, and marked as the chip priori test data of the memory stick to be tested.

3. The method for establishing a temperature environment for chip testing and calibration according to claim 1, characterized in that: The chip a priori test data of the memory stick to be tested, wherein the chip a priori test data specifically includes first a priori test data and second a priori test data; The first a priori test data includes the average read and write speed, average read and write delay, single-bit error rate and multi-bit error rate of each a priori measured memory chip; The second a priori test data includes various electrical parameter perception curves of each a priori measured memory chip.

4. The method for establishing a temperature environment for chip testing and calibration according to claim 3, characterized in that: The chip priori test data of the memory stick to be tested obtained by matching is imported into the cloud computing center of the temperature box controller for preprocessing. The specific preprocessing process is as follows: integrating and labeling each priori determination memory chip into a priori memory chip array; Based on the average read and write speed, average read and write delay, single-bit error rate and multi-bit error rate of each a priori measured memory chip, the average read and write speed, average read and write delay, average single-bit error rate and average multi-bit error rate of the a priori memory chip array are obtained through truncated mean processing, thereby obtaining a first aggregation factor of the a priori memory chip array through convergent analysis processing, and the first aggregation factor is used to characterize the comprehensive measured read and write performance of the a priori memory chip array; The balanced values ​​of various electrical parameters of the memory stick to be tested are extracted from the temperature chamber data register, and the various electrical parameter baselines are simultaneously mapped and constructed in the various electrical parameter perception curves of each priori measured memory chip. The cumulative coverage area and the cumulative total duration of the various electrical parameter perception curves exceeding the corresponding electrical parameter baseline are recorded as the cumulative coverage area of ​​the curve measurement drift and the cumulative total duration of the curve measurement drift, respectively. The cumulative coverage area of ​​the curve measurement drift and the cumulative total duration of the curve measurement drift corresponding to the various electrical parameters of each priori measured memory chip are statistically calculated, and the oscillation frequency and the highest oscillation time span of the various electrical parameter perception curves of each priori measured memory chip are statistically calculated. The second aggregation factor of the priori memory chip array is obtained through convergent analysis and processing, and the second aggregation factor is used to characterize the comprehensive measurement electrical performance of the priori memory chip array.

5. The method for establishing a temperature environment for chip testing and calibration according to claim 4, characterized in that: The specific process of obtaining the chip priori test aggregation index of the memory bar to be tested is as follows: Based on the first aggregation factor of the a priori memory chip array and the second aggregation factor of the a priori memory chip array, a chip a priori test aggregation index of the memory bar to be tested is obtained through weighted processing. The chip a priori test aggregation index of the memory bar to be tested is a numerical result obtained by performing data aggregation analysis on the a priori memory chip array, which is used to characterize the comprehensive measurement performance of the a priori memory chip array and serves as a constraint basic condition for constructing a temperature environment for the memory bar to be tested.

6. The method for establishing a temperature environment for chip testing and calibration according to claim 1, characterized in that: The pre-correction process of the preset adjustable environment construction temperature range based on the chip prior test aggregation index of the memory bar to be tested is performed to obtain the test environment construction temperature range of the memory bar to be tested. The specific process includes: Based on the chip prior test aggregation index of the memory stick to be tested, and compared with the chip prior test aggregation index threshold in the temperature chamber data register, the test environment construction adjustment temperature is obtained through pre-correction processing. The specific correction processing conditions are: ； in, Indicates that the test environment builds the adjustment temperature. Indicates the chip priori test aggregation index of the memory module to be tested. Indicates the chip prior test aggregation index threshold, Indicates the adjusted temperature value corresponding to the chip prior test aggregate unit deviation index defined in the temperature chamber data register; The temperature range is built based on the preset adjustable environment of the test motherboard in the incubator and marked as , and the test environment construction adjustment temperature is processed to obtain the test environment construction temperature range of the memory module to be tested. The numerical expression is: .

7. The method for establishing a temperature environment for chip testing and calibration according to claim 1, characterized in that: The temperature of each fixed-point test environment of the memory module to be tested is obtained by re-correction processing, and the specific correction processing process includes: According to the test environment construction temperature interval of the memory bar to be tested, the test environment construction temperature range value of the memory bar to be tested is extracted, and imported into the temperature range division ratio linear model pre-defined in the temperature box data register, and the first corrected division ratio of the test environment temperature corresponding to the memory bar to be tested is extracted; According to the chip priori test aggregation index of the memory bar to be tested, a mapping match is performed with the second corrected segmentation ratio of the test environment temperature corresponding to each priori test aggregation index interval pre-defined by the temperature chamber data register to obtain the second corrected segmentation ratio of the test environment temperature corresponding to the memory bar to be tested.

8. The method for establishing a temperature environment for chip testing and calibration according to claim 7, characterized in that: The step of obtaining the temperature of each fixed-point test environment of the memory stick to be tested by re-correction processing also includes: The first corrected segmentation ratio of the test environment temperature and the second corrected segmentation ratio of the test environment temperature corresponding to the memory stick to be tested are accumulated and synchronously averaged to obtain the comprehensive corrected segmentation ratio of the test environment temperature corresponding to the memory stick to be tested, and the test environment construction temperature range value of the memory stick to be tested is divided based on the comprehensive corrected segmentation ratio of the test environment temperature to obtain the fixed-point test environment construction temperatures of the memory stick to be tested.

9. The method for establishing a temperature environment for chip testing and calibration according to claim 5, characterized in that: The chip priori test aggregation index of the memory bar to be tested, the specific execution conditions are: ； in, Indicates the chip priori test aggregation index of the memory module to be tested. represents the first aggregation factor of the a priori memory chip array, represents the second aggregation factor of the a priori memory chip array, Indicates the first aggregation factor check value defined in the oven data register, Indicates the second aggregation factor check value defined in the oven data register, represents the weight coefficient of the first aggregation factor, represents the weight coefficient of the second aggregation factor, and e is a natural constant.

10. A temperature environment construction system for chip testing and calibration, characterized by: include: A test memory bar statistics module is used to receive a memory chip test request calibration signal triggered by a temperature chamber controller receiving port, and to count the test memory bars currently placed in the test motherboard in the temperature chamber, marking them as memory bars to be tested; A chip prior test data preprocessing module is used to obtain the chip type of the memory bar to be tested, and obtain the chip prior test data of the memory bar to be tested based on the chip type matching, and import it into the cloud computing center of the temperature chamber controller for preprocessing to obtain the chip prior test aggregation index of the memory bar to be tested; The test environment construction temperature interval acquisition module is used to obtain the preset adjustable environment construction temperature interval of the test motherboard in the temperature box, and pre-correct the preset adjustable environment construction temperature interval based on the chip prior test aggregation index of the memory bar to be tested, so as to obtain the test environment construction temperature interval of the memory bar to be tested; The temperature environment coordinated adjustment construction module is used to construct a temperature range based on the test environment of the memory stick to be tested, obtain the temperature of each fixed-point test environment construction of the memory stick to be tested through re-correction processing, and transmit it to the temperature box controller for temperature environment coordinated adjustment construction.

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