Chip power consumption attack detection method and system based on voltage comparison, and chip

Abstract

The invention provides a chip power consumption attack detection method and system based on voltage comparison and a chip, and the method comprises the steps: deploying an analog voltage comparator between power grid nodes of an integrated circuit, and carrying out the real-time comparison of the voltage between the power grid nodes through the analog voltage comparator, detecting a voltage change caused by a power consumption analysis attack; extracting features of power grid nodes based on a voltage comparison result, and training the extracted features by using a linear support vector machine model to obtain a trained machine learning model; and finally, embedding the trained machine learning model into an integrated circuit to carry out power consumption analysis attack detection. The voltage difference between adjacent power grid nodes is detected through the analog voltage comparator, and the influence of voltage noise is compensated through multiple times of voltage comparison; the linear support vector machine model is selected as the power consumption analysis attack detection model, the power consumption analysis attack can be detected in real time, and the safety of a hardware system is ensured.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit security technology, and in particular to a chip power consumption attack detection method and system based on voltage comparison, and a chip. Background Art

[0002] With the advancement of integrated circuit design and manufacturing technology, the performance of modern electronic devices has been significantly improved, but it has also brought security issues. Among them, Power Analysis Attack (PAA) as a side channel attack method poses a serious threat to hardware security. PAA analyzes the power consumption information of the chip when performing sensitive operations (such as encryption, decryption, etc.). PAA can use the power consumption side channel information to extract sensitive data, thereby non-invasively obtaining sensitive data inside the chip.

[0003] In a typical PAA, the attacker senses the voltage and current changes on the chip through a malicious probe (usually simulated as a resistor) connected externally to the chip power pad. Then, the collected power consumption side channel information is used for statistical analysis to infer sensitive information. Existing countermeasures mainly increase the unpredictability of the system or actively detect the voltage drop caused by the malicious probe.

[0004] However, the detection reliability of these PAA detection methods is always affected by the mixing of noise in the power side channel information. For example, when the power side channel information is mixed with voltage noise, the detection accuracy of most PAA countermeasures will be significantly reduced. In many circuits, the power side channel information obtained by the sensor always contains some circuit noise, and the noise level can even reach 20% of the supply voltage (Vdd). Therefore, a PAA detection technology with noise immunity is needed. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a chip power consumption attack detection method and system based on voltage comparison and a chip to solve the technical problems existing in the prior art.

[0006] To achieve the above objectives and other related objectives, the present application provides a chip power consumption attack detection method and system based on voltage comparison and a chip, comprising the following steps:

[0007] Deploy analog voltage comparators between power grid nodes of the integrated circuit, and use the analog voltage comparators to compare voltages between power grid nodes in real time to detect voltage changes caused by power analysis attacks;

[0008] Extracting features of power grid nodes based on voltage comparison results;

[0009] The extracted features are trained using a linear support vector machine model to obtain a trained machine learning model;

[0010] The trained machine learning model is embedded into integrated circuits for power analysis attack detection.

[0011] Optionally, before extracting the features of the power grid nodes based on the voltage comparison results, the method further includes:

[0012] Counting the number of wins after voltage comparison for each pair of power grid nodes in a predetermined time period; wherein each pair of power grid nodes includes adjacent power grid nodes; and,

[0013] Counting the winning probability of each pair of power grid nodes after voltage comparison within a predetermined time period; and,

[0014] Counting the ratio of the number of winning times after voltage comparison of each pair of power grid nodes in a predetermined time period to the total number of comparisons;

[0015] The number of winning times after voltage comparison, the probability of winning after voltage comparison, and the ratio of the number of winning times to the total number of comparisons are used as the characteristics of the power grid node.

[0016] Optionally, the method further comprises:

[0017] Accumulating the voltage comparison results using an accumulator; and,

[0018] Using a random access memory to store the voltage comparison result; and,

[0019] Using a read-only memory to store the linear support vector machine model parameters; and,

[0020] The voltage comparison results are classified using a linear classifier according to the linear support vector machine model parameters.

[0021] Optionally, the linear classifier is obtained by offline training using the voltage comparison result as training data.

[0022] The present application also provides a chip power consumption attack detection system based on voltage comparison, the system comprising:

[0023] A voltage comparison unit, configured to deploy an analog voltage comparator between power grid nodes of the integrated circuit, and use the analog voltage comparator to perform real-time comparison of voltages between power grid nodes to detect voltage changes caused by power analysis attacks;

[0024] A feature extraction unit, used for extracting features of power grid nodes according to voltage comparison results;

[0025] A machine learning unit, used for training the extracted features using a linear support vector machine model to obtain a trained machine learning model;

[0026] The attack detection unit is used to embed the trained machine learning model into the integrated circuit for power consumption analysis attack detection.

[0027] Optionally, before extracting the feature of the power grid node according to the voltage comparison result, the feature extraction unit further includes:

[0028] Counting the number of wins after voltage comparison for each pair of power grid nodes in a predetermined time period; wherein each pair of power grid nodes includes adjacent power grid nodes; and,

[0029] Counting the winning probability of each pair of power grid nodes after voltage comparison within a predetermined time period; and,

[0030] Counting the ratio of the number of winning times after voltage comparison of each pair of power grid nodes in a predetermined time period to the total number of comparisons;

[0031] The number of winning times after voltage comparison, the probability of winning after voltage comparison, and the ratio of the number of winning times to the total number of comparisons are used as the characteristics of the power grid node.

[0032] Optionally, the system further comprises:

[0033] An accumulator, used for accumulating the voltage comparison results;

[0034] A random access memory, used for storing the voltage comparison result;

[0035] A read-only memory, used for storing linear support vector machine model parameters;

[0036] A linear classifier is used to classify the voltage comparison results according to the linear support vector machine model parameters.

[0037] Optionally, the linear classifier is obtained by offline training using the voltage comparison result as training data.

[0038] The present application also provides a chip, characterized in that the chip is applied to the chip power consumption attack detection method based on voltage comparison as described in any one of the above, or the chip is applied to the chip power consumption attack detection system based on voltage comparison as described in any one of the above.

[0039] Optionally, the chip is configured with an integrated circuit.

[0040] As described above, the present application provides a chip power consumption attack detection method and system based on voltage comparison and a chip, which has the following beneficial effects: the present application deploys an analog voltage comparator between the power grid nodes of the integrated circuit, and uses the analog voltage comparator to compare the voltage between the power grid nodes in real time, so as to detect the voltage change caused by the power consumption analysis attack; then extracts the features of the power grid nodes based on the voltage comparison result, and uses the linear support vector machine model to train the extracted features to obtain the trained machine learning model; finally, the trained machine learning model is embedded in the integrated circuit for power consumption analysis attack detection. It can be seen that the present application detects the voltage difference between adjacent power grid nodes by analog voltage comparator, and compensates the influence of voltage noise by multiple voltage comparisons. Then, the machine learning method is used to analyze the voltage comparison result, and the linear support vector machine model is selected as the power consumption analysis attack detection model, which can detect the power consumption analysis attack in real time and ensure the security of the hardware system. Moreover, the linear support vector machine model in the present application can be embedded in the design of nanometer-level CMOS process. Compared with the existing power consumption analysis attack detection technology based on voltage sensor and analog-to-digital converter, the present application can reduce the circuit area and power consumption. Therefore, the present application can achieve high detection accuracy even in the case of large voltage noise, thereby effectively addressing the threat of power consumption analysis attacks to hardware security. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of a flow chart of a chip power consumption attack detection method based on voltage comparison provided in an embodiment of the present application;

[0042] Figure 2 A schematic diagram of training and generating a linear support vector machine model provided in an embodiment of the present application;

[0043] Figure 3 A schematic diagram of the collection and labeling of a training data set provided in an embodiment of the present application;

[0044] Figure 4 A schematic diagram of deploying a linear support vector machine model provided in an embodiment of the present application;

[0045] Figure 5 A schematic diagram of the hardware structure of a chip power consumption attack detection system based on voltage comparison provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0047] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present application in a schematic manner, and therefore the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0048] In actual chips, the external voltage needs to be distributed as evenly as possible to the various load circuits inside. To achieve this goal, a power supply voltage grid comes into being. It contacts the high level externally through some specific nodes and then brings this high level to each load circuit through wires. In this case, the power change curve of each load circuit is coupled with the voltage change curve on the power supply grid. This means that sensitive information can be further inferred by monitoring the voltage changes on the nodes in the power supply voltage grid that are in contact with the outside. The means of monitoring the nodes that are in contact with the outside is often to attach a malicious probe circuit on it, and this circuit can be simply simulated as a resistor. The above process is a typical PAA model.

[0049] In order to deal with the influence of voltage noise on PAA detection accuracy, Figure 1 A schematic diagram of a chip power consumption attack detection method based on voltage comparison is shown. Specifically, in an exemplary embodiment, Figure 1 As shown, this embodiment provides a chip power consumption attack detection method based on voltage comparison, and the method includes the following steps:

[0050] S110, deploy analog voltage comparators between power grid nodes (Power Grid, PG for short) of the integrated circuit, and use the analog voltage comparators to compare the voltages between the power grid nodes in real time to detect voltage changes caused by power consumption analysis attacks. As an example, in this embodiment or other embodiments, multiple voltage monitoring points can be first arranged inside the integrated circuit to monitor the voltage changes of the integrated circuit in real time when performing specific operations; these monitoring points are generally directly connected to the power supply of the integrated circuit to ensure that the captured voltage fluctuations are the largest. Then, deploy analog voltage comparators between the power grid nodes of the integrated circuit, and use the analog voltage comparators to compare the voltage values ​​of different monitoring points at the same time point to obtain voltage differences.

[0051] S120, extracting the features of the power grid node based on the voltage comparison result. As an example, in this embodiment or other embodiments, the winning number of each pair of power grid nodes after voltage comparison in a predetermined time period can be counted; wherein each pair of power grid nodes includes adjacent power grid nodes; and, the winning probability of each pair of power grid nodes after voltage comparison in a predetermined time period is counted; and, the ratio of the winning number of each pair of power grid nodes after voltage comparison in a predetermined time period to the total comparison number is counted; finally, the winning number after voltage comparison, the winning probability after voltage comparison, and the ratio of the winning number to the total comparison number are used as the features of the power grid node.

[0052] S130, using a linear support vector machine model to train the extracted features to obtain a trained machine learning model. As an example, in this embodiment or other embodiments, the process of using a linear support vector machine model to train the extracted features to obtain a trained machine learning model is as follows: Figure 2 Specifically, the attack detection model architecture can be established with a linear support vector machine model, and then data can be collected from safe and invaded power grid nodes respectively, and then the detection window length is determined, and the data set formed by the features of the power grid nodes is labeled. The collection and labeling process of the training data set is as follows: Figure 3 As shown. At the same time, the data set is divided into a training set, a validation set, and a test set, and then offline model training is performed, and the trained machine learning model is deployed on the chip for performance evaluation. Finally, the adjacent node comparison results are saved and the model is used for evaluation. It can be seen that this embodiment can use the collected feature data set to train a lightweight linear support vector machine model for PAA classification. The model can accurately identify PG nodes affected by PAA and has high detection accuracy.

[0053] S140, embedding the trained machine learning model into the integrated circuit to perform power analysis attack detection. As an example, in this embodiment or other embodiments, the process of embedding the trained machine learning model into the integrated circuit to perform power analysis attack detection is as follows: Figure 4 As shown. Figure 4 As shown, the present embodiment can also use an accumulator to accumulate the voltage comparison results; and use a random access memory to store the voltage comparison results; and use a read-only memory to store the linear support vector machine model parameters; and use a linear classifier to classify the voltage comparison results according to the linear support vector machine model parameters; wherein the linear classifier is obtained by offline training using the voltage comparison results as training data. It can be seen that the present embodiment designs a real-time PAA detection scheme based on the trained linear SVM model. The scheme includes offline linear classifier training and on-chip PAA classifier design. The effectiveness of power consumption analysis attack detection is verified by simulating the IBM power grid benchmark test, and the detection accuracy and resource consumption are evaluated.

[0054] According to the above records, in a specific embodiment, the process of evaluating the voltage difference can be: detecting the voltage difference between adjacent PG nodes by a voltage comparator, and performing multiple voltage comparisons to eliminate noise errors. This embodiment uses the Gaussian distribution characteristics of noise to calculate the probability of the voltage comparison result, so as to more accurately evaluate the voltage difference. For example, there is currently a pair of power supply voltage grid nodes, node i and node j, and the noise-free voltage values ​​of these two nodes at a certain moment are Vi and Vj respectively. After one of the nodes (such as node i) is invaded and the malicious probe causes a voltage drop to the node, the voltage value Vj of another safe node j will be significantly greater than Vi. By continuously accumulating the comparison results, the phenomenon caused by the voltage drop caused by the malicious probe will eventually be significant enough. However, due to the complexity of the power supply voltage grid nodes, Vi may still be lower than Vj under normal circumstances. In this case, it is difficult to determine whether a voltage drop occurs at node i no matter how it is compared. The introduction of noise can introduce new information to this. Since the noise on the circuit can be simply modeled as a Gaussian distribution, the probability that the voltage of the invaded node i is greater than the voltage of the node i in a safe state is lower than the voltage of the node j in a safe state. As an example, there are currently three nodes, and their voltage values ​​are 1v, 1.1v, and 2v respectively. In the absence of noise, the first node will always be smaller than the next two nodes. But when noise that obeys the Gaussian distribution is introduced, the situation changes. The possibility that the second node is larger than the first node should be significantly smaller than the possibility that the third node is larger than the first node. This brings more information to the subsequent machine learning stage while also making the distribution of data more linear. It can be seen that this embodiment improves the detection accuracy of PAA by evaluating the voltage drop of certain nodes caused by PAA and using a series of voltage comparisons to eliminate the errors caused by noise. Specifically, this embodiment uses an analog voltage comparator to detect the voltage difference between adjacent PG nodes, and performs multiple voltage comparisons to accurately identify the voltage changes caused by PAA.

[0055] According to the above records, in another specific embodiment, the specific process of extracting the power grid node features can be: prepare features for each PG node, including the voltage comparison results of its four neighboring nodes above, below, left and right. These features are used as inputs to the machine learning model to identify the "victim nodes" affected by PAA. For boundary nodes, this embodiment adopts a symmetric filling method to ensure that all nodes have four features. Symmetric filling ensures the integrity of the four-dimensional features by copying the data of the symmetrical neighbors of the same vacant neighbors to the vacant positions. For example, the first node has only lower neighbors and right neighbors, but no upper neighbors and left neighbors. Then the symmetric filling will copy the data of the lower neighbor of the node to the position of the vacant upper neighbor, and the data of the right neighbor to the vacant left neighbor. The specific features are generated by the accumulation of each comparison result. For example, for the feature of node i, it is generated after a fixed number of comparisons. Specifically, when node i is smaller than its neighbor node, the accumulated result is subtracted by one, otherwise, the accumulated result is greater than one, until the number of comparisons reaches the set number of comparisons, and the accumulated value will be extracted. This step can actually be regarded as a probabilistic convergence method.

[0056] According to the above records, in an exemplary embodiment of the present application, the embodiment provides a chip power consumption attack detection method based on voltage comparison, comprising the following steps:

[0057] Step 1: Voltage monitoring and acquisition.

[0058] First, multiple voltage monitoring points are arranged inside the integrated circuit to monitor the voltage changes of the integrated circuit in real time when performing specific operations. These monitoring points are generally directly connected to the power supply of the integrated circuit to ensure that the captured voltage fluctuations are the largest.

[0059] Step 2: confirm the voltage comparison window length and the upper limit of the comparison times.

[0060] The ratio of the voltage comparison window length to the upper limit of the comparison times determines the frequency of the two voltage comparison behaviors. The selection principle is as follows: For the voltage comparison window length, a sufficiently long window length should be selected so that the voltage comparison behavior can cover more voltage curves in time. However, too long a window length will cause the detection delay of the PAA detection system to be too long, and a suitable window length should be selected through experiments. For the number of comparisons, although too large a number of comparisons will further converge the probability, it will cause excessive consumption of storage space. For example, when the number of comparisons is 1000 times, the required storage space is 10 bits. As a rule of thumb, the number of comparisons should be set to 125 times, that is, the required storage space is 7 bits.

[0061] Step 3: Voltage comparison and feature extraction.

[0062] This embodiment can use a voltage comparator to compare the monitored voltage data. Specifically, the voltage values ​​of different monitoring points at the same time point are compared to obtain the voltage difference. These voltage differences are used as feature data for subsequent machine learning model analysis. For example, if the number of comparisons is set to 100 times, the comparison result will be completed and saved after 100 comparisons. When the voltage of node i is greater than that of node j, then for node i, the comparison result is increased by one, and for node j, the comparison result is decreased by one. Of course, the relevant operations can also be interchanged as long as the comparison results can produce sufficient differences in the size of the values. The comparison result of a pair of nodes can generate one-dimensional data for a single node in the pair. This embodiment adopts a four-dimensional data extraction method, that is, the voltages of the four neighboring nodes above, below, left and right of the node are compared. For edge nodes, that is, there are no four neighbors, and the missing dimensions will be filled in a mirror-symmetrical manner, such as Figure 3 Finally, depending on whether the current node is invaded, it is labeled as safe or invaded, which is convenient for subsequent machine learning algorithm training.

[0063] Step 4: Machine learning model training and classification.

[0064] In order to improve the accuracy and efficiency of detection, this embodiment uses a linear kernel support vector machine to classify the feature data. First, the extracted training set is used for training. During the training process, the parameters and structure of the model are adjusted so that it can accurately distinguish between attack data and normal data. After training, the machine learning model can classify the new voltage difference feature data to determine whether the integrated circuit is suffering from PAA. It is worth noting that the support vector machine using a linear kernel function is not the only choice. As long as the linear kernel function that can generate a decision hyperplane can be used for the binary classification, such as logistic regression.

[0065] Step 5: Real-time detection and early warning.

[0066] The trained machine learning model is embedded into the monitoring system of the integrated circuit to achieve real-time detection function. When a potential PAA is detected, the monitoring system will immediately issue an early warning signal so that the system administrator can take corresponding defensive measures. The main components used are voltage comparators, random access memory (RAM) and read-only memory (ROM).

[0067] In summary, the present application provides a chip power consumption attack detection method based on voltage comparison, by deploying an analog voltage comparator between the power grid nodes of the integrated circuit, and using the analog voltage comparator to compare the voltage between the power grid nodes in real time, to detect the voltage change caused by the power analysis attack; then extracting the features of the power grid nodes based on the voltage comparison results, and using the linear support vector machine model to train the extracted features to obtain the trained machine learning model; finally, the trained machine learning model is embedded in the integrated circuit for power analysis attack detection. It can be seen that the method detects the voltage difference between adjacent power grid nodes by analog voltage comparator, and compensates the influence of voltage noise by multiple voltage comparisons. Then the machine learning method is used to analyze the voltage comparison results, and the linear support vector machine model is selected as the power analysis attack detection model, which can detect the power analysis attack in real time and ensure the security of the hardware system. Moreover, the linear support vector machine model in the present method can be embedded in the nanometer-level CMOS process design. Compared with the existing power analysis attack detection technology based on voltage sensor and analog-to-digital converter, the present method can reduce the circuit area and power consumption. Therefore, even in the case of large voltage noise, the present method can achieve high detection accuracy, so as to effectively deal with the threat of power analysis attack to hardware security.

[0068] In another exemplary embodiment of the present application, Figure 5 As shown, this embodiment also provides a chip power consumption attack detection system based on voltage comparison, including:

[0069] The voltage comparison unit 510 is used to deploy analog voltage comparators between power grid nodes of the integrated circuit, and use the analog voltage comparators to compare the voltages between the power grid nodes in real time to detect voltage changes caused by power consumption analysis attacks. As an example, in this embodiment or other embodiments, multiple voltage monitoring points can be first arranged inside the integrated circuit to monitor the voltage changes of the integrated circuit in real time when performing specific operations; these monitoring points are generally directly connected to the power supply of the integrated circuit to ensure that the captured voltage fluctuations are the largest. Then, analog voltage comparators are deployed between the power grid nodes of the integrated circuit, and the analog voltage comparators are used to compare the voltage values ​​of different monitoring points at the same time point to obtain voltage differences.

[0070] The feature extraction unit 520 is used to extract the features of the power grid node according to the voltage comparison result. As an example, in this embodiment or other embodiments, the feature extraction unit 520 can be by counting the number of wins after voltage comparison for each pair of power grid nodes in a predetermined time period; wherein each pair of power grid nodes is composed of adjacent power grid nodes; and by counting the probability of winning after voltage comparison for each pair of power grid nodes in a predetermined time period; and by counting the ratio of the number of wins after voltage comparison for each pair of power grid nodes in a predetermined time period to the total number of comparisons; finally, the number of wins after voltage comparison, the probability of winning after voltage comparison, and the ratio of the number of wins to the total number of comparisons are used as the features of the power grid node.

[0071] The machine learning unit 530 is used to train the extracted features using a linear support vector machine model to obtain a trained machine learning model. As an example, in this embodiment or other embodiments, the process of training the extracted features using a linear support vector machine model to obtain a trained machine learning model is as follows: Figure 2 Specifically, the attack detection model architecture can be established with a linear support vector machine model, and then data can be collected from safe and invaded power grid nodes respectively, and then the detection window length is determined, and the data set formed by the features of the power grid nodes is labeled. The collection and labeling process of the training data set is as follows: Figure 3 As shown. At the same time, the data set is divided into a training set, a validation set, and a test set, and then offline model training is performed, and the trained machine learning model is deployed on the chip for performance evaluation. Finally, the adjacent node comparison results are saved and the model is used for evaluation. It can be seen that this embodiment can use the collected feature data set to train a lightweight linear support vector machine model for PAA classification. The model can accurately identify PG nodes affected by PAA and has high detection accuracy.

[0072] The attack detection unit 540 is used to embed the trained machine learning model into the integrated circuit to perform power analysis attack detection. As an example, in this embodiment or other embodiments, the process of embedding the trained machine learning model into the integrated circuit to perform power analysis attack detection is as follows: Figure 4 As shown. Figure 4As shown, the present embodiment can also use an accumulator to accumulate the voltage comparison results; and use a random access memory to store the voltage comparison results; and use a read-only memory to store the linear support vector machine model parameters; and use a linear classifier to classify the voltage comparison results according to the linear support vector machine model parameters; wherein the linear classifier is obtained by offline training using the voltage comparison results as training data. It can be seen that the present embodiment designs a real-time PAA detection scheme based on the trained linear SVM model. The scheme includes offline linear classifier training and on-chip PAA classifier design. The effectiveness of power consumption analysis attack detection is verified by simulating the IBM power grid benchmark test, and the detection accuracy and resource consumption are evaluated.

[0073] According to the above records, in a specific embodiment, the process of evaluating the voltage difference can be: detecting the voltage difference between adjacent PG nodes by a voltage comparator, and performing multiple voltage comparisons to eliminate noise errors. This embodiment uses the Gaussian distribution characteristics of noise to calculate the probability of the voltage comparison result, so as to more accurately evaluate the voltage difference. For example, there is currently a pair of power supply voltage grid nodes, node i and node j, and the noise-free voltage values ​​of these two nodes at a certain moment are Vi and Vj respectively. After one of the nodes (such as node i) is invaded and the malicious probe causes a voltage drop to the node, the voltage value Vj of another safe node j will be significantly greater than Vi. By continuously accumulating the comparison results, the phenomenon caused by the voltage drop caused by the malicious probe will eventually be significant enough. However, due to the complexity of the power supply voltage grid nodes, Vi may still be lower than Vj under normal circumstances. In this case, it is difficult to determine whether a voltage drop occurs at node i no matter how it is compared. The introduction of noise can introduce new information to this. Since the noise on the circuit can be simply modeled as a Gaussian distribution, the probability that the voltage of the invaded node i is greater than the voltage of the node i in a safe state is lower than the voltage of the node j in a safe state. As an example, there are currently three nodes, and their voltage values ​​are 1v, 1.1v, and 2v respectively. In the absence of noise, the first node will always be smaller than the next two nodes. But when noise that obeys the Gaussian distribution is introduced, the situation changes. The possibility that the second node is larger than the first node should be significantly smaller than the possibility that the third node is larger than the first node. This brings more information to the subsequent machine learning stage while also making the distribution of data more linear. It can be seen that this embodiment improves the detection accuracy of PAA by evaluating the voltage drop of certain nodes caused by PAA and using a series of voltage comparisons to eliminate the errors caused by noise. Specifically, this embodiment uses an analog voltage comparator to detect the voltage difference between adjacent PG nodes, and performs multiple voltage comparisons to accurately identify the voltage changes caused by PAA.

[0074] According to the above records, in another specific embodiment, the specific process of extracting the power grid node features can be: prepare features for each PG node, including the voltage comparison results of its four neighboring nodes above, below, left and right. These features are used as inputs to the machine learning model to identify the "victim nodes" affected by PAA. For boundary nodes, this embodiment adopts a symmetric filling method to ensure that all nodes have four features. Symmetric filling ensures the integrity of the four-dimensional features by copying the data of the symmetrical neighbors of the same vacant neighbors to the vacant positions. For example, the first node has only lower neighbors and right neighbors, but no upper neighbors and left neighbors. Then the symmetric filling will copy the data of the lower neighbor of the node to the position of the vacant upper neighbor, and the data of the right neighbor to the vacant left neighbor. The specific features are generated by the accumulation of each comparison result. For example, for the feature of node i, it is generated after a fixed number of comparisons. Specifically, when node i is smaller than its neighbor node, the accumulated result is subtracted by one, otherwise, the accumulated result is greater than one, until the number of comparisons reaches the set number of comparisons, and the accumulated value will be extracted. This step can actually be regarded as a probabilistic convergence method.

[0075] In summary, the present application provides a chip power consumption attack detection system based on voltage comparison, by deploying analog voltage comparators between power grid nodes of an integrated circuit, and using the analog voltage comparators to compare the voltages between power grid nodes in real time, detecting the voltage changes caused by power consumption analysis attacks; then extracting the features of the power grid nodes based on the voltage comparison results, and using the linear support vector machine model to train the extracted features to obtain the trained machine learning model; finally, embedding the trained machine learning model into the integrated circuit for power consumption analysis attack detection. It can be seen that the system detects the voltage difference between adjacent power grid nodes by analog voltage comparators, and compensates for the influence of voltage noise by multiple voltage comparisons. Then, the machine learning method is used to analyze the voltage comparison results, and the linear support vector machine model is selected as the power consumption analysis attack detection model, which can detect power consumption analysis attacks in real time and ensure the security of the hardware system. Moreover, the linear support vector machine model in the present system can be embedded in the design of nanometer-level CMOS process. Compared with the existing power consumption analysis attack detection technology based on voltage sensors and analog-to-digital converters, the present system can reduce the circuit area and power consumption. Therefore, even in the case of large voltage noise, the present system can achieve high detection accuracy, thereby effectively coping with the threat of power consumption analysis attacks to hardware security.

[0076] It should be noted that the chip power consumption attack detection system based on voltage comparison provided in the above embodiment and the chip power consumption attack detection method based on voltage comparison provided in the above embodiment belong to the same concept, wherein the specific manner in which each module and unit performs the operation has been described in detail in the method embodiment and will not be repeated here. In actual application, the chip power consumption attack detection system based on voltage comparison provided in the above embodiment can allocate the above functions to different functional modules as needed, that is, divide the internal structure of the system into different functional modules to complete all or part of the functions described above, which is not limited here. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0077] In another exemplary embodiment of the present application, the embodiment further provides a chip, which includes an integrated circuit, and is applied to a chip power consumption attack detection system based on voltage comparison as described in the above embodiment, or to a chip power consumption attack detection method based on voltage comparison as described in the above embodiment. It can be understood that since the specific manner in which the chip power consumption attack detection system and the chip power consumption attack detection method perform operations has been described in detail in the embodiments, the technical functions and effects of the chip provided in this embodiment can be referred to the above embodiments, and will not be repeated here.

[0078] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

[0079] The structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of this application, so they have no substantial technical significance. Any modification of the structure, change of the proportional relationship or adjustment of the size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical content disclosed in this application. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of this application. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of this application without substantial change in the technical content.

Claims

1. A chip power consumption attack detection method based on voltage comparison, characterized in that: The method comprises the following steps: Deploy analog voltage comparators between power grid nodes of the integrated circuit, and use the analog voltage comparators to compare voltages between power grid nodes in real time to detect voltage changes caused by power analysis attacks; Extracting features of power grid nodes based on voltage comparison results; The extracted features are trained using a linear support vector machine model to obtain a trained machine learning model; The trained machine learning model is embedded into integrated circuits for power analysis attack detection.

2. The chip power consumption attack detection method based on voltage comparison according to claim 1 is characterized in that: Before extracting the features of the power grid nodes based on the voltage comparison results, the method further includes: Counting the number of wins after voltage comparison for each pair of power grid nodes in a predetermined time period; wherein each pair of power grid nodes includes adjacent power grid nodes; and, Counting the winning probability of each pair of power grid nodes after voltage comparison within a predetermined time period; and, Counting the ratio of the number of winning times after voltage comparison of each pair of power grid nodes in a predetermined time period to the total number of comparisons; The number of winning times after voltage comparison, the probability of winning after voltage comparison, and the ratio of the number of winning times to the total number of comparisons are used as the characteristics of the power grid node.

3. The chip power consumption attack detection method based on voltage comparison according to claim 1 is characterized in that: The method further comprises: Accumulating the voltage comparison results using an accumulator; and, Using a random access memory to store the voltage comparison result; and, Using a read-only memory to store the linear support vector machine model parameters; and, The voltage comparison results are classified using a linear classifier according to the linear support vector machine model parameters.

4. The chip power consumption attack detection method based on voltage comparison according to claim 3 is characterized in that: The linear classifier is obtained by offline training using the voltage comparison result as training data.

5. A chip power consumption attack detection system based on voltage comparison, characterized in that: The system comprises: A voltage comparison unit, configured to deploy an analog voltage comparator between power grid nodes of the integrated circuit, and use the analog voltage comparator to perform real-time comparison of voltages between power grid nodes to detect voltage changes caused by power analysis attacks; A feature extraction unit, used for extracting features of power grid nodes according to the voltage comparison result; A machine learning unit, used for training the extracted features using a linear support vector machine model to obtain a trained machine learning model; The attack detection unit is used to embed the trained machine learning model into the integrated circuit for power consumption analysis attack detection.

6. The chip power consumption attack detection system based on voltage comparison according to claim 5 is characterized in that: Before extracting the feature of the power grid node according to the voltage comparison result, the feature extraction unit further includes: Counting the number of wins after voltage comparison for each pair of power grid nodes in a predetermined time period; wherein each pair of power grid nodes includes adjacent power grid nodes; and, Counting the winning probability of each pair of power grid nodes after voltage comparison within a predetermined time period; and, Counting the ratio of the number of winning times after voltage comparison of each pair of power grid nodes in a predetermined time period to the total number of comparisons; The number of winning times after voltage comparison, the probability of winning after voltage comparison, and the ratio of the number of winning times to the total number of comparisons are used as the characteristics of the power grid node.

7. The chip power consumption attack detection system based on voltage comparison according to claim 5 is characterized in that: The system also includes: An accumulator, used for accumulating the voltage comparison results; A random access memory, used for storing the voltage comparison result; A read-only memory, used for storing linear support vector machine model parameters; A linear classifier is used to classify the voltage comparison results according to the linear support vector machine model parameters.

8. The chip power consumption attack detection system based on voltage comparison according to claim 7 is characterized in that: The linear classifier is obtained by offline training using the voltage comparison result as training data.

9. A chip, characterized in that: The chip is applied to the chip power consumption attack detection method based on voltage comparison as described in any one of claims 1 to 4, or the chip is applied to the chip power consumption attack detection system based on voltage comparison as described in any one of claims 5 to 8.

10. The chip according to claim 9, wherein the chip is provided with an integrated circuit.

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