Automatic design method and system for test diagnosis

Abstract

The invention discloses an automatic design method and system for test diagnosis, and the method comprises the steps: reading an application design, determining a to-be-tested device needing to be tested in the application design, building a self-test diagnosis circuit netlist according to the to-be-tested device, generating a schematic circuit diagram according to the self-test diagnosis circuit netlist, and carrying out the self-test diagnosis according to the schematic circuit diagram. The schematic circuit diagram is a schematic circuit diagram of layout of each component and wiring among the components, a self-test diagnosis circuit board design diagram is generated according to the schematic circuit diagram, and the self-test diagnosis circuit board design diagram represents a circuit wiring design diagram of a connection relation between a test circuit and a diagnosis circuit. And designing the self-test diagnosis circuit board through the design drawing of the self-test diagnosis circuit board.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and more specifically, to an automated design method and system for test diagnosis. Background Art

[0002] With the development of integrated circuit technology, the application scale of hardware systems such as base stations, network architectures and lightweight application terminals continues to grow, the functions become more and more complex, and issues such as reliability and security become increasingly prominent.

[0003] In order to improve the reliability and security of the hardware system, the hardware system is tested, diagnosed and maintained. With the continuous improvement of the informatization, intelligence and integration of the hardware system, the realization of the functions of the testing, diagnosis and maintenance operations is highly dependent on some key components, such as optical communication components, lightweight terminal chips, radio frequency microwave components, power components, etc., and the realization of their test circuits. The technical threshold is high, and the design of customized test and diagnosis circuits is difficult and has a long development cycle, resulting in low design efficiency.

[0004] Therefore, how to improve the design efficiency of the test diagnosis circuit is an urgent problem to be solved in this application. Summary of the invention

[0005] In view of this, the present application discloses an automated design method and system for test diagnosis, which aims to realize automated design of a self-test diagnosis circuit for an application circuit according to the requirements of the application design, thereby improving the design efficiency of the self-test diagnosis circuit.

[0006] In order to achieve the above purpose, the disclosed technical solution is as follows:

[0007] In a first aspect, the present application discloses an automated design method for test diagnosis, the method comprising:

[0008] Read application design;

[0009] Determine the device to be tested in the application design, and establish a self-test diagnostic circuit netlist based on the device to be tested;

[0010] Generate a circuit schematic diagram according to the self-test diagnostic circuit netlist; the circuit schematic diagram is a circuit schematic diagram of the layout of each component and the wiring between each component;

[0011] A self-test diagnostic circuit board design diagram is generated according to the circuit principle diagram; the self-test diagnostic circuit board design diagram represents a circuit wiring design diagram of the connection relationship between the test circuit and the diagnostic circuit;

[0012] A self-test diagnostic circuit board is designed according to the self-test diagnostic circuit board design drawing.

[0013] Preferably, before determining the device to be tested that needs to be tested in the application design and establishing a self-test diagnostic circuit netlist according to the device to be tested, the method further includes:

[0014] Analyze the application circuit corresponding to the application design to obtain analysis information; the analysis information at least includes the signal frequency of the application circuit line network and the current of the application circuit line network;

[0015] The device to be tested and the pins to be tested corresponding to the device to be tested are generated through the analysis information.

[0016] Preferably, it also includes:

[0017] According to the diagnostic model of the device under test, the pins to be tested are optimized to improve the test coverage and reduce the number of pins to be tested.

[0018] Preferably, the step of determining a device to be tested in the application design and establishing a self-test diagnostic circuit netlist according to the device to be tested includes:

[0019] Identify the devices to be tested in the application design;

[0020] Selecting a test circuit for the device to be tested from a device test circuit library;

[0021] A self-test diagnosis circuit netlist is constructed through the test circuit of the device under test.

[0022] Preferably, it also includes:

[0023] The self-test diagnostic circuit netlist is optimized.

[0024] Preferably, generating a circuit schematic diagram according to the self-test diagnostic circuit netlist includes:

[0025] Performing signal flow analysis and virtual layout and routing on the self-test diagnostic circuit netlist to extract layout constraints and routing constraints of each component on the circuit diagram; the layout constraints are constraints on the positional relationship of the signal flow between each component; the routing constraints are constraints on the routing sequence and wire net type between each component;

[0026] The layout of each component is driven by the layout constraint, and the wiring between each component is driven by the wiring constraint, so as to generate a circuit schematic diagram.

[0027] Preferably, generating a self-test diagnostic circuit board design diagram according to the circuit schematic diagram includes:

[0028] Performing signal flow analysis on the self-test diagnosis circuit netlist to determine the relative position relationship constraints between various components on the self-test diagnosis circuit board;

[0029] According to the device pins, the positions of the external connections and the target connection points are calculated to obtain the device peripheral dimensions;

[0030] Analyze the self-test diagnosis circuit netlist to obtain wire net constraints; the wire net constraints are constraints on the connection sequence, wire net length and wire net width between various components on the self-test diagnosis circuit board;

[0031] Analyze the self-test diagnosis circuit netlist and circuit schematic diagram to obtain the wiring sequence constraints and physical connection parasitic parameter constraints between the components on the self-test diagnosis circuit board; the physical connection parasitic parameter constraints are determined by the voltage drop, signal delay and signal integrity allowed by the self-test diagnosis circuit board;

[0032] The wiring is performed under the relative position relationship constraint, the wire net constraint, the wiring sequence constraint and the physical connection parasitic parameter constraint, thereby generating a self-test diagnosis circuit board design drawing.

[0033] Preferably, the analyzing the self-test diagnostic circuit netlist to obtain line net constraints includes:

[0034] The endpoints of each wire net in the self-test diagnosis circuit net list are analyzed to obtain the wire net constraints of the wiring sequence, wire net length and wire net width between various components on the self-test diagnosis circuit board.

[0035] Preferably, the process of designing a self-test diagnostic circuit board according to the self-test diagnostic circuit board design drawing includes:

[0036] Analyze the self-test diagnostic circuit board design drawing to obtain design constraints; the design constraints at least include parasitic parameter constraints of the connection, connection sequence constraints of the line net, connection length constraints and connection width constraints;

[0037] Under the design constraints, the test circuit and the diagnostic circuit are wired on a self-test diagnostic circuit board, thereby completing the design of the self-test diagnostic circuit board.

[0038] A second aspect of the present application discloses an automated design system for test diagnosis, the system comprising:

[0039] A reading unit, used for reading the application design;

[0040] A determination unit, used to determine a device to be tested in the application design, and to establish a self-test diagnostic circuit netlist according to the device to be tested;

[0041] A first generating unit is used to generate a circuit schematic diagram according to the self-test diagnostic circuit netlist; the circuit schematic diagram is a circuit schematic diagram of the layout of each component and the wiring between each component;

[0042] A second generating unit is used to generate a self-test diagnostic circuit board design diagram according to the circuit schematic diagram; the self-test diagnostic circuit board design diagram represents a circuit wiring design diagram of the connection relationship between the test circuit and the diagnostic circuit;

[0043] The design unit is used to design a self-test diagnosis circuit board according to the self-test diagnosis circuit board design drawing.

[0044] Through the above technical scheme, it can be known that the present application discloses a test diagnosis method and system, which determines the device to be tested, reads the application design, determines the device to be tested that needs to be tested in the application design, and establishes a self-test diagnosis circuit netlist according to the device to be tested, generates a circuit schematic diagram according to the self-test diagnosis circuit netlist, and the circuit schematic diagram is a circuit schematic diagram of the layout of each component and the wiring between each component, generates a self-test diagnosis circuit board design diagram according to the circuit schematic diagram, and the self-test diagnosis circuit board design diagram represents the circuit wiring design diagram of the connection relationship between the test circuit and the diagnosis circuit, and designs the self-test diagnosis circuit board through the self-test diagnosis circuit board design diagram. Through the above scheme, according to the circuit schematic diagram of the layout of each component and the wiring between each component, a circuit wiring design diagram of the connection relationship between the test circuit and the diagnosis circuit, that is, a self-test diagnosis circuit board design diagram, is generated, and through the self-test diagnosis circuit board design diagram with the connection relationship between the test circuit and the diagnosis circuit, the self-test diagnosis circuit board design diagram of the application circuit is automatically designed according to the needs of the application design, and the design efficiency of the self-test diagnosis circuit is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0046] Figure 1 A schematic diagram of a flow chart of an automated design method for test diagnosis disclosed in an embodiment of the present application;

[0047] Figure 2 A flow chart generated for the test circuit disclosed in the embodiment of the present application;

[0048] Figure 3 A flow chart of generating a circuit schematic diagram disclosed in an embodiment of the present application;

[0049] Figure 4 A flow chart of a PCB physical wiring design between a test circuit and a diagnostic circuit disclosed in an embodiment of the present application;

[0050] Figure 5 A flowchart of a test circuit wiring process disclosed in an embodiment of the present application;

[0051] Figure 6 A flow chart of PCB wiring between self-test diagnostic circuits disclosed in an embodiment of the present application;

[0052] Figure 7 A schematic diagram of the structure of an automated design system for test diagnosis disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0054] In this application, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0055] As can be seen from the background technology, in order to improve the reliability and safety of the hardware system, the hardware system is tested, diagnosed and maintained. With the continuous improvement of the informationization, intelligence and integration of the hardware system, the functional realization of the test and maintenance operations such as testing, diagnosis and maintenance is highly dependent on some key components, such as optical communication components, lightweight terminal chips, radio frequency microwave components, power components, etc., and the realization of their test circuits. The technical threshold is high, and the design of the customized test and diagnosis circuit design is difficult and the development cycle is long, resulting in low design efficiency. Therefore, how to improve the design efficiency of the test and diagnosis circuit is a problem that needs to be solved urgently in this application.

[0056] In order to solve the above problems, the present application discloses a test diagnosis method and system, which reads the application design, determines the device to be tested in the application design, and establishes a self-test diagnosis circuit netlist according to the device to be tested, generates a circuit schematic diagram according to the self-test diagnosis circuit netlist, and the circuit schematic diagram is a circuit schematic diagram of the layout of each component and the wiring between each component, generates a self-test diagnosis circuit board design diagram according to the circuit schematic diagram, and the self-test diagnosis circuit board design diagram represents the circuit wiring design diagram of the connection relationship between the test circuit and the diagnostic circuit, and designs the self-test diagnosis circuit board through the self-test diagnosis circuit board design diagram. Through the above scheme, according to the circuit schematic diagram of the layout of each component and the wiring between each component, a circuit wiring design diagram of the connection relationship between the test circuit and the diagnostic circuit, that is, a self-test diagnosis circuit board design diagram, is generated, and through the self-test diagnosis circuit board design diagram with the connection relationship between the test circuit and the diagnostic circuit, the self-test diagnosis circuit board design diagram of the application circuit is automatically designed according to the requirements of the application design, and the design efficiency of the self-test diagnosis circuit is improved. The specific implementation method is described by the following embodiment.

[0057] refer to Figure 1 FIG. 1 is a flow chart of an automated test diagnosis design method disclosed in an embodiment of the present application. The automated test method mainly includes the following steps:

[0058] S101: Read application design.

[0059] The application circuit corresponding to the application design is analyzed to obtain analysis information; the analysis information at least includes the signal frequency of the application circuit line network and the current of the application circuit line network, and the device to be tested and the pin to be tested corresponding to the device to be tested are generated through the analysis information.

[0060] Among them, the application design is read, and a self-test diagnostic circuit netlist for self-test and self-diagnosis is established based on the embedded chip for the device to be tested that needs to be tested in the application design. Specifically, a test circuit of the device to be tested is selected from a device test circuit library, and a self-test diagnostic circuit netlist for self-test and self-diagnosis is constructed based on the test circuit of the device to be tested.

[0061] For the devices that need to be tested in the application design, a self-test and self-diagnosis circuit netlist is established based on the embedded chip to automatically analyze the application circuit, and the devices and device pins that need to be tested are generated based on the signal frequency of the application circuit network, the current of the application circuit network, etc.

[0062] Self-test is a concept relative to external test. External test refers to applying stimulus to the input end of the device to be tested on the self-test diagnostic circuit board (Printed Circuit Board, PCB) through a test instrument outside the PCB, and the measuring instrument obtains the output signal from the output end of the device to be tested. The self-test of this application is an online test in the system work (in-system), which does not rely on the task external test instrument, does not require an external test instrument to apply test stimulus, and does not need to obtain the signal of the output end of the object to be tested through an external test instrument. The test stimulus of the object to be tested is the signal generated in the actual work of the PCB. Under the premise of not affecting the normal operation of the system, the information of the input and output ends of the device to be tested is automatically obtained through the hardware circuit on the PCB, and the built-in diagnostic program on the PCB performs diagnostic analysis.

[0063] The self-test is controlled by a control circuit, typically a microcontroller or microprocessor.

[0064] The self-test process generally includes selecting a test path for acquiring a signal, acquiring a test signal, deselecting, and the like.

[0065] S102: Determine the device to be tested in the application design, and establish a self-test diagnosis circuit netlist based on the device to be tested.

[0066] Generating the devices and device pins to be tested also includes determining the output power of the device to be tested, the voltage level on the pin to be tested, the current on the pin to be tested, etc.

[0067] According to the diagnostic model of the device under test, the pins to be tested are optimized to improve the test coverage and reduce the number of pins to be tested.

[0068] Specifically, generating the devices and device pins to be tested includes optimizing the pins to be tested of the device to be tested according to the diagnosis model of the device to be tested, so as to improve the test coverage and reduce the number of pins to be tested.

[0069] The process of establishing a self-test diagnostic circuit netlist is combined Figure 2 Provide explanation. Figure 2 A flow chart showing test circuit generation is shown.

[0070] Figure 2 In the method, the application circuit schematic (i.e., circuit schematic), component library, and device test circuit library are used as input data to execute reading of the application circuit, select the device to be tested from the application circuit, select the test circuit of the device from the test circuit, and generate the total test circuit (i.e., self-test diagnostic circuit netlist).

[0071] Select the required device to be tested; select the test circuit of the device to be tested from the device test circuit library; and construct a self-test diagnosis circuit netlist based on the test circuit of the device to be tested.

[0072] The self-test diagnostic circuit netlist includes at least a circuit node analog signal level measurement and control circuit, a circuit branch current measurement and control circuit, a device pin output power consumption measurement and control circuit, a circuit node analog signal frequency measurement and control circuit, a circuit node digital signal frequency measurement and control circuit, a circuit node logic level measurement and control circuit, and a phase difference measurement and control circuit between circuit nodes.

[0073] A test circuit of the device to be tested is selected from a device test circuit library, and a self-test diagnosis circuit netlist is constructed through the test circuit of the device to be tested.

[0074] Circuit node analog signal level measurement and control circuit, including:

[0075] The circuit node is connected to the analog signal input end of the analog signal multiplexer, the output end of the analog signal multiplexer is connected to the input end of the analog-to-digital converter, the digital output end of the analog-to-digital converter is connected to the data input end of the register, the clock input end of the register and the clock signal input end of the analog-to-digital converter are connected to the clock signal circuit, the data output end of the register is connected to the data input end of the embedded chip, and the clock signal circuit may be controlled by the embedded chip.

[0076] The circuit branch current measurement and control circuit is used for:

[0077] A resistor Rsense for testing current is connected in series in the branch, and then the signal level measurement and control circuit is simulated according to the above circuit node, and a test circuit for measuring the level at both ends of the resistor is automatically designed. After obtaining the level value at both ends of the resistor, the embedded chip calculates the current of the branch according to the current calculation formula.

[0078] Device pin output power consumption measurement and control circuit is used for:

[0079] According to the above-mentioned circuit node analog signal level measurement and control circuit, the circuit node analog signal level measurement and control circuit is automatically designed, and according to the above-mentioned circuit branch current measurement and control circuit, the circuit branch current measurement and control circuit is automatically designed. After calculating the current, the embedded chip calculates the output power consumption in combination with the measured node level.

[0080] Circuit node analog signal frequency measurement and control circuit is used for:

[0081] The node is connected to a digital signal input terminal of a digital signal multiplexer, and the output terminal of the digital signal multiplexer is connected to a data input terminal of a register; or the node is directly connected to a data input terminal of a register. The clock input terminal of the register is connected to a clock signal circuit, and the data output terminal of the register is connected to a data input terminal of an embedded chip, and the clock signal circuit may be controlled by the embedded chip.

[0082] It should be noted that for the design of circuit node analog signal frequency measurement and control circuits, circuit node digital signal frequency measurement and control circuits, and phase difference measurement and control circuits between circuit nodes, reference may be made to relevant reference books in the field.

[0083] Optimize the self-test diagnostic circuit netlist. The optimization is used to reduce the scale of the test circuit; reduce the components required for the test circuit; reduce the cost of test circuit components; reduce the PCB area; reduce the difficulty of PCB design layout and wiring, etc. The optimization method includes at least one of the following or any combination:

[0084] Degenerate embedded chip; degenerate analog signal multiplexer; degenerate digital signal multiplexer; degenerate amplifier; degenerate state register; degenerate data register; degenerate clock circuit; degenerate signal frequency measurement circuit; degenerate phase difference measurement circuit.

[0085] S103: Generate a circuit schematic diagram according to the self-test diagnosis circuit netlist; the circuit schematic diagram is a circuit schematic diagram of the layout of each component and the wiring between each component.

[0086] Specifically, based on the self-test diagnostic circuit netlist, the process of generating the circuit schematic is as follows:

[0087] First, signal flow analysis and virtual layout and routing are performed on the self-test diagnosis circuit netlist to extract the layout constraints and routing constraints of each component on the circuit diagram; the layout constraints are the constraints on the positional relationship of the signal flow between each component; the routing constraints are the constraints on the routing sequence and wire net type between each component.

[0088] Then, the layout of each component is driven by the layout constraints, and the wiring between each component is driven by the wiring constraints to generate a circuit schematic.

[0089] The layout constraints of the circuit schematic drive the layout of components; and the wiring constraints of the circuit schematic drive the connections between components.

[0090] Signal flow analysis and virtual layout and routing are performed on the self-test diagnosis circuit netlist to extract the layout constraints and routing constraints of each component on the circuit diagram, and the layout of each component is driven by the layout constraints and the routing between each component is driven by the routing constraints to generate a circuit schematic.

[0091] Among them, the layout constraints are the constraints on the position (such as up and down, left and right) relationship of the signal flow between various components; the wiring constraints are the constraints on the wiring sequence and wire network type between various components.

[0092] According to the circuit node simulation signal level measurement and control circuit, the layout constraints of each component on the circuit diagram are extracted, that is, the up-down and left-right position relationships between the components that protect the signal flow are extracted.

[0093] According to the circuit node simulation signal level measurement and control circuit, the wiring constraints of components on the circuit diagram are extracted. Specifically, according to the electrical properties of the signals carried by the wire nets, the wire nets that can be exempted from electrical connections (such as power wire nets, clock wire nets, wire nets with long-distance connections on the circuit diagram, etc.) and differential wire net constraints are determined.

[0094] Extracting the wiring constraints of components on the circuit diagram can be based on circuit node analog signal level measurement and control circuit, device pin output power consumption measurement and control circuit, combined with component layout information analysis on the circuit diagram to extract the wiring constraints of components on the circuit diagram.

[0095] According to the circuit node analog signal level measurement and control circuit, device pin output power consumption measurement and control circuit, circuit node logic level measurement and control circuit, the wiring constraints of components on the circuit diagram are extracted. Specifically, the wiring sequence is determined by the length of the connection at the geometric position or the wiring sequence is determined by the length of the connection signal flow of the line net on the signal flow. Figure 3 Provide explanation. Figure 3 A flow chart for generating a circuit diagram (i.e., a circuit schematic).

[0096] Figure 3 In the process, the total test circuit and components are used as input data to perform operations such as circuit diagram constraint extraction, circuit diagram automatic layout, circuit diagram automatic wiring and circuit diagram output.

[0097] S104: Generate a self-test diagnosis circuit board design (ie, PCB design) diagram according to the circuit schematic diagram; the self-test diagnosis circuit board design diagram represents a circuit wiring design diagram of the connection relationship between the test circuit and the diagnosis circuit.

[0098] Among them, the PCB physical connection design between the test circuit and the diagnostic circuit (application circuit PCB design and test circuit PCB design) is generated according to the connection relationship between the test circuit and the diagnostic circuit. Figure 4 Provide explanation. Figure 4 A flow chart for generating a PCB physical wiring design between a test circuit and a diagnostic circuit is shown.

[0099] Figure 4 In the method, the application circuit schematic, component library, device test circuit library and application circuit PCB design are used as input data to execute the steps of automatically generating a self-testing and self-diagnosing function circuit netlist, automatically generating a self-testing and self-diagnosing function circuit schematic, automatically generating a self-testing and self-diagnosing function circuit PCB and automatically generating application-self-testing and self-diagnosing circuit connection lines.

[0100] Specifically, the process of generating a self-test diagnosis circuit board design diagram according to the circuit schematic diagram is shown in A1-A5.

[0101] A1: Perform signal flow analysis on the self-test diagnostic circuit netlist to determine the relative position relationship constraints (layout relative positions) between various components on the self-test diagnostic circuit board (PCB).

[0102] A2: Based on the device pins, the locations of external connections and target connection points are calculated to obtain the device perimeter (Halos) size.

[0103] Among them, the size of the device's peripheral Halos, especially the different Halos around the device, is calculated based on the external connection of the device's pins (especially advanced packaging chips such as BGA) and the position of the target connection point.

[0104] A3: Analyze the self-test diagnosis circuit netlist to obtain the wire net constraints; the wire net constraints are the constraints on the connection sequence, wire net length and wire net width between various components on the self-test diagnosis circuit board.

[0105] In A3, the endpoints of each net in the self-test diagnosis circuit netlist are analyzed to obtain the net constraints of the wiring sequence, net length and net width between the components on the self-test diagnosis circuit board.

[0106] A4: Analyze the self-test diagnostic circuit netlist and circuit schematic to obtain the wiring sequence constraints and physical connection parasitic parameter constraints between the components on the self-test diagnostic circuit board; the physical connection parasitic parameter constraints are determined by the allowable voltage drop and signal delay and signal integrity of the self-test diagnostic circuit board.

[0107] In A4, the layout of the components of the self-test diagnosis circuit netlist and circuit schematic diagram is analyzed to obtain the wiring sequence constraints and physical connection parasitic parameter constraints between the components on the PCB.

[0108] Calculate the wiring parasitic parameter constraints based on the allowed voltage drop, signal delay, signal integrity, etc.

[0109] A5: Perform wiring under the constraints of relative position relationship, wire net constraint, wiring sequence constraint and physical connection parasitic parameter constraint to generate a self-test diagnosis circuit board design drawing.

[0110] Specifically, the wiring process is carried out under the constraints of relative position relationship, wire network constraint, wiring sequence constraint and physical connection parasitic parameter constraint. Figure 5 To explain, Figure 5 A flow chart showing the test circuit wiring process is shown.

[0111] The application circuit PCB design, component library, total test circuit and PCB design rules (i.e., the above-mentioned process A1-A5) are used as input data to perform the steps of test circuit layout constraint extraction, constraint-driven test circuit layout, test circuit layout output (optional), test circuit routing constraint extraction, test circuit routing script generation, test circuit routing script execution and test circuit routing output (optional).

[0112] S105: Design a self-test diagnostic circuit board according to a self-test diagnostic circuit board design drawing.

[0113] In S105, the self-test diagnostic circuit board design drawing is analyzed to obtain design constraints; the design constraints include at least parasitic parameter constraints of the connection, the connection sequence constraints of the wire net, the connection length constraints and the connection width constraints. Under the design constraints, the test circuit and the diagnostic circuit are wired for the self-test diagnostic circuit board, thereby completing the design of the self-test diagnostic circuit board.

[0114] Analyze the connection between the application and the self-test and self-diagnosis circuit (i.e., self-test and self-diagnosis circuit) to determine the parasitic parameter constraints of the connection; analyze the endpoints of each wire net between the application and the self-test and self-diagnosis circuit to determine the constraints such as the connection sequence, connection length, and connection width of the wire net; perform PCB wiring between the application and the self-test and self-diagnosis circuit under the above constraints.

[0115] Specifically, the process of PCB wiring between the application and the self-test diagnostic circuit is combined with Figure 6 To explain, Figure 6 A flow chart showing PCB routing between self-test diagnostic circuits.

[0116] The application circuit PCB design, the test circuit PCB design, the component library and the overall test circuit are used as input data to perform the steps of extracting application-test interface routing constraints, generating a test circuit routing script and executing the test circuit routing script.

[0117] The hardware circuit on the self-test diagnostic circuit board can automatically obtain the test signal at the input end and the test signal at the output end of the device under test, and perform test diagnostic operations on the test signal of the device under test through a preset diagnostic program and a pre-designed self-test diagnostic circuit board.

[0118] The test diagnosis operation is used to determine whether the output power of the device under test, the level of the pin under test and the current of the pin under test are within the respective corresponding test reference ranges.

[0119] In an embodiment of the present application, based on a circuit schematic diagram of the layout of each component and the wiring between each component, a circuit wiring design diagram of the connection relationship between the test circuit and the diagnostic circuit, i.e., a self-test diagnostic circuit board design diagram, is generated. By using the self-test diagnostic circuit board design diagram of the connection relationship between the test circuit and the diagnostic circuit, it is possible to automatically design a self-test diagnostic circuit for the application circuit according to the requirements of the application design, thereby improving the design efficiency of the self-test diagnostic circuit.

[0120] Based on the above embodiments Figure 1 The disclosed test diagnosis automated design method, the present application embodiment also discloses a test diagnosis automated design system, such as Figure 7 As shown, the test diagnosis automated design system includes a reading unit 701 , a determining unit 702 , a first generating unit 703 , a second generating unit 704 and a designing unit 705 .

[0121] A reading unit is used to read the application design.

[0122] The determination unit is used to determine the device to be tested in the application design and to establish a self-test diagnosis circuit netlist according to the device to be tested.

[0123] The first generating unit is used to generate a circuit schematic diagram according to the self-test diagnosis circuit netlist; the circuit schematic diagram is a circuit schematic diagram of the layout of each component and the wiring between each component.

[0124] The second generating unit is used to generate a self-test diagnostic circuit board design diagram according to the circuit principle diagram; the self-test diagnostic circuit board design diagram represents a circuit wiring design diagram of the connection relationship between the test circuit and the diagnostic circuit.

[0125] The design unit is used for designing a self-test diagnosis circuit board through a self-test diagnosis circuit board design drawing.

[0126] Furthermore, the automated design system for test diagnosis also includes an acquisition unit and a third generation unit.

[0127] The acquisition unit is used to analyze the application circuit corresponding to the application design to obtain analysis information; the analysis information at least includes the signal frequency of the application circuit line network and the current of the application circuit line network.

[0128] The third generating unit is used to generate a device to be tested and a pin to be tested corresponding to the device to be tested by analyzing the information.

[0129] Furthermore, the automated design system for test diagnosis also includes a first optimization unit.

[0130] The first optimization unit is used to optimize the pins to be tested according to the diagnosis model of the device to be tested, so as to improve the test coverage and reduce the number of the pins to be tested.

[0131] Furthermore, the determining unit includes a first determining module, a selecting module and a constructing module.

[0132] The first determination module is used to determine the device to be tested in the application design.

[0133] The selection module is used to select a test circuit of a device to be tested from a device test circuit library.

[0134] The building module is used to build a self-test diagnosis circuit netlist through the test circuit of the device under test.

[0135] Furthermore, the automated design system for test diagnosis also includes a second optimization unit.

[0136] The second optimization unit is used to optimize the self-test diagnosis circuit netlist.

[0137] Furthermore, the first generating unit includes an extracting module and a generating module.

[0138] The extraction module is used to perform signal flow analysis and virtual layout and routing on the self-test diagnosis circuit netlist to extract the layout constraints and routing constraints of each component on the circuit diagram; the layout constraints are the constraints on the positional relationship of the signal flow between each component; the routing constraints are the constraints on the routing sequence and wire net type between each component.

[0139] The generation module is used to drive the layout of each component through layout constraints and drive the wiring between each component through wiring constraints to generate a circuit schematic.

[0140] Furthermore, the second generating unit includes a second determining module, a calculating module, a first analyzing module, a second analyzing module and a first routing module.

[0141] The second determination module is used to perform signal flow analysis on the self-test diagnosis circuit netlist to determine the relative position relationship constraints between various components on the self-test diagnosis circuit board.

[0142] The calculation module is used to calculate the positions of the device pins, external connections and target connection points to obtain the device peripheral dimensions.

[0143] The first analysis module is used to analyze the self-test diagnosis circuit netlist to obtain the wire net constraints; the wire net constraints are the constraints on the connection sequence, wire net length and wire net width between various components on the self-test diagnosis circuit board.

[0144] The second analysis module is used to analyze the self-test diagnosis circuit netlist and circuit schematic diagram to obtain the wiring sequence constraints and physical connection parasitic parameter constraints between various components on the self-test diagnosis circuit board; the physical connection parasitic parameter constraints are determined by the allowable voltage drop, signal delay and signal integrity of the self-test diagnosis circuit board.

[0145] The first wiring module is used to perform wiring under the constraints of relative position relationship, wire net constraint, wiring sequence constraint and physical connection parasitic parameter constraint, so as to generate a self-test diagnosis circuit board design drawing.

[0146] Furthermore, the first analysis module is specifically used to analyze the endpoints of each wire net in the self-test diagnosis circuit netlist to obtain the wire net constraints of the wiring sequence, wire net length and wire net width between various components on the self-test diagnosis circuit board.

[0147] Furthermore, the second design unit includes a third analysis module and a second wiring module.

[0148] The third analysis module is used to analyze the self-test diagnosis circuit board design drawing to obtain design constraints; the design constraints at least include parasitic parameter constraints of the connection, connection sequence constraints of the wire net, connection length constraints and connection width constraints.

[0149] The second wiring module is used to perform wiring of the self-test diagnostic circuit board for the test circuit and the diagnostic circuit under the design constraints, thereby completing the design of the self-test diagnostic circuit board.

[0150] In an embodiment of the present application, based on a circuit schematic diagram of the layout of each component and the wiring between each component, a circuit wiring design diagram of the connection relationship between the test circuit and the diagnostic circuit, i.e., a self-test diagnostic circuit board design diagram, is generated. By using the self-test diagnostic circuit board design diagram of the connection relationship between the test circuit and the diagnostic circuit, it is possible to automatically design a self-test diagnostic circuit for the application circuit according to the requirements of the application design, thereby improving the design efficiency of the self-test diagnostic circuit.

[0151] The specific implementation processes and derivative methods of the above-mentioned embodiments are all within the protection scope of this application.

[0152] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as clustering components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. A person of ordinary skill in the art can understand and implement it without creative work.

[0153] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0154] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

[0155] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. An automated design method for test diagnosis, characterized in that: The method comprises: Read application design; Determine the device to be tested in the application design, and establish a self-test diagnostic circuit netlist based on the device to be tested; Generate a circuit schematic diagram according to the self-test diagnostic circuit netlist; the circuit schematic diagram is a circuit schematic diagram of the layout of each component and the wiring between each component; Generate a self-test diagnostic circuit board design diagram based on the circuit schematic diagram; the self-test diagnostic circuit board design diagram represents a circuit wiring design diagram of the connection relationship between the test circuit and the diagnostic circuit; A self-test diagnostic circuit board is designed according to the self-test diagnostic circuit board design drawing.

2. The method according to claim 1, characterized in that: Before determining the device to be tested that needs to be tested in the application design and establishing a self-test diagnostic circuit netlist according to the device to be tested, the method further includes: Analyze the application circuit corresponding to the application design to obtain analysis information; the analysis information at least includes a signal frequency of the application circuit line network and a current of the application circuit line network; The device to be tested and the pins to be tested corresponding to the device to be tested are generated through the analysis information.

3. The method according to claim 2, characterized in that Also includes: According to the diagnostic model of the device under test, the pins to be tested are optimized to improve the test coverage and reduce the number of pins to be tested.

4. The method according to claim 1, characterized in that: The step of determining a device to be tested in the application design and establishing a self-test diagnostic circuit netlist according to the device to be tested includes: Identify the devices to be tested in the application design; Selecting a test circuit for the device to be tested from a device test circuit library; A self-test diagnosis circuit netlist is constructed through the test circuit of the device under test.

5. The method according to claim 1, characterized in that Also includes: The self-test diagnostic circuit netlist is optimized.

6. The method according to claim 1, characterized in that The step of generating a circuit schematic diagram according to the self-test diagnostic circuit netlist comprises: Performing signal flow analysis and virtual layout and routing on the self-test diagnostic circuit netlist to extract layout constraints and routing constraints of each component on the circuit diagram; the layout constraints are constraints on the positional relationship of the signal flow between each component; the routing constraints are constraints on the routing sequence and wire net type between each component; The layout of each component is driven by the layout constraint, and the wiring between each component is driven by the wiring constraint, so as to generate a circuit schematic diagram.

7. The method according to claim 1, characterized in that The step of generating a self-test diagnostic circuit board design diagram according to the circuit schematic diagram comprises: Performing signal flow analysis on the self-test diagnosis circuit netlist to determine the relative position relationship constraints between various components on the self-test diagnosis circuit board; According to the device pins, the positions of the external connections and the target connection points are calculated to obtain the device peripheral dimensions; Analyze the self-test diagnosis circuit netlist to obtain wire net constraints; the wire net constraints are constraints on the connection sequence, wire net length and wire net width between various components on the self-test diagnosis circuit board; Analyze the self-test diagnosis circuit netlist and circuit schematic diagram to obtain the wiring sequence constraints and physical connection parasitic parameter constraints between the components on the self-test diagnosis circuit board; the physical connection parasitic parameter constraints are determined by the voltage drop, signal delay and signal integrity allowed by the self-test diagnosis circuit board; The wiring is performed under the relative position relationship constraint, the wire net constraint, the wiring sequence constraint and the physical connection parasitic parameter constraint, thereby generating a self-test diagnosis circuit board design drawing.

8. The method according to claim 7, characterized in that The step of analyzing the self-test diagnostic circuit netlist to obtain line network constraints includes: The endpoints of each wire net in the self-test diagnosis circuit net list are analyzed to obtain the wire net constraints of the wiring sequence, wire net length and wire net width between various components on the self-test diagnosis circuit board.

9. The method according to claim 1, characterized in that: The process of designing a self-test diagnostic circuit board according to the self-test diagnostic circuit board design drawing includes: Analyze the self-test diagnostic circuit board design drawing to obtain design constraints; the design constraints at least include parasitic parameter constraints of the connection, connection sequence constraints of the line net, connection length constraints and connection width constraints; Under the design constraints, the test circuit and the diagnostic circuit are wired on a self-test diagnostic circuit board, thereby completing the design of the self-test diagnostic circuit board.

10. An automated design system for test diagnosis, characterized in that: The system comprises: A reading unit, used for reading the application design; A determination unit, used to determine a device to be tested in the application design, and to establish a self-test diagnostic circuit netlist according to the device to be tested; A first generating unit is used to generate a circuit schematic diagram according to the self-test diagnostic circuit netlist; the circuit schematic diagram is a circuit schematic diagram of the layout of each component and the wiring between each component; A second generating unit is used to generate a self-test diagnostic circuit board design diagram according to the circuit principle diagram; the self-test diagnostic circuit board design diagram represents a circuit wiring design diagram of the connection relationship between the test circuit and the diagnostic circuit; The design unit is used to design a self-test diagnosis circuit board according to the self-test diagnosis circuit board design drawing.

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