Parameter configuration method and device, electronic equipment, storage medium and program product

Abstract

This application provides a parameter configuration method, apparatus, electronic device, storage medium, and program product. The method includes: obtaining a functional description of a target chip design; obtaining a behavioral-level parameter model, a system-level parameter model, and an RTL-level parameter model based on the functional description; the behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters, and the RTL-level parameter model includes RTL-level parameters; establishing dependencies between the parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model to obtain a parameter set; optimizing the parameter set based on the dependencies to obtain a target parameter set that ensures the target chip design is free from timing violations; and outputting parameter configuration based on the target parameter set. This application can reduce the risk of parameter version inconsistencies, improve the reliability of parameter configuration in the chip, and improve chip design efficiency.

Description

Technical Field

[0001] This application relates to the field of chip design technology, and more specifically, to a parameter configuration method, apparatus, electronic device, storage medium, and program product. Background Technology

[0002] In the field of integrated circuit design, existing techniques for configuring parameters of each programmable module in a chip mainly employ hierarchical independent optimization and static template methods, which primarily include independent optimization of parameters at three levels: behavioral parameters, system-level parameters, and RTL (Register Transfer Level) parameters.

[0003] However, currently, each abstraction level (behavioral, system, and RTL levels) employs independent optimization strategies, lacking a cross-level parameter correlation mechanism. This necessitates manual synchronization of configurations across multiple levels for cross-level parameter adjustments, easily leading to parameter version inconsistencies and impacting chip design efficiency. For example, the cache line size defined at the behavioral level (a behavioral parameter) cannot be automatically mapped to the burst transmission length parameter of the system-level DDR (Double Data Rate) controller (a system-level parameter), and RTL-level wiring congestion information (an RTL-level parameter) cannot be propagated back to the system-level NoC (Network-on-Chip) topology decision module for parameter updates within the NoC topology decision module. Summary of the Invention

[0004] The purpose of this application is to provide a parameter configuration method, apparatus, electronic device, storage medium, and program product to improve the reliability of chip parameter configuration.

[0005] This application provides a parameter configuration method, comprising: obtaining a functional description of a target chip design; obtaining a behavioral-level parameter model, a system-level parameter model, and an RTL-level parameter model based on the functional description; wherein the behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters, and the RTL-level parameter model includes RTL-level parameters; establishing dependencies between the parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model to obtain a parameter set; optimizing the parameter set based on the dependencies to obtain a target parameter set that ensures the target chip design is free from timing violations; and outputting parameter configuration based on the target parameter set.

[0006] In the above implementation scheme, dependencies are established between parameters in the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model. Then, the parameter set is optimized based on these dependencies. Thus, when optimizing behavioral-level, system-level, and RTL-level parameters, due to these dependencies, adjusting any one of these parameters will automatically adjust the parameters at other related levels, achieving automated cross-level parameter adjustment. For example, using this scheme, the behavioral-level parameter cache line size will be automatically mapped to the system-level DDR controller burst transfer length parameter, and adjustments to RTL-level routing congestion information will be propagated back to the system-level NoC topology decision module for parameter updates. This reduces the risk of parameter version inconsistencies, improves the reliability of parameter configuration in the chip, and increases chip design efficiency.

[0007] Optionally, obtaining the system-level parameter model based on the functional description includes: obtaining each system-level parameter based on the functional description; converting each system-level parameter into a data flow graph-level IR (Intermediate Representation), a loop nesting-level IR, and an instruction operation-level IR according to their correspondence with data flow graphs, nested loops, and instruction operation levels; and performing orthogonalization processing on the parameters corresponding to the data flow graph-level IR, the nested loop-level IR, and the instruction operation-level IR to obtain the system-level parameter model.

[0008] In the above implementation, for system-level parameters, each system-level parameter is transformed into data flow graph-level IR (Intermediate Representation), loop nesting-level IR, and instruction operation-level IR according to their correspondence with data flow graphs, nested loops, and instruction operations, and then orthogonalized. In the resulting system-level parameter model, each parameter is distinguished through data flow graphs, nested loops, and instruction operations, and the orthogonalization process establishes the dependencies between them. Thus, during subsequent optimization, when any system-level parameter is adjusted, other related types of system-level parameters will also be adjusted, thereby achieving automated linkage optimization of system-level parameters, further improving the reliability of parameter configuration in the chip, and increasing chip design efficiency.

[0009] Optionally, establishing dependencies between parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model to obtain a parameter set includes: orthogonalizing the parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model; constructing a dependency tree for the orthogonalized parameters; and using the dependency tree to record the dependencies between parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model.

[0010] In the above implementation, by orthogonalizing the parameters in the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model, cross-level dependencies can be established effectively and accurately. By constructing a dependency tree, the dependencies between each parameter can be effectively recorded.

[0011] Optionally, the parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model are orthogonalized, including: assigning parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model that have intersection relationships to the same orthogonal subspace to obtain multiple orthogonal subspaces; constructing a dependency tree for the orthogonalized parameters, including: constructing a dependency tree for the parameters in each of the orthogonal subspaces respectively.

[0012] In the above implementation, parameters that have intersection relationships in the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model are assigned to the same orthogonal subspace. In this way, the parameters in each orthogonal subspace are parameters that have interdependencies with each other. Then, a dependency tree is constructed for the parameters in each orthogonal subspace, so that the dependencies between all parameters can be comprehensively constructed.

[0013] Optionally, the dependency tree stores parameter value ranges, association strength, and version identifiers.

[0014] In the above implementation, by storing parameter value ranges, correlation strengths, and version identifiers in the dependency tree, when it is necessary to quickly retrieve or compare parameters or parameter combinations, retrieval can be performed based on the version identifier, and comparative analysis can be performed based on the parameter value range. Furthermore, the correlation strength between each parameter can be clearly defined based on the correlation strength, so that when optimizing parameters, adaptive adjustments can be made to related parameters (i.e., parameters with dependencies).

[0015] Optionally, before establishing dependencies between parameters in the behavior-level parameter model, the system-level parameter model, and the RTL-level parameter model, the method further includes: storing each parameter according to the division of the smallest functional unit; when storing each parameter, only one of the same parameters corresponding to the same smallest functional unit is saved.

[0016] In the above implementation, by storing each parameter in a way that divides it into the smallest functional units, the coupling between parameters can be reduced during the parameter storage stage, and duplicate parameters can be eliminated, thereby reducing the number of parameters involved in subsequent optimization and improving optimization efficiency.

[0017] Optionally, the method further includes: calculating the hash value of various parameter combinations; and storing each parameter combination in association with its hash value.

[0018] In the above implementation, by calculating the hash values ​​of various parameter combinations and storing them in association, it is convenient to quickly retrieve parameter combinations and facilitate parameter version backtracking.

[0019] Optionally, the parameter set is optimized according to the dependency relationship, including: generating a configuration strategy matrix containing priority weights, optimization directions, and constraint boundaries based on a preset constraint library; and optimizing each parameter after the dependency relationship is established according to the dependency relationship and the configuration strategy matrix.

[0020] Optionally, the constraint library records the basic constraints of chip design, as well as the constraints updated during each iteration of the optimization process.

[0021] In the above implementation, by recording the basic constraints of the chip design in the constraint library, as well as the constraints updated in each iteration during the optimization process, a new configuration strategy matrix can be constructed based on the basic constraints of the chip design and the constraints updated in each iteration during the optimization process. This improves the constraint reliability in each round of iterative optimization and thus improves the optimization effect.

[0022] Optionally, the behavioral-level parameter model includes constraint information; based on a preset constraint library, a configuration strategy matrix including priority weights, optimization directions, and constraint boundaries is generated, including: generating a configuration strategy matrix including priority weights, optimization directions, and constraint boundaries according to the constraint information and the basic constraints of chip design in the constraint library; wherein, the constraint information includes the priority weights, optimization directions, and constraint boundaries.

[0023] Optionally, the method further includes: performing formal verification and simulation coverage testing on the optimized parameters; and updating the constraints in the constraint library based on the verification or test results if the verification or test results fail.

[0024] In the above implementation, if the verification or test results fail, the constraints in the constraint library are updated according to the verification or test results. This allows the constraints to better fit the optimization requirements in the next round of iteration optimization, thereby improving the optimization effect.

[0025] Optionally, formal verification of the optimized parameters includes: using computational tree logic model checking technology to perform formal verification during the optimization of each parameter.

[0026] In the above implementation, by using computational tree logic model checking technology and performing formal verification during the optimization of each parameter, the completeness verification of the control logic can be completed in the parameter configuration stage, thereby improving the reliability of the final configured parameters.

[0027] Optionally, performing simulation coverage testing on the optimized parameters includes: generating test cases using a preset assertion library; wherein the assertion library records the inputs and outputs when simulation fails during each iteration of the optimization process; the test cases are generated based on the inputs and outputs; and the test cases are used to perform simulation coverage testing on the optimized parameters.

[0028] In the above implementation, the assertion library records the inputs and outputs when the simulation fails in each iteration of the optimization process, and uses the assertion library to generate test cases to perform simulation coverage testing on the optimized parameters. This enables the automated generation of test cases, thereby shortening the verification cycle of chip design.

[0029] Optionally, obtaining a behavioral-level parameter model based on the functional description includes: extracting behavioral-level features based on the functional description; the behavioral-level features characterizing features in the functional description related to the functions to be implemented in the target chip design; and constructing a behavioral-level parameter model based on the behavioral-level features.

[0030] In the above implementation, behavioral features related to the functions required by the target chip design are extracted from the functional description and automatically converted into a behavioral parameter model. In this way, users only need to input the functional description and do not need to build the behavioral parameter model themselves, which lowers the threshold for users to design chips and improves the user experience.

[0031] Optionally, extracting behavioral features based on the functional description includes: processing the functional description using a natural language model to obtain the behavioral features.

[0032] In the above implementation, the functional description is processed by a natural language model, which can effectively identify behavioral features. Since the functional description can be input in natural language, the threshold for users to design chips is lower.

[0033] Optionally, after constructing the behavior-level parameter model based on the behavior-level features, the method further includes: performing a legalization analysis on the behavior-level parameter model using a static time series analysis engine; and updating the constraint information of the behavior-level parameter model if the constraint information is invalid.

[0034] In the above implementation, a static time series analysis engine is used to perform legalization analysis on the behavioral-level parameter model. If the constraint information of the behavioral-level parameter model is invalid, the constraint information of the behavioral-level parameter model is updated. This reduces the risk of invalid constraints and reduces the difficulty of updating subsequent constraints.

[0035] Optionally, after establishing dependencies, the resulting parameter set has multiple parameter combination spaces, each containing parameters with dependencies. Optimizing the parameters after establishing dependencies includes: performing global parameter tuning on the parameter combination spaces and obtaining Pareto front solutions; performing gradient optimization on the Pareto front solutions of each parameter combination space; and repeating the above process until the parameters with optimal area and power consumption when there are no timing violations are obtained.

[0036] In the above implementation, global parameter tuning is first performed on the parameter combination space, and then gradient optimization (i.e. local tuning) is performed on the Pareto front solution set of each parameter combination space. By iterating continuously, the accuracy of parameter optimization can be improved while reducing the optimization time and improving optimization efficiency.

[0037] Optionally, global parameter tuning is performed on the parameter combination space, including: determining key parameter combination spaces; the key parameter combination space is the parameter combination space that is currently sensitive to parameter adjustment among all parameter combination spaces; global parameter tuning is performed on the key parameter combination space; correspondingly, gradient optimization is performed on the Pareto front solution set of each parameter combination space, including: gradient optimization is performed on the Pareto front solution set of each key parameter combination space.

[0038] In the above implementation, by first identifying the key parameter combination space that is sensitive to parameter adjustment, and then performing global parameter tuning only for the key parameter combination space, and gradient optimization for the Pareto front solution set of the key parameter combination space, the number of parameter combinations that need to be tuned is reduced, thereby reducing the number of parameters that need to be adjusted and improving the efficiency of parameter optimization.

[0039] Optionally, only non-dominated solutions are retained in the resulting Pareto front solution set.

[0040] In the above implementation, only non-dominated solutions are retained in the Pareto front solution set, which can reduce the risk of premature convergence and the risk of getting trapped in local optima.

[0041] Optionally, in each iteration, the adjustment range of parameters involved in the timing violation path in the previous iteration is reduced; wherein, the timing violation path is the path with timing violations discovered when verifying the chip design during the iteration process.

[0042] In the above implementation, by reducing the adjustment range of parameters involved in the timing violation path in each iteration, more refined tuning of the parameters involved in the timing violation path can be performed, thereby improving the parameter tuning effect.

[0043] Optionally, gradient optimization is performed on the Pareto front solution set of each parameter combination space, including: for each parameter combination space, determining the adjustment range of each parameter based on the correlation strength of each parameter in the parameter combination space, and performing gradient optimization on the Pareto front solution set based on the adjustment range of each parameter.

[0044] In the above implementation, the adjustment range of each parameter is determined according to the correlation strength of each parameter in the parameter combination space, and then the Pareto front solution set is optimized by gradient based on the adjustment range of each parameter. This makes the optimization of each parameter related to the correlation between each parameter and other parameters, so that each parameter can be optimized in a targeted manner, thereby improving the reliability of the parameter optimization results.

[0045] This application embodiment also provides a parameter configuration method, including: opening the target interface in response to an opening command of the target interface; obtaining the parameter dependencies of a behavioral-level parameter model, a system-level parameter model, and an RTL-level parameter model in response to an input operation of a functional description of a target chip design generated in the target interface; the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model are obtained according to the functional description, and the behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters, and the RTL-level parameter model includes RTL-level parameters; outputting an optimized parameter set in response to obtaining the parameter dependencies of the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model; wherein, the optimized parameter set is obtained by optimizing the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model with established dependencies according to the dependencies, so that the target chip design has no timing violations.

[0046] The above implementation scheme establishes dependencies between parameters in the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model. Then, the parameter set is optimized based on these dependencies. Thus, when optimizing behavioral-level, system-level, and RTL-level parameters, due to the existence of dependencies, if any of the dependent behavioral-level, system-level, or RTL-level parameters is adjusted, the parameters at other related levels will also be adjusted accordingly. This achieves automated cross-level parameter adjustment, reduces the risk of parameter version inconsistencies, improves the reliability of parameter configuration in the chip, and increases chip design efficiency.

[0047] This application embodiment also provides a parameter configuration device, including: an acquisition module for acquiring a functional description of a target chip design; a parameter extraction module for obtaining a behavioral-level parameter model, a system-level parameter model, and an RTL-level parameter model based on the functional description; wherein the behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters, and the RTL-level parameter model includes RTL-level parameters; a dependency establishment module for establishing dependencies on the parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model to obtain a parameter set; an optimization module for optimizing the parameter set based on the dependencies to obtain a parameter set that ensures the target chip design is free from timing violations; and an output module for outputting parameter configuration based on the target parameter set.

[0048] This application also provides an electronic device, including a processor and a memory, wherein the processor is configured to execute one or more programs stored in the memory to implement any of the parameter configuration methods described above.

[0049] This application also provides a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the parameter configuration methods described above.

[0050] This application also provides a computer program product, which includes computer program code. When the computer program code is run on a processor, it causes the processor to execute any of the above-described parameter configuration methods. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a basic flowchart illustrating a parameter configuration method provided in an embodiment of this application;

[0053] Figure 2 A basic flowchart illustrating another parameter configuration method provided in this application embodiment;

[0054] Figure 3 This is a schematic diagram of the basic structure of a parameter configuration device provided in an embodiment of this application;

[0055] Figure 4 A schematic diagram of the basic structure of another parameter configuration device provided in an embodiment of this application;

[0056] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0057] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0058] To facilitate understanding of the solutions and advantages of the embodiments of this application, the relevant technologies will be introduced and explained below:

[0059] In the field of integrated circuit design, existing techniques for configuring parameters of programmable modules within a chip primarily employ hierarchical independent optimization and static template methods. The core process mainly includes three levels: behavioral optimization, system-level planning, and RTL-level implementation. Behavioral optimization mainly uses high-level language descriptions (such as C / C++ / SystemC) for algorithmic functional modeling, extracts critical path features through static timing analysis, and implements functional mapping using a fixed bit-width allocation strategy and a predefined operator library. System-level planning mainly uses template-based interconnect architecture generation methods, allocates bandwidth resources through pre-defined NoC topology templates, and uses heuristic algorithms for deep configuration of inter-module communication channels. RTL-level implementation relies on EDA (Electronic Design Automation) tools, employs rule-based RTL code generation technology, and achieves physical constraint binding through a hard-coded parameter passing mechanism.

[0060] Currently, all three levels involve parameter optimization, and the parameters at each level are optimized independently. This necessitates manually synchronizing configurations across multiple levels for cross-level parameter adjustments, which can easily lead to parameter version inconsistencies and impact chip design efficiency.

[0061] To address this issue, this application provides a method that establishes dependencies between parameters at three levels and optimizes them together. This allows the tuning of one parameter during the optimization process to adjust its dependent parameters as well, thereby achieving automated parameter adjustment across different levels, reducing the risk of inconsistent parameter versions, and improving chip design efficiency.

[0062] See Figure 1 As shown, Figure 1 This is a basic flowchart illustrating a parameter configuration method provided in an embodiment of this application, including:

[0063] S101: Obtain the functional description of the target chip design.

[0064] In this embodiment of the application, the functional description of the target chip design can be obtained by the user through verbal description or text input.

[0065] In the embodiments of this application, the functional description may be, but is not limited to, a description in natural language.

[0066] S102: Based on the functional description, obtain the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model.

[0067] In the embodiments of this application, the behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters, and the RTL-level parameter model includes RTL-level parameters. Behavioral-level parameters refer to parameters at the behavioral level, i.e., the parameters in the behavioral-level optimization process described above. System-level parameters refer to parameters at the system level, i.e., the parameters in the system-level planning process described above. RTL-level parameters refer to parameters at the RTL level, i.e., the parameters in the RTL-level implementation process described above.

[0068] In this embodiment, behavioral-level features can be extracted from the functional description, and then a behavioral-level parameter model can be constructed based on these features. The behavioral-level features characterize the features in the functional description that are related to the functions to be implemented in the target chip design.

[0069] For example, a natural language model can be pre-trained to understand and recognize functional descriptions and extract behavioral features from them.

[0070] For example, suppose a function is described as "a GPU needs to be designed with a frequency no lower than A and an area no greater than B". Then the behavioral features can be extracted as follows: frequency, with a value greater than or equal to A, and area, with a value less than or equal to B.

[0071] In this embodiment of the application, after obtaining each behavior-level feature, the behavior-level features can be recorded in a text file to obtain a behavior-level parameter model.

[0072] In this embodiment, optionally, after constructing the behavioral-level parameter model based on behavioral-level features, a static time-series analysis engine can be used to perform a legalization analysis on the behavioral-level parameter model, and update the constraint information of the behavioral-level parameter model if the constraint information is invalid. This reduces the risk of invalid constraints and decreases the difficulty of updating subsequent constraints.

[0073] Optionally, in this embodiment, the functional description may also include system-level features (features that can be used to generate a system-level architecture), such as bit width and bandwidth. Optionally, in this embodiment, a system-level template may be preset, including interconnect architecture and NoC topology templates. Based on the system-level template, the system-level features extracted from the functional description are used to generate the system-level architecture, and a system-level parameter model is obtained. For system-level features not present in the functional description, preset default values ​​or preset default algorithms, such as heuristic algorithms, can be used.

[0074] Optionally, in this embodiment of the application, system-level parameters can be recorded in a text file to obtain a system-level parameter model.

[0075] In some feasible embodiments of this application, each system-level parameter can be transformed into a data flow graph-level IR, a loop nesting-level IR, and an instruction operation-level IR according to their correspondence with data flow graphs, loop nesting-level IRs, and instruction operation-level IRs. Then, the parameters corresponding to the data flow graph-level IR, loop nesting-level IR, and instruction operation-level IR are orthogonalized to obtain a system-level parameter model. In this system-level parameter model, each parameter is distinguished through data flow graphs, loop nesting, and instruction operations, and the orthogonalization process establishes inter-parameter dependencies. Therefore, during subsequent optimization, if any system-level parameter is adjusted, its associated other types of system-level parameters will also be adjusted, thereby achieving automated, coordinated optimization of system-level parameters, further improving the reliability of parameter configuration in the chip, and increasing chip design efficiency. Furthermore, the hierarchical structure of the system level is relatively complex, usually containing many small modules. In this feasible implementation, the system is divided into three layers: data flow graph, nested loops, and instruction operations, instead of dividing the system-level parameters into corresponding small modules. This allows the entire system-level parameters to be linked together by establishing dependencies, achieving a better representation of the system level and thus improving the reliability of subsequent parameter optimization.

[0076] Optionally, in the embodiments of this application, existing RTL code automatic generation methods can be used to generate RTL code based on the functional description, thereby obtaining the RTL-level parameters in the RTL code.

[0077] Optionally, in this embodiment of the application, the RTL-level parameters can be recorded in a text file to obtain an RTL-level parameter model.

[0078] S103: Establish dependencies between parameters in the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model to obtain the parameter set.

[0079] Optionally, in the embodiments of this application, the parameters in the behavioral-level parameter model, system-level parameter model and RTL-level parameter model can be orthogonalized to determine whether there is a dependency relationship between the parameters at each level, as well as the specific dependency relationship and the strength of the association (i.e., the strength of the dependency relationship).

[0080] In this embodiment of the application, a dependency tree can be constructed on the orthogonalized parameters, and the dependency tree can be used to record the dependencies between parameters in each behavior-level parameter model, system-level parameter model and RTL-level parameter model.

[0081] In some feasible implementations, during orthogonalization, parameters in the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model that have intersecting relationships can be assigned to the same orthogonal subspace, resulting in multiple orthogonal subspaces. A dependency tree is then constructed for the parameters within each orthogonal subspace. In this way, the parameters in each orthogonal subspace are mutually dependent, and by constructing dependency trees for each subspace, the dependencies between all parameters can be comprehensively constructed.

[0082] In some optional embodiments of this application, the dependency tree may store parameter value ranges, association strengths, and version identifiers.

[0083] The parameter value range can be obtained when converting to the parameter model of each level, and its value can be defined in the function description or the default value of the configuration.

[0084] The version identifier is used to identify the version of the parameters obtained from the current optimization, and it is updated as the optimization process iterates.

[0085] Optionally, in this embodiment, the parameter combinations obtained in each iteration can be saved and the corresponding version identifier can be recorded.

[0086] In this embodiment, the correlation strength refers to the strength of the dependency relationship between two parameters, which can be determined based on the degree of intersection between the two parameters during orthogonal processing. The higher the degree of intersection between the two parameters, the greater the correlation strength.

[0087] In some optional embodiments of this application, during each iteration, the hash values ​​of various parameter combinations can be calculated, and each parameter combination and its hash value can be stored together. This facilitates rapid retrieval of parameter combinations by calculating and storing the hash values ​​of various parameter combinations together, and, combined with version identifiers, facilitates version backtracking of parameters.

[0088] Optionally, in this embodiment, before establishing dependencies between parameters in the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model, the parameters can be stored according to the division of the smallest functional unit. When storing parameters, only one instance of the same parameter corresponding to the same smallest functional unit is saved. This reduces the coupling between parameters during the parameter storage stage, eliminates duplicate parameters, thereby reducing the number of parameters involved in subsequent optimization and improving optimization efficiency.

[0089] S104: Optimize the parameter set according to the dependency relationship to obtain the target parameter set that ensures that the target chip design has no timing violations.

[0090] In this embodiment of the application, a configuration strategy matrix containing priority weights, optimization directions, and constraint boundaries can be generated based on a preset constraint library. Then, the parameters after the dependency relationship is established can be optimized according to the dependency relationship and the configuration strategy matrix.

[0091] In this embodiment, the constraint library can be a pre-established library that records the basic constraints of chip design. The basic constraints of chip design refer to the fundamental constraints that all chip designs must follow.

[0092] In this embodiment of the application, the constraint library can also record the constraints updated in each iteration during the optimization process, thereby continuously updating the constraints during the iteration process, making the constraints in each round of optimization more in line with actual needs, improving the reliability of constraints in each round of optimization, and thus improving the optimization effect.

[0093] Optionally, in this embodiment of the application, the optimized parameters can also be formally verified and subjected to simulation coverage testing to verify the reliability of the optimized parameters.

[0094] Optionally, in this embodiment, if the verification or test results fail, the constraints in the constraint library can be updated based on the verification or test results. This ensures that the constraints better match the optimization requirements in the next iteration, thereby improving the optimization effect.

[0095] For example, if a timing violation (such as a failure to meet setup time requirements) is found on a critical path during simulation coverage testing, the following updates can be made based on the test results: First, locate the specific parameters causing the timing violation, such as the drive strength or delay of one or more logic units on the path; then, in the constraint library, increase the "priority weight" of these specific parameters and tighten their constraint boundaries (e.g., set a stricter maximum delay constraint value for the path). In this way, in the next iteration of optimization, the optimizer will focus on and prioritize adjusting these parameters to resolve the discovered timing issues, thereby more accurately meeting the optimization requirements.

[0096] Optionally, in this embodiment, the initial constraint information may be extracted from the functional description and included as part of the behavioral-level parameter model. The constraint information includes priority weights, optimization directions, and constraint boundaries.

[0097] In the embodiments of this application, priority weight refers to the priority of each parameter during optimization, and its priority is expressed in the form of weight. Priority weight is negatively correlated with the adjustment range of the parameter and positively correlated with the adjustment accuracy of the parameter.

[0098] In this embodiment, the optimization direction refers to the direction in which parameters are optimized within the parameter combination space, and the constraint boundary refers to the boundary in the parameter combination space when searching for the optimal parameter combination. The parameter combination space refers to a multi-dimensional space constructed from the parameters. For example, with 100 parameters, the parameter combination space is a 100-dimensional space, and each point in this space corresponds to a specific combination of these 100-dimensional parameters.

[0099] Optionally, in this embodiment, during the first iteration, a configuration strategy matrix containing priority weights, optimization directions, and constraint boundaries can be generated based on the constraint information contained in the behavioral parameter model and the basic constraints of chip design in the constraint library.

[0100] In this embodiment, the specific method for generating the configuration strategy matrix can be implemented using existing methods, and no restrictions are imposed in this embodiment.

[0101] Optionally, in this embodiment, when formally verifying the optimized parameters, a computational tree logic model checking technique can be used to perform formal verification during the optimization process of each parameter. This allows for the completeness verification of the control logic during the parameter configuration stage, improving the reliability of the final configured parameters.

[0102] Optionally, in this embodiment, when performing simulation coverage testing on the optimized parameters, test cases can be generated using a preset assertion library. The assertion library records the inputs and outputs when simulation fails during each iteration of the optimization process. Test cases can be generated based on the inputs and outputs recorded in the assertion library when simulation fails, and then used to perform simulation coverage testing on the optimized parameters. This enables automated generation of test cases, thereby shortening the chip design verification cycle.

[0103] In this embodiment of the application, when the parameter set is obtained after establishing the dependency relationship, the parameters with dependency relationship can be allocated to the same parameter combination space according to the parameter situation of the dependency relationship, so as to obtain multiple parameter combination spaces, each parameter combination space contains each parameter with dependency relationship.

[0104] Each time optimization is performed, global parameter tuning can be carried out on the parameter combination space, and the Pareto front solution set can be obtained.

[0105] Then, gradient optimization is performed on the Pareto front solution set of each parameter combination space.

[0106] Repeat the above process iteratively until the parameters that are optimal in terms of area and power consumption when there are no timing violations are obtained.

[0107] In this way, the Pareto front solution set is selected through global optimization, and local optimization is achieved through gradient optimization to eliminate timing violations as much as possible. This improves the accuracy of parameter optimization, reduces optimization time, and increases optimization efficiency.

[0108] In this embodiment of the application, in order to obtain the parameters that optimize area and power consumption when there are no timing violations, a weighted objective function including timing margin, area cost, and power consumption can be constructed. For example, the objective function can be: ,in To adjust the coefficient, T slack For timing margin, For area cost, P budget For power consumption. The adjustment factor can be preset or dynamically adjusted; for example, the optimal combination of adjustment factors can be determined through Monte Carlo simulation.

[0109] In this embodiment of the application, the function values ​​of each parameter combination (i.e., each point in the Pareto front solution set) when there are no timing violations can be calculated based on the above objective function, and the parameter combination with the optimal function value can be selected.

[0110] Optionally, in some feasible embodiments of this application, when performing global parameter tuning on the parameter combination space, the key parameter combination space can be determined first, and then global parameter tuning can be performed on the key parameter combination space. Correspondingly, when performing gradient optimization on the Pareto front solution set of each parameter combination space, gradient optimization can be performed on the Pareto front solution set of each key parameter combination space separately.

[0111] Among them, the key parameter combination space is the parameter combination space that is currently sensitive to parameter adjustments among all parameter combination spaces.

[0112] In this way, global parameter tuning is performed only for the key parameter combination space, and gradient optimization is performed for the Pareto front solution set of the key parameter combination space. This reduces the number of parameter combinations that need to be tuned, thereby reducing the number of parameters that need to be adjusted and improving the efficiency of parameter optimization.

[0113] In the embodiments of this application, after each iteration, the sensitivity of each parameter combination space after the current parameter adjustment can be calculated, and the parameter combination space with a sensitivity higher than a preset sensitivity threshold is determined as the key parameter combination space.

[0114] The sensitivity can be calculated using the sensitivity function in existing parameter tuning algorithms.

[0115] Optionally, in the embodiments of this application, algorithms such as hybrid genetic algorithms and simulated annealing algorithms can be used for global parameter tuning, but this is not a limitation.

[0116] Optionally, in this embodiment, only non-dominated solutions may be retained in the obtained Pareto front solution set. This can reduce the risk of premature convergence and the risk of getting trapped in local optima.

[0117] Optionally, in the embodiments of this application, in each iteration, the adjustment range of the parameters involved in the timing violation path in the previous iteration can be reduced, thereby performing more refined optimization of the parameters involved in the timing violation path and improving the parameter optimization effect.

[0118] Among them, timing violation paths are paths with timing violations discovered during the verification of chip design in the iteration process.

[0119] Optionally, in the embodiments of this application, when performing gradient optimization on the Pareto front solution set of each parameter combination space, the adjustment range of each parameter can be determined according to the correlation strength of each parameter in the parameter combination space, and gradient optimization can be performed on the Pareto front solution set according to the adjustment range of each parameter.

[0120] For example, the correlation strength of each parameter can be preset to determine the corresponding relationship of the adjustment range of each parameter. Based on this correspondence and the correlation strength of each parameter, the adjustment range of each parameter can be determined, and then gradient optimization is performed according to the adjustment range of each parameter. For instance, in a parameter combination space, there are parameters A (assumed to be the driving strength of a logic unit), B (assumed to be the threshold voltage of another unit connected to the aforementioned logic unit), and C (assumed to be the operating frequency of another unrelated module). Suppose that, based on physical characteristics or prior knowledge, parameters A and B are determined to have a strong correlation because they jointly determine the delay of a critical path; while parameter C has a weak correlation with A and B. In this case, the following correspondence can be preset: for strongly correlated parameters, the adjustment range (i.e., the step size of gradient optimization) is 0.5% of the parameter value range; for weakly correlated parameters, the adjustment range is 2% of the parameter value range. Therefore, during gradient optimization, the adjustment steps of A and B will be very small to perform a fine-grained collaborative search; while the adjustment step of parameter C will be relatively large to enable faster exploration in the solution space, thereby improving optimization efficiency while ensuring optimization accuracy.

[0121] S105: Output parameter configuration based on the target parameter set.

[0122] In this embodiment, a programmable module configuration package (i.e., parameter configuration in S105) can be generated based on the target parameter set. The programmable module configuration package may include a parameterized RTL code template and a cross-level parameter linkage table. The parameterized RTL code template is obtained by filling the target parameter set into the RTL code generated based on the functional description, and the cross-level parameter linkage table can be constructed based on the dependencies described above. In this embodiment, the parameterized RTL code template and the cross-level parameter linkage table can be output in the form of a netlist file.

[0123] In this embodiment, the programmable module configuration package may also include a physical implementation constraint file (which can be generated from the last updated constraint conditions). Optionally, the physical implementation constraint file may also be output as part of the netlist file.

[0124] The method provided in this application can be implemented in human-computer interaction interfaces such as web pages and APP pages, but is not limited to. Therefore, based on the same inventive concept, this application also provides another parameter configuration method, see [link to relevant documentation]. Figure 2 As shown, it includes:

[0125] S201: In response to the open command of the target interface, open the target interface.

[0126] S202: In response to the input operation of the functional description of the target chip design generated in the target interface, obtain the parameter dependencies of the behavioral-level parameter model, system-level parameter model and RTL-level parameter model.

[0127] The behavioral-level parameter model, system-level parameter model, and RTL-level parameter model are derived from the functional description. The behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters, and the RTL-level parameter model includes RTL-level parameters.

[0128] S203: In response to obtaining the parameter dependencies of the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model, output the optimized parameter set.

[0129] The optimized parameter set is obtained by optimizing the behavioral-level parameter model, system-level parameter model and RTL-level parameter model that have established dependencies based on the dependencies, so that the target chip design has no timing violations.

[0130] It should be understood that, for the sake of brevity, the content described above also applies to this embodiment, and will not be repeated here.

[0131] The parameter configuration method provided in this application establishes dependencies between parameters in the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model. Then, it optimizes the parameter set based on these dependencies. Thus, when optimizing behavioral-level, system-level, and RTL-level parameters, due to these dependencies, adjusting any one of these parameters will automatically adjust the parameters at other related levels, achieving automated cross-level parameter adjustment. For example, using the above implementation, the behavioral-level parameter cache line size will be automatically mapped to the system-level DDR controller burst transmission length parameter, and adjustments to RTL-level routing congestion information will be propagated back to the system-level NoC topology decision module for parameter updates. This reduces the risk of parameter version inconsistencies, improves the reliability of parameter configuration in the chip, and increases chip design efficiency.

[0132] Based on the same inventive concept, this application also provides a parameter configuration device 300 and a parameter configuration device 400 in its embodiments. Please refer to... Figure 3 and Figure 4 As shown, Figure 3 It shows the use of Figure 1 The parameter configuration device of the method shown, Figure 4 It shows the use of Figure 2 The method shown includes a parameter configuration device. It should be understood that the specific functions of devices 300 and 400 are described above; to avoid repetition, detailed descriptions are omitted here. Devices 300 and 400 include at least one software function module that can be stored in memory or embedded in the operating system of devices 300 or 400 in the form of software or firmware. Specifically:

[0133] See Figure 3 As shown, the device 300 includes: an acquisition module 301, a parameter extraction module 302, a dependency establishment module 303, an optimization module 304, and an output module 305. Wherein:

[0134] Acquisition module 301 is used to acquire the functional description of the target chip design;

[0135] The parameter extraction module 302 is used to obtain a behavioral-level parameter model, a system-level parameter model, and an RTL-level parameter model based on the functional description; the behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters, and the RTL-level parameter model includes RTL-level parameters.

[0136] The dependency establishment module 303 is used to establish dependencies on parameters in the behavior-level parameter model, the system-level parameter model, and the RTL-level parameter model to obtain a parameter set;

[0137] The optimization module 304 is used to optimize the parameter set according to the dependency relationship to obtain a parameter set that ensures that the target chip design is free from timing violations.

[0138] Output module 305 is used to output parameter configuration according to the target parameter set.

[0139] In one feasible embodiment of this application, the parameter extraction module 302 is specifically used to: obtain each system-level parameter according to the functional description; convert each system-level parameter into a data flow graph-level intermediate representation (IR), a loop nesting level IR, and an instruction operation level IR according to the correspondence between the system-level parameter and the data flow graph-level IR, the loop nesting level IR, and the instruction operation level IR; and perform orthogonalization processing on the parameters corresponding to the data flow graph-level IR, the loop nesting level IR, and the instruction operation level IR to obtain the system-level parameter model.

[0140] In one feasible embodiment of this application, the dependency establishment module 303 is specifically used to: orthogonalize the parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model; construct a dependency tree for the orthogonalized parameters; and the dependency tree is used to record the dependencies between the parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model.

[0141] In one optional embodiment of this feasible implementation, the dependency establishment module 303 is specifically used to: allocate parameters that have intersection relationships among the parameters in the behavior-level parameter model, the system-level parameter model, and the RTL-level parameter model to the same orthogonal subspace to obtain multiple orthogonal subspaces; and construct a dependency tree for the parameters in each of the orthogonal subspaces respectively.

[0142] In some exemplary implementations of this optional embodiment, the dependency tree stores parameter value ranges, association strengths, and version identifiers.

[0143] In one feasible embodiment of this application, the dependency establishment module 303 is further configured to: store each parameter according to the division of the smallest functional unit before establishing the dependency relationship between the parameters in the behavior-level parameter model, the system-level parameter model and the RTL-level parameter model; when storing each parameter, only one of the same parameters corresponding to the same smallest functional unit is saved.

[0144] In one feasible embodiment of this application, the dependency establishment module 303 is further configured to: calculate the hash value of various parameter combinations; and associate and store the hash values ​​of each parameter combination with each parameter combination.

[0145] In one feasible embodiment of this application, the optimization module 304 is specifically used to: generate a configuration strategy matrix containing priority weights, optimization directions, and constraint boundaries based on a preset constraint library; and optimize each parameter after the dependency relationship is established according to the dependency relationship and the configuration strategy matrix.

[0146] In one alternative embodiment of this feasible implementation, the constraint library records the basic constraints of chip design, as well as the constraints updated during each iteration of the optimization process.

[0147] In one optional embodiment of this feasible implementation, the behavioral-level parameter model includes constraint information; the optimization module 304 is specifically used to: generate a configuration strategy matrix including priority weights, optimization directions, and constraint boundaries based on the constraint information and the basic constraints of chip design in the constraint library; wherein, the constraint information includes the priority weights, optimization directions, and constraint boundaries.

[0148] In one optional embodiment of this feasible implementation, the optimization module 304 is further configured to: perform formal verification and simulation coverage testing on the optimized parameters; and update the constraints in the constraint library according to the verification results or test results if the verification results or test results fail.

[0149] In some exemplary implementations of this optional embodiment, the optimization module 304 is specifically used to: employ computational tree logic model checking technology to perform formal verification during the optimization of each parameter.

[0150] In some exemplary implementations of this optional embodiment, the optimization module 304 is specifically used to: generate test cases through a preset assertion library; wherein, the assertion library records the inputs and outputs when simulation fails during each iteration of the optimization process; the test cases are generated based on the inputs and outputs; and the test cases are used to perform simulation coverage testing on the optimized parameters.

[0151] In one feasible embodiment of this application, the parameter extraction module 302 is specifically used to: extract behavioral features based on the functional description; the behavioral features characterize the features in the functional description that are related to the functions to be implemented in the target chip design; and construct a behavioral parameter model based on the behavioral features.

[0152] In one optional embodiment of this feasible implementation, the parameter extraction module 302 is specifically used to: process the functional description using a natural language model to obtain the behavioral-level features.

[0153] In one optional embodiment of this feasible implementation, the parameter extraction module 302 is specifically used to: after constructing a behavior-level parameter model based on the behavior-level features, perform a legalization analysis on the behavior-level parameter model using a static time series analysis engine; and update the constraint information of the behavior-level parameter model if the constraint information of the behavior-level parameter model is invalid.

[0154] In one feasible embodiment of this application, after establishing the dependency relationship, the parameter set obtained has multiple parameter combination spaces, and each parameter combination space contains parameters with dependency relationships; the optimization module 304 is specifically used to: perform global parameter tuning on the parameter combination space and obtain the Pareto front solution set; perform gradient optimization on the Pareto front solution set of each parameter combination space respectively; repeat the above process until the parameters with optimal area and power consumption when there are no timing violations are obtained.

[0155] In one optional embodiment of this feasible implementation, the optimization module 304 is specifically used to: determine the key parameter combination space; the key parameter combination space is the parameter combination space that is currently sensitive to parameter adjustment among all parameter combination spaces; perform global parameter tuning on the key parameter combination space; and perform gradient optimization on the Pareto front solution set of each key parameter combination space.

[0156] In one alternative embodiment of this feasible implementation, the resulting Pareto front solution set retains only non-dominated solutions.

[0157] In one optional embodiment of this feasible implementation, the optimization module 304 is specifically used to: reduce the adjustment range of parameters involved in the timing violation path in the previous iteration during each iteration; wherein, the timing violation path is a path with timing violations discovered during the verification of the chip design during the iteration process.

[0158] In one optional embodiment of this feasible implementation, the optimization module 304 is specifically used to: determine the adjustment range of each parameter based on the correlation strength of each parameter in each parameter combination space, and perform gradient optimization on the Pareto front solution set based on the adjustment range of each parameter.

[0159] See Figure 4 As shown, the device 400 includes: an interface opening module 401, a dependency acquisition module 402, and a response output module 403. Wherein:

[0160] The interface opening module 401 is used to open the target interface in response to the opening command of the target interface;

[0161] The dependency acquisition module 402 is used to obtain the parameter dependencies of the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model in response to the input operation of the functional description of the target chip design generated in the target interface; the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model are obtained according to the functional description, and the behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters, and the RTL-level parameter model includes RTL-level parameters.

[0162] The response output module 403 is used to output an optimized parameter set in response to obtaining the parameter dependencies of the behavioral-level parameter model, system-level parameter model and RTL-level parameter model; wherein the optimized parameter set is obtained by optimizing the behavioral-level parameter model, system-level parameter model and RTL-level parameter model with dependencies based on the dependencies, so that the target chip design has no timing violations.

[0163] It should be understood that, for the sake of brevity, some of the content described in the method embodiments will not be repeated in this embodiment.

[0164] Based on the same inventive concept, this application also provides an electronic device, see [link to relevant documentation]. Figure 5 As shown, it includes a processor 501 and a memory 502. Wherein:

[0165] The processor 501 is used to execute one or more programs stored in the memory 502 to implement the above parameter configuration method.

[0166] It is understood that processor 501 can be a data processing core such as a GPU (Graphics Processing Unit), CPU (Central Processing Unit), AI (Artificial Intelligence) processor, NPU (Neural Network Processing Unit), ISP (Image Signal Processor), DPU (Display Processing Unit), VPU (Video Processing Unit), or DSP (Digital Signal Processor), or a processor chip used in scenarios involving large-scale data computation. Memory 502 can be RAM (Random Access Memory), ROM (Read-Only Memory), or flash memory. The above are merely examples and should not be construed as limiting this application.

[0167] It's understandable. Figure 5 The structure shown is for illustrative purposes only; the electronic device may also include components that are more advanced than those shown. Figure 5 The more or fewer components shown, or having the same Figure 5 Different configurations are shown. For example, it may also have an internal communication bus for communication between the processor 501 and the memory 502; or it may have an external communication interface, such as a USB (Universal Serial Bus) interface, a CAN (Controller Area Network) bus interface, etc.; or it may have an information display component such as a display screen, but this is not a limitation.

[0168] In the embodiments of this application, the electronic device may be, but is not limited to, a server, a host, a smart terminal device, etc. Furthermore, the electronic device may also be a cluster of electronic devices consisting of multiple servers, multiple hosts, multiple smart terminal devices, servers and hosts, or servers and smart terminal devices.

[0169] Based on the same inventive concept, embodiments of this application also provide a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital Memory Card), MMC (Multimedia Card), etc., in which one or more programs implementing the above steps are stored. These one or more programs can be executed by one or more processors to implement the above parameter configuration method. Further details will not be elaborated here.

[0170] Based on the same inventive concept, this application also provides a computer program product, which includes computer program code. When the computer program code is run on a processor, it causes the processor to execute the above-described parameter configuration method.

[0171] In this embodiment of the application, the computer program product may be, but is not limited to, program installation packages, APPs, software packages, and other program products.

[0172] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0173] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0174] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0175] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0176] In this article, "multiple" refers to two or more.

[0177] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A parameter configuration method, characterized in that, include: Obtain the functional description of the target chip design; Based on the functional description, a behavioral-level parameter model, a system-level parameter model, and an RTL-level parameter model are obtained; the behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters, and the RTL-level parameter model includes RTL-level parameters. Dependencies are established for parameters in the behavior-level parameter model, the system-level parameter model, and the RTL-level parameter model to obtain a parameter set; The parameter set is optimized based on the dependencies to obtain a target parameter set that ensures the target chip design is free from timing violations. Output parameter configuration based on the target parameter set.

2. The method as described in claim 1, characterized in that, Based on the functional description, a system-level parameter model is obtained, including: The system-level parameters are obtained based on the functional description. The system-level parameters are transformed into intermediate representations (IRs) at the data flow graph level, nested loop level, and instruction operation level, according to their correspondence with data flow graphs, nested loops, and instruction operation levels. The parameters corresponding to the data flow graph level IR, the nested loop level IR, and the instruction operation level IR are orthogonalized to obtain the system-level parameter model.

3. The method as described in claim 1, characterized in that, Dependencies are established for parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model to obtain a parameter set, including: The parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model are orthogonalized. A dependency tree is constructed for the orthogonalized parameters; the dependency tree is used to record the dependencies between parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model.

4. The method as described in claim 3, characterized in that, Orthogonalization processing is performed on the parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model, including: Parameters that have intersection relationships in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model are assigned to the same orthogonal subspace to obtain multiple orthogonal subspaces; Construct a dependency tree for the orthogonalized parameters, including: Dependency trees are constructed for the parameters in each of the orthogonal subspaces.

5. The method as described in claim 4, characterized in that, The dependency tree stores parameter value ranges, association strength, and version identifiers.

6. The method as described in claim 1, characterized in that, Before establishing dependencies between parameters in the behavioral-level parameter model, the system-level parameter model, and the RTL-level parameter model, the method further includes: Each parameter is stored according to the division of the smallest functional unit; when storing each parameter, only one of the same parameter corresponding to the same smallest functional unit is saved.

7. The method as described in claim 1, characterized in that, The method further includes: Calculate the hash value of various parameter combinations; The system associates and stores each parameter combination with its hash value.

8. The method as described in claim 1, characterized in that, Optimizing the parameter set based on the dependencies includes: Based on a pre-defined constraint library, a configuration strategy matrix containing priority weights, optimization directions, and constraint boundaries is generated. The parameters after establishing the dependency relationship are optimized based on the dependency relationship and the configuration strategy matrix.

9. The method as described in claim 8, characterized in that, The constraint library contains the basic constraints for chip design, as well as the constraints updated during each iteration of the optimization process.

10. The method as described in claim 8, characterized in that, The behavioral-level parameter model contains constraint information; Based on a pre-defined constraint library, a configuration strategy matrix is ​​generated, including priority weights, optimization directions, and constraint boundaries, comprising: A configuration strategy matrix containing priority weights, optimization directions, and constraint boundaries is generated based on the constraint information and the basic constraints of chip design in the constraint library; wherein, the constraint information includes the priority weights, optimization directions, and constraint boundaries.

11. The method as described in claim 8, characterized in that, The method further includes: The optimized parameters were formally verified and subjected to simulation coverage testing. If the verification or test results fail, update the constraints in the constraint library based on the verification or test results.

12. The method as described in claim 11, characterized in that, Formal verification of the optimized parameters includes: A computational tree logic model checking technique is used to perform formal verification during the optimization of each parameter.

13. The method as described in claim 11, characterized in that, The simulation coverage test of the optimized parameters includes: Test cases are generated using a pre-defined assertion library; wherein the assertion library records the inputs and outputs when the simulation fails during each iteration of the optimization process; the test cases are generated based on the inputs and outputs. The optimized parameters were simulated and covered using the test cases.

14. The method as described in claim 1, characterized in that, Based on the functional description, a behavioral-level parameter model is obtained, including: Behavioral features are extracted from the functional description; the behavioral features characterize the features in the functional description that are related to the functions to be implemented in the target chip design. A behavior-level parameter model is constructed based on the behavior-level features.

15. The method as described in claim 14, characterized in that, Based on the functional description, behavioral-level features are extracted, including: The functional description is processed using a natural language model to obtain the behavioral-level features.

16. The method as described in claim 14, characterized in that, After constructing the behavior-level parameter model based on the behavior-level features, the method further includes: The behavior-level parameter model is validated using a static time series analysis engine. If the constraint information of the behavior-level parameter model is invalid, update the constraint information of the behavior-level parameter model.

17. The method according to any one of claims 1-16, characterized in that, After establishing dependencies, the resulting parameter set has multiple parameter combination spaces, and each parameter combination space contains parameters with dependencies. Optimize the parameters after establishing the dependency relationship, including: Global parameter tuning is performed on the parameter combination space to obtain the Pareto front solution set; Gradient optimization is performed on the Pareto front solution sets of each parameter combination space; Repeat the above process iteratively until the parameters that are optimal in terms of area and power consumption when there are no timing violations are obtained.

18. The method as described in claim 17, characterized in that, Global parameter tuning of the parameter combination space includes: The key parameter combination space is determined; the key parameter combination space is the parameter combination space that is currently sensitive to parameter adjustment among all parameter combination spaces. Global parameter tuning is performed on the key parameter combination space; Correspondingly, gradient optimization is performed on the Pareto front solution set of each parameter combination space, including: Gradient optimization is performed on the Pareto front solution set of each of the key parameter combination spaces.

19. The method as described in claim 17, characterized in that, The obtained Pareto front solution set retains only non-dominated solutions.

20. The method as described in claim 17, characterized in that, In each iteration, the adjustment range of parameters involved in the timing violation path in the previous iteration is reduced; The timing violation path is a path containing timing violations that is discovered during the iteration process when verifying the chip design.

21. The method as described in claim 17, characterized in that, Gradient optimization is performed on the Pareto front solution sets of each parameter combination space, including: For each parameter combination space, the adjustment range of each parameter is determined according to the correlation strength of each parameter in the parameter combination space, and gradient optimization is performed on the Pareto front solution set according to the adjustment range of each parameter.

22. A parameter configuration method, characterized in that, include: In response to an instruction to open the target interface, the target interface is opened; In response to the input operation of the functional description of the target chip design generated in the target interface, the parameter dependencies of the behavioral-level parameter model, system-level parameter model and RTL-level parameter model are obtained; the behavioral-level parameter model, system-level parameter model and RTL-level parameter model are obtained according to the functional description, and the behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters and the RTL-level parameter model includes RTL-level parameters; In response to obtaining the parameter dependencies of the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model, an optimized parameter set is output; wherein, the optimized parameter set is obtained by optimizing the behavioral-level parameter model, system-level parameter model, and RTL-level parameter model with established dependencies according to the dependencies, so that the target chip design has no timing violations.

23. A parameter configuration device, characterized in that, include: The acquisition module is used to obtain the functional description of the target chip design; The parameter extraction module is used to obtain a behavioral-level parameter model, a system-level parameter model, and an RTL-level parameter model based on the functional description; the behavioral-level parameter model includes behavioral-level parameters, the system-level parameter model includes system-level parameters, and the RTL-level parameter model includes RTL-level parameters. The dependency establishment module is used to establish dependencies on parameters in the behavior-level parameter model, the system-level parameter model, and the RTL-level parameter model to obtain a parameter set; An optimization module is used to optimize the parameter set according to the dependency relationship to obtain a target parameter set that ensures the target chip design is free from timing violations. The output module is used to output parameter configurations based on the target parameter set.

24. An electronic device, characterized in that, It includes a processor and a memory, the processor being configured to execute one or more programs stored in the memory to implement the parameter configuration method as described in any one of claims 1-22.

25. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the parameter configuration method as described in any one of claims 1-22.

26. A computer program product, characterized in that, The computer program product includes computer program code that, when run on a processor, causes the processor to perform the parameter configuration method as described in any one of claims 1-22.

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