Power supply control system and display device

Abstract

The invention relates to the technical field of display, in particular to a power supply control system and a display device. The power supply control system comprises a battery management chip and a display driving chip; the display driving chip comprises a first pin and a second pin, the first pin is used for at least outputting a first control signal, the second pin is used for at least outputting a second control signal, the first control signal is used for enabling the battery management chip to output a first voltage signal to the display driving chip, and the second control signal is used for enabling the battery management chip to output a second voltage signal; the second control signal is used for enabling the battery management chip to output a second voltage signal to the display driving chip; the battery management chip comprises a third pin and a fourth pin, the third pin is used for at least receiving the first control signal, and the fourth pin is used for at least receiving the second control signal; at least one first resistor is connected in series between the first pin and the third pin, and / or at least one first resistor is connected in series between the second pin and the fourth pin; the first resistor and the display driving chip are arranged adjacently. According to the invention, the product yield is effectively improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a power supply control system and a display device. Background Art

[0002] At present, the light emission of the display module is mainly provided by the battery management module (PMIC). At present, the voltage output and adjustment of the battery management module are controlled by the display driver chip (DDIC) in the display module. The display driver chip controls the battery management module to output a voltage that meets the requirements according to the picture information and brightness information.

[0003] However, the pins of the display driver chip are easily introduced with static electricity, which may cause electrostatic discharge (ESD) in the display driver chip, thereby damaging the display driver chip and reducing product yield. Summary of the invention

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a power supply control system and a display device to effectively improve product yield.

[0005] The present disclosure provides a power supply control system, including: a battery management chip and a display driver chip; the display driver chip includes a first pin and a second pin, the first pin is used to output at least a first control signal, the second pin is used to output at least a second control signal, the first control signal is used to enable the battery management chip to output a first voltage signal to the display driver chip, and the second control signal is used to enable the battery management chip to output a second voltage signal to the display driver chip; the battery management chip includes a third pin and a fourth pin, the third pin is used to receive at least the first control signal, and the fourth pin is used to receive at least the second control signal; at least one first resistor is connected in series between the first pin and the third pin, and / or at least one first resistor is connected in series between the second pin and the fourth pin; the first resistor is arranged adjacent to the display driver chip.

[0006] The present disclosure also provides a display device, which includes a power supply control system and a display panel that are electrically connected, wherein the power supply control system is the above-mentioned power supply control system.

[0007] Compared with the prior art, the technical solution provided by the present invention has the following advantages:

[0008] In the power supply control system provided by the present disclosure, at least one first resistor is connected in series between the first pin and the third pin, and / or at least one first resistor is connected in series between the second pin and the fourth pin, and the first resistor is arranged adjacent to the display driver chip, that is, the first resistor is arranged on a side close to the display driver chip, so that the static charge generated during the electrostatic test and the use process can first pass through the first resistor and then pass through the first pin or the second pin, that is, the static charge first passes through the first resistor, and the first resistor plays a role of current limiting, thereby reducing the peak value of the instantaneous current, thereby effectively reducing the static charge passing through the display driver chip, effectively reducing the risk of the display driver chip being broken down by static electricity, and improving the yield of the product.

[0009] Correspondingly, the display device provided by the present disclosure also has the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0011] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0012] Figure 1 It is a structural schematic diagram of a power supply control system provided by the present disclosure;

[0013] Figure 2 is a structural schematic diagram of another power supply control system provided by the present disclosure;

[0014] Figure 3 It is a structural schematic diagram of another power supply control system provided by the present disclosure;

[0015] Figure 4 It is a structural schematic diagram of another power supply control system provided by the present disclosure;

[0016] Figure 5 It is a structural schematic diagram of another power supply control system provided by the present disclosure;

[0017] Figure 6 It is a structural schematic diagram of another power supply control system provided by the present disclosure;

[0018] Figure 7 It is a structural schematic diagram of another power supply control system provided by the present disclosure;

[0019] Figure 8is a circuit diagram of a negative feedback circuit provided by the present disclosure;

[0020] Fig. 9 It is a structural schematic diagram of a display device provided by the present disclosure. DETAILED DESCRIPTION

[0021] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0022] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0023] Figure 1 This is a schematic diagram of a power supply control system provided by the present invention. Figure 1 , this embodiment provides a power supply control system, the power supply control system includes: a battery management chip (Power Management Integrated Circuit, PMIC) 10 and a display driver chip (Display Driver Integrated Circuit, DDIC) 20;

[0024] The display driver chip 20 includes a first pin Swire1 and a second pin Swire2, the first pin Swire1 is used to output at least a first control signal, the second pin Swire1 is used to output at least a second control signal, the first control signal Swire1 is used to enable the battery management chip 10 to output a first voltage signal to the display driver chip 20, and the second control signal Swire2 is used to enable the battery management chip 10 to output a second voltage signal to the display driver chip 20;

[0025] The battery management chip 10 includes a third pin Swire3 and a fourth pin Swire4, the third pin Swire1 is used to receive at least a first control signal, and the fourth pin Swire4 is used to receive at least a second control signal;

[0026] At least one first resistor 30 is connected in series between the first pin Swire1 and the third pin Swire3 , and / or at least one first resistor 30 is connected in series between the second pin Swire2 and the fourth pin Swire4 ;

[0027] The first resistor 30 is disposed adjacent to the display driving chip 20 .

[0028] Specifically, the power supply control system provided in this embodiment includes a battery management chip 10 and a display driver chip 20, wherein the battery management chip 10 is used to provide the display driver chip 20 with the voltage required for display, so that the display driver chip 20 can provide the display panel with the voltage required for display, thereby the display panel realizes display.

[0029] Among them, the display driver chip 20 includes a first pin Swire1, and the battery management chip 10 includes a third pin Swire3. The first pin Swire1 and the third pin Swire3 are connected. The first pin Swire1 is used to output at least a first control signal. Correspondingly, the third pin Swire1 is used to receive at least a first control signal. The first control signal is an enable signal. The first control signal can enable the battery management chip 10 to emit a first voltage signal. The first voltage signal can be a positive voltage signal PVDD or a negative voltage signal PVEE. The voltage obtained by the display driver chip 20 based on the first voltage signal is the positive voltage signal and the negative voltage signal of the light-emitting component in the display panel.

[0030] The display driver chip 20 includes a second pin Swire2, and the battery management chip 10 includes a fourth pin Swire4. The second pin Swire2 and the fourth pin Swire4 are connected. The second pin Swire2 is used to output at least a second control signal. Correspondingly, the fourth pin Swire4 is used to receive at least a second control signal. The second control signal is an enable signal. The second control signal can enable the battery management chip 10 to emit a second voltage signal AVDD. The voltage obtained by the display driver chip 20 based on the second voltage signal AVDD is the operating voltage of the display driver chip 20.

[0031] At least one first resistor 30 is connected in series between the first pin Swire1 and the third pin Swire3. The first resistor 30 is arranged adjacent to the display driver chip 20, that is, the first resistor 30 is arranged on a side close to the display driver chip 20, so that the static charge generated during the electrostatic test and the use process can first pass through the first resistor 30 and then pass through the first pin Swire1, that is, the static charge first passes through the first resistor 30, and the first resistor 30 plays a role of current limiting, thereby reducing the peak value of the instantaneous current, thereby effectively reducing the static charge passing through the display driver chip 20, effectively reducing the risk of the display driver chip 20 being broken down by static electricity, and improving the yield of the product.

[0032] Similarly, reference Figure 2 , Figure 2It is a structural schematic diagram of another power supply control system provided by the present invention, at least one first resistor 30 is connected in series between the second pin Swire2 and the fourth pin Swire4, and the first resistor 30 is arranged adjacent to the display driver chip 20, that is, the first resistor 30 is arranged on a side close to the display driver chip 20, so that the static charge generated during the electrostatic test and the use process can first pass through the first resistor 30 and then pass through the second pin Swire2, that is, the static charge first passes through the first resistor 30, and the first resistor 30 plays a role of current limiting, thereby reducing the peak value of the instantaneous current, thereby effectively reducing the static charge passing through the display driver chip 20, effectively reducing the risk of the display driver chip 20 being broken down by static electricity, and improving the yield of the product.

[0033] Similarly, reference Figure 3 , Figure 3 It is a structural schematic diagram of another power supply control system provided by the present invention, at least one first resistor 30 is connected in series between the first pin Swire1 and the third pin Swire3, and at least one first resistor 30 is connected in series between the second pin Swire2 and the fourth pin Swire4, and the first resistor 30 is arranged adjacent to the display driver chip 20, that is, the first resistor 30 is arranged on the side close to the display driver chip 20, so that the static charge generated during the electrostatic test and the use process can first pass through the first resistor 30 and then pass through the first pin Swire1 and the second pin Swire2, that is, the static charge first passes through the first resistor 30, and the first resistor 30 plays a role of current limiting, thereby reducing the peak value of the instantaneous current, thereby effectively reducing the static charge passing through the display driver chip 20, effectively reducing the risk of the display driver chip 20 being broken down by static electricity, and improving the yield of the product.

[0034] It should be noted that Figure 1 and Figure 3 exemplarily shows that a first resistor 30 is connected in series between the first pin Swire1 and the third pin Swire3. Figure 2 and Figure 3 It is exemplarily shown that a first resistor 30 is connected in series between the second pin Swire2 and the fourth pin Swire4. In other embodiments of the present disclosure, two or more first resistors 30 may be connected in series between the first pin Swire1 and the third pin Swire3, and two or more first resistors 30 may be connected in series between the second pin Swire2 and the fourth pin Swire4. The present disclosure will not elaborate on them one by one here.

[0035] Continue to refer Figure 1In some optional embodiments, the first pin Swire1 and the second pin Swire2 are arranged along the first direction X, and along the first direction X, the distance between the first pin Swire1 and the center of the display driver chip 20 is greater than the distance between the second pin Swire2 and the center of the display driver chip 20;

[0036] At least one first resistor 30 is connected in series between the first pin Swire1 and the third pin Swire2 .

[0037] Specifically, the first pin Swire1 and the second pin Swire2 are arranged along the first direction X. Along the first direction X, the distance between the first pin Swire1 and the center of the display driver chip 20 is greater than the distance between the second pin Swire2 and the center of the display driver chip 20, that is, along the first direction X, the first pin Swire1 and the second pin Swire2 are located on the same side of the display driver chip 20, and the first pin Swire1 is located on the side of the second pin Swire2 away from the center of the display driver chip 20, that is, relative to the second pin Swire2, the first pin Swire1 is located at the edge of the display driver chip 20, and the first pin Swire1 is more likely to introduce static charge.

[0038] A first resistor 30 is connected in series between the first pin Swire1 and the third pin Swire3, so that the static charge generated during the electrostatic test and the use process can first pass through the first resistor 30 and then pass through the first pin Swire1, that is, the static charge first passes through the first resistor 30, and the first resistor 30 plays a current limiting role, thereby reducing the peak value of the instantaneous current, effectively reducing the static charge introduced by the first pin Swire1, thereby effectively reducing the static charge passing through the display driver chip 20, effectively reducing the risk of the display driver chip 20 being broken down by static electricity, and improving the yield of the product.

[0039] Figure 4 This is a schematic diagram of another power supply control system provided by the present disclosure, referring to Figure 4 In some optional embodiments, the display driver chip 20 further includes a first control circuit 21, a second control circuit 22 and a third control circuit 23, wherein the first control circuit 21 and the third control circuit 23 are both used to generate a first control signal, and the second control circuit 22 is used to generate a second control signal;

[0040] The first pin Swire1 is electrically connected to the first control circuit 21, and the second pin Swire2 is electrically connected to the second control circuit 22 and the third control circuit 23;

[0041] The battery management chip 10 further includes a first identification circuit 11, a second identification circuit 12 and a third identification circuit 13, the first identification circuit 11 is electrically connected to the third pin Swire3, and the first identification circuit 11 is used to identify the first control signal generated by the first control circuit 21;

[0042] The second identification circuit 12 and the third identification circuit 13 are both electrically connected to the fourth pin Swire4 . The second identification circuit 12 is used to identify the second control signal generated by the second control circuit 22 . The third identification circuit 13 is used to identify the first control signal generated by the third control circuit 23 .

[0043] Specifically, the display driver chip 20 also includes a first control circuit 21, the first pin Swire1 is electrically connected to the first control circuit 21, and the first control circuit 21 is used to generate a first control signal. The battery management chip 10 also includes a first identification circuit 11, and the first identification circuit 11 is electrically connected to the third pin Swire3. The first identification circuit 11 can identify the first control signal generated by the first control circuit 21, thereby enabling the battery management chip 10 to emit a first voltage signal through the first control signal.

[0044] The display driver chip 20 also includes a second control circuit 22, the second pin Swire2 is electrically connected to the second control circuit 22, and the second control circuit 22 is used to generate a second control signal. The battery management chip 10 also includes a second identification circuit 12, and the second identification circuit 12 is electrically connected to the fourth pin Swire4. The second identification circuit 12 is used to identify the second control signal generated by the second control circuit 22, thereby enabling the battery management chip 10 to emit a second voltage signal AVDD through the second control signal.

[0045] A first resistor 30 is connected in series between the first pin Swire1 and the third pin Swire3, thereby effectively reducing the static charge passing through the display driver chip 20, effectively reducing the risk of the display driver chip 20 being broken down by static electricity, and improving the yield of the product. However, the first resistor 30 is at risk of being broken down by static electricity. After the first resistor 30 is broken down by static electricity, the resistance value of the first resistor 30 will increase, thereby causing the first control signal received by the battery management chip 10 to fail to trigger a logic high level, resulting in the failure to send a first voltage signal, resulting in the display panel being unable to light up.

[0046] The display driver chip 20 further includes a third control circuit 23, the second pin Swire2 is electrically connected to the third control circuit 23, and the third control circuit 23 is used to generate a first control signal. The battery management chip 10 further includes a third identification circuit 13, and the third identification circuit 13 is electrically connected to the fourth pin Swire4. The third identification circuit 13 can identify the first control signal generated by the third control circuit 23, thereby enabling the battery management chip 10 to send out a first voltage signal through the first control signal. Therefore, after the first resistor 30 connected in series between the first pin Swire1 and the third pin Swire3 is electrostatically broken down, the first control signal can be transmitted to the fourth pin Swire4 through the second pin Swire2, thereby enabling the battery management chip 10 to send out a first voltage signal through the first control signal.

[0047] Continue to refer Figure 4 In some optional embodiments, when the second control signal generated by the second control circuit 22 is a high voltage signal, the second control signal is used to enable the battery management chip 10 to output the second voltage signal AVDD to the display driver chip 20;

[0048] When the first control signal generated by the third control circuit 23 is a pulse signal, the first control signal is used to enable the battery management chip 10 to output a first voltage signal to the display driver chip 20 .

[0049] Specifically, after the first resistor 30 connected in series between the first pin Swire1 and the third pin Swire3 is broken down by static electricity, the first control signal can be transmitted to the fourth pin Swire4 through the second pin Swire2, thereby enabling the battery management chip 10 to emit a first voltage signal through the first control signal. Among them, the second control signal can be first generated by the second control circuit 22, and the second control signal is a high voltage signal, and the second control signal is transmitted to the fourth pin Swire4. After the second identification circuit 12 identifies the second control signal, the second control signal is used to enable the battery management chip 10 to output the second voltage signal AVDD to the display driver chip 20. During the time from the second control circuit 22 generating the second control signal with a high voltage signal to the display driver chip 20 receiving the second voltage signal AVDD, the third control circuit 23 generates a first control signal as a pulse signal, and transmits the first control signal to the fourth pin Swire4. After the third identification circuit 13 identifies the first control signal, the first control signal is used to enable the battery management chip 10 to output the first voltage signal to the display driver chip 20, thereby realizing the battery management chip 10 outputting the first voltage signal without affecting the battery management chip 10 outputting the second voltage signal AVDD.

[0050] It should be noted that this embodiment exemplarily shows a communication logic in which the second pin Swire2 outputs the first control signal and the second control signal after the first resistor 30 connected in series between the first pin Swire1 and the third pin Swire3 is broken down by static electricity. In other embodiments of the present disclosure, the second pin Swire2 can also output the first control signal and the second control signal through the setting of other communication logics, which will not be elaborated in the present disclosure.

[0051] Optionally, a judgment module may be provided between the second pin Swire2 and the receiving pin of the first voltage signal. When the display driver chip 20 does not receive the first voltage signal after the display driver chip 20 outputs the first control signal, it may be judged that the first resistor 30 connected in series between the first pin Swire1 and the third pin Swire3 is electrostatically broken down, thereby outputting the first control signal and the second control signal through the second pin Swire2. When the display driver chip 20 receives the first voltage signal after the display driver chip 20 outputs the first control signal, the second pin Swire2 outputs the second control signal. Optionally, the judgment module may be an inverter.

[0052] Figure 5 This is a schematic diagram of another power supply control system provided by the present disclosure, referring to Figure 5 In some optional embodiments, at least one first resistor 30 is connected in series between the second pin Swire2 and the fourth pin Swire4.

[0053] Specifically, at least one first resistor 30 is connected in series between the second pin Swire2 and the fourth pin Swire4. The first resistor 30 is arranged adjacent to the display driver chip 20, that is, the first resistor 30 is arranged on a side close to the display driver chip 20, so that the static charge generated during the electrostatic test and the use process can first pass through the first resistor 30 and then pass through the second pin Swire2, that is, the static charge first passes through the first resistor 30, and the first resistor 30 plays a current limiting role, thereby reducing the peak value of the instantaneous current, thereby effectively reducing the static charge passing through the display driver chip 20, effectively reducing the risk of the display driver chip 20 being broken down by static electricity, and improving the yield of the product.

[0054] Figure 6 This is a schematic diagram of another power supply control system provided by the present disclosure, referring to Figure 6 In some optional embodiments, the display driver chip 20 further includes a fourth control circuit 24, the fourth control circuit 24 is electrically connected to the first pin Swire1, and the fourth control circuit 24 is used to generate a second control signal;

[0055] The battery management chip 10 further includes a fourth identification circuit 14 , which is electrically connected to the third pin Swire3 . The fourth identification circuit 14 is used to identify the second control signal generated by the fourth control circuit 24 .

[0056] Specifically, the display driver chip 20 further includes a fourth control circuit 24, which is electrically connected to the first pin Swire1 and is used to generate a second control signal. The battery management chip 10 further includes a fourth identification circuit 14, which is electrically connected to the third pin Swire3 and is used to identify the second control signal generated by the fourth control circuit 24, thereby enabling the battery management chip 10 to emit a second voltage signal AVDD through the second control signal. Therefore, after the first resistor 30 connected in series between the second pin Swire2 and the fourth pin Swire4 is electrostatically broken down, the second control signal can be transmitted to the third pin Swire3 through the first pin Swire1, thereby enabling the battery management chip 10 to emit a second voltage signal AVDD through the second control signal.

[0057] Continue to refer Figure 6 In some optional embodiments, when the first control signal generated by the first control circuit 21 is a pulse signal, the first control signal is used to enable the battery management chip 10 to output a first voltage signal to the display driver chip 20;

[0058] When the second control signal generated by the fourth control circuit 24 is a high voltage signal, the second control signal is used to enable the battery management chip 10 to output the second voltage signal AVDD to the display driver chip 20 .

[0059] Specifically, after the first resistor 30 connected in series between the second pin Swire2 and the fourth pin Swire4 is broken down by static electricity, the second control signal can be transmitted to the third pin Swire3 through the first pin Swire1, thereby enabling the battery management chip 10 to emit the second voltage signal AVDD through the second control signal. Among them, the second control signal can be first generated by the fourth control circuit 24, and the second control signal is a high voltage signal, and the second control signal is transmitted to the third pin Swire3. After the fourth identification circuit 14 identifies the second control signal, the second control signal is used to enable the battery management chip 10 to output the second voltage signal AVDD to the display driver chip 20. During the time from the fourth control circuit 24 generating the second control signal with a high voltage signal to the display driver chip 20 receiving the second voltage signal AVDD, the first control circuit 21 generates a first control signal as a pulse signal, and transmits the first control signal to the third pin Swire3. After the first identification circuit 11 identifies the first control signal, the first control signal is used to enable the battery management chip 10 to output the first voltage signal to the display driver chip 20, thereby realizing that the battery management chip 10 outputs the second voltage signal AVDD without affecting the battery management chip 10 outputting the first voltage signal.

[0060] It should be noted that the present embodiment exemplarily shows a communication logic in which the first pin Swire1 outputs the first control signal and the second control signal after the first resistor 30 connected in series between the second pin Swire2 and the fourth pin Swire4 is broken down by static electricity. In other embodiments of the present disclosure, the first pin Swire1 can also output the first control signal and the second control signal through the setting of other communication logics, which will not be elaborated in the present disclosure.

[0061] Optionally, a judgment module may be provided between the first pin Swire1 and the receiving pin of the second voltage signal AVDD. When the display driver chip 20 does not receive the second voltage signal AVDD after the display driver chip 20 outputs the second control signal, it may be judged that the first resistor 30 connected in series between the second pin Swire2 and the fourth pin Swire4 is electrostatically broken down, thereby outputting the first control signal and the second control signal through the first pin Swire1. When the display driver chip 20 receives the second voltage signal AVDD after the display driver chip 20 outputs the second control signal, the first pin Swire1 outputs the first control signal. Optionally, the judgment module may be an inverter.

[0062] Figure 7 This is a schematic diagram of another power supply control system provided by the present disclosure, referring to Figure 7 In some optional embodiments, the power supply control system further includes a negative feedback circuit 40, and the negative feedback circuit 40 is electrically connected to the external power supply 50;

[0063] A negative feedback circuit 40 is connected between the first pin Swire1 and the third pin Swire3 . The negative feedback circuit 40 is used to adjust the voltage value of the first control signal received by the third pin Swire3 through an external power supply 50 .

[0064] Specifically, a negative feedback circuit 40 is connected between the first pin Swire1 and the third pin Swire3, and the negative feedback circuit 40 is electrically connected to an external power supply 50. The negative feedback circuit 40 is used to adjust the voltage value of the first control signal received by the third pin Swire3 through the external power supply 50. When the first resistor 30 between the first pin Swire1 and the third pin Swire3 is not broken down by static electricity, the voltage value of the first control signal transmitted by the first pin Swire1 can be normally transmitted to the third pin Swire3. After the first resistor 30 between the first pin Swire1 and the third pin Swire3 is broken down by static electricity, the resistance value of the first resistor 30 will increase. At this time, the voltage value of the first control signal received by the third pin Swire3 can be adjusted by the external power supply 50, so that the first control signal received by the battery management chip 10 can normally trigger a logic high level, so that the battery management chip 10 can send a first voltage signal to the display driver chip 20.

[0065] Figure 8 is a circuit diagram of a negative feedback circuit provided by the present disclosure, with reference to Figure 7 and Figure 8 In some optional embodiments, the negative feedback circuit 40 includes an operational amplifier A, a positive input terminal UP of the operational amplifier A is electrically connected to an external power supply 50, a reverse input terminal UN of the operational amplifier A is electrically connected to an output terminal UO of the operational amplifier A, and an output terminal UO of the operational amplifier A is electrically connected to one end of the first resistor 30 and the first pin Swire1.

[0066] Specifically, the positive input terminal UP of the operational amplifier A is electrically connected to the external power supply 50, and the voltage of the positive input terminal UP of the operational amplifier A remains unchanged. After the first resistor 30 between the first pin Swire1 and the third pin Swire3 is broken down by static electricity, the resistance of the first resistor 30 will increase, and the voltage at one end of the first resistor 30 electrically connected to the first pin Swire1 will increase, that is, the voltage of the output terminal UO of the operational amplifier A will increase, and the voltage of the reverse input terminal UN of the operational amplifier A will inevitably increase, causing the voltage of the output terminal UO of the operational amplifier A to decrease, thereby achieving the purpose of negative feedback, and the first control signal received by the battery management chip 10 can normally trigger a logic high level.

[0067] It should be noted that this embodiment exemplarily shows a circuit structure of the negative feedback circuit 40. In other embodiments of the present disclosure, the negative feedback circuit 40 may also adopt other circuit configurations, which will not be described in detail herein.

[0068] like Fig. 9 As shown, Fig. 9 is a schematic diagram of the structure of a display device provided by the present disclosure. This embodiment provides a display device, and the display device includes an electrically connected power supply control system 100 and a display panel 200, wherein the power supply control system 100 is the power supply control system provided by the embodiment of the present disclosure. It can be understood that the display device provided by the embodiment of the present disclosure application can be any electronic product with a display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc., and the embodiment of the present disclosure does not specifically limit this.

[0069] The display device provided in the embodiment of the present disclosure has the same technical features as the power supply control system provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0070] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0071] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power supply control system, characterized in that: include: Battery management chip and display driver chip; The display driver chip comprises a first pin and a second pin, the first pin is used to output at least a first control signal, the second pin is used to output at least a second control signal, the first control signal is used to enable the battery management chip to output a first voltage signal to the display driver chip, and the second control signal is used to enable the battery management chip to output a second voltage signal to the display driver chip; The battery management chip comprises a third pin and a fourth pin, the third pin is used to at least receive the first control signal, and the fourth pin is used to at least receive the second control signal; At least one first resistor is connected in series between the first pin and the third pin, and / or at least one first resistor is connected in series between the second pin and the fourth pin; The first resistor is disposed adjacent to the display driving chip.

2. The power supply control system according to claim 1, characterized in that: The first pin and the second pin are arranged along a first direction, and along the first direction, the distance between the first pin and the center of the display driver chip is greater than the distance between the second pin and the center of the display driver chip; At least one first resistor is connected in series between the first pin and the third pin.

3. The power supply control system according to claim 2, characterized in that: The display driver chip further includes a first control circuit, a second control circuit and a third control circuit, wherein the first control circuit and the third control circuit are both used to generate the first control signal, and the second control circuit is used to generate the second control signal; The first pin is electrically connected to the first control circuit, and the second pin is electrically connected to the second control circuit and the third control circuit; The battery management chip further includes a first identification circuit, a second identification circuit and a third identification circuit, the first identification circuit is electrically connected to the third pin, and the first identification circuit is used to identify the first control signal generated by the first control circuit; The second identification circuit and the third identification circuit are both electrically connected to the fourth pin, the second identification circuit is used to identify the second control signal generated by the second control circuit, and the third identification circuit is used to identify the first control signal generated by the third control circuit.

4. The power supply control system according to claim 3, characterized in that: When the second control signal generated by the second control circuit is a high voltage signal, the second control signal is used to enable the battery management chip to output a second voltage signal to the display driver chip; When the first control signal generated by the third control circuit is a pulse signal, the first control signal is used to enable the battery management chip to output a first voltage signal to the display driver chip.

5. The power supply control system according to claim 3, characterized in that: At least one first resistor is connected in series between the second pin and the fourth pin.

6. The power supply control system according to claim 5, characterized in that: The display driver chip further includes a fourth control circuit, the fourth control circuit is electrically connected to the first pin, and the fourth control circuit is used to generate the second control signal; The battery management chip further includes a fourth identification circuit, which is electrically connected to the third pin and is used to identify the second control signal generated by the fourth control circuit.

7. The power supply control system according to claim 6, characterized in that: When the first control signal generated by the first control circuit is a pulse signal, the first control signal is used to enable the battery management chip to output a first voltage signal to the display driver chip; When the second control signal generated by the fourth control circuit is a high voltage signal, the second control signal is used to enable the battery management chip to output a second voltage signal to the display driver chip.

8. The power supply control system according to claim 2, characterized in that: The power supply control system further comprises a negative feedback circuit, wherein the negative feedback circuit is electrically connected to an external power supply; The negative feedback circuit is connected between the first pin and the third pin, and the negative feedback circuit is used to adjust the voltage value of the first control signal received by the third pin through the external power supply.

9. The power supply control system according to claim 8, characterized in that: The negative feedback circuit includes an operational amplifier, a positive input terminal of the operational amplifier is electrically connected to the external power supply, a reverse input terminal of the operational amplifier is electrically connected to an output terminal of the operational amplifier, and an output terminal of the operational amplifier is electrically connected to one end of the first resistor and the first pin.

10. A display device, characterized in that: The display device comprises a power supply control system and a display panel which are electrically connected, wherein the power supply control system is the power supply control system according to any one of claims 1 to 9.

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