Display panel and driving method thereof

Abstract

The invention discloses a display panel and a driving method thereof. The display panel comprises a plurality of pixel driving circuits, and each pixel driving circuit comprises a switching transistor, a driving transistor, a write-in control transistor and a compensation transistor. The switching transistor comprises a first pole connected with a data signal, a second pole connected with the first node, and a control pole connected with a first scanning control signal. The driving transistor includes a first pole connected to a first node, a second pole connected to a second node, and a control pole connected to a third node. The write control transistor includes a first pole connected to the second node, a second pole connected to the first pole of the compensation transistor, and a control pole to which a control signal is accessed. The compensation transistor comprises a first pole connected with the second pole of the write control transistor, a second pole connected with the third node, and a control pole connected with a second scanning control signal.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a driving method thereof. Background Art

[0002] With the development of display technology, users have higher and higher requirements for the display effect of display panels. In the related art, by controlling the writing and level transmission of scanning signals, the display panel is divided into multiple display areas in the vertical direction, and each display area presents a different pixel refresh frequency. Although the display area with a higher pixel refresh frequency has a higher power consumption, the display area with a lower pixel refresh frequency has a lower power consumption, which can improve the display effect of the display panel while reducing the overall power consumption of the display panel as much as possible. However, by controlling the writing and level transmission of scanning signals, only the adjustment of the pixel refresh frequency of the display panel in the vertical direction can be achieved. Summary of the invention

[0003] The embodiments of the present application provide a display panel and a driving method thereof, which can enable the display panel to achieve different pixel refresh frequencies in different display areas in both the horizontal and vertical directions.

[0004] An embodiment of the present application provides a display panel, the display panel comprising a plurality of pixel driving circuits, each of the pixel driving circuits comprising a switch transistor, a driving transistor, a write control transistor and a compensation transistor;

[0005] The switch transistor includes a first electrode connected to the data signal, a second electrode connected to the first node, and a control electrode connected to the first scan control signal;

[0006] The driving transistor includes a first electrode connected to the first node, a second electrode connected to the second node, and a control electrode connected to a third node;

[0007] The write control transistor includes a first electrode connected to the second node, a second electrode connected to the first electrode of the compensation transistor, and a control electrode connected to a control signal;

[0008] The compensation transistor includes a first electrode connected to the second electrode of the write control transistor, a second electrode connected to the third node, and a control electrode connected to the second scan control signal;

[0009] The write control transistor is used to control whether the data signal is written into the third node according to the control signal.

[0010] Accordingly, an embodiment of the present application provides a method for driving a display panel, wherein the display panel includes a plurality of pixel driving circuits, each of the pixel driving circuits includes a switch transistor, a drive transistor, a write control transistor, and a compensation transistor; the switch transistor includes a first electrode connected to a data signal, a second electrode connected to a first node, and a control electrode connected to a first scan control signal; the drive transistor includes a first electrode connected to the first node, a second electrode connected to a second node, and a control electrode connected to a third node; the write control transistor includes a first electrode connected to the second node, a second electrode connected to the first electrode of the compensation transistor, and a control electrode connected to a control signal; the compensation transistor includes a first electrode connected to the second electrode of the write control transistor, a second electrode connected to the third node, and a control electrode connected to a second scan control signal;

[0011] The driving method comprises:

[0012] The write control transistor controls whether the data signal is written into the third node according to the control signal.

[0013] The beneficial effects provided by the embodiments of the present application include at least:

[0014] The display panel provided by the embodiment of the present application includes a pixel driving circuit, and the pixel driving circuit is connected in series with a write control transistor next to the compensation transistor. The write control transistor is maintained on or off according to the control signal. When the write control transistor is turned on, if the compensation transistor is turned on, the channel between the second node and the third node is turned on; when the write control transistor is turned off, regardless of whether the compensation transistor is turned on, the channel between the second node and the third node is turned off. Therefore, the write control transistor in the pixel driving circuit of the embodiment of the present application can control whether to perform data writing according to the control signal, that is, whether the data signal is written to the third node, so as to achieve flexible adjustment of the pixel refresh frequency. In addition, the embodiment of the present application can set the pixel driving circuit in the display area where the display panel needs to adjust the pixel refresh frequency to achieve the adjustment of the pixel refresh frequency of this part of the display area, so that different display areas of the display panel present different pixel refresh frequencies. In addition, the embodiment of the present application adds a write control transistor to the pixel driving circuit, and controls whether to perform data writing according to the control signal through the write control transistor, which is not subject to the longitudinal constraint of the scanning signal, so that the display panel can achieve the effect of different display areas presenting different pixel refresh frequencies in both the horizontal and vertical directions. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of a pixel driving circuit provided in an embodiment of the present application;

[0016] Figure 2 is a schematic diagram of another pixel driving circuit provided in an embodiment of the present application;

[0017] Figure 3 is a schematic diagram of a driving timing provided by an embodiment of the present application;

[0018] Figure 4 is a schematic diagram of a display panel provided in an embodiment of the present application;

[0019] Figure 5 is a schematic diagram of a pixel driving circuit;

[0020] Figure 6 is a schematic diagram of another pixel driving circuit;

[0021] Figure 7 is a schematic diagram of another display panel provided in an embodiment of the present application;

[0022] Figure 8 is a flow chart of a method for driving a display panel provided in an embodiment of the present application;

[0023] Fig. 9 is a flow chart of another display panel driving method provided in an embodiment of the present application;

[0024] Fig.10 This is a flow chart of another display panel driving method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The described technical solutions are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0026] In addition, the "plurality" in the embodiments of the present application refers to two or more. The "first" and "second" in the embodiments of the present application are used to distinguish different technical features, and do not indicate any order, quantity or importance.

[0027] The various embodiments provided in this application are similar, and features in different embodiments may be combined with each other.

[0028] The order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0029] See also Figure 1 , Figure 1 is a schematic diagram of a pixel driving circuit provided in an embodiment of the present application. Figure 1 As shown, the pixel driving circuit includes a switch transistor T2, a driving transistor T1, a write control transistor T9 and a compensation transistor T3.

[0030] The switch transistor T2 includes a first electrode connected to the data signal DATA, a second electrode connected to the first node A, and a control electrode connected to the first scan control signal PSCAN. The compensation transistor T3 includes a first electrode connected to the first node A, a second electrode connected to the second node B, and a control electrode connected to the third node Q. The write control transistor T9 includes a first electrode connected to the second node B, a second electrode connected to the first electrode of the compensation transistor T3, and a control electrode connected to the control signal Control. The compensation transistor T3 includes a first electrode connected to the second electrode of the write control transistor T9, a second electrode connected to the third node Q, and a control electrode connected to the second scan control signal NSCAN_T3.

[0031] Wherein, the write control transistor T9 is maintained on or off according to the control signal Control. When the write control transistor T9 is turned on, if the compensation transistor T3 is turned on, the channel between the second node B and the third node Q is turned on, and the data signal DATA can be written to the third node Q. When the write control transistor T9 is turned off, regardless of whether the compensation transistor T3 is turned on, the channel between the second node B and the third node Q is turned off, and the data signal DATA cannot be written to the third node Q. Therefore, the write control transistor T9 can control whether the data signal DATA is written to the third node Q according to the control signal Control.

[0032] In some embodiments, Figure 1 As shown, the pixel driving circuit further includes a reset control transistor T10 and a first reset transistor T4.

[0033] The reset control transistor T10 includes a first electrode connected to the first reset signal VI_T4_2, a second electrode connected to the first electrode of the first reset transistor T4, and a control electrode connected to the control signal Control. The first reset transistor T4 includes a first electrode connected to the second electrode of the reset control transistor T10, a second electrode connected to the third node Q, and a control electrode connected to the third scan control signal NSCAN_T4.

[0034] The reset control transistor T10 is maintained on or off according to the control signal Control. When the reset control transistor T10 is turned on, if the first reset transistor T4 is turned on, the third node Q can be reset by the first reset signal VI_T4_2. When the reset control transistor T10 is turned off, regardless of whether the first reset transistor T4 is turned on, the first reset signal VI_T4_2 cannot reach the third node Q, thereby failing to reset the third node Q. Therefore, the reset control transistor T10 is used to control whether the third node Q is reset according to the control signal Control.

[0035] In some embodiments, the write control transistor T9 and the reset control transistor T10 in a pixel driving circuit are both N-type Thin Film Transistors (NTFT) or both P-type Thin Film Transistors (PTFT). Figure 1 In the example, the write control transistor T9 and the reset control transistor T10 are N-type thin film transistors.

[0036] like Figure 1 As shown, the pixel driving circuit further includes a first light emitting control transistor T5, a second light emitting control transistor T6 and a light emitting device.

[0037] The first light-emitting control transistor T5 includes a first electrode connected to the high potential signal VDD, a second electrode connected to the first node A, and a control electrode connected to the light-emitting control signal EM1. The second light-emitting control transistor T6 includes a first electrode connected to the second node B, a second electrode connected to the fourth node C, and a control electrode connected to the light-emitting control signal EM1. The light-emitting device includes an anode terminal connected to the fourth node C and a cathode terminal connected to the low potential signal VSS. In the light-emitting stage, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on, and the current flowing through the driving transistor T1 can pass through the second node B and the fourth node C, thereby driving the light-emitting device to emit light.

[0038] like Figure 1 As shown, the pixel driving circuit further includes a second reset transistor T7 and a third reset transistor T8. The second reset transistor T7 includes a first electrode connected to the second reset signal VI_A_3, a second electrode connected to the fourth node C, and a control electrode connected to the fourth scan control signal PSCAN2. The third reset transistor T8 includes a first electrode connected to the third reset signal VI_T8_1, a second electrode connected to the first node A, and a control electrode connected to the fourth scan control signal PSCAN2.

[0039] like Figure 1 As shown, the pixel driving circuit further includes a storage capacitor Cst and a boost capacitor Cboost. The storage capacitor Cst includes one end connected to the high potential signal and the other end connected to the third node Q. The boost capacitor Cboost includes one end connected to the first scan control signal PSCAN and the other end connected to the third node Q.

[0040] See also Figure 2 , Figure 2 is a schematic diagram of a pixel driving circuit provided in an embodiment of the present application. Figure 2 The pixel driving circuit shown is Figure 1 The difference between the pixel driving circuit shown is that Figure 2 The pixel driving circuit shown resets the third node Q through the second node B.

[0041] like Figure 2 As shown, the pixel driving circuit includes a switching transistor T2, a driving transistor T1, a write control transistor T9 and a compensation transistor T3. The switching transistor T2 includes a first electrode connected to the data signal DATA, a second electrode connected to the first node A, and a control electrode connected to the first scan control signal PSCAN. The compensation transistor T3 includes a first electrode connected to the first node A, a second electrode connected to the second node B, and a control electrode connected to the third node Q. The write control transistor T9 includes a first electrode connected to the second node B, a second electrode connected to the first electrode of the compensation transistor T3, and a control electrode connected to the control signal Control. The compensation transistor T3 includes a first electrode connected to the second electrode of the write control transistor T9, a second electrode connected to the third node Q, and a control electrode connected to the second scan control signal NSCAN_T3. Among them, the write control transistor T9 can control whether the data signal DATA is written to the third node Q according to the control signal Control. In some embodiments, the write control transistor T9 can be an N-type thin film transistor, or a P-type thin film transistor. Figure 2 In the example, the write control transistor T9 is an N-type thin film transistor.

[0042] like Figure 2 As shown, the pixel driving circuit further includes a first reset transistor T4. The first reset transistor T4 includes a first electrode connected to the first reset signal VI_T4_2, a second electrode connected to the second node B, and a control electrode connected to the third scan control signal NSCAN_T4.

[0043] like Figure 2 As shown, the pixel driving circuit further includes a first light-emitting control transistor T5, a second light-emitting control transistor T6 and a light-emitting device. The first light-emitting control transistor T5 includes a first electrode connected to the high potential signal VDD, a second electrode connected to the first node A, and a control electrode connected to the light-emitting control signal EM1. The second light-emitting control transistor T6 includes a first electrode connected to the second node B, a second electrode connected to the fourth node C, and a control electrode connected to the light-emitting control signal EM1. The light-emitting device includes an anode terminal connected to the fourth node C and a cathode terminal connected to the low potential signal VSS.

[0044] like Figure 2As shown, the pixel driving circuit further includes a second reset transistor T7 and a third reset transistor T8. The second reset transistor T7 includes a first electrode connected to the second reset signal VI_A_3, a second electrode connected to the fourth node C, and a control electrode connected to the fourth scan control signal PSCAN2. The third reset transistor T8 includes a first electrode connected to the third reset signal VI_T8_1, a second electrode connected to the first node A, and a control electrode connected to the fourth scan control signal PSCAN2.

[0045] like Figure 2 As shown, the pixel driving circuit further includes a storage capacitor Cst and a boost capacitor Cboost. The storage capacitor Cst includes one end connected to the high potential signal and the other end connected to the third node Q. The boost capacitor Cboost includes one end connected to the first scan control signal PSCAN and the other end connected to the third node Q.

[0046] In some embodiments, the control electrode may be a gate electrode, the first electrode may be one of a source electrode and a drain electrode, and the second electrode may be the other of the source electrode and the drain electrode.

[0047] It should be understood that Figure 1 and Figure 2 In the example, the switch transistor T2, the driving transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are P-type thin-film transistors, and the compensation transistor T3 and the first reset transistor T4 are N-type thin-film transistors. However, this does not constitute a limitation on the embodiments of the present application. In actual applications, each transistor can be arbitrarily set to an N-type thin-film transistor or a P-type thin-film transistor in accordance with the driving timing.

[0048] See also Figure 3 , Figure 3 It is a schematic diagram of a driving timing provided in an embodiment of the present application. Figure 3 The drive timing shown is for driving Figure 1 and Figure 2 The corresponding devices in the pixel driving circuit shown.

[0049] One frame display time can be divided into a data writing stage and a light emitting stage. In the light emitting stage, the light emitting control signal EM1 is at a low level, and the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned on. In the data writing stage, the light emitting control signal EM1 is at a high level, and the first light emitting control transistor T5 and the second light emitting control transistor T6 are turned off; when the control signal Control is at a high level and the second scanning control signal NSCAN_T3 is at a high level, the channel between the second node B and the third node Q is turned on, and the data signal DATA can be written to the third node Q; when the control signal Control is at a low level, the write control transistor T9 is turned off, so that the channel between the second node B and the third node Q is turned off, and the data signal cannot be written to the third node Q.

[0050] The embodiment of the present application can adjust the pixel refresh frequency by setting the high level duration and low level duration of the control signal so that data writing is not always performed within a frame display time. Figure 3 As shown, through the first control signal Control1, data writing can be performed in one frame display time of two adjacent frame display times, while data writing is not performed in the other frame display time, thereby reducing the pixel refresh frequency by one half. Figure 3 As shown, through the second control signal Control2, data writing can be performed in one frame display time of three adjacent frame display times, while data writing is not performed in the other two frame display times, thereby reducing the pixel refresh frequency by two thirds.

[0051] Based on this, assuming that the write control transistor T9 and the reset control transistor T10 remain turned on during the first level duration of the control signal Control, and remain turned off during the second level duration of the control signal Control, the greater the ratio of the first level duration of the control signal Control to the second level duration, the greater the pixel refresh frequency of the pixel driving circuit. Wherein, the first level is a high level, the second level is a low level, and the write control transistor T9 and the reset control transistor T10 are both N-type thin film transistors; or, the first level is a low level, the second level is a high level, and the write control transistor T9 and the reset control transistor T10 are both P-type thin film transistors.

[0052] See also Figure 4 , Figure 4 It is a schematic diagram of a display panel provided in an embodiment of the present application.

[0053] like Figure 4As shown, the display panel 1000 may include a plurality of pixel driving circuits 1100. In the embodiment of the present application, the pixel driving circuit 1100 may include a pixel driving circuit 1110. The pixel driving circuit 1110 may be as follows: Figure 1 or Figure 2 As shown, the introduction of the pixel driving circuit 1110 can be referred to the above embodiment, and will not be repeated here. In some embodiments, the pixel driving circuit 1100 may further include an original pixel driving circuit 1120, and the original pixel driving circuit 1120 may be as follows: Figure 5 or Figure 6 For the description of each device and its connection relationship in the original pixel driving circuit 1120, please refer to the above Figures 1 to 3 The embodiments are not described in detail here.

[0054] In some embodiments, the display panel 1000 may include at least two display areas 1200 , at least one display area 1200 includes a pixel driving circuit 1110 , and the remaining display areas 1200 may include an original pixel driving circuit 1120 .

[0055] For example, Figure 4 As shown, the display panel 1000 may include a first display area 1210, a second display area 1220, and a third display area 1230. Among them, at least one display area 1200 includes a pixel driving circuit 1110, and the pixel driving circuits 1100 included in one display area 1200 are of the same type. Figure 4 As shown, the pixel driving circuits in the first display area 1210 are all pixel driving circuits 1110 , the pixel driving circuits in the second display area 1220 are all pixel driving circuits 1110 , and the pixel driving circuits in the third display area 1230 are all original pixel driving circuits 1120 .

[0056] In some embodiments, the display panel includes a first display area and a second display area, and the first display area and the second display area both include a pixel driving circuit. The control signal connected to the pixel driving circuit in the first display area is a first control signal, and the control signal connected to the pixel driving circuit in the second display area is a second control signal. The first control signal and the second control signal are different control signals.

[0057] In some embodiments, the write control transistor and the reset control transistor in the pixel driving circuit remain turned on during the first level duration of the control signal, and remain turned off during the second level duration of the control signal. If the ratio of the first level duration of the first control signal to the second level duration is greater than the ratio of the first level duration to the second level duration of the second control signal, the pixel refresh frequency of the first display area is greater than the pixel refresh frequency of the second display area.

[0058] For example, Figure 4 As shown, the pixel driving circuit 1110 in the first display area 1210 of the display panel 1000 is connected to the first control signal Control1, and the pixel driving circuit 1110 in the second display area 1220 is connected to the second control signal Control2. The first control signal Control1 and the second control signal Control2 are different control signals. Figure 3 The first control signal Control1 and the second control signal Control2 shown in FIG. 1 reduce the pixel refresh frequency of the first display area 1210 by one half, and reduce the pixel refresh frequency of the second display area 1220 by two thirds. Figure 7 As shown, the pixel refresh rate of the third display area 1230 is 120 Hz; the pixel refresh rate of the first display area 1210 is 120 Hz. Figure 3 The first control signal Control1 shown in FIG. 1 reduces the pixel refresh frequency to 60 Hz; the second display area 1220 is controlled by Figure 3 The second control signal Control2 shown reduces the pixel refresh frequency to 40 Hz.

[0059] In summary, the display panel provided by the embodiment of the present application includes a pixel driving circuit, and the pixel driving circuit is connected in series with a write control transistor next to the compensation transistor. The write control transistor is maintained on or off according to the control signal. When the write control transistor is turned on, if the compensation transistor is turned on, the channel between the second node and the third node is turned on; when the write control transistor is turned off, regardless of whether the compensation transistor is turned on, the channel between the second node and the third node is turned off. Therefore, the write control transistor in the pixel driving circuit of the embodiment of the present application can control whether to perform data writing according to the control signal, that is, whether the data signal is written to the third node, so as to achieve flexible adjustment of the pixel refresh frequency. In addition, the embodiment of the present application can set the pixel driving circuit in the display area where the pixel refresh frequency needs to be adjusted on the display panel to achieve the adjustment of the pixel refresh frequency of this part of the display area, so that different display areas of the display panel present different pixel refresh frequencies. In addition, the embodiment of the present application adds a write control transistor to the pixel driving circuit, and controls whether to perform data writing according to the control signal through the write control transistor, which is not subject to the longitudinal constraint of the scanning signal, so that the display panel can achieve the effect of different display areas presenting different pixel refresh frequencies in both the horizontal and vertical directions.

[0060] Correspondingly, an embodiment of the present application also provides a method for driving a display panel.

[0061] The display panel includes a plurality of pixel driving circuits, each pixel driving circuit includes a switching transistor, a driving transistor, a write control transistor and a compensation transistor. The switching transistor includes a first electrode connected to a data signal, a second electrode connected to a first node, and a control electrode connected to a first scan control signal. The driving transistor includes a first electrode connected to a first node, a second electrode connected to a second node, and a control electrode connected to a third node. The write control transistor includes a first electrode connected to a second node, a second electrode connected to a first electrode of the compensation transistor, and a control electrode connected to a control signal. The compensation transistor includes a first electrode connected to a second electrode of the write control transistor, a second electrode connected to a third node, and a control electrode connected to a second scan control signal.

[0062] like Figure 8 As shown, the driving method of the display panel includes:

[0063] Step 810: The write control transistor controls whether the data signal is written into the third node according to the control signal.

[0064] In some embodiments, each pixel driving circuit further includes a reset control transistor and a first reset transistor. The reset control transistor includes a first electrode connected to the first reset signal, a second electrode connected to the first electrode of the first reset transistor, and a control electrode connected to the control signal. The first reset transistor includes a first electrode connected to the second electrode of the reset control transistor, a second electrode connected to the third node, and a control electrode connected to the third scan control signal.

[0065] like Fig. 9 As shown, the driving method of the display panel also includes:

[0066] Step 820: The reset control transistor controls whether the third node is reset according to the control signal.

[0067] It should be understood that step 820 may be performed before step 810 or after step 810. Fig. 9 The order in which the steps are executed does not constitute a limitation on this application.

[0068] In some embodiments, the display panel includes a first display area and a second display area, and both the first display area and the second display area include a pixel driving circuit.

[0069] like Fig.10 As shown, the driving method of the display panel also includes:

[0070] Step 830: driving the pixel driving circuit in the first display area according to the first control signal;

[0071] Step 840: Drive the pixel driving circuit in the second display area according to the second control signal.

[0072] The first control signal and the second control signal are different control signals.

[0073] It should be understood that step 830 and step 840 can be performed simultaneously. Fig.10 The order in which the steps are executed does not constitute a limitation on the present application.

[0074] The specific implementation methods and corresponding beneficial effects of the above operations can be found in the above detailed description of the pixel driving circuit, driving timing and display panel, which will not be elaborated here.

[0075] The above is a detailed introduction to a display panel and a driving method thereof provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: The display panel includes a plurality of pixel driving circuits, each of which includes a switch transistor, a driving transistor, a write control transistor and a compensation transistor; The switch transistor includes a first electrode connected to the data signal, a second electrode connected to the first node, and a control electrode connected to the first scan control signal; The driving transistor includes a first electrode connected to the first node, a second electrode connected to the second node, and a control electrode connected to a third node; The write control transistor includes a first electrode connected to the second node, a second electrode connected to the first electrode of the compensation transistor, and a control electrode connected to a control signal; The compensation transistor includes a first electrode connected to the second electrode of the write control transistor, a second electrode connected to the third node, and a control electrode connected to the second scan control signal; The write control transistor is used to control whether the data signal is written into the third node according to the control signal.

2. The display panel according to claim 1, characterized in that: Each of the pixel driving circuits further includes a first reset transistor; The first reset transistor includes a first electrode connected to a first reset signal, a second electrode connected to the second node, and a control electrode connected to a third scan control signal.

3. The display panel according to claim 1, characterized in that: Each of the pixel driving circuits further includes a reset control transistor and a first reset transistor; The reset control transistor includes a first electrode connected to a first reset signal, a second electrode connected to the first electrode of the first reset transistor, and a control electrode connected to the control signal; The first reset transistor includes a first electrode connected to the second electrode of the reset control transistor, a second electrode connected to the third node, and a control electrode connected to the third scan control signal; The reset control transistor is used to control whether the third node is reset according to the control signal.

4. The display panel according to claim 3, characterized in that: The write control transistor and the reset control transistor in one of the pixel driving circuits are both N-type thin film transistors, or are both P-type thin film transistors.

5. The display panel according to claim 1, characterized in that: The display panel includes at least two display areas, and at least one of the display areas includes the pixel driving circuit.

6. The display panel according to claim 5, characterized in that: The display panel comprises a first display area and a second display area, and the first display area and the second display area both comprise the pixel driving circuit; Among them, the control signal connected to the pixel driving circuit in the first display area is a first control signal, and the control signal connected to the pixel driving circuit in the second display area is a second control signal; the first control signal and the second control signal are different control signals.

7. The display panel according to claim 6, characterized in that: The write control transistor remains turned on during a first level duration of the control signal, and remains turned off during a second level duration of the control signal; Among them, if the ratio of the first level duration to the second level duration of the first control signal is greater than the ratio of the first level duration to the second level duration of the second control signal, the pixel refresh frequency of the first display area is greater than the pixel refresh frequency of the second display area.

8. A method for driving a display panel, characterized in that: The display panel includes a plurality of pixel driving circuits, each of which includes a switch transistor, a drive transistor, a write control transistor, and a compensation transistor; the switch transistor includes a first electrode connected to a data signal, a second electrode connected to a first node, and a control electrode connected to a first scan control signal; the drive transistor includes a first electrode connected to the first node, a second electrode connected to a second node, and a control electrode connected to a third node; the write control transistor includes a first electrode connected to the second node, a second electrode connected to the first electrode of the compensation transistor, and a control electrode connected to a control signal; the compensation transistor includes a first electrode connected to the second electrode of the write control transistor, a second electrode connected to the third node, and a control electrode connected to a second scan control signal; The driving method comprises: The write control transistor controls whether the data signal is written into the third node according to the control signal.

9. The driving method according to claim 8, characterized in that: Each of the pixel driving circuits further includes a reset control transistor and a first reset transistor; the reset control transistor includes a first electrode connected to a first reset signal, a second electrode connected to the first electrode of the first reset transistor, and a control electrode connected to the control signal; the first reset transistor includes a first electrode connected to the second electrode of the reset control transistor, a second electrode connected to the third node, and a control electrode connected to a third scan control signal; The driving method further includes: The reset control transistor controls whether the third node is reset according to the control signal.

10. The driving method according to claim 8, characterized in that: The display panel comprises a first display area and a second display area, and the first display area and the second display area both comprise the pixel driving circuit; The driving method further includes: driving the pixel driving circuit in the first display area according to a first control signal; driving the pixel driving circuit in the second display area according to a second control signal; The first control signal and the second control signal are different control signals.

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