Method of operating phase change memory, corresponding apparatus and computer program product

Abstract

Embodiments of the present disclosure relate to a method of operating a phase change memory, a corresponding apparatus and a computer program product. A method of operating a phase change memory and a corresponding apparatus and computer program product are provided. An example of a write operation in a phase change memory includes: if a first group includes at least one cell set to a high logic level, performing a reset write operation by applying at least one current reset pulse to set to a low logic level; and if the second group includes at least one cell set to a low logic level, performing a set write operation to set to a high logic level. The setup write operation is verified to be successful or failed. The success or failure of the reset write operation is verified. In response to the reset write operation being considered to fail or the set write operation being considered to fail, the write operation is considered to fail.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Italian Patent Application No. 102023000019332, filed on September 20, 2023, entitled “Method of Operating PhaseChange Memories, Corresponding Device and Computer Program Product”, which is incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] This specification relates to the field of data storage technology.

[0004] One or more embodiments may be applied to various types of computer memory technologies, such as PCM, ie phase change memory, for example ePCM (ie embedded phase change memory) and / or ePCM NVM (ie non-volatile memory ePCM). Background Art

[0005] Phase change memory, or PCM for short, is a computer storage technology, ie, a memory technology, and is typically a non-volatile random access memory technology that can be embedded in an integrated circuit (IC) semiconductor device.

[0006] Typically, PCMs operate in a bit-by-bit manner, as heat generated by an electric current flowing through a heated material (called a phase change material, such as, for example, chalcogenide glass) is used to melt and quench the phase change material, causing it to become amorphous, or to maintain the phase change material within its crystallization temperature range, thereby switching it to a crystalline state.

[0007] Thus, a PCM memory cell can use this phase change material to store 1 bit of information because the two states of the phase change material, amorphous or crystalline, are characterized by different resistance values ​​that facilitate distinguishing one state from the other, i.e., each of the two states corresponds to a different value of a single bit.

[0008] Therefore, phase change materials can stably exist in two states:

[0009] an amorphous or disordered state characterized by high resistivity, i.e., high resistance, such as to represent a low logic state, such as "0", or

[0010] The crystalline state or ordered state is characterized by low resistivity, ie, low resistance, eg, lower resistance than the amorphous state, eg, representing a high logic state, such as "1".

[0011] The PCM memory cell can be switched between these two states by heating the phase change material differently, i.e., by applying a current to the phase change material for a given time to switch to the first state, and by applying different values ​​of current to the phase change material for different times to switch to the second state.

[0012] For example, a "set" write operation to a particular cell, ie, setting the cell to a high logic state, may be performed by applying a current pulse having a triangular shape to the phase change material of the particular cell.

[0013] Thus, the current flowing within the PCM cell increases rapidly to a value, for example, which may heat the corresponding phase change material to a value above the crystallization temperature associated with the corresponding phase change material but below the melting temperature associated with the same phase change material, and then decreases slowly.

[0014] For example, a "reset" write operation to a particular cell, ie, setting the cell to a low logic state, may be performed by applying a short rectangular current pulse to the phase change material of that particular cell.

[0015] Thus, the current flowing within the PCM cell rapidly increases to a certain value, for example, may heat the corresponding phase change material to a value above the melting temperature associated with the corresponding phase change material, and then rapidly decreases after a short time (e.g., 100 ns). For example, a read operation on a particular cell may involve measuring the resistance value of the phase change material of the particular cell and the corresponding state (i.e., amorphous or crystalline) of the particular cell by applying a given voltage change thereto and by measuring the corresponding current flowing therein.

[0016] It should be noted that after any write operation (i.e., a reset or set write operation), a write verification operation is usually performed, i.e., a read operation used to check whether the corresponding write operation is successful, and:

[0017] - if the write verification operation is deemed successful (i.e., if the read operation used to check whether the corresponding write operation was successful is deemed successful because the read operation detected that the cell associated with this corresponding write operation contains the correct value that should be written into this cell), then the corresponding write operation is completed because the value contained in the cell is correct and the write operation is therefore successful, and

[0018] -If the write verification operation is deemed unsuccessful (i.e., if the read operation detects that the cell associated with this corresponding write operation contains a value different from the correct value that should be written into this cell), the write operation will be applied again, i.e., current is applied to the cell again to repeat the write operation.

[0019] Therefore, a write verify operation can be:

[0020] a reset write verify operation, used to check whether the cell to be reset (i.e., the cell set to a low logic level in response to the reset write operation) is effectively in a reset state, i.e., set to a low logic level, after the corresponding reset pulse; and

[0021] - A set write verify operation, used to check whether the cell to be set (ie, the cell set to a high logic level in response to the set write operation) is effectively in the set state, ie, set to a high logic level, after the corresponding set pulse.

[0022] Single-ended PCM is a type of PCM in which a single cell corresponds to a single bit (ie, 1 cell / bit).

[0023] A read operation in single-ended PCM is performed by using a reference current (eg, supplied by a reference current generator) and a sense amplifier that receives:

[0024] At one terminal, the current from the PCM cell being read, and

[0025] At the other terminal, a reference current is supplied by a reference current generator.

[0026] The sense amplifier is also configured to compare the current received from the PCM cell being read with the reference current to determine the logic level stored within the PCM cell being read, ie, its state.

[0027] The single-ended PCM architecture suffers from resistance drift caused by the relaxation phenomenon of the amorphous material, ie, the intrinsic behavior of the amorphous state of the phase change material causes its resistance value to increase.

[0028] In response to the "reset" write operation, the resistance of the amorphous phase change material begins to increase over time. This increase is the result of relaxation affecting the amorphous state of the phase change material and is caused by the rearrangement of the atomic structure of the amorphous phase change material over time.

[0029] In response to such a reset write operation, the phase change material is rapidly quenched and its atomic structure is frozen in a high stress state, ie, an amorphous state.

[0030] The atomic configuration of the amorphous state of the phase change material rearranges over time to a configuration with lower free energy. This rearrangement is the result of thermally activated annihilation of trapping centers (e.g., vacancies, dangling bonds, or disorder-induced local states) and causes the resistance to increase over time.

[0031] Therefore, the observed resistance drift of the amorphous phase change material, ie the increased resistance value, is a result of the intrinsic behavior of this amorphous phase change material, namely the rearrangement of the atomic structure due to an attempt to reduce the free energy in this structure.

[0032] This resistance drift causes the resistance value of the PCM cell to change during its lifetime, starting from a minimum resistance value after a reset write operation, i.e., when the rearrangement caused by relaxation effects is still negligible, and increasing over time.

[0033] Therefore, one disadvantage of the single-ended PCM architecture is the difficulty in selecting a reference current that remains constant throughout the operating life of the PCM cell.

[0034] In fact, this reference current should preferably be:

[0035] being disposed between a first current range including currents that may pass through the cell when the cell's state is set to a high logic state and a second current range including currents that may pass through the same cell when the cell's state is set to a low logic state, the second current range varying during the useful life of the PCM cell in accordance with a change in the resistance value of the phase change material, and

[0036] is maintained at a distance from both the first current range and the second current range to ensure the reliability and retention of the non-volatile memory.

[0037] Relaxation effects affect read operations of PCM cells that are in a "reset" state (ie, containing a low logic level) because the resistance of the phase change material changes over time, making it more difficult to select a fixed reference current for the read operation.

[0038] One possible solution may be to use a PCM architecture with two cells per bit, as disclosed in patent document US 2009 / 0161417 A1.

[0039] Document US 2009 / 0161417 A1 discloses a two-cell-per-bit PCM architecture, ie two cells in the PCM architecture contain a single data bit and one of the two cells (complement cell) is programmed to the complementary state of the other of the two cells.

[0040] Thus, the bit is determined by reading the bit stored in one of the two cells and comparing it with the bit stored in the complement cell.

[0041] Therefore, in a PCM architecture with two cells per bit, no reference current is required since the read operation of any data (i.e., high or low logic state) is based on the value stored in the cell of this data in its direct form (i.e., high or low logic state, respectively), the value stored in the complementary cell of this data in its complement form (i.e., low or high logic state, respectively), and the use of a sense amplifier that is configured to receive the current of the "direct" cell that has to be read (i.e., containing the data in direct form) at one terminal and the current of the associated complement cell (i.e., containing the data in complement form) at the other terminal.

[0042] Relative to a single-ended PCM architecture, the two-cell-per-bit PCM architecture has both significantly increased footprint and production cost because two cells are used instead of a single cell to store a single bit.

[0043] A solution to reduce the impact of resistance drift of a single-ended PCM architecture would be beneficial in reducing the production cost and required area of ​​the PCM architecture without sacrificing PCM ruggedness. Summary of the invention

[0044] It is an aim of one or more embodiments to provide such a solution.

[0045] According to one or more embodiments, this object is achieved by a method for performing a PCM write operation having the characteristics set out in the appended claims.

[0046] One or more embodiments relate to corresponding memory devices and corresponding computer program products, which can be loaded into at least one processing circuit (e.g., a computer) and include software code portions for performing the steps of the method when the product is run on at least one processing circuit. As used herein, references to such computer program products should be understood as being equivalent to references to computer-readable media containing instructions for controlling a processing system to coordinate the implementation of the method according to one or more embodiments.

[0047] The claims are an integral part of the technical teaching provided with respect to the exemplary embodiments.

[0048] The solution described herein includes a method of performing a write operation (i.e., writing data comprising one or more bits) in a phase change memory (PCM) device, the PCM device comprising a first group of cells and a second group of cells, the first group of cells and the second group of cells being configured to be set to a low logic level and a high logic level, respectively, in response to a write operation, the write operation comprising a reset write operation and / or a set write operation.

[0049] The method according to the solution described in this article includes:

[0050] If the first group is a non-empty group comprising at least one cell set to a high logic level, performing a reset write operation by applying at least one current reset pulse to at least one cell in the first group to set at least one cell in the first group to a low logic level, i.e., resetting the value comprised in this at least one cell to a low logic level,

[0051] If the second group is a non-empty group including at least one cell set to a low logic level, a set write operation is performed to set the at least one cell in the second group to a high logic level, i.e., to set the value included in the at least one cell to a high logic level.

[0052] The success or failure of the set write operation is verified via at least one set verify operation to check whether at least one cell in the second group is set to a high logic level in response to the set write operation.

[0053] Set write operations to be considered:

[0054] i) success, in response to at least one set verify operation indicating that at least one cell in the second group is set to a high logic level in response to the set write operation, and

[0055] ii) a failure, in response to at least one set verify operation indicating that at least one cell in the second group was set to a low logic level in response to the set write operation.

[0056] The success or failure of the reset write operation is verified via at least one verification operation to check whether at least one cell in the first group is set to a low logic level in response to the reset write operation. The at least one verification operation may be an individual reset write verification operation and / or one or more reset write verification operations in a cyclic reset write verification operation.

[0057] A reset write operation is therefore considered:

[0058] i) success, in response to either of a single reset write-verify operation and a cycled reset write-verify operation indicating that at least one cell in the first group is set to a low logic level in response to the reset write operation; and

[0059] ii) Failure, in response to a single reset write-verify operation and the cycled reset write-verify operations all indicating that at least one cell in the first group is set to a high logic level in response to the reset write operation.

[0060] The write operation is deemed to have failed in response to a reset write operation being deemed to have failed and / or a set write operation being deemed to have failed.

[0061] The solution described herein facilitates the realization of a single-ended PCM architecture that minimizes the effect of resistance drift of the phase change material (i.e., reduces or substantially eliminates the effect of resistance drift of the phase change material, i.e., makes it negligible), thereby reducing production costs and the area required for the PCM architecture without sacrificing its durability. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0063] Figure 1 is a graph showing an example of current distribution in a PCM cell at different times;

[0064] Figure 2 is a block diagram of a method for a write operation according to an embodiment of the present specification;

[0065] Figure 3 is a block diagram illustrating an example of a method for a write operation according to an embodiment of the present specification; and

[0066] Figure 4 is a block diagram of a method for performing a reset verification read attempt.

[0067] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.

[0068] The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

[0069] The edges of a feature drawn in a diagram do not necessarily indicate the end of the feature's extent. DETAILED DESCRIPTION

[0070] In the following description, one or more specific details will be described to provide a deeper understanding of examples of embodiments of the present specification. Embodiments can be obtained without one or more specific details, or using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not described or illustrated in detail so that certain aspects of the embodiments will not be obscured.

[0071] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic associated with the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment.

[0072] Furthermore, particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0073] The headings / references used herein are provided for convenience only, and therefore do not limit the scope of protection or the scope of the embodiments.

[0074] For simplicity and ease of explanation, throughout the specification, unless the context indicates otherwise, the same reference numerals are used to designate the same parts or elements in the various figures, and the corresponding description will not be repeated for each figure.

[0075] The architecture of a phase change memory (PCM) device includes first and second groups of cells configured to be set to a low logic level and a high logic level, respectively, in response to a write operation including a reset write operation and / or a set write operation.

[0076] It is noted that the first group of cells may also be an empty set, that is to say if the data to be written into the PCM memory consist of bits all set to a high logic level.

[0077] Similarly, it is noted that the second group of cells may also be an empty set, that is to say if the data to be written into the PCM memory consist of bits all set to a low logic level.

[0078] This write operation in the PCM device is performed under the control of a control unit which is programmed to operate as discussed below such that:

[0079] If the first group contains at least one cell set to a high logic level, performing a reset write operation by applying at least one current reset pulse to a cell in the first group to set this cell in the first group to a low logic level,

[0080] If the second group includes at least one cell that is set to a low logic level, a set write operation is performed to set this cell in the second group to a high logic level.

[0081] Figure 1 FIG20 is an example of showing current distribution, in a portion of a PCM array (i.e., a group of cells), at different times AE, the current distribution is generally referred to as IR (distribution of current flowing through (through) the cell after a reset write operation) and IS (distribution of current flowing through the cell after a set write operation), with the current measurement value on the x-axis being I (e.g., in μA) and the current distribution on the y-axis being D.

[0082] Figure 1 The current distributions IR, IS shown in are illustrated merely by way of example: other current distributions are possible without departing from the scope of the embodiment.

[0083] An exemplary current distribution IS may be a distribution of current ranges RHC,D,RHE including currents that may flow through a portion of the PCM array (i.e., a group of cells) when the states of cells included in the PCM array are set to a high logic state (e.g., set to “1”), while an exemplary current distribution IR may be a distribution of current ranges RLA,RLB including currents that may flow through the same portion of the PCM array when the states of cells included in the PCM array are set to a low logic state (e.g., set to “0”).

[0084] For example, a first current distribution ISC,D of a first current range RHC,D associated with a portion of a PCM array (i.e., a group of cells) may remain substantially stable over time after a set write operation. For example, this first current distribution ISC,D may be the same at a first instant C and a second instant D, the first instant C and the second instant D respectively indicating an instant after a given amount of time since the start of the set write operation (e.g., after a few days), and an instant just after the same set write operation (i.e., after a given amount of time that is much smaller than the amount of time considered by the first instant C), for example, a few instants after the set write operation.

[0085] In fact, the first current range RHC,D is associated with a current that may flow through a portion of the PCM array when the state of the cells comprised in the PCM array is set to a high logic state, that is to say when these cells comprised in the PCM array are in a crystalline state not affected by relaxation and are therefore characterized by a constant resistance.

[0086] In contrast, the current distribution associated with a portion of a PCM array (i.e., a group of cells) after a reset write operation may vary over time because the corresponding current ranges RLA, RLB are associated with a current that may flow through a portion of the PCM array when the state of the cells included in the PCM array is set to a low logic state, that is, when these cells included in the PCM array are in an amorphous state affected by relaxation and are therefore characterized by a resistance that increases over time.

[0087] Therefore, a second current distribution IRA of a second current range RLA associated with a portion of the PCM array after a reset write operation obtained at a third moment A may be different from a third current distribution IRB of a third current range RLB associated with the same portion of the PCM array after the same reset write operation obtained at a fourth moment B, wherein the third moment A indicates an instant after a given amount of time from the start of the reset write operation, i.e., when the rearrangement caused by the relaxation effect has a non-negligible effect on the resistance values ​​of the phase change materials of the cells included in the PCM array, and the fourth moment B indicates an instant just after the reset write operation, i.e., when the rearrangement caused by the relaxation effect is still negligible and does not affect the resistance values ​​of the phase change materials of the cells included in the PCM array, for example, a few moments after the reset write operation.

[0088] In fact, at the fourth moment B, i.e., just after the reset write operation (when the rearrangement caused by the relaxation effect is still negligible), the resistance value of the phase change material of these cells included in the PCM array reaches its minimum value, and therefore, the current that may flow through these cells at this fourth moment B may reach a higher value if compared with the current that may flow through the same cells immediately after the fourth moment B (for example, at the third moment A), because the resistance value of the phase change material increases over time in response to the relaxation effect of the amorphous state of the phase change material.

[0089] As mentioned above, the read operation in single-ended PCM is performed using a reference current, which is supplied by a reference current generator, for example. This reference current IREF is optionally:

[0090] is placed between a first current range including currents that may flow through a cell (e.g., a group of cells included in a PCM array) when the state of the cell is set to a high logic state and a second current range including currents that may flow through the same cell when the state of the cell is set to a low logic state, and

[0091] is maintained at a distance, such as an equal distance, from both the first current range and the second current range to improve reliability and facilitate retention of the non-volatile memory.

[0092] This read operation is performed, for example in response to a user request, after a given amount of time from the reset write operation (e.g., at a third time instant A), and therefore, the second current range RLA obtained at this third time instant A can be considered as one of the ranges used to define the reference current IREF for the PCM architecture. Another range that can be used to define this reference current IREF can be a substantially constant first current range RHC,D.

[0093] However, it is noted that the first current distribution ISC,D of the first current range RHC,D may vary in response to a set resistance drift that is temperature and time dependent, ie an increase in resistance of the phase change material of the cells within the PCM array.

[0094] This set resistance drift may be the result of the phase change material's composition changing in response to hot atomic diffusion or collisions with electrons at high temperatures, resulting in electromigration, thereby causing atoms of the phase change material to move and causing the composition of the phase change material to change.

[0095] This setting resistance drift causes the current flowing through the cells included in the corresponding array to decrease accordingly, so the first current range RHC,D and the first current distribution ISC,D shift toward the fourth current range RHE and the corresponding fourth current distribution ISE respectively.

[0096] Therefore, in order to avoid the read operation failure after the setting resistance drifts, another range used to define the reference current IREF may be a fourth current range RHE, so as to obtain Figure 1 The reference current IREF shown in FIG.

[0097] However, if Figure 1 As shown in FIG. 1 , the current flowing through a portion of the PCM array at the fourth time B may be higher than the selected reference current IREF, and if a read operation is performed at the fourth time B or shortly thereafter, the contents of the cells contained therein may not be read.

[0098] For example, if a read operation is performed at the fourth moment B (i.e., just after this reset write operation), when the rearrangement caused by the relaxation effect is still negligible, in order to check whether the reset write operation is successful, the read operation (in this case referred to as a reset verification operation) may fail, and therefore, the corresponding reset write operation will be considered to have failed, resulting in a large number of reset write attempts with increased current, which may damage the cell after (many) write cycles, i.e., produce open bits that affect the durability of the PCM.

[0099] A possible solution may be obtained by performing a reset verification operation or any other similar read operation performed at the fourth time B or shortly thereafter, taking into account the second reference current HIREF, which has a higher value than the reference current IREF.

[0100] Using a second reference current HIREF having a higher value than the value of the reference current IREF may affect the reliability of the read operation because the set state (i.e., high logic value) of a group of cells may be confused with the reset state (i.e., low logic value) of the same group of cells because the resistance of the phase change material of these cells may be affected by a long-term drift phenomenon when the state of these cells is the set state, which results in a reduction in the current that may flow through these cells in the set state, thereby shifting the fourth current range RHE toward the higher reference current HIREF.

[0101] It is noted that both wear of the PCM memory and high temperatures may increase such long-term drift phenomena affecting the cells in the set state.

[0102] Figure 2 is a block diagram of a method 10 for a write operation, i.e., an operation of writing data of an arbitrary number of bits (e.g., 32 bits) in a PCM memory, wherein a group of such bits (e.g., 16 bits) will be set to a high logic level (i.e., a second group), and the remaining bits (e.g., 16 bits) will be set to a low logic level (i.e., a first group), this write operation includes performing both a set write operation and a reset write operation, and includes corresponding verification operations (i.e., a set verification operation and a reset verification operation, respectively) to check the correctness of both the set write operation and the reset write operation of cells containing bits to be set to a high logic level and a low logic level, respectively, according to an embodiment of the present specification.

[0103] It should be noted that the first group of cells can consist of any number of cells (any number less than the total number of bits of the data to be written into the PCM memory), and can also be an empty set, that is, if the data to be written into the PCM memory consists of all bits set to a high logic level.

[0104] Similarly, it is noted that the second set of cells may consist of any number of cells (any number less than the total number of bits of the data to be written into the PCM memory), and may also be an empty set, that is, if the data to be written into the PCM memory consists of all bits set to a low logic level.

[0105] Method 10 is based on a balance between a separate reset-verify operation and a reset-verify operation cycle, respectively considering to minimize the impact of relaxation on the execution time of the write operation and to improve the reliability of the read operation, so as to avoid a large number of reset write attempts with increased current, i.e., current reset pulses RP, which may damage the cell after many write cycles, i.e., generate an "open bit".

[0106] Therefore, method 10 includes at least the following operations:

[0107] if the one or more cells are to be set to a low logic level, and if at least one of the one or more cells is set to a high logic level, performing 102 one or more reset write operations on at least one of the one or more cells, i.e., resetting the value contained in at least one of the one or more cells to a low logic level,

[0108] - if the one or more cells are to be set to a high logic level, and if at least one of the one or more cells is to be set to a low logic level, performing 104 one or more set write operations on the one or more cells, i.e. setting the value contained in the one or more cells to a high logic level,

[0109] - if one or more cells are to be set to a high logic level, performing 104 at least one set verification operation on this one or more cells, i.e. checking whether the cells in the second group are set to a high logic level,

[0110] - if at least one set verify operation fails, i.e. at least for cells in the second group, at least one high logic level check fails, then the corresponding set write operation is considered 104 to have failed,

[0111] - if at least one set verify operation is successful, i.e., at least one high logic level check is successful for a cell in the second group, then the corresponding set write operation is deemed 104 to be successful, e.g., the execution of the set verify operations may end in response to the first detection of a successful set verify operation without executing subsequent set verify operations,

[0112] - if one or more cells are to be set to a low logic level, performing 106 at least one separate reset verification operation on this one or more cells, i.e. checking whether the cells in the first group are set to a low logic level,

[0113] - if one or more cells are to be set to a low logic level and a previously performed reset verification operation failed, performing 108 at least one cycle of a reset verification operation on this one or more cells, i.e. using a cycle to check again whether the cells in the first group are set to a low logic level,

[0114] - if all reset verification operations in at least one individual reset verification operation and at least one cycle of reset verification operations fail, i.e., if both the performed reset verification operation and the performed reset verification operation cycle fail, i.e., the low logic level check fails at least for the cells in the first group, then the corresponding reset write operation is considered 110 to have failed,

[0115] - if at least one of the at least one individual reset verify operation and at least one cycle of the reset verify operation is successful, i.e., if at least one of the performed reset verify operation and the performed cycle of the reset verify operation is successful, i.e., the low logic level check is successful for the cells in the first group, then the corresponding reset write operation is considered 110 successful, e.g., the execution of the reset verify operation may end in response to the first detection of a successful reset verify operation without performing a subsequent reset verify operation or reset verify operation cycle, and

[0116] - If at least one of the reset write operation and the set write operation fails 110, 104, the corresponding write operation is considered failed.

[0117] After a set write operation fails, additional set write operations and set verify operations may be performed before determining that the corresponding write operation has failed.

[0118] Additional set write operations, ie, set write operations subsequent to a failed set write operation, may be performed using current set pulses of increased value.

[0119] It is noted that if each of the setup write operations performed fails, for example, a maximum number of setup write operations performed fail, method 10 can advantageously end before performing other steps (e.g., reset verification operations 106 and 108) (i.e., setup write operation step 104 can also be configured to check whether each of this maximum number of setup write operations fails, and if so, continue to end block 114).

[0120] After a reset write operation fails, additional reset write operations from separate reset-verify operations and / or reset-verify operation cycles may be performed before determining that the corresponding write operation has failed.

[0121] exist Figure 3 In the exemplary embodiment shown in , as long as the first set verification operation is deemed successful and the first reset verification operation is deemed successful, the corresponding write operation can be deemed successful without performing subsequent set verification operations and / or reset verification operations (both the separate reset verification operation 106 and the cyclic reset verification operation 108).

[0122] Therefore, method 10 may include: in response to a first set write verification operation and a first reset write verification operation indicating that the cells in the first group and the cells in the second group are set to a low logic level or a high logic level in response to the write operation, respectively, considering the write operation 110 successful, and stopping the set write verification operation and the reset write verification operation.

[0123] The steps of method 10 may be performed in a different order, for example, by first performing reset verify operation step 106, then performing reset write operation step 102, then performing set write operation step 104, then performing reset verify operation steps 106 and / or 108 again, or other orders.

[0124] The reset verification operation steps 106 and / or 108 may be performed multiple times as different steps of the method 10 . For example, the reset verification operation step 106 may be performed before the reset write operation step 102 and after the set write operation step 104 .

[0125] It is noted that it may be advantageous to perform the set write operation step 104 after the reset write operation step 102 and before the reset verification operation steps 106 and / or 108 to benefit from the delay introduced by this set write operation between the reset write operation and the reset verification operation, which delay depends on the time taken to perform the set write operation in this set write operation step 104, thereby facilitating a successful reset verification operation in this reset verification operation step 106 and / or 108 because the resistance of the cell subjected to this reset write operation in this reset write operation step 102 increases in response to partial depletion of the relaxation phenomenon.

[0126] It may be advantageous to perform the reset verification operation step 106 before the reset write operation step 102 so that if the cells to be set to a low logic level in this reset write operation step 102 have already been set to this low logic level, the reset write operation step 102 may not be performed.

[0127] Similarly, it may be advantageous to perform a set verify operation (within a step referred to as 104) prior to a set write operation so that if a cell to be set to a high logic level in this set write operation has already been set to this high logic level, the set write operation may not be performed.

[0128] It may be advantageous to perform a reset verification operation step 106 (duration T1) including at least one separate reset verification operation before a reset verification operation step 108 (duration T2, which is longer than duration T1) including at least one cycle of a reset verification operation, because most reset write operations will end in response to performing, for example, a reset verification operation step 106 that only includes one or more separate reset verification operations, thereby resulting in a reduction in the execution time required for this reset write operation.

[0129] In summary, the method 10 may include performing at least one separate reset write-verify operation 106 prior to the cyclic reset write-verify operation 108 .

[0130] Can exist with Figure 2 Other steps that differ from those reported in Figure 3 Additional steps 112 or 116 are described.

[0131] If a successful separate reset-verify operation 106 has already been performed on the same cell, then the looped reset-verify operation 108 may not be performed.

[0132] In summary, in the solution disclosed herein, a method 10 for performing a write operation in a phase change memory (PCM) device is disclosed. The PCM device includes a first group of cells (which may also be an empty set) and a second group of cells (which may also be an empty set), which are configured to be set to a low logic level and a high logic level, respectively, in response to a write operation including a set write operation and / or a reset write operation, wherein the method 10 includes:

[0133] If the first group includes at least one cell set to a high logic level, performing 102 a reset write operation to set the at least one cell in the first group to a low logic level, thereby resetting the value of the at least one cell in the first group to a low logic level,

[0134] If the second group includes at least one cell set to a low logic level, performing 104 a set write operation to set the at least one cell in the second group to a high logic level, thereby setting the value of the at least one cell in the second group to a high logic level,

[0135] verifying the success or failure of the set write operation via at least one set verify operation to check whether at least one cell in the second group is set to a high logic level in response to the set write operation, i.e., whether the performed set write operation is successful,

[0136] Consider 104 to set the write operation:

[0137] i) success, in response to at least one set verify operation indicating that at least one cell in the second group is set to a high logic level in response to the set write operation, and

[0138] ii) a failure, in response to at least one set verify operation indicating that at least one cell in the second group is set to a low logic level in response to a set write operation;

[0139] verifying 110 the success or failure of the reset write operation via at least one verification operation selected from a separate 106 reset write verification operation and a cyclic 108 reset write verification operation to check whether at least one cell in the first group is set to a low logic level in response to the reset write operation, i.e., whether the performed reset write operation is successful,

[0140] Consider 110 reset write operation:

[0141] i) success, in response to either of the single 106 reset write verify operation and the cyclic 108 reset write verify operation indicating that at least one cell in the first group is set to a low logic level in response to the reset write operation, and

[0142] ii) a failure in response to both the single 106 reset write verify operation and the cyclic 108 reset write verify operation indicating that at least one cell in the first group is set to a high logic level in response to the reset write operation; and

[0143] In response to the reset write operation being deemed failed 110 and / or the set write operation being deemed failed 104, the write operation is deemed to have failed.

[0144] Figure 3 is a block diagram illustrating an example of a method 10 for a write operation according to an embodiment of the present specification.

[0145] The method 10 starts with a start write operation block 100 configured to receive an indication including instructions for a write operation (ie, for writing data consisting of a given number of bits in a memory location) and send a start command SC to a first reset verification operation block 106a1.

[0146] The first reset verification operation block 106a1 is configured to receive a start command SC, and in response to its reception, it is also configured to perform a read operation (which is referred to as a reset verification operation) on a cell of a memory location containing a bit that will be set to a low logic level in a write operation, and provide a result R1 of this read operation to the first reset verification operation check block 106b1.

[0147] The first reset verification operation check block 106 b 1 is configured to receive the results R1 of the read operation and check whether all the results R1 of the read operation are set to a low logic level.

[0148] If the check is successful, that is, if all the results R1 of the read operation are set to a low logic level, the first reset verification operation check block 106b1 is configured to send a success check signal Y to the end reset block 116a, otherwise, if the check is unsuccessful, that is, if at least one of the results R1 of the read operation is set to a high logic level, the first reset verification operation check block 106b1 is configured to send an unsuccessful check signal N to the first reset write operation block 102a.

[0149] The end reset block 116a is configured to receive a success check signal Y from the first reset verification operation check block 106b1, and in response to its reception, it is also configured to set the value of the end reset variable ER (for example, by writing its value to a specific memory location) so as to record that the reset verification operation for each cell of the memory location containing a bit to be set to a low logic level is successful, and send an end signal ES1 to the set write operation block 104.

[0150] The first reset write operation block 102a is configured to receive the unsuccessful check signal N from the first reset verification operation check block 106b1, and in response to its reception, it is also configured to perform a reset write operation on each cell of the memory location containing a bit to be set to a low logic level in the write operation. This reset write operation is performed using a first current reset pulse RP1, which has a value of, for example, 240 μA (microamperes): of course, this value is merely exemplary and not restrictive.

[0151] The reset write operation block 102 may be configured to perform a reset write operation on each cell of a memory location that contains a bit to be set to a low logic level in a write operation and whose value is currently set to a high logic level.

[0152] The first reset write operation block 102 a is also configured to send an end signal ES2 to the set write operation block 104 after performing the reset write operation.

[0153] The set write operation block 104 is configured to receive end signals ES1, ES2 from the end reset block 116a or the first reset write operation block 102a, and in response to its reception, it is also configured to perform a set write operation on each cell of the memory location containing a bit to be set to a high logic level in the write operation, and send an end signal ES3 to the end reset check block 116b.

[0154] This setting write operation block 104 may be configured to also perform a setting verification operation to check whether the performed setting write operation ends successfully.

[0155] The setting write operation and the setting verification operation may be performed cyclically. For example, the following operations may be performed:

[0156] - performing a first set verification operation to check whether at least one of the cells to be set to a high logic level is set to a low logic level,

[0157] - if the first set verify operation fails, performing a first set write operation by providing a first set pulse to the at least one cell,

[0158] - performing a second set verification operation to check whether the at least one cell is set to a high logic level, and

[0159] - If the second set verify operation fails, performing a second set write operation by providing a second set pulse (eg, having a higher value than the first set pulse) to the at least one cell.

[0160] The set verify operation and the corresponding set write operation may be repeated for at least one cell a given number of times until:

[0161] - the set verify operation is deemed successful, and therefore the set write operation performed is deemed successful; or

[0162] - The number of repetitions of this setup verification operation and the corresponding setup write operation reaches a given maximum number of repetitions, so the executed setup write operation is considered to have failed.

[0163] If the number of repetitions of the set verification operation and the set write operation reaches this given maximum number of repetitions, this set write operation block 104 can also be configured to set the value of the failure variable F (for example, by writing its value to a specific memory location or, for example, sending an alarm to a microprocessor, microcontroller, logic circuit, etc.) to record that the write operation of the corresponding unit is considered to have failed, and send this failure variable F to the end write block 114 (described below).

[0164] The set write operation block 104 may be configured to perform a set write operation on each cell of a memory location containing a bit to be set to a high logic level in a write operation, and the value of the bit is currently set to a low logic level.

[0165] The end reset check block 116b is configured to receive the end signal ES3 and check whether the end reset variable ER is set, for example, by reading its value in a specific memory location and comparing the value with an expected reference value (for example, a logic value set to a high logic level).

[0166] If the check is successful, that is, the value of the end reset variable ER is equal to the reference value, the end reset check block 116b is configured to send a success check signal Y to the end write block 114, otherwise, if the check is unsuccessful, that is, the value of the end reset variable ER is different from the reference value, the end reset check block 116b is configured to send an unsuccessful check signal N to the second reset verification operation block 106a2.

[0167] The end write block 114 is configured to receive the success check signal Y or the failure signal F and signal the end of the write operation to, for example, a microprocessor, a microcontroller, a logic circuit, etc.

[0168] The end write block 114 may be configured to send an indication to, for example, a microprocessor, microcontroller, logic circuit, etc., including the result of the write operation (eg, failure / success), an indication of cells having incorrect values ​​in the event of a failure, and the like.

[0169] The second reset verification operation block 106a2 is configured to receive an unsuccessful check signal N from the end reset check block 116b, and in response to its reception, it is also configured to perform a read operation (which is referred to as a reset verification operation) on a cell of a memory location containing a bit that will be set to a low logic level in a write operation, and provide a result R2 of this read operation to the second reset verification operation check block 106b2.

[0170] It should be noted that this second reset verification operation block 106a2 can be configured to be executed after the set write operation block 104, that is, after the set write operation and the set verification operation which can also be cycled as described above, so as to introduce a delay between the reset write operation performed by the first reset write operation block 102a and the subsequent reset verification operation performed by this reset verification operation block 106a2.

[0171] Therefore, this delay may depend on the time taken to perform the operations in the set write operation block 104, i.e., the time taken by the set write operation and the set verification operation, thereby facilitating a successful reset verification operation because the resistance of the cell subjected to this reset write operation increases in response to the relaxation phenomenon being partially depleted.

[0172] The second reset verification operation check block 106 b 2 is configured to receive the results R2 of the read operation and check whether all the results R2 of the read operation are set to a low logic level.

[0173] If the check is successful, that is, if all the results R2 of the read operation are set to a low logic level, the second reset verification operation check block 106b2 is configured to send a success check signal Y to the end write block 114, otherwise, if the check is unsuccessful, that is, if at least one of the results R2 of the read operation is set to a high logic level, the second reset verification operation check block 106b2 is configured to send an unsuccessful check signal N to the second reset write operation block 102b.

[0174] The second reset write operation block 102b is configured to receive the unsuccessful check signal N from the second reset verification operation check block 106b2, and in response to its reception, it is also configured to perform a reset write operation on each cell of the memory location containing a bit to be set to a low logic level in the write operation. This reset write operation is performed using a second current reset pulse RP2, which has a value of, for example, 270μA (microamperes): Of course, this value is also merely exemplary and non-limiting.

[0175] The value of the second current reset pulse RP2 may be greater than the value of the first current reset pulse RP1.

[0176] The second reset write operation block 102 b is further configured to send an end signal ES4 to the first reset verification operation loop block 108 a 1 after performing the reset write operation.

[0177] The first reset verification operation loop block 108a1 is configured to receive the end signal ES4, and in response to its reception, it is also configured to perform one or more read operations (e.g., from a single read operation to hundreds of read operations, referred to as reset verification operations) on the cells of the memory locations containing the bits that will be set to a low logic level in the write operation, and provide a verification success variable VS1 to the first reset verification operation loop check block 108b1.

[0178] This verification success variable VS1 is set to record that at least one of the one or more reset verification operations for each cell of the memory location containing a bit to be set to a low logic level is successful, that is, if at least one of the one or more reset verification operations verifies that all results of the read operations associated with this at least one reset verification operation are set to a low logic level.

[0179] In order to reduce the execution time of the write operation, when the first reset verification operation is successful, the cycle of the reset verification operation can be ended without performing a subsequent reset verification operation and setting the verification success variable VS1 thereafter.

[0180] It should be noted that the looping performed in the first reset verify operation loop block 108a1 (and also in the reset verify operation loop blocks generally referred to by the reference numeral 108a described below) may introduce additional delays between consecutive reset verify operations, for example, if the duration of the delay introduced by the set write operation block 104 is insufficient and additional time may be helpful.

[0181] The first reset verification operation loop check block 108b1 is configured to receive the verification success variable VS1 and check whether the verification success variable VS1 is set, for example, by comparing its value with an expected reference value (for example, a logic value set to a high logic level).

[0182] If the check is successful, that is, if the value of the verification success variable VS1 is equal to the reference value, the first reset verification operation cycle check block 108b1 is configured to send a success check signal Y to the end write block 114, otherwise, if the check is unsuccessful, that is, if the value of the verification success variable VS1 is different from the reference value, the first reset verification operation cycle check block 108b1 is configured to send an unsuccessful check signal N to the third reset write operation block 102c.

[0183] The third reset write operation block 102c is configured to receive the unsuccessful check signal N from the first reset verification operation cycle check block 108b1, and in response to its reception, it is also configured to perform a reset write operation on each cell of the memory location containing a bit to be set to a low logic level in the write operation. This reset write operation is performed using a third current reset pulse RP3, which has a value of, for example, 300μA (microamperes): Of course, this value is again merely exemplary and non-limiting.

[0184] The value of the third current reset pulse RP3 may be greater than the value of the second current reset pulse RP2.

[0185] The value of the third current reset pulse RP3 may be greater than the value of the first current reset pulse RP1.

[0186] Thus, method 10 may include, in response to the reset write operation being deemed to have failed, repeating the reset write operation using current reset pulses of increasing values ​​(eg, RP2 or RP3 ).

[0187] The third reset write operation block 102c is further configured to send an end signal ES5 to the second reset verification operation loop block 108a2 after performing the reset write operation.

[0188] The second reset verification operation loop block 108a2 is configured to receive the end signal ES5, and in response to its reception, it is also configured to perform one or more read operations (e.g., from a single read operation to hundreds of read operations, referred to as reset verification operations) on the cells of the memory locations containing the bits that will be set to a low logic level in the write operation, and provide a verification success variable VS2 to the second reset verification operation loop check block 108b2.

[0189] This verification success variable VS2 is set to record that at least one of the one or more reset verification operations for each cell of the memory location containing a bit to be set to a low logic level is successful, that is, if at least one of the one or more reset verification operations verifies that all results of the read operations associated with this at least one reset verification operation are set to a low logic level.

[0190] The second reset verification operation loop check block 108b2 is configured to receive the verification success variable VS2 and check whether the verification success variable VS2 is set, for example, by comparing its value with an expected reference value.

[0191] If the check is successful, that is, if the value of the check success variable VS2 is equal to the reference value, the second reset verification operation loop check block 108b2 is configured to send a successful check signal Y to the end write block 114, otherwise, if the check is unsuccessful, that is, if the value of the check success variable VS2 is different from the reference value, the second reset verification operation loop check block 108b2 is configured to send an unsuccessful check signal N to the optional error correction block 112.

[0192] It should be noted that if the error correction block 112 does not exist, the unsuccessful check signal N is directly provided to the failure block 110 .

[0193] The error correction block 112 is configured to receive the unsuccessful check signal N to count the number of cells currently set to an erroneous logic level (i.e., the number of cells in which a set write operation or a reset write operation fails), and to check whether the number of cells currently set to an erroneous logic level is less than or equal to the number of bits that can be corrected using an error detection code, for example, by a parity check bit, an error correction bit (ECC), an error detection bit (EDC), a cyclic redundancy check (CRC), and the like.

[0194] If the checking step of the error correction block 112 is successful, that is, if the number of cells currently set to the wrong logic level is less than or equal to the number of bits that can be corrected using the error detection code, the error correction block 112 is configured to send a success check signal Y to the end write block 114, and the corresponding write operation is successfully ended.

[0195] Otherwise, if the checking step of the error correction block 112 is unsuccessful, that is, if the number of cells currently set to the wrong logic level is greater than the number of bits that can be corrected using the error detection code, the error correction block 112 is configured to send an unsuccessful check signal N to the fail block 110.

[0196] Note that the number of cells currently set to an incorrect logic level will be calculated taking into account both cells that were not correctly set to a high logic level in response to a set write operation and cells that were not correctly set to a low logic level in response to a reset write operation.

[0197] This method 10 may be configured to perform the operation of the error correction block 112 before the value of the fail variable F is set by the set write operation block 104 .

[0198] In this case, if the number of repetitions of the set verification operation and the set write operation reaches a given maximum number of repetitions, the set write operation block 104 may be configured to perform the operation of the error correction block 112 before setting the value of the fail variable F, and:

[0199] - if the number of cells currently set to an erroneous logic level (i.e., the number of cells in the second group set to a low logic level in response to the set write operation) is less than or equal to the number of bits that can be corrected using the error detection code, then this set write operation block 104 may also be configured to send an end signal ES3 to the end reset check block 116b; and

[0200] -If the number of cells currently set to an erroneous logic level is greater than the number of bits that can be corrected using the error detection code, this set write operation block 104 can also be configured to set the value of a fail variable F (as described above) and send this fail variable F to the end write block 114.

[0201] Advantageously, in order to avoid a large number of reset write attempts at increasing current, which may damage the cells after (many) write cycles, i.e., produce open bits that affect the durability of the PCM, even if the reset verification operation (i.e., both the reset verification operation alone and the reset verification operation cycle) fails, but the error correction block 112 detects that the number of cells currently set to the wrong logic level is less than or equal to the number of bits that can be corrected using the error detection code, the data written in the cells of the selected memory location can still be considered correct.

[0202] In order to prioritize the reliability of data written to a memory location over the durability of the PCM, the data written to the cells at the selected memory location may still be considered correct if both the set verification operation and the reset verification operation are successfully completed and the error correction block 112 detects that the number of cells currently set to an erroneous logic level is less than or equal to the number of bits that can be corrected using the error detection code.

[0203] The failure block 110 is configured to receive the unsuccessful check signal N from the error correction block 112 to set the value of the failure variable F (for example, by writing its value to a specific memory location or, for example, sending an alarm to a microprocessor, a microcontroller, a logic circuit, etc.) so as to record that the write operation of the corresponding unit is considered to have failed, and send this failure variable F to the end write block 114.

[0204] As previously mentioned, the blocks of method 10 may be considered in a different order.

[0205] For example, in the first exemplary embodiment, the first reset write operation block 102a can be considered as the first block after the start write operation block 100, and the set write operation block 104, the first reset verification operation block 106a1 and the first reset verification operation check block 106b1 can be considered as after this first reset write operation block 102a.

[0206] In the first exemplary embodiment provided, since the first reset write operation block 102a can provide its output, for example, directly to the second reset verification operation block 106a2, and the first reset verification operation check block 106b1 can provide a success check signal Y to the end write block 114, the end reset block 116a and the end reset check block 116b can be removed.

[0207] therefore, Figure 3 Some of the blocks illustrated in may not be present in method 10, for example, by removing blocks 116a and 116b and / or one or more of the blocks generally indicated by 106 and / or 108 and / or the error correction block 112 as explained above, and / or additional blocks may be added to method 10, for example, in the second exemplary embodiment, a fourth reset write operation block 102d, a third reset verification operation cycle block 108a3 and a third reset verification operation cycle check block 108b3 may be added between block 108b2 and block 112.

[0208] It is noted that by using a reset verification operation cycle instead of a separate reset verification operation for one or more cells to be set to a low logic level, the probability of having a second current reset pulse RP2 and / or a third current reset pulse RP3 can be reduced by a large multiple relative to known solutions, e.g. Figure 3 In the structure disclosed in the exemplary embodiment shown in , the probability of having the third current reset pulse RP3 can be reduced by more than about 300 times relative to the known solution.

[0209] Figure 4 is a block diagram of a method 108a for performing a reset verify read attempt.

[0210] A method for performing a reset verify read attempt, generally referred to as 108a, may be characterized using a maximum count variable MC and a time delay variable TD.

[0211] This method 108a can be used to implement different reset verification operation loop blocks, for example, both the first reset verification operation loop block 108a1 and the second reset verification operation loop block 108a2, by setting the values ​​of the maximum count variable MC and the time delay variable TD for each block. It should be noted that different reset verification operation loop blocks can have the same or different maximum count variable values ​​MC and / or the same or different time delay variable values ​​TD.

[0212] Therefore, the method 10 may include multiple cycles of the cyclic reset write-verify operation 108 with different upper count values ​​MC.

[0213] Similarly, method 10 may include multiple cycles of a cyclic reset write verification operation with different total times, i.e., the duration of the cyclic reset write verification operation, TD*MD. Therefore, method 10 may include multiple cycles of a cyclic reset write verification operation with different time delay values ​​TD.

[0214] The method 108 a starts in a start-reset verification loop block 200 , which is configured to receive an end signal ES from any of the previously described blocks and send a start instruction SI to a counter reset block 202 .

[0215] The counter reset block 202 is configured to receive a start instruction SI, and in response to the receipt thereof, it is configured to reset the value of the counter to a known value, for example, to zero, and send an end counter reset signal ERC to the verification success reset block 204 .

[0216] The verification success reset block 204 is configured to receive the end counter reset signal ERC, and in response to receiving it, it is also configured to reset the value of the verification success variable VS to a known value, such as zero, and send an end verification reset ERV signal to the maximum count check block 206.

[0217] It is noted that even the blocks of the method 108a may be considered in a different order, for example, the counter reset block 202 and the verification success reset block 204 may be interchanged.

[0218] The maximum count check block 206 is configured to receive an end verification reset ERV signal and / or an end count EC signal, and in response to receiving it, it is also configured to retrieve the value of a corresponding maximum count variable MC, for example from a variable, a memory location, a file, etc., and check whether the value of the counter (i.e., the number of reset verification read attempts performed) is equal to the value of this corresponding maximum count variable MC (i.e., the maximum number of reset verification read attempts allowed).

[0219] Note that if all reset verify read attempts (up to the maximum number of reset verify read attempts allowed) fail, then the reset verify operation cycle is considered to have failed.

[0220] If the check is successful, that is, if the value of the counter is equal to the value of the corresponding maximum count variable MC, the maximum count check block 206 is configured to send a successful check signal Y to the end reset verification cycle block 218, otherwise, if the check is unsuccessful, that is, if the value of the counter is different from the value of the corresponding maximum count variable MC, the maximum count check block 206 is configured to send an unsuccessful check signal N to the reset verification read block 208.

[0221] The corresponding maximum count variable MC may be programmable and set to 100, for example.

[0222] It should be noted that the method 108a performs a number of reset verification attempts comprised in the range from 1 to the value of the maximum count variable MC. If no successful reset verification attempt occurs in the number of attempts equal to the value of the maximum count variable MC, the method 108a ends and the reset verification operation cycle is considered to have failed.

[0223] In summary, method 10 may include:

[0224] - Set the optional programmable up-count value MC for the reset write-verify operation for this cycle, and

[0225] - In response to this up-count value MC being reached when the reset write verification operation of the cycle does not indicate that at least one cell in the first group is set to a low logic level in response to the reset write operation (i.e., when the previous reset write operation was not successfully performed), it is considered 110 that the reset write verification operation of this cycle has failed.

[0226] The end reset verification loop block 218 is configured to receive the success check signal Y and / or the verification success variable VS and provide the verification success variable VS as an output.

[0227] If the end reset verification loop block 218 does not receive a verification success variable VS, this block 218 may be configured to provide as an output the verification success variable VS set to a default value (eg, zero).

[0228] If the end reset verification loop block 218 does not receive a verification success variable VS, this block 218 may be configured to provide as output a verification success variable VS retrieved, for example, from a variable, memory location, file, etc., where this verification success variable VS is stored.

[0229] If the value of the verify success variable VS provided as output is equal to the reset value associated with this verify success variable VS, then a plurality of reset verify read attempts (ie, a reset verify operation cycle) is considered to have failed, otherwise, the reset verify operation cycle is considered to have succeeded.

[0230] The reset verification read block 208 is configured to receive the unsuccessful check signal N from the maximum count check block 206, and in response to its reception, it is also configured to perform a read operation (referred to as a reset verification operation) on the cells of the memory locations containing the bits that will be set to a low logic level in the write operation, and provide the result R of this read operation to the reset verification check block 210.

[0231] The reset verification check block 210 is configured to receive the results R of the read operation and check whether all the results R of the read operation are set to a low logic level.

[0232] If the check is successful, that is, if all the results R of the read operation are set to a low logic level, the reset verification check block 210 is configured to send a successful check signal Y to the verification success setting block 216, otherwise, if the check is unsuccessful, that is, if at least one of the results R of the read operation is set to a high logic level, the reset verification check block 210 is configured to send an unsuccessful check signal N to the delay block 212.

[0233] The verification success setting block 216 is configured to receive the success check signal Y from the reset verification check block 210, and in response to its reception, it is also configured to set the value of the verification success variable VS to a value different from the reset value, for example, to a high logic level, i.e., "1", indicating that the reset verification operation cycle is successful, and send this verification success variable VS to the end reset verification cycle block 218.

[0234] The delay block 212 is configured to receive the unsuccessful check signal N from the reset verification check block 210, and in response to its reception, it is also configured to retrieve the value of the corresponding time delay variable TD, i.e., indicating the time delay between subsequent reset verification operation attempts, for example from a variable, a memory location, a file, etc., and wait for the amount of time indicated in this time delay variable TD.

[0235] The corresponding time delay variable TD may be programmable and set to, for example, 1 μs.

[0236] It is to be noted that this time delay variable TD may be set in order to reduce the influence of the relaxation phenomenon, since after this time delay variable TD the relaxation phenomenon may be partially exhausted.

[0237] As previously noted, method 108a performs a number of reset verification attempts comprised in the range from 1 to the value of a maximum count variable MC, so that if a delay equal to the time delay TD is introduced between two reset verification attempts, the maximum execution time of the reset verification operation cycle is approximately MC*TD, for example, if MC=100 and TD=1 μs, the maximum execution time is approximately 100 μs.

[0238] Therefore, if all reset-verify-read attempts within a time window equal to approximately MC*TD fail, then the reset-verify operation cycle may be considered to have failed.

[0239] In summary, the method 10 described herein may include:

[0240] - Sets an optional programmable time delay TD between reset-verify operations of subsequent cycles, and

[0241] -When the total duration of the reset write verify operation in response to this cycle is reached without the reset write verify operation of the cycle indicating that at least one cell in the first group is set to a low logic level in response to the reset write operation (i.e., without a previous reset write operation being successfully performed), it is considered that 110 the reset write verify operation of this cycle has failed.

[0242] The optimal value of this time delay variable TD can be obtained empirically.

[0243] Note that reset verify attempts performed after a given reset verify attempt have a reduced probability of failure because the probability of a reset verify operation (ie, a read operation immediately following a write operation) failing decreases over time according to a relaxation phenomenon.

[0244] Therefore, the time delay TD may be selected by considering a desired balance between the maximum execution time of a reset verify operation cycle and the probability of a reset verify operation failure (eg, obtained by empirically testing that the failure probability decreases over time due to relaxation phenomena).

[0245] The delay block 212 is further configured to provide an end delay ED signal indicating the end of the wait to the counter block 214 .

[0246] The counter block 214 is configured to receive the end delay ED signal and in response to receipt thereof it is further configured to add, for example, a unit value to the value of the counter and send an end count EC signal to the maximum count check block 206 .

[0247] The methods 10 and 108a described herein may be implemented using one or more computer products loadable in the memory of at least one computer and comprising portions of software code for executing the previously described stages.

[0248] The solution described herein facilitates implementation of a method for reducing the failure probability of a reset verify operation using a balance between a separate reset verify operation and cycling of the reset verify operation, which considers respectively minimizing the effect of relaxation on the write operation time and improving the reliability of the read operation to avoid a large number of reset write attempts with increased current, which may damage the cell after many write cycles.

[0249] Thus, the solution described herein facilitates a single-ended PCM architecture that minimizes (ie, reduces or substantially eliminates) the effects of resistance drift of the phase change material, thereby reducing production costs and the area required for the PCM architecture without sacrificing the durability of the PCM architecture.

[0250] Furthermore, the solution described herein facilitates achieving an ideal balance between reliability and execution time by balancing the number of reset-verify operation cycles and separate reset-verify operations, wherein this reset-verify operation cycle can also reduce the probability of having a second and / or third current reset pulse, thereby improving the durability of the PCM and avoiding open bits.

[0251] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described merely by way of example, without departing from the scope of the embodiments.

[0252] The scope of protection is determined by the appended claims.

Claims

1. A method of performing a write operation in a phase change memory device, the phase change memory device comprising a first group of cells and a second group of cells, the first group of cells and the second group of cells being configured to be set to a low logic level and a high logic level, respectively, in response to a write operation, the write operation comprising a reset write operation or a set write operation; The method comprises: If the first group of cells includes at least one cell set to a high logic level, performing a reset write operation by applying at least one current reset pulse to the at least one cell in the first group of cells to set the at least one cell in the first group of cells to a low logic level; If the second group of cells includes at least one cell set to a low logic level, performing a set write operation to set the at least one cell in the second group of cells to a high logic level; verifying success or failure of the set write operation via at least one set verify operation to check whether the at least one cell in the second group of cells is set to a high logic level in response to the set write operation; Consider the setup write operation: i) success, in response to the at least one set verify operation indicating that the at least one cell in the second group of cells is set to a high logic level in response to the set write operation; and ii) fails, in response to the at least one set verify operation indicating that the at least one cell in the second group of cells is set to a low logic level in response to the set write operation; verifying success or failure of the reset write operation via at least one verification operation selected from a separate reset write verification operation and a cyclic reset write verification operation to check whether the at least one cell in the first group of cells is set to a low logic level in response to the reset write operation; Consider the reset write operation: i) success, in response to either of a single reset write-verify operation and a cycled reset write-verify operation indicating that the at least one cell of the first group of cells is set to a low logic level in response to the reset write operation; and ii) failure, in response to both the reset write-verify operation alone and the cycled reset write-verify operations indicating that the at least one cell in the first group of cells is set to a high logic level in response to the reset write operation; and In response to the reset write operation being deemed to have failed and / or the set write operation being deemed to have failed, the write operation is deemed to have failed.

2. The method according to claim 1, further comprising: In response to a first reset write verify operation indicating that the at least one cell in the first group of cells is set to a low logic level in response to the reset write operation, the reset write operation is deemed successful and verification of success or failure of the reset write operation is stopped.

3. The method according to claim 1, further comprising: At least one separate reset write-verify operation is performed before the reset write-verify operation of any cycle, and / or at least one reset write operation is performed before any set write operation.

4. The method according to claim 1, further comprising: In response to a corresponding up-count value that is preferably programmable being reached without the cycled reset write-verify operation indicating that the at least one cell in the first group of cells is set to a low logic level in response to the reset write operation, the cycled reset write-verify operation is deemed to have failed.

5. The method according to claim 4, further comprising: A plurality of cycles of a cyclic reset write verify operation having different corresponding up-count values ​​of the cyclic reset write verify operation.

6. The method according to claim 1, further comprising: The reset write verify operation in response to the cycle is considered to have failed if the corresponding total duration of the reset write verify operation in response to the cycle is reached without the reset write verify operation indicating that the at least one cell in the first group of cells is set to a low logic level in response to the reset write operation.

7. The method according to claim 6, wherein: In case the reset write verification operation of the cycle includes a cycle of separate reset verification operations, the method further comprises: setting a time delay value between the separate reset verification operations in the cycle.

8. The method according to claim 6, further comprising: Multiple cycles of the cyclical reset write-verify operation having different total durations of the cyclical reset write-verify operation.

9. The method according to claim 1, further comprising: counting the number of cells included in the first group of cells that are set to a high logic level in response to the reset write operation and the number of cells included in the second group of cells that are set to a low logic level in response to the set write operation, checking whether the result of the counting operation is less than or equal to the number of bits that can be corrected by the error detection code, and The result of the check is considered successful if the result of the counting operation is less than or equal to the number of bits that can be corrected, or is considered unsuccessful if the result of the counting operation is greater than the number of bits that can be corrected.

10. The method according to claim 1, further comprising: In response to each of the at least one set verify operation indicating that the at least one cell in the second group of cells is set to a low logic level in response to the set write operation, the write operation is deemed to have failed and further operations are ceased.

11. The method of claim 9 , wherein in response to each of the at least one set verification operation indicating that the at least one cell in the second group of cells is set to a low logic level in response to the set write operation, the counting operation, the checking operation, and the considering operation are performed, and if the checking operation is considered unsuccessful, further operations are stopped and the write operation is considered to have failed.

12. The method of claim 9, wherein the write operation is deemed successful in response to: The reset write operation is deemed successful, and the set write operation is deemed successful; or The check operation is considered successful regardless of the result of the reset write operation and the result of the set write operation.

13. The method according to claim 1, further comprising: in response to the reset write operation being deemed to have failed, repeating the reset write operation using a current reset pulse of an increased value; or In response to the set write operation being deemed to have failed, the set write operation is repeated with the current set pulse of an increased value.

14. A phase change memory device comprising a first group of cells and a second group of cells, the first group of cells and the second group of cells being configured to be set to a low logic level and a high logic level, respectively, in response to a write operation, the phase change memory device being configured to implement the method according to claim 1.

15. A computer program product capable of being loaded into a control unit of a phase change memory device, the phase change memory device comprising a first group of cells and a second group of cells, the first group of cells and the second group of cells being configured to be set to a low logic level and a high logic level, respectively, the computer program product comprising a portion of software code, the portion of the software code being configured to cause the phase change memory device to implement in response to the computer program product being run in the control unit of the phase change memory device The method according to claim 1.

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