Chip packaging structure, chip packaging method, electronic equipment and preparation method thereof

Abstract

The invention discloses a chip packaging structure, a chip packaging method, electronic equipment and a preparation method thereof, and relates to the technical field of chip packaging, and the chip packaging structure comprises a packaging substrate which is provided with a first surface and a second surface which are opposite to each other; a first chip fixed on the first surface; the heat dissipation assembly is provided with a heat conduction top and a heat conduction side wall, one end, deviating from the heat conduction top, of the heat conduction side wall penetrates through the packaging substrate from the first surface and is exposed out of the second surface, and a containing cavity is formed among the heat conduction top, the heat conduction side wall and the first surface; the first chip is located in the accommodating cavity, and the surface, deviating from the packaging substrate, of the first chip is in thermal contact with the heat conduction top.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a chip packaging structure, a chip packaging method, an electronic device and a preparation method thereof. Background Art

[0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, which brings great convenience to people's daily life and work, and becomes an indispensable tool for people today. The core structure of electronic devices to realize various functions is the chip. The chip needs to be packaged and protected during use to prevent the chip from being damaged by external forces, and it can also facilitate the circuit connection between the chip and the external circuit.

[0003] At present, in the existing chip packaging structure, the chip is simply packaged and protected by a packaging substrate, and the heat dissipation effect of the chip packaging structure is poor. Summary of the invention

[0004] In view of the above problems, the present application provides a chip packaging structure, a chip packaging method, an electronic device and a preparation method thereof, which can improve the heat dissipation effect of the chip packaging structure. The specific scheme is as follows:

[0005] A first aspect of the present application provides a chip packaging structure, comprising:

[0006] A packaging substrate having a first surface and a second surface opposite to each other;

[0007] a first chip fixed to the first surface;

[0008] The heat dissipation component comprises a heat-conducting top and a heat-conducting side wall. An end of the heat-conducting side wall facing away from the heat-conducting top penetrates the packaging substrate from the first surface and is exposed on the second surface. An accommodating cavity is formed between the heat-conducting top, the heat-conducting side wall and the first surface. The first chip is located in the accommodating cavity, and the surface of the first chip facing away from the packaging substrate is in thermal contact with the heat-conducting top.

[0009] Optionally, in the above chip packaging structure, an auxiliary component is disposed on the second surface, and the auxiliary component is in thermal contact with an end portion of the heat dissipation component exposed from the second surface.

[0010] Optionally, in the above chip packaging structure, the heat dissipation component has a first microchannel inside, and the auxiliary component has a second microchannel; the second microchannel is connected to the first microchannel, and there is a flowable heat-conducting medium in the second microchannel and the first microchannel.

[0011] Optionally, in the above chip packaging structure, the auxiliary component has a target port, the target port is used to connect to a target component on the circuit board, and the target component is at least used to provide power for the flow of the heat-conducting medium.

[0012] Optionally, in the above chip packaging structure, a surface of the first chip facing away from the packaging substrate has a concave structure;

[0013] The inner surface of the heat-conducting top has a convex structure arranged opposite to the concave structure;

[0014] At least a portion of the protruding structure is inserted into the corresponding recessed structure to increase the thermal contact area.

[0015] Optionally, in the above chip packaging structure, the packaging substrate has a first area and a second area surrounding the first area, the first area is located in the accommodating cavity, and the second area is located outside the accommodating cavity;

[0016] A first conductive hole penetrating the package substrate is provided in the first region, and a second conductive hole penetrating the package substrate is provided in the second region; solder balls are respectively connected to ends of the first conductive hole and the second conductive hole facing the second surface, and the solder balls are used to connect to an external circuit;

[0017] Wherein, the first chip is electrically connected to the end of the first conductive hole facing the first surface;

[0018] A second chip is also arranged on a side of the heat-conducting top facing away from the first chip, and the second chip is electrically connected to an end of the second conductive hole facing the first surface.

[0019] Optionally, in the above chip packaging structure, the packaging substrate includes: a first stacking layer, a central layer and a second stacking layer stacked in sequence;

[0020] The first conductive hole includes: a first through hole passing through the central layer; a metal layer covering the side wall of the first through hole; an insulating medium filling the first through hole; and a heat conducting layer located between the insulating medium and the metal layer.

[0021] A second aspect of the present application provides an electronic device, including:

[0022] Circuit boards;

[0023] A chip packaging structure fixed on a circuit board, the chip packaging structure comprising: a packaging substrate having a first surface and a second surface opposite to each other; a first chip fixed on the first surface; a heat dissipation component, the heat dissipation component having a heat-conducting top and a heat-conducting side wall, an end of the heat-conducting side wall facing away from the heat-conducting top penetrates the packaging substrate from the first surface and is exposed on the second surface, a receiving cavity is formed between the heat-conducting top, the heat-conducting side wall and the first surface; the first chip is located in the receiving cavity, and the surface of the first chip facing away from the packaging substrate is in thermal contact with the heat-conducting top.

[0024] Optionally, in the above electronic device, an auxiliary component is provided on the second surface; a first microchannel is provided inside the heat dissipation component, and a second microchannel is provided inside the auxiliary component; the second microchannel is connected to the first microchannel, and a flowable heat-conducting medium is provided inside the second microchannel and the first microchannel;

[0025] A target part is arranged on the surface of the circuit board; the auxiliary part has a target port, the target port is used to connect to the target part on the circuit board, and the target part is at least used to provide power for the flow of the heat-conducting medium.

[0026] A third aspect of the present application provides a method for manufacturing an electronic device, comprising:

[0027] Provide circuit boards;

[0028] A chip packaging structure is welded and fixed on a circuit board, the chip packaging structure comprising: a packaging substrate having a first surface and a second surface opposite to each other; a first chip fixed on the first surface; a heat dissipation component, the heat dissipation component having a heat-conductive top and a heat-conductive side wall, an end of the heat-conductive side wall facing away from the heat-conductive top penetrates the packaging substrate from the first surface and is exposed on the second surface, an accommodating cavity is formed between the heat-conductive top, the heat-conductive side wall and the first surface; the first chip is located in the accommodating cavity, and a surface of the first chip facing away from the packaging substrate is in thermal contact with the heat-conductive top.

[0029] Optionally, in the above manufacturing method, an auxiliary component is provided on the second surface; a first microchannel is provided inside the heat dissipation component, and a second microchannel is provided inside the auxiliary component; the second microchannel is connected to the first microchannel, and a flowable heat-conducting medium is provided inside the second microchannel and the first microchannel;

[0030] It also includes: fixing a target component on a circuit board; wherein the auxiliary component has a target port, the target port is connected to the target component, and the target component is at least used to provide power for the flow of the heat-conducting medium.

[0031] A fourth aspect of the present application provides a chip packaging method, comprising:

[0032] Providing a packaging substrate having a first surface and a second surface opposite to each other;

[0033] Fixing a first chip on the first surface;

[0034] A heat dissipation component is fixed above the first chip, the heat dissipation component has a heat-conductive top and a heat-conductive side wall, an end of the heat-conductive side wall facing away from the heat-conductive top penetrates the packaging substrate from the first surface and is exposed on the second surface, and an accommodating cavity is formed between the heat-conductive top, the heat-conductive side wall and the first surface; the first chip is located in the accommodating cavity, and the surface of the first chip facing away from the packaging substrate is in thermal contact with the heat-conductive top.

[0035] Optionally, in the above chip packaging method, the method further comprises: disposing an auxiliary member on the second surface, the auxiliary member being in thermal contact with an end of the heat dissipation component exposed from the second surface;

[0036] The heat dissipation component has a first microchannel inside, and the auxiliary component has a second microchannel inside; the second microchannel is connected with the first microchannel, and there is a flowable heat-conducting medium in the second microchannel and the first microchannel.

[0037] Optionally, in the above chip packaging method, it also includes:

[0038] forming a first plastic sealing layer on the first surface, wherein the first plastic sealing layer surrounds the heat-conducting side wall;

[0039] forming a transfer layer above the first plastic encapsulation layer and the thermally conductive top portion;

[0040] fixing a second chip above the transfer layer;

[0041] The second chip is connected to the circuit in the packaging substrate based on the conductive parts in the transfer layer and the plastic packaging layer.

[0042] By means of the above technical scheme, in the chip packaging structure, chip packaging method, electronic device and preparation method thereof provided by the present application, a heat dissipation component is integrated in the chip packaging structure, and the heat dissipation component includes a heat-conducting top and a heat-conducting side wall. The heat-conducting side wall passes through the packaging substrate from the first surface of the packaging substrate. A accommodating cavity can be formed through the heat-conducting top and the heat-conducting side wall of the heat dissipation component and the first surface of the packaging substrate. The first chip is fixed on the first surface covered by the accommodating cavity, and the surface of the first chip away from the packaging substrate is in thermal contact with the heat-conducting top. In this way, the heat generated by the first chip can be transferred to the heat-conducting top based on heat conduction, and part of the heat can be conducted to the side of the packaging substrate facing the second surface at the heat-conducting top based on the heat-conducting side wall, so as to be dissipated to the outside of the chip packaging structure on the side of the chip packaging structure close to the second surface, and part of the heat can continue to be conducted to the outside of the chip packaging structure at the heat-conducting top toward the side away from the packaging substrate. Therefore, based on the heat dissipation component that runs through the packaging structure, heat can be conducted on the opposite sides of the chip packaging structure, thereby improving the heat dissipation effect of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0044] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0045] Figure 1 A cross-sectional view of a chip packaging structure;

[0046] Figure 2 A cross-sectional view of a chip packaging structure provided in an embodiment of the present application;

[0047] Figure 3 A cross-sectional view of another chip packaging structure provided in an embodiment of the present application;

[0048] Figure 4 A cross-sectional view of another chip packaging structure provided in an embodiment of the present application;

[0049] Figure 5 A cross-sectional view of another chip packaging structure provided in an embodiment of the present application;

[0050] Figure 6 A cross-sectional view of another chip packaging structure provided in an embodiment of the present application;

[0051] Figure 7 A cross-sectional view of another chip packaging structure provided in an embodiment of the present application;

[0052] Figure 8 It is a cross-sectional view of the core layer in the packaging substrate;

[0053] Fig. 9 is a top view of the first conductive hole;

[0054] Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0055] Fig.11 A schematic diagram of a process for manufacturing an electronic device provided in an embodiment of the present application;

[0056] Fig.12 A schematic diagram of a process flow of another method for manufacturing an electronic device provided in an embodiment of the present application;

[0057] Figure 13-Figure 19 A cross-sectional view of a product at different process steps of a chip packaging method provided in an embodiment of the present application;

[0058] Figure 20-24A cross-sectional view of a packaging substrate preparation method at different process stages provided in an embodiment of the present application.

[0059] Reference numerals:

[0060] 10-solder ball; 11-package substrate; 111-first surface; 112-second surface; 12-first chip; 121-recessed structure; 13-thermal conductive glue; 14-heat dissipation component; 141-thermal conductive top; 142-thermal conductive side wall; 143-convex structure; 15-accommodating cavity; 16-auxiliary part; 161-target port; 171-first microchannel; 172-second microchannel; 18-target part; 181-micropower pump; 182-heat exchanger; 19-circuit board; 201-first area; 202- The second area; 211-the first conductive hole; 212-the second conductive hole; 22-the second chip; 230-the center layer; 231-the first stacking layer; 232-the second stacking layer; 241-the first through hole; 242-the metal layer; 243-the insulating medium; 244-the thermal conductive layer; 25-the switching layer; 251-the switching line; 26-the circuit board; 27-the first plastic layer; 271-the first conductive part; 28-the mounting hole; 29-the second conductive part; 30-the second plastic layer; 301-the intermediate substrate; 302-the gap area. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments of the present application. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0062] As described in the background art, in conventional chip packaging structures, the chip is generally packaged and protected simply through a packaging substrate, and the heat dissipation effect of the chip is poor.

[0063] In order to improve the heat dissipation effect of the chip, one way is to Figure 1 As shown, a heat dissipation component is fixed above the chip.

[0064] refer to Figure 1 , Figure 1 : is a cross-sectional view of a chip packaging structure, the chip packaging structure shown includes:

[0065] A packaging substrate 11, the packaging substrate having a first surface 111 and a second surface 112 opposite to each other;

[0066] A first chip 12 fixed on the first surface 111;

[0067] The heat dissipation component 14 is fixed on the first surface 111 , and has a receiving cavity 15 . The first chip 12 is located in the receiving cavity. The heat dissipation component 14 and the first chip 12 are contacted and fixed by a thermal conductive adhesive 13 .

[0068] The package substrate 11 has connection circuits in it, the connection circuits are connected to the solder balls 10 disposed on the second surface 112 , and the connection circuits are also connected to the solder pads located on the first surface 111 . Figure 1 The connecting circuits and pads are not shown in the figure. The pins on the back of the first chip 12 are fixed by welding to the pads.

[0069] Figure 1 The chip is packaged based on the Flip Chip Ball Grid Array (FCBGA). Figure 1 In the chip packaging structure shown, although the heat dissipation effect of the first chip 12 can be improved to a certain extent by the heat dissipation component, most of the heat can only be dissipated outside the chip packaging structure from the side of the packaging substrate 11 facing the first surface, and the heat dissipation effect of the chip packaging structure still needs to be further improved.

[0070] In view of this, an embodiment of the present application provides a chip packaging structure, including:

[0071] A packaging substrate having a first surface and a second surface opposite to each other;

[0072] a first chip fixed to the first surface;

[0073] The heat dissipation component comprises a heat-conducting top and a heat-conducting side wall. An end of the heat-conducting side wall facing away from the heat-conducting top penetrates the packaging substrate from the first surface and is exposed on the second surface. An accommodating cavity is formed between the heat-conducting top, the heat-conducting side wall and the first surface. The first chip is located in the accommodating cavity, and the surface of the first chip facing away from the packaging substrate is in thermal contact with the heat-conducting top.

[0074] In the chip packaging structure provided in the embodiment of the present application, a heat dissipation component is integrated in the chip packaging structure, and the heat dissipation component includes a heat-conducting top and a heat-conducting side wall. The heat-conducting side wall passes through the packaging substrate from the first surface of the packaging substrate. A accommodating cavity can be formed through the heat-conducting top and the heat-conducting side wall of the heat dissipation component and the first surface of the packaging substrate. The first chip is fixed on the first surface covered by the accommodating cavity, and the surface of the first chip facing away from the packaging substrate is in thermal contact with the heat-conducting top. In this way, the heat generated by the first chip can be transferred to the heat-conducting top based on heat conduction, and a part of the heat can be conducted to the side of the packaging substrate facing the second surface at the heat-conducting top based on the heat-conducting side wall, so as to be dissipated to the outside of the chip packaging structure on the side of the chip packaging structure close to the second surface, and a part of the heat can continue to be conducted to the outside of the chip packaging structure at the heat-conducting top toward the side facing away from the packaging substrate. Therefore, based on the heat dissipation component that runs through the packaging structure, heat can be conducted on the opposite sides of the chip packaging structure, thereby improving the heat dissipation effect of the chip packaging structure.

[0075] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0076] refer to Figure 2 , Figure 2 A cross-sectional view of a chip packaging structure provided in an embodiment of the present application, wherein the chip packaging structure includes:

[0077] A packaging substrate 11, wherein the packaging substrate 11 has a first surface 111 and a second surface 112 opposite to each other;

[0078] A first chip 12 fixed on the first surface 111;

[0079] The heat dissipation component 14 has a heat-conducting top 141 and a heat-conducting side wall 142. The end of the heat-conducting side wall 142 facing away from the heat-conducting top 141 penetrates the packaging substrate 11 from the first surface 111 and is exposed on the second surface 112. A receiving cavity 15 is formed between the heat-conducting top 141, the heat-conducting side wall 142 and the first surface 111; the first chip 12 is located in the receiving cavity 15, and the surface of the first chip 12 facing away from the packaging substrate 11 is in thermal contact with the heat-conducting top 141.

[0080] The chip packaging structure integrates a heat dissipation component 14. The heat-conducting side wall 142 of the heat dissipation component 14 passes through the packaging substrate 11 from the first surface 111 of the packaging substrate 11. A receiving cavity 15 can be formed through the heat-conducting top 141 and the heat-conducting side wall 142 of the heat dissipation component 14 and the first surface 111 of the packaging substrate 11. The first chip 12 is fixed on the first surface 111 covered by the receiving cavity 15. The surface of the first chip 12 facing away from the packaging substrate 11 is in thermal contact with the heat-conducting top 141. In this way, the heat generated by the first chip 12 can be transferred to the heat-conducting top 141 based on heat conduction, and part of the heat can be transferred to the side of the packaging substrate 11 facing the second surface 112 based on the heat-conducting side wall 142 at the heat-conducting top 141 ( Figure 1 The heat can be conducted to the bottom of the chip package structure shown in the figure) to dissipate to the outside of the chip package structure on this side, and part of the heat can continue to be directed toward the side away from the package substrate 11 ( Figure 1 Therefore, based on the heat dissipation component 14 that penetrates the package structure, the heat can be conducted on the opposite sides of the chip package structure (the top and bottom of the chip package structure), thereby improving the heat dissipation effect of the chip package structure.

[0081] In one implementation, the first chip 12 may be in direct contact with the heat-conducting top portion 141 , and in this case, the top surface of the first chip 12 is in direct contact with the inner surface of the heat-conducting top portion 141 .

[0082] Optionally, in order to improve the thermal contact effect between the first chip 12 and the heat-conducting top 141 and improve the heat conduction rate between the two, a thermally conductive adhesive 13 is provided between the first chip 12 and the heat-conducting top 141 to improve the heat dissipation effect of the chip packaging structure. The thermally conductive adhesive 13 is a high thermally conductive metamaterial, including liquid metal, graphene, or thermally conductive silica gel.

[0083] In the embodiment of the present application, the heat dissipation component 14 is a rigid part with great mechanical strength, such as a metal part (such as metal copper), a ceramic part, etc. Rigid heat dissipation component 14 can suppress the warpage of the package substrate 11, ensure the performance of the chip package structure, and is suitable for the packaging of advanced large-size, high-power, high-functionality and high-reliability SOC chips.

[0084] refer to Figure 3 , Figure 3 A cross-sectional view of another chip packaging structure provided in an embodiment of the present application, based on the above implementation, Figure 3 In the chip packaging structure shown, an auxiliary component 16 is disposed on the second surface 112 , and the auxiliary component 16 is in thermal contact with the end of the heat dissipation component 14 exposed from the second surface 112 .

[0085] exist Figure 3In the shown manner, by providing an auxiliary component 16 connected to the heat-conducting side wall 142 on the second surface 112, the heat in the heat-conducting side wall 142 can at least be conducted to other areas of the second surface 112 through the auxiliary component 16, so as to avoid heat concentration on the second surface 112, increase the heat dissipation area, and improve the heat dissipation effect of the chip packaging structure.

[0086] In the embodiment of the present application, the auxiliary part 16 can be set at the edge position of the second surface 112, so as to reduce the heat conducted from the heat-conducting side wall 142 to the auxiliary part 16 and conduct it to the edge area of ​​the second surface 112 of the chip packaging structure, thereby avoiding heat accumulation in the central area of ​​the second surface 112 facing the chip, so as to improve the heat dissipation effect.

[0087] Optionally, in the embodiment of the present application, one or more auxiliary members 16 may be fixed to the second surface 112. When there are multiple auxiliary members 16, the multiple auxiliary members may be dispersedly arranged at the edge of the second surface 112, so as to improve the heat dispersion, facilitate heat dissipation, and avoid local heat concentration. On the other hand, based on the spacing area between the auxiliary members 16, it is convenient to layout the solder balls 10 on the second surface 112.

[0088] If the second surface 112 is provided with a plurality of auxiliary components 16, as described below, when the chip packaging structure is connected to a micro-power pump, one auxiliary component 16 may be provided to be connected to the micro-power pump, or a plurality of auxiliary components 16 may be provided to be connected to the micro-power pump.

[0089] In one implementation of the present application, the heat dissipation component 14 can be a solid heat-conducting component, such as a metal component or a ceramic component with a high thermal conductivity. The auxiliary component 16 can be a solid heat-conducting component, such as a metal component or a ceramic component with a high thermal conductivity.

[0090] The auxiliary part 16 can not only improve the heat distribution performance and avoid local heat concentration, but also improve the strength of the packaging substrate 11 and prevent the packaging substrate 11 from warping at the edge through the lateral extension of the auxiliary part 16 on the second surface 112, which can be suitable for the packaging of large-size chips.

[0091] refer to Figure 4 , Figure 4 A cross-sectional view of another chip packaging structure provided in an embodiment of the present application, Figure 3 Based on the method shown, Figure 4 In the chip packaging structure shown, the heat dissipation component 14 has a first microchannel 171 inside, and the auxiliary component 16 has a second microchannel 172 inside; the second microchannel 172 is connected to the first microchannel 171, and there is a flowable heat-conducting medium in the second microchannel 172 and the first microchannel 171. Figure 4The heat transfer medium is not shown.

[0092] Optionally, the heat-conducting medium may be a liquid medium, including but not limited to water and alcohol, etc. The heat-conducting medium may also be a gaseous medium, including but not limited to air, nitrogen and inert gas, etc.

[0093] exist Figure 4 In the manner shown, by forming interconnected microchannels within the heat dissipation component 14 and the auxiliary component 16, and based on the heat-conducting medium circulating in the microchannels, the heat transfer rate inside the chip packaging structure can be increased, and the heat inside the chip packaging structure can be quickly transferred to the outside of the chip packaging structure through the microchannels, thereby improving the heat dissipation effect of the chip packaging structure.

[0094] As described below, the auxiliary component 16 can be connected to a micro power pump to increase the circulation flow rate of the heat-conducting medium in the microchannel, thereby improving the heat dissipation effect of the chip package.

[0095] In other embodiments, the auxiliary component 16 may also be unconnected. In this case, the microchannels connected to the heat dissipation component 14 and the auxiliary component 16 may be in a closed state. At this time, the heat inside the chip packaging structure may be transferred to the second surface 112 based on the heat exchange between the high-temperature end close to the chip and the low-temperature end far from the chip in the microchannel, so as to dissipate the heat inside the chip packaging structure to the external environment. If the heat-conducting medium is air, the auxiliary component 16 may also be provided with a vent connected to the external atmosphere, so that the high-temperature gas in the microchannel of the heat dissipation component 14 can exchange heat with the low-temperature gas of the external environment through the vent, so as to dissipate the heat inside the chip packaging structure to the external environment.

[0096] In one implementation of the embodiment of the present application, the heat-conducting medium can exchange heat with the external low-temperature environment based on the temperature difference between the inside and the external environment of the chip packaging structure.

[0097] refer to Figure 5 , Figure 5 A cross-sectional view of another chip packaging structure provided in an embodiment of the present application, Figure 4 Based on the method shown, Figure 5 In the chip packaging structure shown, the auxiliary component 16 has a target port 161, and the target port 161 is used to connect to the target component 18 on the circuit board 19. The target component 18 is at least used to provide power for the flow of the heat-conducting medium.

[0098] exist Figure 5In the manner shown, by setting the target part 18, flow power can be provided for the heat conduction cutoff, accelerating the circulation flow rate of the heat-conducting medium in the connected first microchannel 171 and the second microchannel 172, so as to improve the heat exchange efficiency between the high-temperature heat-conducting medium inside the chip and the external low-temperature environment, thereby improving the heat dissipation effect.

[0099] Optionally, the target component 18 at least includes a micro power pump 181 , and the micro power pump 181 is connected to the target port 161 and can provide power for the circulation of the heat-conducting medium.

[0100] Furthermore, the target component 18 may also include a heat exchanger 182 to increase the heat exchange rate between the high-temperature heat-conducting medium inside the microchannel and the external low-temperature environment to improve the heat dissipation effect.

[0101] The circuit board 19 may be a circuit board of an electronic device. The electronic device includes a chip packaging structure. The target part 18 may be fixedly provided with a circuit board 19 for connecting and fixing a side surface of the chip packaging structure so as to communicate with the target port 161 .

[0102] refer to Figure 6 , Figure 6 A cross-sectional view of another chip packaging structure provided in an embodiment of the present application, based on any of the above implementations, Figure 6 In the chip packaging structure shown, the surface of the first chip 12 facing away from the packaging substrate 11 has a recessed structure 121; the inner surface of the heat-conducting top 141 has a convex structure 143 arranged opposite to the recessed structure 121; wherein at least part of the convex structure 143 is inserted into the opposite recessed structure 121 to increase the thermal contact area. In this way, the surface between the convex structure 143 and the recessed structure 121 can be in direct contact, the two surfaces are directly abutted, or as Figure 6 As shown, the protruding structure 143 is in thermal contact with the recessed structure 121 based on the thermal conductive adhesive 13 located between the first chip 12 and the thermal conductive top 141 .

[0103] exist Figure 6 In the shown manner, a recessed structure 121 is provided on the surface of the first chip 12, and a raised structure 143 matching the recessed structure 121 is provided on the inner surface of the heat-conducting top 141. Through the nested structure of the raised structure 143 and the recessed structure 121, the thermal contact area between the first chip 12 and the heat-conducting top 141 can be increased, thereby increasing the thermal conduction rate of the heat in the first chip 12 to the heat dissipation component 14, thereby improving the heat dissipation effect.

[0104] Optionally, the protrusion structure 143 may be a plurality of parallel-arranged strip-shaped protrusions, which may be a rectangular parallelepiped structure, a triangular prism structure, or a semi-cylindrical structure, etc. The protrusion structure 143 may also be a plurality of dot-shaped protrusions arranged in a dot matrix, which may be a cylindrical structure, a cubic structure, a triangular pyramid structure, or a hemispherical structure, etc. The shape and distribution of the recessed structure 121 complement the protrusion structure 143, so that the protrusion structure 143 can be embedded in the recessed structure 121 one by one, thereby increasing the thermal contact area between the first chip 12 and the heat-conducting top 141.

[0105] refer to Figure 7 , Figure 7 A cross-sectional view of another chip packaging structure provided in an embodiment of the present application, based on any of the above implementations, Figure 7 In the chip packaging structure shown, the packaging substrate 11 has a first area 201 and a second area 202 surrounding the first area 201, the first area 201 is located in the accommodating cavity 15, and the second area 202 is located outside the accommodating cavity 15; the first area 201 has a first conductive hole 211 penetrating the packaging substrate 11, and the second area 202 has a second conductive hole 212 penetrating the packaging substrate 11; the ends of the first conductive hole 211 and the second conductive hole 212 facing the second surface 112 are respectively connected to the solder ball 10, and the solder ball 10 is used to connect to the external circuit; wherein the first chip 12 is electrically connected to the end of the first conductive hole 211 facing the first surface 111; the second chip 22 is also arranged on the side of the heat conductive top 141 away from the first chip 12, and the second chip 22 is electrically connected to the end of the second conductive hole 212 facing the first surface 111. This method adopts the package stacking technology (Package on Package, referred to as PoP).

[0106] Optionally, a transfer layer 25 is fixedly connected above the first chip 12 , a circuit board 26 is fixedly connected above the transfer layer 25 , and the second chip 22 is fixedly connected to the surface of the circuit board 26 .

[0107] When the conventional PoP technology is used to stack two chips, the transfer layer 25, the circuit board 26 and the second chip 22 need to be arranged in sequence above the first chip 12, resulting in a thicker stacked structure above the first chip 12, and the first surface 111 also has a first plastic layer 27. The plastic material of the first plastic layer 27 fills the accommodating cavity 15 and surrounds the side wall of the heat dissipation component 14. The plastic material and the thick stacked structure will affect the heat dissipation of the first chip 12 toward the top side of the chip packaging structure, resulting in the first chip 12 being unable to dissipate as Figure 1-Figure 6The method shown is based on the fact that after the heat is conducted between the thermal conductive adhesive 13 and the heat dissipation component 14 , the heat is directly dissipated to the outside of the chip packaging structure through the heat dissipation component 14 , which affects the heat dissipation effect of the first chip 12 and limits the maximum power and performance improvement of the first chip 12 .

[0108] Therefore, in conventional chip packaging structures, in order to improve the heat dissipation effect of the first chip 12, the distance from the first chip 12 to the transfer layer 25 is reduced by increasing the thickness of the first chip 12 to reduce the heat conduction distance from the first chip 12 to the transfer layer 25. In this way, the increase in chip thickness has a small improvement on the heat dissipation effect and causes the thickness of the chip packaging structure to increase; or, by developing and using high thermal conductivity plastic encapsulation materials to increase the thermal conductivity rate of the plastic encapsulation material, but limited by the composition of the plastic encapsulation material, its thermal conductivity is generally lower than 1W / m·K. Therefore, when conventional PoP technology stacks two chips, it will seriously affect the heat dissipation effect of the first chip 12, and conventional solutions cannot effectively improve the heat dissipation effect of the first chip 12.

[0109] In the application embodiment, it can be as follows Figure 7 In the manner shown, based on the PoP process, the first chip 12 and the second chip 22 can be stacked on the same packaging substrate 11, and two chips can be stacked and packaged in the same chip packaging structure, which can reduce the area of ​​the chip packaging structure, and can reduce the mounting area of ​​the chip packaging structure while increasing the functional structure density, which can improve the integration of the chip packaging structure and facilitate the miniaturization design of the device. Moreover, when the first chip 12 and the second chip 22 are arranged, the heat generated by the first chip 12 can be quickly conducted based on the heat conduction path of the top of the first chip 12 → the heat-conducting top 141 → the heat-conducting side wall → the surface of one side of the chip packaging structure provided with the solder ball 10, so as to improve the heat dissipation rate of the first chip 12, and reduce the influence of the second chip 22 stacked on the first chip 12 on the heat dissipation effect of the first chip 12.

[0110] Optionally, the first chip 12 may be a SOC, and the second chip 22 may be a DRAM. The chip types of the first chip 12 and the second chip 22 may be set according to the performance requirements of the electronic device, and the embodiment of the present application does not limit the types of the two chips.

[0111] refer to Figure 8 and Fig. 9 , Figure 8 This is a cross-sectional view of the core layer in the package substrate. Fig. 9 is a top view of the first conductive hole, combined with Figure 7-Figure 8As shown, the packaging substrate 11 includes: a first stacking layer 231, a central layer 230 and a second stacking layer 232 stacked in sequence; the first conductive hole 211 includes: a first through hole 241 passing through the central layer 230; a metal layer 242 covering the side wall of the first through hole 241; an insulating medium 243 filling the first through hole 241; and a thermal conductive layer 244 located between the insulating medium 243 and the metal layer 242.

[0112] Optionally, the metal layer 242 may be copper or other metal layers. The insulating medium 243 may be a resin material or other insulating material. The thermal conductive layer 244 may be graphene or other thermal conductive materials. Graphene has super two-dimensional thermal conductivity. The thermal conductivity of graphene is 2000W / m·K~3000W / m·K, and the thermal conductivity of copper is 401W / m·K. Using graphene as the thermal conductive layer 244 can significantly improve the thermal conductivity of the first conductive hole 211, and can make the heat in the chip packaging structure quickly conduct from the bottom to the bottom, which can improve the heat dissipation effect of the chip packaging structure. In conventional chip packaging structures, the conductive holes are generally filled with insulating resin after the surface of the through hole is covered with copper, and the thermal conductivity is poor. In the embodiment of the present application, if Figure 8 and Fig. 9 As shown, the first conductive hole 211 has a heat-conducting layer 244. Based on the heat-conducting layer 244, the first conductive hole 211 can have a higher thermal conductivity. In this way, the heat generated by the first chip 12 can not only be conducted to the bottom of the chip packaging structure based on the above-mentioned heat-conducting path, but also can be vertically conducted to the bottom of the chip packaging structure based on the first conductive hole 211, which can improve the heat dissipation rate of the first chip 12 and improve the heat dissipation effect of the chip packaging structure.

[0113] Based on the chip packaging structure provided in the above embodiment, another embodiment of the present application further provides an electronic device, the structure of the electronic device can be as follows: Fig.10 shown.

[0114] refer to Fig.10 , Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application, the electronic device shown includes: a circuit board 19;

[0115] A chip packaging structure fixed on a circuit board 19, the chip packaging structure includes: a packaging substrate 11, the packaging substrate 11 has a first surface 111 and a second surface 112 relative to each other; a first chip 12 fixed on the first surface 111; a heat dissipation component 14, the heat dissipation component 14 has a heat-conducting top 141 and a heat-conducting side wall 142, the end of the heat-conducting side wall 142 facing away from the heat-conducting top 141 penetrates the packaging substrate 11 from the first surface 111 and is exposed at the second surface 112, and an accommodating cavity 15 is formed between the heat-conducting top 141, the heat-conducting side wall 142 and the first surface 111; the first chip 12 is located in the accommodating cavity 15, and the surface of the first chip 12 facing away from the packaging substrate 11 is in thermal contact with the heat-conducting top 141.

[0116] Electronic devices include but are not limited to mobile phones, tablet computers, laptop computers, smart wearable devices, etc. Electronic devices using the chip packaging structure of the above embodiment can improve the heat dissipation effect of the chip packaging structure, improve the performance of the chip packaging structure, and thus improve the performance of the electronic device.

[0117] In the embodiment of the present application, Figure 5 As shown, the second surface 112 is provided with an auxiliary part 16; the heat dissipation component 14 has a first microchannel 171 inside, and the auxiliary part 16 has a second microchannel 172; the second microchannel 172 is connected to the first microchannel 171, and the second microchannel 172 and the first microchannel 171 have a flowable heat-conducting medium; the surface of the circuit board 19 is provided with a target part 18; the auxiliary part 16 has a target port 161, and the target port 161 is used to connect the target part 18 on the circuit board 19, and the target part 18 is at least used to provide power for the flow of the heat-conducting medium. By installing the target part 18 on the circuit board 19, the flow speed of the heat-conducting medium in the microchannel can be increased, and then the heat exchange rate between the heat-conducting medium and the external low-temperature environment can be increased, and the heat dissipation effect can be improved.

[0118] Based on the chip packaging structure and electronic device provided in the above embodiments, another embodiment of the present application further provides a method for manufacturing an electronic device. The manufacturing method is as follows: Fig.11 shown.

[0119] refer to Fig.11 , Fig.11 A schematic diagram of a process flow of an electronic device manufacturing method provided in an embodiment of the present application, combined with the drawings of the chip packaging structure of the above embodiment and Fig.11 As shown, including:

[0120] Step S11: providing a circuit board 19.

[0121] Step S12: soldering and fixing a chip packaging structure on the circuit board 19, the chip packaging structure comprising: a packaging substrate 11, the packaging substrate 11 having a first surface 111 and a second surface 112 relative to each other; a first chip 12 fixed on the first surface 111; a heat dissipation component 14, the heat dissipation component 14 having a heat-conducting top 141 and a heat-conducting side wall 142, an end of the heat-conducting side wall 142 facing away from the heat-conducting top 141 penetrates the packaging substrate 11 from the first surface 111 and is exposed at the second surface 112, a receiving cavity 15 is formed between the heat-conducting top 141, the heat-conducting side wall 142 and the first surface 111; the first chip 12 is located in the receiving cavity 15, and the surface of the first chip 12 facing away from the packaging substrate 11 is in thermal contact with the heat-conducting top 141.

[0122] The manufacturing method can be used to prepare the electronic device provided in the above embodiment. The chip packaging structure in the electronic device can improve the heat dissipation effect through the heat dissipation component 14, thereby improving the performance of the electronic device.

[0123] As described above, the second surface 112 is provided with an auxiliary part 16; the heat dissipation component 14 has a first microchannel 171 inside, and the auxiliary part 16 has a second microchannel 172; the second microchannel 172 is connected to the first microchannel 171, and the second microchannel 172 and the first microchannel 171 have a flowable heat-conducting medium.

[0124] refer to Fig.12 , Fig.12 A schematic diagram of a process flow of another electronic device manufacturing method provided in an embodiment of the present application, wherein Fig.11 Based on the method shown, the manufacturing method also includes:

[0125] Step S13: Fix the target component 18 on the circuit board 19; wherein the auxiliary component 16 has a target port 161, the target port 161 is connected to the target component 18, and the target component 18 is at least used to provide power for the flow of the heat-conducting medium.

[0126] exist Fig.12 In the illustrated embodiment, the target component 18 is fixed on the circuit board 19 , and the target component 18 does not need to occupy the layout space of the chip packaging structure.

[0127] Based on the chip packaging structure, electronic device and manufacturing method provided in the above embodiments, another embodiment of the present application further provides a chip packaging method, which can be as follows: Figure 13-Figure 19 shown.

[0128] refer to Figure 13-Figure 19 , Figure 13-Figure 19 A product cross-sectional view of a chip packaging method in different process steps provided in an embodiment of the present application includes:

[0129] Step S21: Fig.13 As shown, a packaging substrate 11 is provided, having a first surface 111 and a second surface 112 opposite to each other.

[0130] The prepared packaging substrate 11 can be baked to remove moisture.

[0131] Step S22: Fig.14 As shown, the first chip 12 is fixed on the first surface 111 .

[0132] After the first chip 12 is welded and fixed to the first surface 111 , a glue layer may be filled between the bottom of the first chip 12 and the first surface 111 to improve the stability of the first chip 12 .

[0133] Step S23: Fig.15 As shown, a heat dissipation component 14 is fixed above the first chip 12, and the heat dissipation component 14 has a heat-conducting top 141 and a heat-conducting side wall 142. The end of the heat-conducting side wall 142 facing away from the heat-conducting top 141 penetrates the packaging substrate 11 from the first surface 111 and is exposed on the second surface 112. An accommodating cavity 15 is formed between the heat-conducting top 141, the heat-conducting side wall 142 and the first surface 111; the first chip 12 is located in the accommodating cavity 15, and the surface of the first chip 12 facing away from the packaging substrate 11 is in thermal contact with the heat-conducting top 141.

[0134] Optionally, before fixing the heat dissipation component 14, a thermal conductive adhesive 13 may be applied on the top of the first chip 12 to achieve thermal contact between the top of the first chip 12 and the thermal conductive top 141 based on the thermal conductive adhesive 13. The heat dissipation component 14 with microchannels may be formed by a 3D printing process.

[0135] like Fig.13 and Fig.14 As shown, the package substrate 11 has a mounting hole 28 that penetrates the first surface 111 and the second surface 112; the method for fixing the heat dissipation component above the first chip 12 includes: Fig.15 As shown, based on the mounting hole 28 , one end of the heat-conducting side wall 142 away from the heat-conducting top 141 passes through the mounting hole 28 to seal the first chip 12 between the heat-conducting top 141 and the first surface 111 .

[0136] The chip packaging method also includes:

[0137] Step S24: Fig.16 As shown, an auxiliary part 16 is provided on the second surface 112, and the auxiliary part 16 is in thermal contact with the end of the heat dissipation component 14 exposed from the second surface 112; the heat dissipation component 14 has a first microchannel 171 inside, and the auxiliary part 16 has a second microchannel 172; the second microchannel 172 is connected to the first microchannel 171, and there is a flowable heat-conducting medium in the second microchannel 172 and the first microchannel 171.

[0138] By providing the auxiliary member 16, not only can the heat in the heat-conducting side wall 142 be quickly conducted to other areas of the second surface 112 to improve the heat uniformity of the second surface 112 and avoid local heat concentration, thereby improving the heat dissipation effect, but the auxiliary member 16 can also improve the mechanical strength of the package substrate 11 and prevent the package substrate 11 from warping due to stress during the packaging process. Moreover, the microchannels in the auxiliary member 16 and the heat dissipation component 14 can accommodate the heat-conducting medium to increase the heat exchange speed between the chip packaging structure and the external low-temperature environment, further improving the heat dissipation effect.

[0139] The chip packaging method also includes:

[0140] Step S25: Fig.17 As shown, a first plastic encapsulation layer 27 is formed on the first surface, and the first plastic encapsulation layer 27 surrounds the heat-conducting side wall 142 .

[0141] Optionally, through holes may be reserved in the heat-conducting side wall 142 so that when the first plastic encapsulation layer 27 is formed, the plastic encapsulation material can enter the accommodating cavity 15 through the through holes in the heat-conducting side wall 142 , so that the plastic encapsulation material can fill the gap area in the accommodating cavity 15 .

[0142] The first plastic encapsulation layer 27 and the heat dissipation component 14 are flush with each other on the side away from the packaging substrate 11. Fig.17 As shown, the first plastic packaging layer 27 is flush with the top plane of the heat dissipation component 14 so as to provide a flat bearing surface for subsequent processes.

[0143] Step S26: Fig.18 As shown, a transfer layer 25 is formed above the first plastic packaging layer 27 and the heat conductive top 141 .

[0144] Step S27: Fig.19 As shown, the second chip 22 is fixed above the transfer layer 25 .

[0145] The second chip 22 is connected to the circuit in the package substrate 11 based on the switching circuit 251 in the switching layer 25 and the first conductive member 271 in the first plastic layer 27. The first plastic layer 27 has a first conductive member 271, the switching layer 25 has a switching circuit 251, the second chip 22 is connected to the switching circuit 251, the switching circuit 251 is connected to the first conductive member 271, and the first conductive member 271 is connected to the second conductive via 212 below.

[0146] The method for fixing the second chip 22 on the transfer layer 25 includes: firstly, connecting and fixing the circuit board 26 on the transfer layer 25 through the second conductive member 29, then soldering and fixing the second chip 22 on the surface of the circuit board 26, and finally sealing and protecting the second chip 22 through the second plastic layer 30. Finally, balls can be planted on the second surface 112 to form solder balls 10 to complete the preparation of the chip packaging structure.

[0147] After the chip packaging structure is fixed on the circuit board 19 of the electronic device, a target component 18 can be arranged on the circuit board, and the target component 18 is connected to the auxiliary component 16 to improve the heat exchange rate.

[0148] In order to increase the thermal contact area between the first chip 12 and the heat-conducting top 141 , as described above, a recessed structure 121 may be formed on the surface of the first chip 12 facing away from the packaging substrate 11 ; and a protruding structure 143 may be formed on the inner surface of the heat-conducting top 141 opposite to the recessed structure 121 .

[0149] The preparation method of the packaging substrate 11 can be as follows Figure 20-24 shown.

[0150] refer to Figure 20-24 , Figure 20-24 A cross-sectional view of a packaging substrate preparation method provided in an embodiment of the present application at different process stages, wherein the preparation method includes:

[0151] Step S31: Fig. 20 As shown, an intermediate substrate 301 is provided for preparing the core layer 230 .

[0152] The upper and lower surfaces of the intermediate substrate 301 are both covered with a metal layer 242, which may be a copper layer. The intermediate substrate 301 may be baked at a high temperature to remove surface moisture.

[0153] The intermediate substrate 301 includes a first area 201 and a second area 202 surrounding the first area 201. A gap area 302 is provided between the first area 201 and the second area 202 for forming a mounting hole 28.

[0154] Step S32: Fig.21 As shown, a first through hole 241 is formed through the intermediate substrate 301. The first through hole 241 can be formed by mechanical drilling or laser drilling. The first through holes 241 are formed at corresponding positions of the first conductive hole 211 and the second conductive hole 212.

[0155] Step S33: Figure 8 and Fig. 9 As shown, a first conductive hole 211 and a second conductive hole 212 are formed in the intermediate substrate 301 to complete the preparation of the core layer 230 .

[0156] In this step, after forming the first through hole 241, a metal layer 242 is deposited on the side wall of the first through hole 241, and the metal layer 242 on the side wall of the first through hole 241 is connected to the metal layer 242 on the upper and lower surfaces of the intermediate substrate 301. After forming the metal layer 242, an insulating medium 243 is filled in the first through hole 241 to form the first conductive hole 211 and the second conductive hole 212. When forming the first conductive hole 211, after forming the metal layer 242, a heat conductive layer 244 may be formed on the surface of the metal layer 242, and then filled with the insulating medium 243.

[0157] Step S34: Fig. 22 As shown, a first stacked layer 231 and a second stacked layer 232 are respectively formed on both side surfaces of the central layer 230 through processes such as exposure, development and etching.

[0158] Step S35: Fig.23 As shown, the mounting hole 28 is formed in the gap area 302 by a mechanical drilling process.

[0159] Step S36: Fig.24 As shown, solder resist layers 31 are formed on the upper and lower surfaces of the package substrate 11. Subsequent processes can form a first conductive member 271 on the upper surface of the package substrate 11 based on the solder resist layer 31 on the upper surface, and plant balls on the lower surface of the package substrate 11 based on the solder resist layer 31 on the lower surface to form solder balls 10.

[0160] In the specification of this application, each embodiment is described in a progressive, parallel, or progressive and parallel manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. The embodiments provided in the embodiments of this application can be combined with each other if there is no contradiction.

[0161] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially refer to positioning on the upper side of another element according to the direction of gravity.

[0162] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0163] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0164] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip packaging structure, comprising: A packaging substrate having a first surface and a second surface opposite to each other; a first chip fixed on the first surface; A heat dissipation component, wherein the heat dissipation component has a heat-conductive top and a heat-conductive side wall, wherein one end of the heat-conductive side wall facing away from the heat-conductive top penetrates the packaging substrate from the first surface and is exposed at the second surface, and an accommodating cavity is formed between the heat-conductive top, the heat-conductive side wall and the first surface; the first chip is located in the accommodating cavity, and the surface of the first chip facing away from the packaging substrate is in thermal contact with the heat-conductive top. 2 . The chip packaging structure according to claim 1 , wherein an auxiliary component is disposed on the second surface, and the auxiliary component is in thermal contact with an end portion of the heat dissipation component exposed from the second surface.

3. According to the chip packaging structure of claim 2, the heat dissipation component has a first microchannel inside, and the auxiliary component has a second microchannel inside; the second microchannel is connected to the first microchannel, and the second microchannel and the first microchannel have a flowable heat-conducting medium. 4 . The chip packaging structure according to claim 3 , wherein the auxiliary component has a target port, the target port is used to connect to a target component on a circuit board, and the target component is at least used to provide power for the flow of the heat-conducting medium.

5. The chip packaging structure according to claim 1, wherein a surface of the first chip facing away from the packaging substrate has a concave structure; The inner surface of the heat-conducting top has a convex structure arranged opposite to the concave structure; in, At least a portion of the protruding structure is inserted into the opposite concave structure to increase a thermal contact area.

6. The chip packaging structure according to claim 1, wherein the packaging substrate comprises a first area and a second area surrounding the first area, the first area is located in the accommodation cavity, and the second area is located outside the accommodation cavity; The first region has a first conductive hole penetrating the package substrate, and the second region has a second conductive hole penetrating the package substrate; ends of the first conductive hole and the second conductive hole facing the second surface are respectively connected to solder balls, and the solder balls are used to connect to an external circuit; in, The first chip is electrically connected to the end of the first conductive hole facing the first surface; A second chip is also arranged on a side of the heat-conducting top facing away from the first chip, and the second chip is electrically connected to an end of the second conductive hole facing the first surface.

7. The chip packaging structure according to claim 6, wherein the packaging substrate comprises: A first stacking layer, a center layer, and a second stacking layer stacked in sequence; The first conductive hole includes: a first through hole passing through the central layer; a metal layer covering the side wall of the first through hole; an insulating medium filling the first through hole; and a heat conducting layer located between the insulating medium and the metal layer.

8. An electronic device comprising: Circuit boards; A chip packaging structure fixed on the circuit board, the chip packaging structure comprising: a packaging substrate having a first surface and a second surface opposite to each other; a first chip fixed on the first surface; a heat dissipation component, the heat dissipation component having a heat-conductive top and a heat-conductive side wall, the end of the heat-conductive side wall facing away from the heat-conductive top penetrates the packaging substrate from the first surface and is exposed at the second surface, a receiving cavity is formed between the heat-conductive top, the heat-conductive side wall and the first surface; the first chip is located in the receiving cavity, and the surface of the first chip facing away from the packaging substrate is in thermal contact with the heat-conductive top.

9. The electronic device according to claim 8, wherein the second surface is provided with an auxiliary component; the heat dissipation component has a first microchannel inside, and the auxiliary component has a second microchannel inside; the second microchannel is connected to the first microchannel, and a flowable heat-conducting medium is present in the second microchannel and the first microchannel; A target part is arranged on the surface of the circuit board; the auxiliary part has a target port, the target port is used to connect to the target part on the circuit board, and the target part is at least used to provide power for the flow of the heat-conducting medium.

10. A method for manufacturing an electronic device, comprising: Provide circuit boards; A chip packaging structure is welded and fixed on a circuit board, the chip packaging structure comprising: a packaging substrate having a first surface and a second surface opposite to each other; a first chip fixed on the first surface; a heat dissipation component, the heat dissipation component having a heat-conductive top and a heat-conductive side wall, an end of the heat-conductive side wall facing away from the heat-conductive top penetrates the packaging substrate from the first surface and is exposed at the second surface, a receiving cavity is formed between the heat-conductive top, the heat-conductive side wall and the first surface; the first chip is located in the receiving cavity, and a surface of the first chip facing away from the packaging substrate is in thermal contact with the heat-conductive top.

11. The manufacturing method according to claim 10, wherein the second surface is provided with an auxiliary component; the heat dissipation component has a first microchannel inside, and the auxiliary component has a second microchannel inside; the second microchannel is connected to the first microchannel, and the second microchannel and the first microchannel have a flowable heat-conducting medium inside; Also includes: fixing a target component on the circuit board; The auxiliary component has a target port, the target port is connected to the target component, and the target component is at least used to provide power for the flow of the heat-conducting medium.

12. A chip packaging method, comprising: Providing a packaging substrate having a first surface and a second surface opposite to each other; Fixing a first chip on the first surface; A heat dissipation component is fixed above the first chip, the heat dissipation component having a heat-conductive top and a heat-conductive side wall, an end of the heat-conductive side wall facing away from the heat-conductive top penetrates the packaging substrate from the first surface and is exposed at the second surface, and a receiving cavity is formed between the heat-conductive top, the heat-conductive side wall and the first surface; the first chip is located in the receiving cavity, and a surface of the first chip facing away from the packaging substrate is in thermal contact with the heat-conductive top.

13. The chip packaging method according to claim 12, further comprising: An auxiliary member is arranged on the second surface, wherein the auxiliary member is in thermal contact with an end portion of the heat dissipation component exposed from the second surface; The heat dissipation component has a first microchannel inside, and the auxiliary component has a second microchannel inside; the second microchannel is connected to the first microchannel, and there is a flowable heat-conducting medium in the second microchannel and the first microchannel.

14. The chip packaging method according to claim 12, further comprising: forming a first plastic sealing layer on the first surface, wherein the first plastic sealing layer surrounds the heat-conducting side wall; forming a transfer layer above the first plastic packaging layer and the heat conductive top; Fixing a second chip above the transfer layer; The second chip is connected to the circuit in the packaging substrate based on the switching circuit in the switching layer and the first conductive member in the first plastic packaging layer.

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