Integrated circuit capable of reducing power supply pins

Abstract

The invention provides an integrated circuit capable of reducing power supply pin positions, which comprises a packaging shell, a power supply pin position terminal, a crystal grain, a conductive path and more than two first small bonding pads, the power supply pin position terminal is arranged on the packaging shell in a penetrating manner, the crystal grain is arranged in the packaging shell, and the conductive path is arranged in the packaging shell. The conductive path and the more than two first small bonding pads are respectively arranged on the crystal grain; a connecting region is arranged between the conductive path and the crystal grain, and the more than two first small bonding pads are respectively arranged in the connecting region and are adjacently connected; wherein any one of the more than two small-sized bonding pads is connected with the conductive path, and any one of the more than two first small-sized bonding pads is connected with the power supply pin terminal through a lead. Therefore, the arrangement number of the power supply pins can be reduced, and the expansible functionality of the I / O pins in the integrated circuit is increased.

Description

Technical Field

[0001] The invention relates to an integrated circuit, in particular to an integrated circuit capable of reducing power pins. Background Art

[0002] In the prior art, a known integrated circuit (IC) packaging method is composed of a packaging shell, a die and a plurality of pin terminals. The die is packaged in the packaging shell, and the plurality of pin terminals are arranged on the packaging shell. In addition to preventing moisture from penetrating into the die and reducing damage to the die caused by external force impact, the plurality of pin terminals include a plurality of power pin terminals. An external power circuit can provide the electrical energy required by the die through the plurality of power pin terminals and the integrated circuit.

[0003] However, the package shell of the traditional integrated circuit must be provided with a considerable number of power pin terminals in order to provide the die with stable power, which results in the number of pins originally used for data input / output (I / O) in the traditional integrated circuit being occupied by the majority of power pin terminals. Therefore, how to solve the above-mentioned problems of the prior art is indeed necessary to propose a better solution. Summary of the invention

[0004] In view of the above-mentioned deficiencies of the prior art, the main purpose of the present invention is to provide an integrated circuit that can reduce power pins, improve the integrated circuit architecture, and solve the problem in the prior art that most power pin terminals occupy I / O pins.

[0005] In order to solve the above-mentioned problems of the prior art, the technical solution adopted by the present invention is to make the above-mentioned integrated circuit capable of reducing the number of power pins include: a packaging shell; A power pin terminal is provided on the package shell; A die is disposed inside the package shell; a conductive path disposed on the die and having a first connection region between the conductive path and an outer edge of the die; and Two or more first small solder pads are arranged in the first connection area and are adjacently connected; Wherein, any one of the two or more first small solder pads is connected to the conductive path, and any one of the two or more first small solder pads is connected to the power pin terminal through a wire.

[0006] Preferably, a second connection region is provided between the conductive path and the outer edge of the die, and the two or more first small pads are disposed in the first connection region or the second connection region.

[0007] Preferably, the conductive path is arranged on the die in an annular shape, and the second connection area is formed by the interior of the annular conductive path.

[0008] Preferably, it further comprises two or more second small pads, wherein the two or more second small pads are arranged in the first connection area or the second connection area and are adjacently connected; Wherein, any one of the two or more second small pads is connected to the conductive path, and any one of the two or more second small pads is connected to any one of the two or more first small pads through another conductive wire.

[0009] Preferably, it further comprises two or more third small pads and two or more fourth small pads, wherein the two or more third small pads are arranged in the first connection area or the second connection area and are adjacently connected; the two or more fourth small pads are arranged in the first connection area or the second connection area and are adjacently connected; Among them, any one of the two or more third small solder pads is connected to the conductive path, any one of the two or more fourth small solder pads is connected to the conductive path, any one of the two or more third small solder pads is connected to any one of the two or more first small solder pads through another wire, any one of the two or more fourth small solder pads is connected to any one of the two or more second small solder pads through another wire, and any one of the two or more fourth small solder pads is connected to any one of the two or more third small solder pads through another wire.

[0010] Preferably, it further comprises two or more second small pads and a first long pad, wherein the two or more second small pads are arranged in the first connection area or the second connection area and are adjacently connected, and the first long pad is arranged in the second connection area; Among them, any one of the two or more second small solder pads is connected to the conductive path, the first long solder pad is connected to any one of the two or more second small solder pads through another conductive wire, and the first long solder pad is connected to any one of the two or more first small solder pads through another conductive wire.

[0011] Preferably, it further comprises two or more third small pads, two or more fourth small pads, a second long pad, a third long pad and a fourth long pad, wherein the two or more third small pads are arranged in the first connection area or the second connection area and are adjacently connected; the two or more fourth small pads are arranged in the first connection area or the second connection area and are adjacently connected, and the second long pad, the third long pad and the fourth long pad are arranged in the second connection area; Among them, any one of the two or more third small solder pads is connected to the conductive path, any one of the two or more fourth small solder pads is connected to the conductive path, the second long solder pad is connected to any one of the two or more second small solder pads through another wire, and the second long solder pad is connected to any one of the two or more fourth small solder pads through another wire; the third long solder pad is connected to any one of the two or more fourth small solder pads through another wire, and the third long solder pad is connected to any one of the two or more third small solder pads through another wire; the fourth long solder pad is connected to any one of the two or more third small solder pads through another wire, and the fourth long solder pad is connected to any one of the two or more first small solder pads through another wire.

[0012] Preferably, it further comprises two or more second small pads and two or more fifth small pads, wherein the two or more second small pads are arranged in the first connection area or the second connection area and are adjacently connected, and the two or more fifth small pads are arranged in the second connection area and are adjacently connected; Among them, any one of the two or more second small solder pads is connected to the conductive path, any one of the two or more fifth small solder pads is connected to any one of the two or more second small solder pads through another conductive wire, and any one of the two or more fifth small solder pads is connected to any one of the two or more first small solder pads through another conductive wire.

[0013] The present invention arranges the two or more first small solder pads in the first connection area to be adjacently connected and connected to the conductive path, and the power pin terminal is connected to any one of the two or more first small solder pads through the conductive wire. This can reduce the number of power pins and increase the expandable functionality of the I / O pins in the integrated circuit.

[0014] In order to solve the above-mentioned problems of the prior art, another technical solution adopted by the present invention is to make the aforementioned integrated circuit capable of reducing the number of power pins include: a packaging shell; A power pin terminal is provided on the package shell; A die is disposed inside the package shell; an annular conductive path, which is disposed on the crystal grain and forms a first connection area between the conductive path and the outer edge of the crystal grain, and a second connection area is formed by the inside of the conductive path; Two or more first elongated pads are arranged at relative positions of the first connection area; wherein the two or more first elongated pads are connected to the conductive path, and any one of the two or more first elongated pads is connected to the power pin terminal through a wire; and A large pad is provided in the second connection area, and the large pad is connected to the two or more first elongated pads through two or more other conductive wires.

[0015] Preferably, it further comprises two or more second elongated pads, wherein the two or more second elongated pads are arranged in the first connection area and are arranged at different positions from the two or more first elongated pads; The two or more second elongated pads are connected to the conductive path, and the large pad is connected to the two or more second elongated pads respectively through another two or more conductive wires.

[0016] The present invention arranges the two or more first elongated pads in the first connection area and the large pad in the second connection area, and the power pin terminal is connected to any one of the two or more first elongated pads through the wire. This can reduce the number of power pins and increase the expandable functionality of the I / O pins in the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 FIG. 1 is a schematic diagram of an integrated circuit capable of reducing power pins according to a first embodiment of the present invention. Figure 2 FIG. 4 is another schematic diagram of the integrated circuit capable of reducing power pins according to the first embodiment of the present invention. Figure 3 It is another schematic diagram of the integrated circuit capable of reducing power pins according to the first embodiment of the present invention. Figure 4 FIG. 4 is a schematic diagram of an integrated circuit capable of reducing power pins according to a second embodiment of the present invention. Figure 5 FIG. 2 is another schematic diagram of an integrated circuit capable of reducing power pins according to the second embodiment of the present invention. Figure 6 FIG. 4 is a schematic diagram of an integrated circuit capable of reducing power pins according to a third embodiment of the present invention. Figure 7FIG. 4 is a schematic diagram of an integrated circuit capable of reducing power pins according to a fourth embodiment of the present invention. Figure 8 FIG. 4 is a schematic diagram of another integrated circuit capable of reducing power pins according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0018] Regarding the first embodiment of the present invention, an integrated circuit is provided which can reduce the number of power pins. Figure 1 , which includes a package shell 10, a power pin terminal 20, a die 30, a conductive path 40 and two or more first small pads 50, wherein the power pin terminal 20 can be passed through the package shell 10, the die 30 is arranged inside the package shell 10, the conductive path 40 is arranged on the die 30, and a first connection area A1 is provided between the conductive path 40 and the outer edge of the die 30, the two or more first small pads 50 are respectively arranged in the first connection area A1, and the two or more first small pads 50 are adjacent to each other and form an electrical connection; wherein any one of the two or more first small pads 50 is electrically connected to the conductive path 40, and any one of the two or more first small pads 50 is electrically connected to the power pin terminal 20 through a wire W1.

[0019] The present invention reduces the number of power pins and increases the expandable functionality of I / O pins in the integrated circuit by virtue of the two or more first small solder pads 50 arranged in the first connection area A1 being adjacently connected and connected to the conductive path 40, and the power pin terminal 20 being connected to any one of the two or more first small solder pads 50 through the wire W1.

[0020] In this embodiment, if Figure 1As shown, it further has a second connection area A2 between the conductive path 40 and the outer edge of the die 30, and the second connection area A2 does not overlap with the first connection area A1. The conductive path 40 is arranged on the die 30 in an annular shape, and the conductive path 40 can be in a square shape. Further, the first connection area A1 is formed from the outer side of the conductive path 40 to the outer edge of the die 30, and the second connection area A2 can be formed by the inner part of the annular conductive path 40. In this embodiment, the two or more first small pads 50 are electrically connected through a conductive layer 60, and any one of the two or more first small pads 50 is electrically connected to the conductive path 40 through another conductive layer 60. In addition, one end of the wire W1 is welded to the surface of any one of the two or more first small pads 50, and the other end of the first wire W1 is welded to the power pin terminal 20, so that any one of the two or more first small pads 50 is electrically connected to the power pin terminal 20.

[0021] See also Figure 2 In the present embodiment, it further includes two or more second small solder pads 51, and the two or more second small solder pads 51 are respectively arranged in the first connection area A1 or the second connection area A2, and are located adjacent to each other and form an electrical connection, the two or more first small solder pads 50 are located on a top side of the conductive path 40, and the two or more second small solder pads 51 are located on an adjacent side of the top side of the conductive path 40; wherein any one of the two or more second small solder pads 51 is electrically connected to the conductive path 40, and any one of the two or more second small solder pads 51 is electrically connected to any one of the two or more first small solder pads 50 through another wire W2.

[0022] For other application options, see Figure 3 In the present embodiment, it further includes two or more third small solder pads 52 and two or more fourth small solder pads 53, the two or more third small solder pads 52 are respectively arranged in the first connection area A1 or the second connection area A2, and the two or more third small solder pads 52 are located adjacent to each other and form an electrical connection; the two or more fourth small solder pads 53 are respectively arranged in the first connection area A1 or the second connection area A2, and the two or more fourth small solder pads 53 are located adjacent to each other and form an electrical connection; the two or more third small solder pads 52 are located at the other adjacent side of the top side of the conductive path 40, and the two or more fourth small solder pads 53 are located opposite to the two or more first small solder pads 50. In the present embodiment, the two or more fourth small solder pads 53 are located at a bottom side of the conductive path 40, and the bottom side is opposite to the top side.

[0023] Among them, any one of the two or more third small pads 52 is electrically connected to the conductive path 40, any one of the two or more fourth small pads 53 is electrically connected to the conductive path 40, any one of the two or more third small pads 52 is electrically connected to any one of the two or more first small pads 50 through another wire W3, any one of the two or more fourth small pads 53 is electrically connected to any one of the two or more second small pads 51 through another wire W4, and any one of the two or more fourth small pads 53 is electrically connected to any one of the two or more third small pads 52 through another wire W5. It must be particularly noted that all the small pads 50, 51, 52, 53 in the present invention can be respectively arranged not only in the first connection area A1, but also in the second connection area A2. In this embodiment, it is only an example, and the spatial configuration of all the small pads 50, 51, 52, 53 is not limited.

[0024] In addition, in this embodiment, the area of ​​the two or more first small pads 50, the two or more second small pads 51, the two or more third small pads 52, and the two or more fourth small pads 53 is between 900 and 7225 square micrometers (μm 2 ) to provide a more suitable welding space and space utilization.

[0025] For the second embodiment of the present invention, please refer to Figure 2 , Figure 4 , its main technical contents are roughly the same as those of the first embodiment, such as Figure 4 As shown, the main difference is that this embodiment further includes a first elongated pad 70, and the first elongated pad 70 is arranged in the second connection area A2; wherein, the first elongated pad 70 is electrically connected to any one of the more than two second small pads 51 through another conductive wire W6, and the first elongated pad 70 is electrically connected to any one of the more than two first small pads 50 through another conductive wire W7.

[0026] See also Figure 5Another difference between the present embodiment and the first embodiment is that the present embodiment further includes a second elongated pad 71, a third elongated pad 72 and a fourth elongated pad 73. The second elongated pad 71, the third elongated pad 72 and the fourth elongated pad 73 are respectively arranged in the second connection area A2. In the present embodiment, the first to fourth elongated pads 70, 71, 72, 73 may be unconnected, connected, non-overlapping or overlapping with each other. The second long solder pad 71 is electrically connected to any one of the two or more second small solder pads 51 through another wire W8, and the second long solder pad 71 is electrically connected to any one of the two or more fourth small solder pads 53 through another wire W9; the third long solder pad 72 is electrically connected to any one of the two or more fourth small solder pads 53 through another wire W10, and the third long solder pad 72 is electrically connected to any one of the two or more third small solder pads 52 through another wire W11; the fourth long solder pad 73 is electrically connected to any one of the two or more third small solder pads 52 through another wire W12, and the fourth long solder pad 73 is electrically connected to any one of the two or more first small solder pads 50 through another wire W13.

[0027] In addition, in this embodiment, the area of ​​the first elongated pad 70, the second elongated pad 71, the third elongated pad 72 and the fourth elongated pad 73 is between 2800 and 14800 μm. 2 To provide more extensible welding space and space utilization.

[0028] For the third embodiment of the present invention, please refer to Figure 6 , its main technical contents are roughly the same as those of the above embodiments, such as Figure 4 , Figure 6 , but the main difference is that this embodiment provides more than two fifth small solder pads 54 to replace the long solder pads in the second embodiment; in this embodiment, the two or more fifth small solder pads 54 are respectively arranged in the second connection area A2, and the two or more fifth small solder pads 54 are located adjacent to each other and form an electrical connection; wherein any one of the two or more fifth small solder pads 54 is electrically connected to any one of the two or more second small solder pads 51 through another wire W14, and any one of the two or more fifth small solder pads 54 is electrically connected to any one of the two or more first small solder pads 50 through another wire W15.

[0029] In addition, in this embodiment, the area of ​​the two or more fifth small pads 54 is between 900 and 7225 μm. 2 To provide more flexible welding space and space utilization.

[0030] The fourth embodiment of the present invention provides another integrated circuit capable of reducing the number of power pins. Figure 7 As shown, it includes a packaging shell 100, a power pin terminal 200, a die 300, a ring-shaped conductive path 400, two or more first elongated solder pads 500 and a large solder pad 600. However, the difference between this embodiment and the aforementioned embodiments is that this embodiment further provides the two or more first elongated solder pads 500 and the large solder pad 600. The two or more first elongated solder pads 500 can replace the solder pads in the first connection area A1 or the second connection area A2 in the aforementioned embodiments, and the large solder pad 600 can also replace the solder pads in the first connection area A1 or the second connection area A2 in the aforementioned embodiments.

[0031] In this embodiment, if Figure 7 As shown, the power pin terminal 200 can also be passed through the packaging shell 100, the die 300 is arranged inside the packaging shell 100, the conductive path 400 is arranged in a ring shape on the die 300, and is also in a U-shape, and a first connection area A10 is formed between the conductive path 400 and the outer edge of the die 300, and a second connection area A20 is formed by the U-shape inside of the conductive path 400 in a ring shape, and the two or more first elongated pads 500 are respectively arranged at relative positions of the first connection area A10.

[0032] In this embodiment, Figure 7 As shown, the relative position of the first connection area A10 refers to the non-adjacent side, and the two or more first elongated pads 500 can be disposed on the top side and the bottom side of the first connection area A10; or in this embodiment, the two or more first elongated pads 500 can also be disposed on two adjacent sides of the first connection area A10, which is only an example and not a limitation. Among them, the two or more first elongated pads 500 are electrically connected to the conductive path 400, and any one of the two or more first elongated pads 500 is electrically connected to the power pin terminal 200 through a wire WR1; through the two or more first elongated pads 500, a more extensible welding space and space utilization can be provided for the first connection area A10.

[0033] In this embodiment, the large solder pad 600 can be set at any position within the second connection area A20, and can be located at a central position in this embodiment. The large solder pad 600 is electrically connected to the two or more first long solder pads 500 through two or more other wires WR2. The large solder pad 600 can reduce the welding space within the second connection area A20 and improve space utilization.

[0034] The present invention reduces the number of power pins by setting the two or more first long pads 500 in the first connection area A10 and the large pad 600 in the second connection area A20, and the power pin terminal 200 is connected to any one of the two or more first long pads 500 through the wire WR1, so as to increase the expandable functionality of the I / O pins in the integrated circuit.

[0035] In this embodiment, to improve its application, please refer to Figure 8 , which further includes more than two second elongated pads 510, and the more than two second elongated pads 510 can also replace the pads in the first connection area A1 or the second connection area A2 in the aforementioned embodiments; in this embodiment, the more than two second elongated pads 510 are respectively arranged at another relative position of the first connection area A10, and are arranged at different positions from the more than two first elongated pads 500, and the more than two second elongated pads 510 can be arranged on two adjacent sides of the conductive path 400, or on the top and bottom sides of the first connection area A10; wherein the more than two second elongated pads 510 are electrically connected to the conductive path 400, and the large pad 600 is electrically connected to the more than two second elongated pads 510 through another two or more wires WR3.

[0036] In addition, in this embodiment, the area of ​​the two or more first elongated pads 500 and the two or more second elongated pads 510 is between 2800 and 14800 μm. 2 The area of ​​the large pad 600 is between 2800 and 34225 μm 2 In order to provide a more extensible and flexible welding space and improve space utilization.

Claims

1. An integrated circuit capable of reducing power pins, characterized in that: include: a packaging shell; A power pin terminal is provided on the package shell; A die is disposed inside the package shell; a conductive path disposed on the die and having a first connection region between the conductive path and an outer edge of the die; and Two or more first small solder pads are arranged in the first connection area and are adjacently connected; Wherein, any one of the two or more first small solder pads is connected to the conductive path, and any one of the two or more first small solder pads is connected to the power pin terminal through a wire.

2. The integrated circuit capable of reducing power pins according to claim 1, characterized in that: A second connection area is provided between the conductive path and the outer edge of the crystal grain, and the two or more first small pads are arranged in the first connection area or the second connection area.

3. The integrated circuit capable of reducing power pins according to claim 2, characterized in that: The conductive path is arranged on the die in an annular shape, and the second connection area is formed by the inner part of the conductive path in an annular shape.

4. The integrated circuit capable of reducing power pins according to claim 2 or 3, characterized in that: Further comprising two or more second small pads, wherein the two or more second small pads are arranged in the first connection area or the second connection area and are adjacently connected; Wherein, any one of the two or more second small pads is connected to the conductive path, and any one of the two or more second small pads is connected to any one of the two or more first small pads through another conductive wire.

5. The integrated circuit capable of reducing power pins according to claim 4, characterized in that: Further comprising more than two third small pads and more than two fourth small pads, wherein the more than two third small pads are disposed in the first connection area or the second connection area and are adjacently connected; the more than two fourth small pads are disposed in the first connection area or the second connection area and are adjacently connected; Among them, any one of the two or more third small solder pads is connected to the conductive path, any one of the two or more fourth small solder pads is connected to the conductive path, any one of the two or more third small solder pads is connected to any one of the two or more first small solder pads through another wire, any one of the two or more fourth small solder pads is connected to any one of the two or more second small solder pads through another wire, and any one of the two or more fourth small solder pads is connected to any one of the two or more third small solder pads through another wire.

6. The integrated circuit capable of reducing power pins according to claim 2 or 3, characterized in that: Further comprising two or more second small pads and a first long pad, wherein the two or more second small pads are arranged in the first connection area or the second connection area and are adjacently connected, and the first long pad is arranged in the second connection area; Among them, any one of the two or more second small solder pads is connected to the conductive path, the first long solder pad is connected to any one of the two or more second small solder pads through another conductive wire, and the first long solder pad is connected to any one of the two or more first small solder pads through another conductive wire.

7. The integrated circuit capable of reducing power pins according to claim 6, characterized in that: Further comprising more than two third small pads, more than two fourth small pads, a second long pad, a third long pad and a fourth long pad, wherein the more than two third small pads are arranged in the first connection area or the second connection area and are adjacently connected; the more than two fourth small pads are arranged in the first connection area or the second connection area and are adjacently connected, and the second long pad, the third long pad and the fourth long pad are arranged in the second connection area; Among them, any one of the two or more third small solder pads is connected to the conductive path, any one of the two or more fourth small solder pads is connected to the conductive path, the second long solder pad is connected to any one of the two or more second small solder pads through another wire, and the second long solder pad is connected to any one of the two or more fourth small solder pads through another wire; the third long solder pad is connected to any one of the two or more fourth small solder pads through another wire, and the third long solder pad is connected to any one of the two or more third small solder pads through another wire; the fourth long solder pad is connected to any one of the two or more third small solder pads through another wire, and the fourth long solder pad is connected to any one of the two or more first small solder pads through another wire.

8. The integrated circuit capable of reducing power pins according to claim 2 or 3, characterized in that: Further comprising more than two second small pads and more than two fifth small pads, wherein the more than two second small pads are arranged in the first connection area or the second connection area and are adjacently connected, and the more than two fifth small pads are arranged in the second connection area and are adjacently connected; Among them, any one of the two or more second small solder pads is connected to the conductive path, any one of the two or more fifth small solder pads is connected to any one of the two or more second small solder pads through another conductive wire, and any one of the two or more fifth small solder pads is connected to any one of the two or more first small solder pads through another conductive wire.

9. An integrated circuit capable of reducing power pins, characterized in that: include: a packaging shell; A power pin terminal is provided on the package shell; A die is disposed inside the package shell; an annular conductive path, which is disposed on the crystal grain and forms a first connection area between the conductive path and the outer edge of the crystal grain, and a second connection area is formed by the inside of the conductive path; Two or more first elongated pads are arranged at relative positions of the first connection area; wherein the two or more first elongated pads are connected to the conductive path, and any one of the two or more first elongated pads is connected to the power pin terminal through a wire; and A large pad is provided in the second connection area, and the large pad is connected to the two or more first elongated pads through two or more other conductive wires.

10. The integrated circuit capable of reducing power pins according to claim 9, characterized in that: Further comprising two or more second elongated pads, wherein the two or more second elongated pads are arranged in the first connection area and are arranged at different positions from the two or more first elongated pads; The two or more second elongated pads are connected to the conductive path, and the large pad is connected to the two or more second elongated pads respectively through another two or more conductive wires.

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