Control circuit, switching power supply, power supply system and power distribution system

Abstract

The invention discloses a control circuit, a switching power supply, a power supply system and a power distribution system, and the control circuit comprises a first biasing circuit which is used for controlling a field-effect tube to be conducted; the turn-off circuit is used for controlling the field effect transistor to be turned off when the current in the field effect transistor flows from the drain electrode to the source electrode, and comprises a second bias circuit, a first bipolar transistor and a compensation circuit, the other end of the second biasing circuit, the base electrode of the first bipolar transistor and the first end and the second end of the compensating circuit are connected to a first node, the collector electrode of the first bipolar transistor is connected with the grid electrode of the field-effect transistor, the emitter electrode is connected with the source electrode of the field-effect transistor, and the third end of the compensating circuit is connected with the drain electrode of the field-effect transistor; the compensation circuit is used for compensating the voltage between the source electrode and the drain electrode of the field effect transistor and the voltage between the base electrode and the emitter electrode of the first bipolar transistor. The field effect transistor is low in conduction voltage drop and high in turn-off speed, and the efficiency and applicability of a switching power supply and a power distribution system are improved.

Description

Technical Field

[0001] The present invention belongs to the field of switching power supplies, and in particular relates to a control method of an ORing circuit and a circuit thereof, a switching power supply, and a power distribution system having the switching power supply. Background Art

[0002] The application of ORing circuit (automatic switching anti-backflow circuit) in switching power supplies is currently very widespread, especially in the need for parallel operation and multi-channel redundant power supplies. Multiple small current power supplies in parallel usually use diodes directly to prevent backflow. However, in high current applications, such as new energy vehicle charging piles and other power distribution system applications, diodes will cause significant losses and heat problems. Therefore, MOSFET-based ORing circuits have become the most popular demand in the power supply industry. In order to prevent a single power supply output short-circuit fault from pulling down the bus voltage, it is necessary to quickly turn off the MOSFET by detecting the voltage across the MOSFET, and prevent current backflow by reverse-biasing the MOSFET body diode. It is also necessary to ensure output voltage accuracy and low cost. Summary of the invention

[0003] In view of this, the technical problem to be solved by the present invention is to provide a control circuit, a switching power supply, a power supply system and a power distribution system, which can at least solve one of the technical problems existing in the prior art to a certain extent.

[0004] As a first aspect of the present invention, the technical solution of the control circuit provided is as follows: A control circuit for controlling the on and off of a field effect tube, wherein the source of the field effect tube is used to connect to the output of a power supply, and the drain of the field effect tube is used to connect to a bus, wherein the control circuit comprises: A first bias circuit, used for controlling the field effect transistor to remain turned on, wherein one end of the first bias circuit is used for inputting a first bias voltage, and the other end is used for connecting to the gate of the field effect transistor; A shutdown circuit, used for controlling the field effect tube to shut down when the current in the field effect tube flows from the drain to the source, the shutdown circuit comprising a second bias circuit, a first bipolar transistor and a compensation circuit, one end of the second bias circuit is used to input a second bias voltage, the other end of the second bias circuit, the base of the first bipolar transistor, the first end of the compensation circuit and the second end of the compensation circuit are connected to a first node, the collector of the first bipolar transistor is used to connect the gate of the field effect tube, the emitter of the first bipolar transistor is used to connect the source of the field effect tube, and the third end of the compensation circuit is used to connect the drain of the field effect tube; The compensation circuit is used to compensate for the voltage between the source and the drain of the field effect transistor and the voltage between the base and the emitter of the first bipolar transistor, thereby reducing the conduction voltage drop of the field effect transistor when the current in the field effect transistor flows from the source to the drain, and increasing the turn-off speed of the field effect transistor when the current in the field effect transistor flows from the drain to the source.

[0005] Preferably, the compensation circuit comprises a second bipolar transistor and a third bipolar transistor, the base of the second bipolar transistor and the base of the third bipolar transistor are connected together to form a first end of the compensation circuit, the collector of the second bipolar transistor is a second end of the compensation circuit, the emitter of the second bipolar transistor is connected to the emitter of the third bipolar transistor, and the collector of the third bipolar transistor is a third end of the compensation circuit; The voltage between the collector and the emitter of the second bipolar transistor is a first compensation voltage, which compensates the voltage between the base and the emitter of the first bipolar transistor; The voltage between the emitter and the collector of the third bipolar transistor is a second compensation voltage, which compensates the voltage between the source and the drain of the field effect transistor.

[0006] Furthermore, the second bipolar transistor and the first bipolar transistor have the same specifications.

[0007] Furthermore, the third bipolar transistor is a bipolar transistor whose voltage between the emitter and the collector is consistent with the conduction voltage drop of the field effect transistor.

[0008] Further, the first bipolar transistor, the second bipolar transistor and the third bipolar transistor are each packaged separately, or two of them are packaged together, or the three are packaged together. Preferably, the first bias circuit is a resistor R1 and / or the second bias circuit is a resistor R2.

[0009] Furthermore, the first bias voltage and the second bias voltage are the same.

[0010] Preferably, the compensation circuit comprises a second bipolar transistor and a third bipolar transistor, the base of the second bipolar transistor and the base of the third bipolar transistor are connected together to form a first end of the compensation circuit, the collector of the second bipolar transistor is a second end of the compensation circuit, the emitter of the second bipolar transistor is connected to the emitter of the third bipolar transistor, and the collector of the third bipolar transistor is a third end of the compensation circuit; The first bias circuit is a resistor R1; The second bias circuit is a resistor R2; The first bias voltage and the second bias voltage are the same.

[0011] As a first aspect of the present invention, the technical solution of the embodiment of the switching power supply provided is as follows: A switching power supply, comprising a field effect transistor, wherein the field effect transistor is arranged in an output circuit inside the switching power supply, and the switching power supply also comprises a control circuit of any of the above schemes.

[0012] As a third aspect of the present invention, the technical solution of the embodiment of the switching power supply provided is as follows: A power supply system, wherein: the power supply system includes N switching power supplies and N field effect transistors, N is a natural number greater than or equal to 2, the source of each field effect transistor is used to connect to the output of a switching power supply, and the drain is used to connect to a bus, the power supply system also includes N control circuits as described in any one of claims 1 to 7, each of the control circuits is used to control the conduction and shutdown of one of the N field effect transistors.

[0013] As a fourth aspect of the present invention, there is provided a power distribution system, which includes the above-mentioned switching power supply.

[0014] The beneficial effects of the present invention are: 1. A compensation circuit is provided in the control circuit of the embodiment of the present invention, which can compensate the voltage between the source and the drain of the field effect tube, so that the conduction voltage drop of the field effect tube can be reduced when the current in the field effect tube flows from the source to the drain, so that the conduction voltage drop of the field effect tube is reduced to about 30mV, thereby improving the power supply efficiency; 2. The compensation circuit provided in the control circuit of the embodiment of the present invention can also compensate for the voltage between the base and the emitter of the bipolar transistor, thereby increasing the turn-off speed of the field effect transistor when the current in the field effect transistor flows from the drain to the source, making the backflow current of the field effect transistor smaller, improving the power supply reliability, and further improving the applicability of the power supply system and the power distribution system. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a circuit schematic diagram of a first existing ORing circuit; Figure 2 is a circuit schematic diagram of a second conventional ORing circuit; Figure 3 is a circuit schematic diagram of a third existing ORing circuit; Figure 4 It is a structural schematic diagram of an existing NPN bipolar transistor; Figure 5 is a circuit schematic diagram of a fourth conventional ORing circuit; Figure 6 A specific circuit schematic diagram of the control circuit of the first embodiment of the present invention; Figure 7 for Figure 6 The circuit's working waveform simulation diagram; Figure 8 for Figure 6 The application schematic diagram of the circuit in the current-sharing parallel power supply system; Fig. 9 for Figure 8 Simulation diagram of the circuit's working waveform. DETAILED DESCRIPTION

[0016] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other.

[0017] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0018] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application are described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, the process, method, system, product or equipment comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0019] It should be understood that, in the specification, claims and drawings, when a step is described as being connected to another step, the step may be directly connected to the other step, or be connected to the other step through a third step; when an element / unit is described as being "connected" to another element / unit, the element / unit may be "directly connected" to the other element / unit, or be "connected" to the other element / unit through a third element / unit.

[0020] In addition, the drawings of the present disclosure are only schematic diagrams of the present disclosure and are not necessarily drawn to scale. The same symbols in the drawings represent the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented using software, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontrollers.

[0021] The ORing circuit based on MOSFET is a hot demand in the power supply industry. The inventor of this application has conducted in-depth research on the prior art and found that although the on and off control of MOSFET can be achieved by only a few components, the effect is not satisfactory. The reason is that the circuit design of the prior art mainly stays at the application layer, ignoring the working mechanism of the physical layer of the components and the impact of the manufacturing process deviation on the circuit implementation performance. For this reason, the inventor of this application has conducted in-depth analysis and verification of the typical ORing circuit of the prior art, and found that there are certain defects, which are as follows: Patent No. US6060943 discloses an ORing circuit, such as Figure 1 , Figure 2 As shown (derived from the patent appendix Figure 7 , Attachment Figure 8 ). Among them, Figure 1 The ORing circuit solution described above has the disadvantages of poor accuracy of the power supply output voltage under different loads and large reverse current due to the different production processes of the bipolar transistor 56 and the diode 59, which leads to a large difference between the voltage VBE between the base and the emitter of the bipolar transistor 56 and the forward conduction voltage drop VF of the diode 59. Figure 2 The ORing circuit solution described above, because the reverse bias voltage VEB between the emitter and base of the bipolar transistor 69 is usually only about 6~7V in the industry, when a single power supply fails, the bus voltage is added to the emitter and base of the bipolar transistor 69 and the base and emitter series branch of the bipolar transistor 68, which will cause voltage stress breakdown damage to the bipolar transistors 68 and 69.

[0022] Patent No. US7636011B2 also discloses an ORing circuit, such as Figure 3 As shown (derived from the patent appendix Figure 1 ). Among them, Figure 3 The ORing circuit scheme is to obtain a diode structure formed by the base and the collector by short-circuiting the emitter and the base of the bipolar transistor 106, so as to reduce the voltage between the base and the emitter of the bipolar transistor and the voltage between the base and the collector of the bipolar transistor, so as to solve the problem of Figure 1 Program and Figure 2The inventors of this application have found that Figure 4 As shown in the structural diagram of the NPN bipolar transistor shown in the figure, after the base and emitter of the bipolar transistor are short-circuited, the PN junction between the base and the emitter is essentially short-circuited, so that the PN junction (diode) between the base and the collector is used to work. However, due to the difference in the bipolar transistor structure itself, VEB and VEC still have a large deviation, which makes the power supply accuracy and reverse current still have large defects.

[0023] The patent with publication number US8207779B2 also discloses an ORing circuit, such as Figure 5 As shown (derived from the patent appendix Figure 4 ). Among them, the added diodes D1 and D2 can effectively solve the problem Figure 2 The pressure resistance problem mentioned above can also be solved Figure 1 The problem of conduction voltage drop deviation mentioned above is solved, but the number of components is inevitably large, and the board area is large. In addition, the inventor of the present application noticed that the turn-off voltage between the gate and the source of the MOSFET is equal to the VF of the diode D1 plus the collector and emitter voltage VCE of the bipolar transistor Q1. The increase of the turn-off voltage of the MOSFET is not conducive to the application of low drive voltage MOSFET.

[0024] It should be noted that the above analysis content is only intended to deepen the understanding of the overall background technology of the present application, and should not be regarded as an admission or implication in any form that the content constitutes the prior art already known to those skilled in the art. In particular, the discovery of the above-mentioned prior art problems should not be regarded as an admission or implication in any form that the content constitutes the prior art already known to those skilled in the art.

[0025] The disclosure of the above content is only used to assist in understanding the concept and technical solution of the present application. It does not necessarily belong to the prior art of the present patent application. In the absence of clear evidence that the above content has been disclosed on the filing date of the present patent application, the above content should not be used to evaluate the novelty and creativity of the present application.

[0026] Based on the analysis of the above-mentioned prior art, the inventor of the present application proposed the inventive concept of the present application, which is specifically: a field effect tube is controlled to remain turned on through a bias circuit, and when the current in the field effect tube is reversed, the driving voltage of the gate source of the field effect tube is pulled down by the conduction of the bipolar transistor to control the field effect tube to be turned off, the driving circuit of the bipolar transistor includes a field effect tube, and a compensation circuit is set in the driving circuit of the bipolar transistor to compensate for the voltage between the source and the drain of the field effect tube and the voltage between the base and the emitter of the bipolar transistor, thereby reducing the conduction voltage drop of the field effect tube when the current in the field effect tube flows from the source to the drain, and increasing the turn-off speed of the field effect tube when the current in the field effect tube flows from the drain to the source.

[0027] First embodiment Figure 6 This is a specific circuit schematic diagram of the control circuit of the first embodiment of the present invention. This embodiment provides a control circuit for controlling the on and off of the field effect transistor FET1. The source of the field effect transistor FET1 is used to connect the output Vout of the power supply, and the drain of the field effect transistor FET1 is used to connect the bus Vbus. The control circuit includes: A first bias circuit R1 is used to control the field effect transistor FET1 to remain turned on, one end of the first bias circuit R1 is used to input a first bias voltage BIAS, and the other end is used to connect to the gate of the field effect transistor FET1; A shutdown circuit, used for controlling the field effect transistor FET1 to be turned off when the current in the field effect transistor FET1 flows from the drain to the source, the shutdown circuit comprises a second bias circuit R2, a first bipolar transistor Q1 and a compensation circuit E1, one end of the second bias circuit R2 is used for inputting a second bias voltage, the other end of the second bias circuit R2, the base of the first bipolar transistor Q1, the first end of the compensation circuit E1 and the second end of the compensation circuit E1 are connected to the first node A, the collector of the first bipolar transistor Q1 is used for connecting the gate of the field effect transistor FET1, the emitter of the first bipolar transistor Q1 is used for connecting the source of the field effect transistor FET1, and the third end of the compensation circuit E1 is used for connecting the drain of the field effect transistor FET1; The compensation circuit E1 is used to compensate the voltage between the source and the drain of the field effect transistor FET1 and the voltage between the base and the emitter of the first bipolar transistor Q1, thereby reducing the on-state voltage drop of the field effect transistor FET1 when the current in the field effect transistor FET1 flows from the source to the drain, and increasing the turn-off speed of the field effect transistor FET1 when the current in the field effect transistor FET1 flows from the drain to the source.

[0028] The control circuit of the present embodiment is provided with a compensation circuit E1, which can compensate for the voltage between the source and the drain of the field effect transistor FET1, so that when the current in the field effect transistor FET1 flows from the source to the drain, the on-state voltage drop of the field effect transistor FET1 can be reduced, so that the on-state voltage drop of the field effect transistor FET1 is reduced to about 30mV, thereby improving the power supply efficiency; the compensation circuit E1 provided in the control circuit of the present embodiment can also compensate for the voltage between the base and the emitter of the first bipolar transistor Q1, so that when the current in the field effect transistor FET1 flows from the drain to the source, the turn-off speed of the field effect transistor FET1 can be improved, so that the reverse current of the field effect transistor FET1 is smaller, and the power supply reliability is improved.

[0029] Wherein: the compensation circuit E1 includes a second bipolar transistor Q2 and a third bipolar transistor Q3. The base of the second bipolar transistor Q2 and the base of the third bipolar transistor Q3 are connected together as the first end of the compensation circuit E1, the collector of the second bipolar transistor Q2 is the second end of the compensation circuit E1, the emitter of the second bipolar transistor Q2 is connected to the emitter of the third bipolar transistor Q3, and the collector of the third bipolar transistor Q3 is the third end of the compensation circuit E1. The first bias voltage and the second bias voltage are both BIAS, and usually the ground level of BIAS is the output Vout of the power supply. The bipolar transistor of the present invention is a triode.

[0030] Figure 6 The circuit only needs three bipolar transistors and two resistors to realize the control of the ORing circuit, which occupies a small board area, has low cost and simple control.

[0031] The working principle of the control circuit of this embodiment to control the conduction of the field effect tube FET1 is combined with Figure 6 The circuit shown is analyzed as follows: When the current in the field effect transistor FET1 flows from the source to the drain, the bias resistors R1 and R2 are properly set to make the bipolar transistors Q1 and Q2 work in the amplification state, and the bipolar transistor Q3 works in the saturation state. The voltage between the base and emitter of the bipolar transistor Q2 is used to compensate the voltage between the base and emitter of the bipolar transistor Q1, and the voltage between the emitter and collector of the bipolar transistor Q3 is used to compensate the voltage between the source and drain of the field effect transistor FET1, so that when the load current changes, the driving voltage of the field effect transistor FET1 changes accordingly, but the effect of optimal efficiency can be obtained. The detailed working waveform simulation diagram is as follows Figure 7 shown.

[0032] Wherein: Vout is the output voltage of the power supply, Io is the current flowing from the source to the drain of the field effect transistor FET1, Vgs is the driving voltage from the gate to the source of the field effect transistor FET1, and Vds is the conduction voltage drop from the drain to the source of the field effect transistor FET1 (also called the drain-source voltage of the field effect transistor FET1).

[0033] The detailed analysis of the working waveform simulation diagram is as follows: Because both transistors Q1 and Q2 are working in the amplification state, the base and emitter are turned on, and the conduction voltage drop is basically unchanged, so the voltage VQ1_be between the base and emitter of transistor Q1 is approximately equal to the voltage VQ2_be between the base and emitter of transistor Q2, that is, VQ1_be≈VQ2_be and basically remains unchanged. Because the base and collector of transistor Q2 are connected, it can be obtained from the amplification working characteristics of transistor Q2 that VQ2_be≈VQ2_ce, that is, VQ1_be≈VQ2_ce, and basically remains unchanged. Transistor Q3 works in the saturation state, and the voltage VQ3_ec between the emitter and collector of transistor Q3 is ≈30mV; There are two paths for the current flowing through the bias resistor R2 from the node A to the output Vout: Path 1 is from the node A → the base of the transistor Q1 → the emitter of the transistor Q1 → the output Vout, where the current flowing is recorded as I1; Path 2 is from the node A → the collector of the transistor Q2 → the emitter of the transistor Q2 → the emitter of the transistor Q3 → the collector of the transistor Q3 → the drain of the field effect transistor FET1 → the source of the field effect transistor FET1 → the output Vout, where the current flowing is recorded as I2; Correspondingly, the voltage (VA-Vout) between node A and output Vout can be calculated through the above two current paths: Path 1 is equal to the voltage VQ1_be between the base and emitter of transistor Q1, that is, (VA-Vout)=VQ1_be; Path 2 is equal to the sum of the voltage VQ2_ce between the collector and emitter of transistor Q2, the voltage VQ3_ec between the emitter and collector of transistor Q3 and the drain-source voltage Vds of field effect transistor FET1, that is, (VA-Vout)=(VQ2_ce+VQ3_ec+Vds), so (VA-Vout)=VQ1_be=(VQ2_ce+ VQ3_ec+Vds) and is basically unchanged; When the switching power supply is working normally, the current Io flows from the source to the drain of the field effect transistor FET1, so the drain-source voltage Vds of the field effect transistor FET1 is a negative voltage. When the current Io gradually increases, the negative voltage on the drain-source voltage Vds of the field effect transistor FET1 will be forced to gradually increase, which will cause the voltage (VQ2_ce+VQ3_ec+Vds) at both ends of the above-mentioned path 2 to have a decreasing trend. In order to maintain the voltage at both ends of the path 2 unchanged, the current I2 flowing from the bias resistor R2 into the path 2 will be forced to gradually increase, thereby increasing the voltage (VQ2_ce+VQ3_ec) between point A in the path 2 and the collector of the transistor Q3 to offset the increase in the negative voltage of the drain-source voltage Vds of the field effect transistor FET1. The current I2 flowing into the second path through the bias resistor R2 becomes larger, causing the current I1 flowing into the first path to gradually decrease. Since the transistor Q1 works in the amplification state, the current flowing between the collector and the emitter of the transistor Q1 through the bias resistor R1 is forced to gradually decrease. The on-resistance of the transistor working in the amplification state is opposite to the change trend of the current flowing through the collector and the emitter. Therefore, the impedance between the collector and the emitter of the transistor Q1 increases, so the driving voltage Vgs from the gate to the source of the field effect transistor FET1 gradually increases. The increase in the driving voltage Vgs can further reduce the negative pressure on the drain-source voltage Vds of the field effect transistor FET1, thereby improving the power supply efficiency.

[0034] See also Figure 7 In the simulated waveform, the driving voltage Vgs also increases as the current Io gradually increases, proving that the above theoretical analysis is consistent with the actual working mechanism of the circuit.

[0035] On the contrary, when the current Io gradually decreases, the technicians in this field can know from the above analysis when the current Io gradually increases that the negative voltage on the drain-source voltage Vds of the field effect transistor FET1 will gradually decrease, and the current flowing into the path two from the bias resistor R2 will gradually decrease, so that the current flowing into the path one will gradually increase, and the current flowing from the bias resistor R1 between the collector and the emitter of the transistor Q1 will also gradually increase, and the impedance between the collector and the emitter of the transistor Q1 will decrease, so the driving voltage Vgs from the gate to the source of the field effect transistor FET1 will gradually decrease, preparing for the rapid shutdown of the field effect transistor FET1.

[0036] Further, Figure 6 The second bipolar transistor Q2 and the first bipolar transistor Q1 have the same specifications, so that the first compensation voltage is as consistent as possible with the voltage between the collector and the emitter of the first bipolar transistor Q1.

[0037] Further, Figure 6 The third bipolar transistor Q3 is a bipolar transistor whose voltage between the emitter and the collector is consistent with the conduction voltage drop between the drain and the source of the field effect transistor FET1, thereby ensuring the output voltage accuracy of the batch power supply.

[0038] Further, the first bipolar transistor Q1 , the second bipolar transistor Q2 , and the third bipolar transistor Q3 are each packaged separately, or two of them are packaged together, or three of them are packaged together.

[0039] It should be noted that Figure 6 The circuit also has the following two beneficial effects: (1) The problem of voltage stress damage when Vbus>Vout is solved by the high withstand voltage characteristic between the collector and base of transistor Q3.

[0040] (2) Through the low saturation voltage (about 0.1V) of the transistor Q1, it can be applied to both low driving voltage field effect transistors and high driving voltage field effect transistors, and has a wider application range.

[0041] Second embodiment This embodiment provides a switching power supply, which includes a field effect transistor, which is arranged in an output circuit inside the switching power supply. The switching power supply also includes any control circuit in the first embodiment.

[0042] Since the switching power supply of this embodiment includes any one of the control circuits in the first embodiment, the on-state voltage drop of the field effect tube can be reduced when the current in the field effect tube flows from the source to the drain, so that the on-state voltage of the field effect tube is reduced to about 30mV, thereby improving the power supply efficiency; and when the current in the field effect tube flows from the drain to the source, the turn-off speed of the field effect tube can be increased, so that the reverse current of the field effect tube is smaller, thereby improving the reliability of the power supply.

[0043] Third embodiment The present embodiment provides a power supply system, wherein: the power supply system includes N switching power supplies and N field effect transistors, N is a natural number greater than or equal to 2, the source of each field effect transistor is used to connect to the output of a switching power supply, and the drain is used to connect to a bus, and the power supply system also includes N control circuits of any one of the first embodiments, each control circuit is used to control the conduction and shutdown of one of the N field effect transistors.

[0044] Since the power supply system of this embodiment includes any one of the control circuits in the first embodiment, the on-state voltage drop of the field effect tube can be reduced when the current in the field effect tube flows from the source to the drain, so that the on-state voltage of the field effect tube is reduced to about 30mV, thereby improving the power supply efficiency; and when the current in the field effect tube flows from the drain to the source, the turn-off speed of the field effect tube can be increased, so that the backflow current of the field effect tube is smaller, thereby improving the power supply reliability.

[0045] Figure 8 for Figure 6 The circuit is used in the current-sharing parallel power supply system. Figure 8 , which includes two power supplies. The anti-reverse-flow field effect transistor of the second power supply (referred to as power supply 2) is FET2. The control circuit of the field effect transistor FET2 includes a resistor R3, a resistor R4, a transistor Q4, a transistor Q5 and a transistor Q6. The specific connection method corresponds to the connection method of each component in the control circuit of the anti-reverse-flow field effect transistor FET1 of the first power supply (referred to as power supply 1). Figure 8 The working principle of turning off the field effect tube FET1 in the control unit is analyzed as follows: When the output of power supply 1 is short-circuited, the current originally flowing from the source to the drain in the field effect transistor FET1 in power supply 1 is rapidly reduced to 0A, and the current then flows from the drain to the source and rapidly increases. At this time, by properly setting the bias resistors R1, R2, R3 and R4, the bipolar transistors Q1, Q2, Q4 and Q5 are all working in the amplification state, and the bipolar transistors Q3 and Q6 are working in the saturation state. The voltage between the base and emitter of the transistor Q2 is used to compensate the voltage between the base and emitter of the transistor Q1, and the voltage between the source and drain of FET1 is compensated by the voltage between the emitter and collector of the transistor Q3, so that the field effect transistor FET1 is quickly turned off when the current flows from the drain to the source, so that the reverse current of the field effect transistor FET1 is small, and the reliability of the power supply is improved. The detailed working waveform simulation diagram is as follows Fig. 9 As shown: Wherein: Vout1 is the output voltage of power supply 1, Vout2 is the output voltage of power supply 2, Vbus is the output voltage of the bus, Vgs1 is the driving voltage from the gate to the source of the field effect transistor FET1, Vgs2 is the driving voltage from the gate to the source of the field effect transistor FET2, Io1 is the current flowing from the source to the drain of the field effect transistor FET1, Io2 is the current flowing from the source to the drain of the field effect transistor FET2, and Ibus is the total current on the bus.

[0046] The detailed analysis of the working waveform simulation diagram is as follows: When the output of power supply 1 is short-circuited and the current originally flowing from the source to the drain in field effect transistor FET1 in power supply 1 is rapidly reduced to 0A, the working principle is as described above. Figure 7 The analysis of a single power supply has been described and will not be repeated here. The control circuit of this embodiment can be implemented to prepare for the rapid shutdown of the field effect transistor FET1; when the output of the power supply 1 is short-circuited and the current flows from the drain to the source and increases rapidly, the drain-source voltage Vds of the field effect transistor FET1 becomes a positive voltage and increases rapidly. It can be known by those skilled in the art, in combination with the analysis of the first embodiment above, that the current flowing from the bias resistor R2 into the second path rapidly decreases to 0A, thereby the current flowing into the first path rapidly increases, and the current flowing from the bias resistor R1 into the collector and emitter of the transistor Q1 also rapidly increases, and the impedance between the collector and emitter of the transistor Q1 rapidly decreases, so the driving voltage Vgs from the gate to the source of the field effect transistor FET1 rapidly decreases until the field effect transistor FET1 is turned off.

[0047] After the field effect transistor FET1 is turned off, Vout1 maintains 0V output, the collector and base of the transistor Q3 are cut off due to the reverse voltage, the transistor Q2 is in a non-working state, and the current of the second bias circuit R2 flows between the base and emitter of the transistor Q1. The transistor Q1 is saturated and turned on, and the voltage between its collector and emitter is about 0.1V, so that the field effect transistor FET1 remains reliably turned off.

[0048] Figure 8 When the output of power supply 1 is short-circuited, the working principle of the ORing circuit in power supply 2 is the same as Figure 6 The same as in, no further description is given here.

[0049] The switching power supply described in the present invention is specifically applied to power distribution systems and can be widely used in industrial control, intelligent transportation, smart grid, smart medical care, new energy, Internet of Things, communications and other fields to meet the power distribution requirements necessary for system operation.

[0050] The above are only preferred embodiments of the present invention. The above preferred embodiments should not be regarded as limiting the present invention. For those skilled in the art, several equivalent transformations, improvements and modifications can be made without departing from the spirit and scope of the present invention. These equivalent transformations, improvements and modifications should also be regarded as the protection scope of the present invention. The embodiments will not be repeated here. The protection scope of the present invention shall be based on the scope defined by the claims.

Claims

1. A control circuit for controlling the on and off of a field effect tube, wherein the source of the field effect tube is connected to the output of a power supply, and the drain of the field effect tube is connected to a bus, characterized in that: The control circuit comprises: A first bias circuit, used for controlling the field effect transistor to remain turned on, wherein one end of the first bias circuit is used for inputting a first bias voltage, and the other end is used for connecting to the gate of the field effect transistor; A shutdown circuit, used for controlling the field effect tube to shut down when the current in the field effect tube flows from the drain to the source, the shutdown circuit comprising a second bias circuit, a first bipolar transistor and a compensation circuit, one end of the second bias circuit is used to input a second bias voltage, the other end of the second bias circuit, the base of the first bipolar transistor, the first end of the compensation circuit and the second end of the compensation circuit are connected to a first node, the collector of the first bipolar transistor is used to connect the gate of the field effect tube, the emitter of the first bipolar transistor is used to connect the source of the field effect tube, and the third end of the compensation circuit is used to connect the drain of the field effect tube; The compensation circuit is used to compensate for the voltage between the source and the drain of the field effect transistor and the voltage between the base and the emitter of the first bipolar transistor, thereby reducing the conduction voltage drop of the field effect transistor when the current in the field effect transistor flows from the source to the drain, and increasing the turn-off speed of the field effect transistor when the current in the field effect transistor flows from the drain to the source.

2. The control circuit according to claim 1, characterized in that: The compensation circuit comprises a second bipolar transistor and a third bipolar transistor, the base of the second bipolar transistor and the base of the third bipolar transistor are connected together as the first end of the compensation circuit, the collector of the second bipolar transistor is the second end of the compensation circuit, the emitter of the second bipolar transistor is connected to the emitter of the third bipolar transistor, and the collector of the third bipolar transistor is the third end of the compensation circuit; The voltage between the collector and the emitter of the second bipolar transistor is a first compensation voltage, which compensates the voltage between the base and the emitter of the first bipolar transistor; The voltage between the emitter and the collector of the third bipolar transistor is a second compensation voltage, which compensates the voltage between the source and the drain of the field effect transistor.

3. The control circuit according to claim 2, characterized in that: The second bipolar transistor has the same specifications as the first bipolar transistor.

4. The control circuit according to claim 2, characterized in that: The third bipolar transistor is a bipolar transistor whose voltage between the emitter and the collector is consistent with the conduction voltage drop of the field effect transistor.

5. The control circuit according to claim 2, characterized in that: The first bipolar transistor, the second bipolar transistor and the third bipolar transistor are each packaged separately, or two of them are packaged together, or the three of them are packaged together.

6. The control circuit according to claim 1, characterized in that: The first bias circuit is a resistor R1 and / or the second bias circuit is a resistor R2.

7. The control circuit according to claim 1, characterized in that: The first bias voltage and the second bias voltage are the same.

8. The control circuit according to claim 1, characterized in that: The compensation circuit comprises a second bipolar transistor and a third bipolar transistor, the base of the second bipolar transistor and the base of the third bipolar transistor are connected together as the first end of the compensation circuit, the collector of the second bipolar transistor is the second end of the compensation circuit, the emitter of the second bipolar transistor is connected to the emitter of the third bipolar transistor, and the collector of the third bipolar transistor is the third end of the compensation circuit; The first bias circuit is a resistor R1; The second bias circuit is a resistor R2; The first bias voltage and the second bias voltage are the same.

9. A switching power supply, characterized in that: It comprises a field effect transistor, wherein the field effect transistor is arranged in an output circuit inside the switching power supply, and the switching power supply further comprises the control circuit according to any one of claims 1 to 8.

10. A power supply system, characterized in that: The power supply system includes N switching power supplies and N field effect transistors, N is a natural number greater than or equal to 2, the source of each field effect transistor is used to connect to the output of a switching power supply, and the drain is used to connect to a bus, and the power supply system also includes N control circuits as described in any one of claims 1 to 7, each of the control circuits is used to control the conduction and shutdown of one of the N field effect transistors.

11. A power distribution system, characterized in that: Includes the switching power supply described in claim 9.

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