Image sensor structure and manufacturing method thereof

Abstract

The invention discloses an image sensor structure and a manufacturing method thereof. The image sensor structure comprises a substrate; the photosensitive area of the photosensitive unit is arranged in the substrate and is positioned below the surface of the substrate; the plurality of grids are arranged on the surface of the substrate in the photosensitive area, and each grid forms a grid array arranged in multiple rows and multiple columns on the surface of the substrate; in the grid array, the row direction is the resolution direction, the column direction is the charge transmission direction, and the grids on any row are connected to the same control time sequence. According to the invention, a large-area high-density gate structure can be prevented from being formed in the pixel region, the difference between the pixel region and the logic region is effectively reduced, and the process stability and the yield are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit technology, and in particular to an image sensor structure and a manufacturing method thereof. Background Art

[0002] Time-Delay-Integration (TDI) image sensors are an evolution of linear image sensors. TDI image sensors are area array structures with linear array output working mode. They can realize multiple exposures of the same object and accumulate the results of each exposure, which is equivalent to increasing the exposure time and improving the image signal-to-noise ratio. Therefore, they are suitable for use in high-speed moving objects or scenes with insufficient light.

[0003] TDI image sensors are divided into two types: TDI CCD and TDI CMOS. Traditional TDI is generally manufactured using CCD technology. Among them, TDI CCD can achieve lossless charge transfer and accumulation without introducing additional noise. However, TDI CCD has the disadvantages of needing to be processed on a dedicated CCD process line, low integration, and high power consumption.

[0004] TDI CMOS is manufactured based on the general CMOS manufacturing process. Each pixel corresponds to a charge transfer region, and the charge transferred to this region is converted into a voltage signal through a charge amplifier module. However, the performance of image sensors with TDI CMOS structure is still poor.

[0005] like Figure 1 As shown, a top view of an existing TDI image sensor based on CMOS technology and CCD architecture is shown, which retains both the noise-free charge transfer advantage of the CCD architecture and the high integration advantage of the CMOS technology. In the existing CCDTDI image sensor, a polysilicon gate 2 structure is provided on a silicon substrate 1, which is composed of a plurality of polysilicon gates 2 arranged repeatedly. Figure 1 The horizontal direction is the resolution direction, and the vertical direction is the charge transfer direction. The polysilicon gate 2 is a long strip structure along the resolution direction. The higher the resolution, the longer the polysilicon gate 2 needs to be, and its length can reach several millimeters to tens of millimeters. The distance between the long strips of polysilicon gates 2 in the charge transfer direction is only a few microns. This will inevitably lead to a large-area and high-density distribution of polysilicon gates 2 in the entire pixel area. The area of ​​the logic circuit area on the chip only accounts for less than about 10% of the entire chip area, and the size of the polysilicon gate structure of the device in the logic circuit area is very small compared to the polysilicon gate 2 area in the pixel area. Therefore, the large size difference between the large-area polysilicon gate 2 in the pixel area and the small-size polysilicon gate structure of the device in the logic area brings great challenges to the preparation process of the polysilicon gate 2 in the pixel area. Summary of the invention

[0006] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and to provide an image sensor structure and a manufacturing method thereof.

[0007] To achieve the above object, the technical solution of the present invention is as follows: The present invention provides an image sensor structure, comprising: substrate; A photosensitive area of ​​a photosensitive unit disposed in the substrate and below the surface of the substrate; A plurality of grid electrodes are arranged on the surface of the substrate within the photosensitive area, each of the grid electrodes forms a grid array arranged in multiple rows and columns on the surface of the substrate; In the gate array, the row direction is the resolution direction, the column direction is the charge transfer direction, and each gate on any row is connected to the same control timing.

[0008] Furthermore, a first dielectric layer is provided between the gate and the surface of the substrate to form a capacitor structure.

[0009] Furthermore, an isolation region is provided in the substrate, and the isolation region is arranged below the surface of the substrate along the column direction. The isolation region divides the photosensitive region into multiple sub-photosensitive regions, and the isolation region divides the gate array into multiple sub-gate arrays corresponding to each of the sub-photosensitive regions.

[0010] Further, a first side of the photosensitive region close to the substrate surface is exposed to the surface of the substrate or is at a distance greater than zero from the surface of the substrate, a distance between a first end of the isolation region close to the substrate surface and the substrate surface is less than or equal to a distance between a first side of the photosensitive region close to the substrate surface and the substrate surface, and a distance between a second end of the isolation region far from the substrate surface and the substrate surface is greater than a distance between a second side of the photosensitive region far from the substrate surface and the substrate surface; and / or the photosensitive region forms a surface channel or a buried channel.

[0011] Furthermore, the orthographic projection of any one of the gate electrodes closest to the isolation region on the substrate surface is separated from or exactly connected to the orthographic projection of the first end of the isolation region close to the substrate surface on the substrate surface; and / or, the spacing a between any two adjacent gate electrodes on any column is equal, and the spacing b between any two adjacent gate electrodes on any row is equal, 0.05µm≤a≤b≤2µm; and / or, the width L of the isolation region along the row is less than or equal to the spacing b between any two adjacent gate electrodes on any row, and is greater than or equal to 0.1µm; and / or, the dimension c of the gate along the row and the dimension d along the column satisfy the following relationship: 0.1µm≤c≤d, d is determined by the size of a single pixel and the number of the gate electrodes in a single pixel.

[0012] Further, a second dielectric layer is provided on the surface of the substrate, a metal interconnection layer is provided in the second dielectric layer, and the gate is connected to the metal interconnection layer through a contact structure located in the second dielectric layer to connect to the control timing; and / or, the substrate comprises a P-type or N-type epitaxial silicon substrate, the thickness of the epitaxial layer is not less than 2µm, and the doping concentration is not less than 1E15cm -3 ; and / or, the photosensitive region includes an N-type photosensitive region; and / or, the isolation region includes a P-type isolation region; and / or, the gate includes a polysilicon control gate.

[0013] The present invention also provides a method for manufacturing the above-mentioned image sensor structure, comprising: providing a substrate; forming a photosensitive area of ​​a photosensitive unit located below a surface of the substrate in the substrate; A plurality of gates are formed on the surface of the substrate within the photosensitive area, and each of the gates forms a gate array arranged in multiple rows and columns on the surface of the substrate; in the gate array, the row direction is the resolution direction, and the column direction is the charge transfer direction, and each of the gates on any row is connected to the same control timing.

[0014] Furthermore, it also includes: forming an isolation region in the substrate along the column direction below the surface of the substrate, the isolation region divides the photosensitive region into multiple sub-photosensitive regions, and the isolation region divides the gate array into multiple sub-gate arrays corresponding to each of the sub-photosensitive regions.

[0015] Further, a P-type or N-type epitaxial silicon substrate is formed by a doping epitaxial process; and / or, an N-type photosensitive region located in the substrate is formed on the surface of the substrate by an ion implantation process; and / or, a P-type isolation region located in the substrate is formed on the surface of the substrate by an ion implantation process; and / or, a first dielectric layer of silicon dioxide and a polysilicon gate material layer are sequentially formed on the surface of the substrate, and a plurality of gates located on the first dielectric layer are formed on the surface of the substrate within the photosensitive region by patterning the gate material layer, thereby forming a gate array arranged in rows and columns.

[0016] Furthermore, it also includes: forming a second dielectric layer on the surface of the substrate; A metal interconnection layer and contact through holes respectively connected between the metal interconnection layer and each of the gate electrodes as a contact structure are formed in the second dielectric layer.

[0017] It can be seen from the above technical scheme that the present invention sets multiple gates on the substrate surface within the photosensitive area of ​​the photosensitive unit, so that each gate forms a gate array arranged in multiple rows and columns on the substrate surface, and connects each gate on any row along the resolution direction to the same control timing, so that the size of each gate in the pixel area can be reduced to match the gate size of the device in the logic circuit area, thereby avoiding the formation of a large-area high-density gate structure in the pixel area, effectively reducing the difference between the pixel area and the logic area, and improving the process stability and yield. In addition, when making the image sensor structure of the present invention, there is no need to add an additional mask, and no additional cost will be introduced, so it has a wide range of application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the top view structure of a photosensitive unit in an existing TDI image sensor.

[0019] Figure 2 A top view of an image sensor structure according to a preferred embodiment of the present invention.

[0020] Figure 3 A side view of an image sensor structure according to a preferred embodiment of the present invention.

[0021] Figure 4-Figure 7 The figure is a schematic diagram of the process steps of a method for manufacturing an image sensor structure according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0023] The specific implementation modes of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0024] An image sensor structure of the present invention comprises: substrate; A photosensitive area of ​​a photosensitive unit disposed in the substrate and below the surface of the substrate; A plurality of grid electrodes are arranged on the surface of the substrate within the photosensitive area, each of the grid electrodes forms a grid array arranged in multiple rows and columns on the surface of the substrate; In the gate array, the row direction is the resolution direction, the column direction is the charge transfer direction, and each gate on any row is connected to the same control timing.

[0025] refer to Figure 2-Figure 3 An image sensor structure of the present invention includes a photosensitive unit disposed on a substrate 10. The photosensitive unit includes a photosensitive region 11 and a gate 12.

[0026] The photosensitive region 11 is disposed in the substrate 10 and is located on the surface of the substrate 10 ( Figure 3 Below the upper surface of the substrate 10 shown).

[0027] There are multiple gates 12. Each gate 12 is disposed on the surface of the substrate 10 and is located within the photosensitive area 11. In addition, each gate 12 forms a gate array arranged in multiple rows and columns on the surface of the substrate 10.

[0028] For the convenience of explanation, Figure 2 The horizontal direction is defined as the row direction, and the vertical direction is defined as the column direction. Then the row direction is the resolution direction, and the column direction is the charge transfer direction.

[0029] According to the above definition, each gate 12 located in any row of the gate array is connected to the same control timing.

[0030] Furthermore, a first dielectric layer (not shown) is provided between the gate 12 and the surface of the substrate 10 to form a capacitor structure. Each gate 12 on each row is connected to the same control sequence, and the generation, collection, transfer and transmission of charge can be realized through the sequence voltage control.

[0031] In some embodiments, the first dielectric layer includes a gate dielectric layer disposed between the gate 12 and the surface of the substrate 10 .

[0032] refer to Figure 2-Figure 3 In some embodiments, the substrate 10 is further provided with an isolation region 13. The isolation region 13 is arranged along the column direction and is located below the surface of the substrate 10. The isolation region 13 separates the photosensitive region 11 into Figure 2 A plurality of sub-photosensitive areas 111 extending in a vertical direction. For example, Figure 2 and Figure 3 FIG. 2 exemplarily shows an example in which two isolation regions 13 are provided in the photosensitive region 11 to divide the photosensitive region 11 into three sub-photosensitive regions 111. However, the present invention is not limited thereto.

[0033] Furthermore, the isolation region 13 divides the gate array on the substrate 10 into a plurality of sub-gate arrays corresponding to each sub-photosensitive region 111. For example, Figure 2 and Figure 3 exemplarily shows an example of three sub-gate arrays corresponding to three sub-photosensitive areas 111. Each sub-gate array has multiple rows and columns of gates 12. The number of rows in each sub-gate array is the same, and the number of columns can be the same or different. For example, Figure 2 and Figure 3 2 shows an example in which the number of columns of the middle sub-gate array of the three sub-gate arrays is 3, and the number of columns of the two sub-gate arrays located on both sides of the middle sub-gate array is 2 each. However, the present invention is not limited thereto.

[0034] In some embodiments, the upper side of the photosensitive region 11 (sub-photosensitive region 111 ) close to the surface of the substrate 10 is exposed on the surface of the substrate 10 , such as Figure 3 shown.

[0035] In some embodiments, the upper side of the photosensitive region 11 (sub-photosensitive region 111 ) close to the surface of the substrate 10 is at a distance greater than zero from the surface of the substrate 10 .

[0036] In some embodiments, the distance between the upper end of the isolation region 13 close to the surface of the substrate 10 and the surface of the substrate 10 is less than or equal to the distance between the upper side of the photosensitive region 11 close to the surface of the substrate 10 and the surface of the substrate 10. In addition, the distance between the lower end of the isolation region 13 away from the surface of the substrate 10 and the surface of the substrate 10 is greater than the distance between the lower side of the photosensitive region 11 away from the surface of the substrate 10 and the surface of the substrate 10.

[0037] For example, the upper end of the isolation region 13 close to the surface of the substrate 10 is exposed on the surface of the substrate 10, and the depth of the lower end of the isolation region 13 in the substrate 10 is greater than the depth of the lower side of the photosensitive region 11 in the substrate 10. Figure 3 shown.

[0038] In some embodiments, the isolation region 13 is arranged along the column direction of the gate array; and both ends of the isolation region 13 in the column direction extend beyond the boundary of the photosensitive region 11 in the column direction until the photosensitive unit is on the boundary of the column direction. Figure 2 shown.

[0039] In some embodiments, two ends of the isolation region 13 in the column direction may continue to extend along the column direction into adjacent photosensitive units.

[0040] In some embodiments, when the upper side of the photosensitive region 11 (the sub-photosensitive region 111 ) is exposed on the surface of the substrate 10 , the photosensitive region 11 may form a surface channel.

[0041] In some other embodiments, when the distance between the upper side of the photosensitive region 11 (the sub-photosensitive region 111 ) and the surface of the substrate 10 is greater than zero, the photosensitive region 11 may form a buried channel.

[0042] In some embodiments, both sides of an isolation region 13 each have a column of gates 12 closest to the isolation region 13, and each gate 12 in the column is the gate 12 closest to the isolation region 13. Moreover, the orthographic projection of any gate 12 in the column closest to the isolation region 13 on the surface of the substrate 10 is separated from the orthographic projection of the upper end of the isolation region 13 on the surface of the substrate 10. Alternatively, the orthographic projection of any gate 12 in the column closest to the isolation region 13 on the surface of the substrate 10 is exactly connected to the orthographic projection of the upper end of the isolation region 13 on the surface of the substrate 10.

[0043] In some embodiments, the gates 12 on each row of the gate array may continue to extend along the row direction to be arranged in adjacent photosensitive cells.

[0044] In some embodiments, the spacing a between any two adjacent gates 12 on any column in the gate array is equal, that is, the row spacing a between any two adjacent rows is equal.

[0045] In some embodiments, the spacing b between any two adjacent gates 12 in any row of the gate array is equal, that is, the column spacing b between any two adjacent columns is equal.

[0046] In some embodiments, the above-mentioned interval a and interval b satisfy the following relationship: a≤b≤2µm; And, 0.05µm≤a≤2µm.

[0047] In some embodiments, the width L of the isolation region 13 along the row and the above-mentioned spacing b satisfy the following relationship: 0.1µm≤L≤b.

[0048] In some embodiments, the gates 12 in the gate array are of equal size.

[0049] In some embodiments, the dimension c of any gate 12 along the row and the dimension d along the column satisfy the following relationship: 0.1µm≤c≤d, where the size of d is determined by the size of a single pixel and the number of gates 12 in a single pixel.

[0050] For example, assuming a single pixel size of 10µm with 4 gates, the following equation can be established: 4d+3a=10µm Among them, the range of a is known to be 0.05µm~2µm, so the range of d is 1µm~2.4625µm.

[0051] refer to Figure 3 In some embodiments, a second dielectric layer 14 is disposed on the surface of the substrate 10 to cover the photosensitive region 11 and the gate array thereon.

[0052] In some embodiments, a metal interconnection layer 16 is disposed in the second dielectric layer 14 , and each gate 12 in the gate array is connected to the metal interconnection layer 16 to be led out.

[0053] In some embodiments, a contact structure 15 is disposed in the second dielectric layer 14 and disposed between the metal interconnect layer 16 and the gate 12. Each gate 12 is connected to the metal interconnect layer 16 via a contact structure 15 in the second dielectric layer 14 to connect to the control timing.

[0054] In some embodiments, the contact structure 15 includes a contact via 151 .

[0055] Furthermore, in the gate array, each gate 12 in a row is connected to the same metal interconnection line of the metal interconnection layer 16 through the contact via 151 to be connected to the same control timing.

[0056] In some embodiments, the substrate 10 includes a silicon substrate 101 .

[0057] Furthermore, the substrate 10 includes a P-type or N-type silicon substrate 101 .

[0058] In some embodiments, the P-type or N-type silicon substrate 101 includes a P-type or N-type epitaxial layer (not shown), and the epitaxial layer is formed by doping.

[0059] In some embodiments, the top surface of the epitaxial layer is flush with the surface of the silicon substrate 101 , and the bottom surface of the epitaxial layer is located in the silicon substrate 101 .

[0060] In some embodiments, the thickness of the epitaxial layer is not less than 2 μm.

[0061] In some embodiments, the doping concentration of the epitaxial layer is not less than 1E15 cm -3 .

[0062] In some embodiments, the photosensitive region 11 includes an N-type photosensitive region 11 .

[0063] In some embodiments, the N-type photosensitive region 11 is doped with N-type ions, such as phosphorus ions and arsenic ions, to form an N-type photoelectric doping region.

[0064] In some embodiments, the N-type photoelectric doping region is formed by performing overall doping implantation on the photosensitive region 11 .

[0065] In some embodiments, the N-type photoelectric doping region is formed by performing doping implantation on each sub-photosensitive region 111 .

[0066] Figure 2 The vertical direction is the direction of signal accumulation of the photosensitive unit, and the photogenerated signal is converted into an electrical signal for readout via the CMOS readout structure; the horizontal direction is the direction of image sensor resolution.

[0067] In some embodiments, the isolation region 13 includes a P-type isolation region 13 .

[0068] In some embodiments, the P-type isolation region 13 is formed by doping P-type ions, such as doping boron or boron fluoride plasma. The P-type isolation region 13 is located between two adjacent N-type sub-photosensitive regions 111 and vertically penetrates the charge transfer direction in the horizontal resolution direction, such as Figure 2 shown.

[0069] In some embodiments, the gate 12 includes a polysilicon control gate 121. Each polysilicon control gate 121 forms a polysilicon control gate array located on the surface of the substrate 10.

[0070] In some embodiments, the photosensitive unit includes a CCD photosensitive unit. Because the CCD photosensitive unit is embedded in the CMOS process, the timing voltage is a standard CMOS voltage, wherein the IO device voltage is ≤5V and the core device voltage is ≤2V.

[0071] The image sensor structure of the present invention can be applied to a back-illuminated TDI image sensor.

[0072] The following further describes in detail a method for manufacturing an image sensor structure of the present invention through specific implementation modes and in conjunction with the accompanying drawings.

[0073] A method for manufacturing an image sensor structure of the present invention comprises: providing a substrate; forming a photosensitive area of ​​a photosensitive unit located below a surface of the substrate in the substrate; A plurality of gates are formed on the surface of the substrate within the photosensitive area, and each of the gates forms a gate array arranged in multiple rows and columns on the surface of the substrate; in the gate array, the row direction is the resolution direction, and the column direction is the charge transfer direction, and each of the gates on any row is connected to the same control timing.

[0074] Furthermore, it also includes: forming an isolation region in the substrate along the column direction below the surface of the substrate, the isolation region divides the photosensitive region into multiple sub-photosensitive regions, and the isolation region divides the gate array into multiple sub-gate arrays corresponding to each of the sub-photosensitive regions.

[0075] The method for manufacturing an image sensor structure described above in the present invention can be used to manufacture, for example, Figure 2-Figure 3 An image sensor structure of the present invention is shown.

[0076] refer to Figure 4-Figure 7 In some embodiments, a method for manufacturing an image sensor structure of the present invention comprises the following steps: Step S1: forming a photosensitive area 11 of a photosensitive unit in a substrate 10 .

[0077] like Figure 4 As shown, a silicon substrate 101 having a P-type epitaxial layer is formed by, for example, a P-type doping epitaxial process, that is, a P-type silicon substrate 101 is formed. The thickness of the formed P-type epitaxial layer is not less than 2 μm, and the doping concentration is not less than 1E15 cm -3 .

[0078] A photoresist (not shown) is formed on the surface of the silicon substrate 101 , and an image of a photosensitive area of ​​the CCD photosensitive unit module is formed on the surface of the silicon substrate 101 by exposing and developing the photoresist.

[0079] Then, an ion implantation process is used to implant N-type doping into the silicon substrate 101 through the image window of the photosensitive region, so as to form an N-type photosensitive region 11 of the photosensitive unit in the substrate 10. Afterwards, the photoresist is removed.

[0080] Step S2 : forming an isolation region 13 in the substrate 10 .

[0081] like Figure 5As shown, a photoresist (not shown) is formed again on the surface of the silicon substrate 101, and an image of the isolation region is formed by exposing and developing the photoresist.

[0082] Then, an ion implantation process is used to implant P-type doping into the silicon substrate 101 through an image window in the isolation region, thereby forming a P-type isolation region 13 in the substrate 10 for separating the photosensitive region 11. Afterwards, the photoresist is removed.

[0083] Step S3 : forming a gate array on the surface of the substrate 10 within the photosensitive area 11 .

[0084] like Figure 6 As shown, a first dielectric layer (not shown) of silicon dioxide is formed on the surface of the silicon substrate 101 by high temperature growth, serving as a dielectric isolation layer between the gate 12 to be formed subsequently and the silicon substrate 101 .

[0085] Then, a polysilicon gate material layer is formed on the first dielectric layer on the surface of the silicon substrate 101 by using a deposition process.

[0086] Next, the polysilicon gate material layer is patterned by photolithography and etching processes, and a plurality of polysilicon gates 12 (polysilicon control gates 121 ) of the CCD photosensitive unit modules are formed on the first dielectric layer and arranged in multiple rows and columns on the surface of the silicon substrate 101 within the photosensitive area 11 , thereby forming a polysilicon gate array located above the photosensitive area 11 .

[0087] Step S4: forming a metal interconnection layer 16 connected to the gate array.

[0088] like Figure 7 As shown, a deposition process is used to form a third dielectric layer 141 such as silicon dioxide on the surface of the silicon substrate 101 to cover the first dielectric layer and the gate array.

[0089] Then, a plurality of through holes are formed downward on the surface of the third dielectric layer 141 by photolithography and etching processes, so that the bottoms of the through holes stop on the tops of the corresponding gates 12 respectively.

[0090] Next, the through holes are filled with conductive material through a deposition process, and excess conductive material on the surface of the third dielectric layer 141 is removed by chemical mechanical polishing to form contact through holes 151 on the surface of the third dielectric layer 141 whose bottoms correspond to the gates 12 and serve as contact structures 15.

[0091] Next, a fourth dielectric layer 142 is formed on the surface of the third dielectric layer 141 through a deposition process. And metal interconnection lines of the rear metal interconnection layer 16 whose bottoms respectively connect to the contact through holes 151 below are formed on the surface of the fourth dielectric layer 142 through processes such as photolithography, etching, metal filling, and planarization.

[0092] Finally, a fifth dielectric layer 143 is formed on the surface of the fourth dielectric layer 142 to cover the metal interconnect layer 16. The third dielectric layer 141, the fourth dielectric layer 142 and the fifth dielectric layer 143 together form, for example Figure 3 The second dielectric layer 14 in.

[0093] In summary, the present invention sets a plurality of gates 12 on the surface of the substrate 10 within the photosensitive area 11 of the photosensitive unit, so that each gate 12 forms a gate array arranged in multiple rows and columns on the surface of the substrate 10, and connects each gate 12 on any row along the resolution direction to the same control timing, so that the size of each gate 12 in the pixel area can be reduced to match the gate size of the device in the logic circuit area, thereby avoiding the formation of a large-area high-density gate structure in the pixel area, effectively reducing the difference between the pixel area and the logic area, and improving the process stability and yield. In addition, when making the image sensor structure of the present invention, there is no need to add an additional mask, and no additional cost will be introduced, so it has a wide range of application prospects.

[0094] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. An image sensor structure, characterized in that: include: substrate; A photosensitive area of ​​a photosensitive unit disposed in the substrate and below the surface of the substrate; A plurality of grid electrodes are arranged on the surface of the substrate within the photosensitive area, each of the grid electrodes forms a grid array arranged in multiple rows and columns on the surface of the substrate; In the gate array, the row direction is the resolution direction, the column direction is the charge transfer direction, and each gate on any row is connected to the same control timing.

2. The image sensor structure according to claim 1, characterized in that: A first dielectric layer is arranged between the gate and the surface of the substrate to form a capacitor structure.

3. The image sensor structure according to claim 1, characterized in that: An isolation region is also provided in the substrate, and the isolation region is provided below the surface of the substrate along the column direction. The isolation region divides the photosensitive region into a plurality of sub-photosensitive regions, and the isolation region divides the gate array into a plurality of sub-gate arrays corresponding to each of the sub-photosensitive regions.

4. The image sensor structure according to claim 3, characterized in that: A first side of the photosensitive region close to the substrate surface is exposed on the surface of the substrate or is at a distance greater than zero from the surface of the substrate, a distance between a first end of the isolation region close to the substrate surface and the substrate surface is less than or equal to a distance between a first side of the photosensitive region close to the substrate surface and the substrate surface, and a distance between a second end of the isolation region far from the substrate surface and the substrate surface is greater than a distance between a second side of the photosensitive region far from the substrate surface and the substrate surface; and / or the photosensitive region forms a surface channel or a buried channel.

5. The image sensor structure according to claim 3, characterized in that: The orthographic projection of any one of the gate electrodes closest to the isolation region on the substrate surface is separated from or just connected to the orthographic projection of the first end of the isolation region close to the substrate surface on the substrate surface; and / or, the spacing a between any two adjacent gate electrodes on any column is equal, and the spacing b between any two adjacent gate electrodes on any row is equal, 0.05µm≤a≤b≤2µm; and / or, the width L of the isolation region along the row is less than or equal to the spacing b between any two adjacent gate electrodes on any row, and is greater than or equal to 0.1µm; And / or, the dimension c of the gate along the row and the dimension d along the column satisfy the following relationship: 0.1µm≤c≤d, where d is determined by the size of a single pixel and the number of the gates in a single pixel.

6. The image sensor structure according to claim 3, characterized in that: A second dielectric layer is provided on the surface of the substrate, a metal interconnection layer is provided in the second dielectric layer, and the gate is connected to the metal interconnection layer through a contact structure located in the second dielectric layer to connect to the control timing; and / or, the substrate comprises a P-type or N-type epitaxial silicon substrate, the thickness of the epitaxial layer is not less than 2µm, and the doping concentration is not less than 1E15cm -3 ; and / or, the photosensitive region includes an N-type photosensitive region; and / or, the isolation region includes a P-type isolation region; and / or, the gate includes a polysilicon control gate.

7. A method for manufacturing an image sensor structure according to any one of claims 1 to 6, characterized in that: include: providing a substrate; forming a photosensitive area of ​​a photosensitive unit located below a surface of the substrate in the substrate; A plurality of gates are formed on the surface of the substrate within the photosensitive area, and each of the gates forms a gate array arranged in multiple rows and columns on the surface of the substrate; in the gate array, the row direction is the resolution direction, and the column direction is the charge transfer direction, and each of the gates on any row is connected to the same control timing.

8. The method for manufacturing an image sensor structure according to claim 7, characterized in that: Also includes: An isolation region is formed in the substrate along the column direction and below the surface of the substrate. The isolation region divides the photosensitive region into a plurality of sub-photosensitive regions, and the isolation region divides the gate array into a plurality of sub-gate arrays corresponding to each of the sub-photosensitive regions.

9. The method for manufacturing an image sensor structure according to claim 8, characterized in that: Forming a P-type or N-type epitaxial silicon substrate by a doping epitaxial process; and / or forming an N-type photosensitive region located in the substrate on the surface of the substrate by an ion implantation process; And / or, a P-type isolation region is formed on the surface of the substrate through an ion implantation process; and / or, a first dielectric layer of silicon dioxide and a polysilicon gate material layer are sequentially formed on the surface of the substrate, and a plurality of gates are formed on the first dielectric layer on the surface of the substrate within the photosensitive area by patterning the gate material layer, thereby forming a gate array arranged in rows and columns.

10. The method for manufacturing an image sensor structure according to claim 8, characterized in that: Also includes: forming a second dielectric layer on the surface of the substrate; A metal interconnection layer and contact through holes respectively connected between the metal interconnection layer and each of the gate electrodes as a contact structure are formed in the second dielectric layer.

Images