Silicon heterojunction solar cell and copper grid line edge cutting method thereof

Abstract

The invention discloses a silicon heterojunction solar cell and a copper grid line edge cutting method thereof, and relates to the field of solar cells, and the copper grid line edge cutting method comprises the steps: providing a silicon wafer with metal seed layers deposited on the front and back surfaces; mask layers are formed on the front face and the back face of the silicon wafer, the width of each mask layer is smaller than that of the silicon wafer, and the distance between the edge of each mask layer and the edge of the silicon wafer ranges from 0.1 mm to 0.5 mm; exposing the silicon wafer; etching areas where the mask layers are not formed on the front and back surfaces of the silicon wafer; developing the silicon wafer, then removing unexposed areas on the front and back surfaces of the silicon wafer, and forming groove pattern layers on the front and back surfaces of the silicon wafer; forming a copper grid line layer and an anti-oxidation metal layer on the groove pattern layer; and removing the mask layer and the metal seed layer to obtain a finished product. The method has the beneficial effects that the mask does not wrap the edges of the side surfaces and the front surface of the battery, and metal and ITO (Indium Tin Oxide) which are plated on the side surfaces in a winding manner are etched by using etching liquid before electroplating, so that the side surfaces, the front surface and the back surface are silicon during electroplating and cannot be electroplated with metal, edge covering equipment and consumables are reduced, the ITO area of the back surface is increased, and the power generation efficiency is improved.

Description

Technical Field

[0001] The invention relates to the field of solar cells, and in particular to a silicon heterojunction solar cell and a copper grid line engraving method thereof. Background Art

[0002] Among many types of solar cells, silicon heterojunction solar cells have gradually established a significant dominant position in the photovoltaic industry due to their advantages such as high conversion efficiency, low temperature coefficient, no LID and PID attenuation. An important reason for the high efficiency of silicon heterojunction cells is that the excellent passivation effect of the intrinsic amorphous silicon film on the surface of the crystalline silicon substrate ensures the high open circuit voltage of the cell. The passivation effect of the intrinsic amorphous silicon film on the crystalline silicon surface is closely related to the thin film deposition process. The thin film deposition process is optimized to reduce the recombination of carriers at the amorphous silicon / crystalline silicon interface, improve the interface passivation ability, and thus increase the cell open circuit voltage. However, the cost of heterojunction solar cells has remained high due to the use of low-temperature silver paste on the front and back sides, making it difficult to further mass-produce.

[0003] The grid lines of solar cells collect and conduct current. From the perspective of conductivity, the wider and denser the grid lines are, the lower the resistance loss is. However, for the front surface of the cell, the shielding effect of the metal grid lines on the incident light is an important cause of current loss. Therefore, the core of the cell grid line graphic design is how to strike a balance between light shielding loss and conductivity. The backlight surface of the cell can be all metal or have wide grid lines.

[0004] In order to improve the conversion efficiency of cells and reduce the cost of grid line process, the number of solar cell main grids has gone from 2 to 3 to 5 or even more than 10 as the size of silicon wafers has increased in the past few years, and the currently popular multi-busbar technology has emerged. There is also a process that has been changed from silver aluminum paste screen printing to wet film lithography as a mask and electroplating copper grid deposition.

[0005] The copper grid of the heterojunction battery has lower resistance than the silver grid and higher power conversion efficiency. The copper grid technology solution is to use a mask to make the grid line pattern on the conductive layer and the seed layer, and electroplate copper-tin metal on the mask grooves.

[0006] In the prior art, after the transparent conductive layer TCO and the copper seed layer are sputtered on the heterojunction battery, because TCO and copper will be sputtered around the side of the battery, copper will be plated on the side when the copper grid is electroplated, resulting in leakage and short circuit on both sides of the battery. The conventional battery side insulation method is to wrap the edge of the battery with a mask such as ink before electroplating to prevent the side from being electroplated with metal during electroplating. However, wrapping the edge of the battery with a mask such as ink before electroplating requires two processes: wrapping and curing. The wrapping process can be done by screen printing. During mass production, there will be ink on the screen printing platform, and repeated processes are difficult to achieve. Another problem is that when screen printing, the screen is larger than the battery, and it is difficult for the printed ink to flow down the edge of the battery. Double-sided printing will leave ink on the side of the battery cell, and it is difficult to cover the entire side. Summary of the invention

[0007] The purpose of the present invention is to solve at least one of the technical problems existing in the prior art and to provide a silicon heterojunction solar cell and a copper grid line engraving method thereof.

[0008] The technical solution of the present invention is as follows:

[0009] A first aspect of the present invention provides a method for engraving copper grid lines of a silicon heterojunction solar cell, comprising the following steps:

[0010] Providing a silicon wafer with metal seed layers deposited on the front and back sides;

[0011] Forming a mask layer on the front and back sides of the silicon wafer, wherein the width of the mask layer is smaller than the width of the silicon wafer, and the distance between the edge of the mask layer and the edge of the silicon wafer is 0.1 mm to 0.5 mm;

[0012] exposing the silicon wafer;

[0013] Etching the copper regions at the edge of the silicon wafer where the mask layer is not formed on the front and back sides of the silicon wafer;

[0014] Developing the silicon wafer, then removing the unexposed areas on the front and back sides of the silicon wafer, and forming groove pattern layers on the front and back sides of the silicon wafer;

[0015] Etching the ITO regions at the edges of the silicon wafer where the mask layer is not formed on the front and back sides of the silicon wafer;

[0016] forming a copper gate line layer on the groove pattern layer, and forming an anti-oxidation metal layer on the copper gate line layer;

[0017] The mask layer and the metal seed layer on the front and back sides of the silicon wafer are removed to obtain copper grid lines.

[0018] Optionally, the step of forming a mask layer on the front and back sides of the silicon wafer specifically includes:

[0019] A layer of photosensitive material with a thickness of 5um-50um is coated on the front and back sides of the silicon wafer, and the photosensitive material is cured by drying at 80°C-200°C for 5min-30min to form a mask layer;

[0020] The width of the mask layer is smaller than the width of the silicon wafer, and the distance between the edge of the mask layer and the edge of the silicon wafer is 0.1 mm to 0.45 mm.

[0021] Optionally, the distance between the edge of the mask layer and the edge of the silicon wafer is 0.1 mm to 0.4 mm.

[0022] Optionally, the distance between the edge of the mask layer and the edge of the silicon wafer is 0.1 mm to 0.3 mm.

[0023] Optionally, the step of etching the areas on the front and back sides of the silicon wafer where the mask layer is not formed specifically includes:

[0024] Etching the edges of the front and back sides of the silicon wafer using a first etching solution to remove the metal seed layer at the edges of the front and back sides of the silicon wafer that are not protected by the mask layer;

[0025] The first etching solution includes persulfate composite salt and dilute sulfuric acid, the concentration of the persulfate composite salt is 10 g / L to 20 g / L, and the concentration of the dilute sulfuric acid is 11 g / L to 18.4 g / L.

[0026] Optionally, the silicon wafer having the metal seed layer deposited on the front and back sides, before depositing the metal seed layer, a transparent conductive film is also deposited on the front and back sides of the silicon wafer;

[0027] Optionally, an ITO etching solution or dry etching is used to etch the edge ITO regions on the front and back sides of the silicon wafer where the mask layer is not formed;

[0028] Wherein, the ITO etching solution is hydrochloric acid with a mass concentration of 3% to 22%; or a mixture of oxalic acid, hydrochloric acid, water, a metal complexing agent, polymethyl hydrogen siloxane and vinyl glycol ether;

[0029] The dry etching method comprises: overlapping a plurality of battery cells, using at least one of SF6, CF4, and CHF3 to dissociate free radicals, and bombarding the battery side with Ar ions to perform dry etching.

[0030] Specifically, after development, 3% to 22% hydrochloric acid or a mixture of oxalic acid, hydrochloric acid, water, a metal complexing agent, polymethylhydrogensiloxane and vinyl glycol ether is used to etch the edges of both ends of the front and back sides of the silicon wafer to remove the transparent conductive film at the edges of both ends of the front and back sides of the silicon wafer that are not protected by the mask layer;

[0031] Alternatively, several battery cells are overlapped, and at least one of SF6, CF4, and CHF3 is used to dissociate free radicals, and Ar ions are added to bombard the side of the battery for dry etching.

[0032] Among them, the middle developing part of the silicon battery has copper as a mask, and the transparent conductive film under the copper will not be etched.

[0033] Optionally, the anti-oxidation metal layer has a thickness of 50 nm-10000 nm, and the anti-oxidation metal layer includes at least one of tin and silver.

[0034] A second aspect of the present invention provides a copper grid line of a silicon heterojunction solar cell, which is prepared by the above method.

[0035] A third aspect of the present invention provides a method for preparing a silicon heterojunction solar cell, characterized in that the copper grid lines of the heterojunction cell are prepared by the above method.

[0036] A fourth aspect of the present invention provides a silicon heterojunction solar cell prepared by the above method.

[0037] The present invention has at least one of the following beneficial effects:

[0038] The present invention forms a mask layer by coating a layer of photosensitive material on the front and back sides of the battery. The width of the mask layer is smaller than the width of the battery, so that the photosensitive material is 0.1mm to 0.5mm away from the front and back edges of the battery, and the battery side is not wrapped by the photosensitive ink. Compared with the prior art, the side insulation scheme of the battery of the present invention is that the mask does not wrap the side and front edges of the battery, and the metal and ITO plated on the side are etched away with an etching liquid before electroplating, so that the side and the front and back sides are silicon during electroplating and will not be electroplated with metal; and the edge wrapping equipment and consumables are reduced; the ITO area on the back is increased, and the power generation efficiency is increased.

[0039] Compared with the prior art, the technical solution of the present invention only adds one etching process, but can reduce a large number of automated edge-wrapping equipment and consumables, which can not only reduce production costs, but also effectively isolate the leakage of the two poles of the battery and reduce the defective rate of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figures 1 to 9 It is a schematic diagram of the side view structure of the process for depositing metal grid lines on a solar cell in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to make the technical problems, technical solutions and beneficial effects solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0042] An embodiment of the present invention provides a method for engraving copper grid lines of a silicon heterojunction solar cell, comprising the following steps:

[0043] S1, such as Figure 1 As shown, the silicon wafer is placed in a 0.5%-10% concentration KOH solution and reacted at 50-85° C. for 1 min-20 min to form a double-sided velvet structure on the surface of the silicon wafer, and the reflectivity of the double-sided velvet surface is 10%-20%.

[0044] A first layer of amorphous silicon is deposited on the first surface, and a second layer of amorphous silicon is deposited on the second surface.

[0045] A first layer of ITO is deposited on the first surface, with a thickness of 40nm-200nm, and a second layer of ITO is deposited on the second surface, with a thickness of 40nm-200nm.

[0046] Vacuum sputtering method, including PVD / RPD and electron beam evaporation, is used on the front and back sides to prepare a metal layer respectively, which serves as the seed layer for subsequent electroplating. Its main function is to enhance the conductivity and improve the subsequent gate line pull-off force. The metal layer includes conductive metals such as copper, nickel, silver, gold, titanium, and aluminum, with a thickness of 30nm-1000nm and a film layer square resistance of 0.1mΩ-10mΩ.

[0047] S2, such as Figure 2 As shown, a layer of photosensitive material with a thickness of 5um-50um is coated on both sides of the battery, and the photosensitive ink is 0.1-0.5mm away from the edge of the front and back of the battery (so that the side is not covered by the photosensitive ink), and then the photosensitive material is cured by drying at 80-200℃ for 5min-30min.

[0048] S3, such as Figure 3 As shown, the ink or wet film is aligned with the cell using an exposure machine, and a UV exposure of 365nm to 405nm, 10 to 100mj / cm 2 Energy exposure.

[0049] S4, such as Figure 4 As shown, a trough or chain device is used to etch the copper at the edge of the battery without mask protection with an etching solution.

[0050] S5, such as Figure 5 As shown, a tank or chain device is used for development, and the unexposed area is removed by a developer, and finally a groove pattern layer to be electroplated is formed on the first surface with a main grid and a sub-grid perpendicular to each other, wherein the width of the main grid is 10um-500um, and the width of the sub-grid is 5um-80um.

[0051] S6, such as Figure 6As shown, a tank or chain device is used, and an ITO etching solution is used, which is a mixture of oxalic acid, hydrochloric acid, water, metal complexing agent, polymethylhydrogensiloxane and vinyl glycol ether with a mass concentration of 3% to 22%, to etch the edge of the battery without a mask TCO. Alternatively, a large number of battery cells can be overlapped and dry etching can be used, such as SF6, CF4, CHF3 dissociating free radicals, and Ar ions bombarding the side of the battery to etch the ITO on the side.

[0052] S7, such as Figure 7 As shown, a copper grid line layer is formed in the front and back grooves by chemical electroplating, or an anti-oxidation metal layer with a thickness of 50nm-10000nm is formed on the formed copper grid line layer by electroplating, including tin, silver and other metal layers.

[0053] S8, such as Figure 8 As shown, after chemical electroplating, the photosensitive resin on the front and the insulating ink on the back are removed with NaOH and KOH solutions.

[0054] S9, such as Fig. 9 As shown, the copper seed layer is etched to obtain the required copper grid. If the anti-oxidation metal layer is not electroplated in S7 chemical plating, chemical tin plating is required to form the anti-oxidation metal layer.

[0055] In some embodiments, Figure 1 As shown, a silicon wafer is placed in a 0.5%-10% concentration, 50-90°C KOH or NaOH solution for 1-20 minutes to form a pyramid light trapping structure on the surface of the silicon wafer through the anisotropic etching mechanism of alkali on silicon. The size of the surface pyramid is 0.5um-10um, and the surface reflectivity of the silicon wafer is between 5%-30%. Then, the front and back sides of the silicon wafer are cleaned with HF solution to remove surface metal ion contamination, and a velvet structure on the front and back sides is formed.

[0056] Then, a layer of intrinsic amorphous silicon and a layer of phosphorus-doped n-type amorphous silicon are sequentially deposited on the front side by using a PECVD chemical deposition method, wherein the intrinsic amorphous silicon has a thickness of 2nm-20nm and the phosphorus-doped amorphous silicon has a thickness of 2nm-20nm. A layer of intrinsic amorphous silicon and a layer of boron-doped p-type amorphous silicon are also deposited on the back side at one time, wherein the intrinsic amorphous silicon has a thickness of 2nm-20nm and the boron-doped amorphous silicon has a thickness of 2nm-20nm.

[0057] A layer of TCO conductive film or multiple layers of TCO conductive films with different refractive indices are deposited on the front and back of the silicon wafer respectively using physical methods such as PVD or RPD. The total film thickness is 50nm-200nm and the refractive index is 1.6-2.5.

[0058] A metal seed layer of 10nm-500nm is deposited on the front and back of the battery by sputtering. The metal seed layer is pure copper metal, or contains alloy metals such as copper, nickel, and molybdenum.

[0059] In some embodiments, Figure 2 As shown, photosensitive ink or wet film is printed on the front and back of the battery by screen printing. The ink viscosity is 1000-15000cps, the screen printing screen is 100-350 mesh, the screen film thickness is 10-30 microns, the yarn thickness is 30-60 microns, the ink is baked at a temperature of 80-200°C after screen printing, the baking time is 5-30 minutes, and the film thickness is 5-50 microns after the ink is dried.

[0060] In some embodiments, Figure 3 As shown, exposure, using 365 ~ 405nm wavelength ultraviolet light to expose the front of the battery by projection, projection scanning, the grid line pattern mask has grid lines, divided into main grid and auxiliary grid, the main grid and auxiliary grid are perpendicular to each other, the number of main grid roots is 3-20, the width is 10μm-100μm, the number of auxiliary grid roots is 30-300, the width is 5μm-50μm, or there is only auxiliary grid without main grid, the number of auxiliary grid roots is 30-300, the width is 5μm-50μm. Projection exposure, the distance between the mask and the battery is 20 ~ 1000μm, and the exposure energy is 10 ~ 100mj / cm 2 .

[0061] In some embodiments, a copper seed layer etching solution (first etching solution) is used to etch the edges of the front and back sides of the silicon wafer to remove the metal seed layer at the edges of the front and back sides of the silicon wafer that are not protected by the mask layer;

[0062] The copper seed layer etching solution includes persulfate composite salt and dilute sulfuric acid, the concentration of the persulfate composite salt is 10-20 g / L, and the concentration of the dilute sulfuric acid is 11-18.4 g / L.

[0063] In some embodiments, the step of etching the areas on the front and back sides of the silicon wafer where the mask layer is not formed further comprises:

[0064] Etching the edges of the front and back sides of the silicon wafer using an ITO etching solution to remove the transparent conductive film on the edges of the front and back sides of the silicon wafer that is not protected by the mask layer;

[0065] The composition of the ITO etching solution generally includes: hydrofluoric acid or ferric chloride + acid + additives. In some embodiments, the ITO etching solution of the present invention includes pure hydrochloric acid, or includes oxalic acid, hydrochloric acid, water, a metal complexing agent, polymethyl hydrogen siloxane and vinyl glycol ether. Since the composition, content and principle of the ITO etching solution are well known to those skilled in the art, they will not be described in detail in the present invention.

[0066] Another embodiment of the present invention provides a method for preparing copper grid electrode of silicon heterojunction solar cell, including depositing intrinsic amorphous silicon layer and n-type amorphous silicon layer on one side of n-type silicon wafer, depositing intrinsic amorphous silicon layer and p-type amorphous silicon layer on the other side, and then depositing metal oxide on both sides as conductive transparent film layer, and depositing thin metal seed layer on double-sided conductive layer. Print wet film or photosensitive ink on double-sided seed layer, ink or wet film is 0.1-0.5mm away from the edge of battery, expose the front and back sides of battery, transfer the pattern from mask plate to wet film, develop after exposure to obtain mask layer with grid electrode pattern, then etch copper or copper and TCO at the edge of battery cell that is not protected by ink mask, and then electroplate copper and tin on n-side and p-side, and remove mask after electroplating. Finally, electroplate seed layer at etching point to prepare heterojunction battery.

[0067] The main feature of the copper grid line electrode of the silicon heterojunction solar cell of the present invention is that: when the front surface of the cell requires a small shading area and the back surface does not require a high shading area, after the conductive layer and the metal seed layer are evaporated on the front surface of the cell, ink coating, exposure and development are adopted, and a cheap photosensitive wet film such as ink is used to prepare a mask for opening grid line patterns with a line width of 5μm-50μm and a height of 5μm-50μm by photolithography.

[0068] The technical solution also includes etching the copper of the non-protected portion of the battery edge before development.

[0069] The technical solution also includes the copper seed layer on the non-protected part of the battery edge before development. After the electroplating process on the battery side is optimized, copper will not be electroplated on the battery edge and side.

[0070] The technical solution also includes etching away the non-protective TCO layer on the edge of the battery after development. After the electroplating process on the side of the battery is optimized, copper will not be electroplated on the edge and side of the battery.

[0071] The technical solution also includes, after completing the graphic mask process, electroplating and depositing copper metal or copper and tin metal, removing the masks on the front and back of the battery cell, etching the battery to remove the metal seed layer, chemically tinning the battery grid metal, plating tin on the back of the copper grid line, and making the tin fully wrap around the copper grid to protect the grid line electrode.

[0072] Another embodiment of the present invention provides a method for preparing a silicon heterojunction solar cell, comprising the following steps:

[0073] The copper grid lines of the heterojunction battery are prepared by the above method, and a tin protective layer is plated on the surface of the copper grid lines by chemical replacement, so as to finally form a complete high-efficiency heterojunction solar cell product.

[0074] The present invention is further described in detail below with specific examples, but the present invention is not limited to the following specific examples.

[0075] Example 1

[0076] See also Figures 1 to 9 This embodiment provides a method for preparing a silicon heterojunction solar cell, comprising the following steps:

[0077] S1, such as Figure 1 As shown, the silicon wafer is placed in a 10% concentration KOH solution and reacted at 85° C. for 2 minutes to form a double-sided velvet structure on the surface of the silicon wafer, and the reflectivity of the double-sided velvet surface is 10%.

[0078] A first layer of amorphous silicon is deposited on the first surface, and a second layer of amorphous silicon is deposited on the second surface.

[0079] A first layer of ITO is deposited on the first surface, with a thickness of 50 to 200 nm, and a second layer of ITO is deposited on the second surface, with a thickness of 50 to 200 nm.

[0080] Vacuum sputtering, including PVD / RPD and electron beam evaporation, is used on the front and back sides to prepare a metal layer respectively, which serves as a seed layer for subsequent electroplating. Its main function is to enhance conductivity and improve the subsequent gate line pull-off force. The metal layer is copper with a thickness of 30 to 500 nm and a film resistance of 0.1 mΩ.

[0081] S2, such as Figure 2 As shown, a layer of photosensitive material with a thickness of 5 to 20 um is coated on both sides of the battery, and the photosensitive ink is 0.1 mm away from the edge of the front and back sides of the battery (so that the side is not covered by the photosensitive ink), and then the photosensitive material is cured by drying at 100°C for 10 minutes.

[0082] S3, such as Figure 3 As shown, the ink or wet film is aligned with the cell using an exposure machine, and 365-405nm UV, 10-100mj / cm 2 Energy exposure, line width 10 to 50 microns.

[0083] S4, such as Figure 4 As shown, a trough or chain equipment uses acid and TCO etching solution to etch the copper at the edge of the cell without mask protection.

[0084] Etching the edges of the front and back sides of the silicon wafer using a first etching solution to remove the metal seed layer at the edges of the front and back sides of the silicon wafer that are not protected by the mask layer;

[0085] The first etching solution includes persulfate composite salt and dilute sulfuric acid, the concentration of the persulfate composite salt is 15 g / L, and the concentration of the dilute sulfuric acid is 12 g / L.

[0086] S5, such as Figure 5As shown, a tank or chain device is used for development, and the unexposed area is removed by a developer, and finally a groove pattern layer to be electroplated is formed on the first surface with a main grid and a sub-grid perpendicular to each other, wherein the width of the main grid is 10 to 100 um and the width of the sub-grid is 10 to 50 um.

[0087] S6, such as Figure 6 As shown, the edges of both ends of the front and back sides of the silicon wafer are etched with an ITO etching solution to remove the transparent conductive film on both ends of the front and back sides of the silicon wafer that are not protected by the mask layer;

[0088] Among them, wet etching with hydrochloric acid of 3% to 22% mass concentration can be used. After development, the copper in the gate line will block the ITO under the copper. In addition, a large number of battery cells can be overlapped and dry etching can be used, such as CF4 and CHF3 dissociating free radicals, and Ar ions bombarding the side of the battery to etch the ITO on the side.

[0089] S7, such as Figure 7 As shown, a copper grid line layer is formed in the front and back grooves by chemical electroplating, and then an anti-oxidation metal layer with a thickness of 50 to 10000 nm is formed on the formed copper grid line layer by electroplating, including tin, silver and other metal layers.

[0090] S8, such as Figure 8 As shown, after chemical electroplating, the photosensitive resin on the front and the insulating ink on the back are removed with a KOH solution.

[0091] S9, such as Fig. 9 As shown, the copper seed layer is etched to obtain the required copper grid, and the battery is chemically tinned to finally form a complete high-efficiency heterojunction solar cell product.

[0092] In the method of Example 1, when masking, the photosensitive ink does not wrap the side and front edges of the battery. The distance between the photosensitive ink and the front and back edges of the battery is 0.1 mm, and before electroplating, an etching solution is used to etch away the metal and ITO plated on the side. In this way, the side and the front and back are silicon during electroplating and no metal will be plated. The edge wrapping equipment and consumables are reduced, the production cost is significantly reduced, and the leakage of the two poles of the battery is effectively isolated, and the defective rate is significantly reduced.

[0093] Example 2

[0094] The only difference from Example 1 is that in step S2, the photosensitive ink is 0.3 mm away from the front and back edges of the battery.

[0095] The other steps are the same as those in Example 1.

[0096] In the method of Example 2, when masking, the photosensitive ink does not wrap the side of the battery, the distance between the photosensitive ink and the edge of the front and back of the battery is 0.3 mm, and before electroplating, an etching solution is used to etch away the metal and ITO plated on the side. In this way, the side and the front and back are silicon during electroplating, and no metal will be plated, which reduces the edge wrapping equipment and consumables, significantly reduces the production cost, and effectively isolates the leakage of the two poles of the battery, and significantly reduces the defective rate; the production cost and defective rate of Example 2 are equivalent to those of Example 1.

[0097] Example 3

[0098] The only difference from Example 1 is that in step S2, the photosensitive ink is 0.5 mm away from the front and back edges of the battery.

[0099] The other steps are the same as those in Example 1.

[0100] In the method of Example 3, when masking, the photosensitive ink does not wrap the side of the battery, the distance between the photosensitive ink and the edge of the front and back of the battery is 0.5 mm, and before electroplating, an etching solution is used to etch away the metal and ITO plated on the side. In this way, the side and the front and back are silicon during electroplating, and no metal will be plated, which reduces the edge wrapping equipment and consumables, significantly reduces the production cost, and effectively isolates the leakage of the two poles of the battery, and significantly reduces the defective rate. The production cost and defective rate of Example 3 are equivalent to those of Example 1.

[0101] Comparative Example 1

[0102] The only difference from Example 1 is that in step S2, the photosensitive ink mask wraps the edge of the battery.

[0103] The other steps are the same as those in Example 1.

[0104] In the method of Comparative Example 1, when masking, the photosensitive ink wraps the side and front edges of the battery. Since the wrapping process adopts screen printing, there will be ink on the screen printing platform during mass production, which makes it difficult to implement a repeated process. In addition, since the screen is larger than the battery, it is difficult for the printed ink to flow down the edge of the battery and it is difficult to cover the entire side, resulting in a high defective rate, complicated process and high consumables.

[0105] Comparative Example 2

[0106] The only difference from Example 1 is that in step S2, the photosensitive ink is 0.05 mm away from the front and back edges of the battery.

[0107] The other steps are the same as those in Example 1.

[0108] In the method of Comparative Example 2, when masking, the photosensitive ink does not wrap the side and front edges of the battery, and the distance between the photosensitive ink and the front and back edges of the battery is 0.05 mm. Since the photosensitive ink is too close to the front and back edges of the battery, only 0.05 mm, the edge ITO etching is larger, the front and back ITO areas are 1.1% smaller, and the battery power generation efficiency is lower.

[0109] Comparative Example 3

[0110] The only difference from Example 1 is that in step S2, the photosensitive ink is 1.5 mm away from the front and back edges of the battery.

[0111] The other steps are the same as those in Example 1.

[0112] In the method of Comparative Example 3, when masking, the photosensitive ink does not wrap the side and front edges of the battery, and the distance between the photosensitive ink and the front and back edges of the battery is 1.5 mm. Since the photosensitive ink is too far away from the front and back edges of the battery, the edge etching area is large, the front and back ITO areas are 4% smaller, and the power generation efficiency is lower.

[0113] Comparing the preparation processes and prepared batteries of Examples 1 to 3 with Comparative Examples 1 to 3, it can be seen that compared with the photosensitive ink mask wrapping the battery edge in Comparative Example 1, Examples 1 to 3 do not wrap the battery edge because the photosensitive ink is 0.1mm to 0.5mm away from the front and back edges of the battery, so that the side and front edges are not wrapped by the photosensitive ink. Before electroplating, the metal and ITO plated on the side are etched away with an etching solution, so that the side and front and back are silicon during electroplating and will not be electroplated with metal, reducing the edge wrapping equipment and consumables, and the conversion efficiency of the battery does not decrease. Although Comparative Examples 2 and Comparative Examples 3 also do not wrap the battery side with photosensitive ink, the production cost and defective rate of Comparative Examples 2 and Comparative Examples 3 are higher than those of Examples 1 to 3, which may be caused by the distance between the photosensitive ink and the front and back edges of the battery being too close or too far, indicating that when the distance between the two end edges of the mask layer and the two end edges of the silicon wafer is 0.1mm to 0.5mm, the effect is better.

[0114] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A method for engraving copper grid lines of a silicon heterojunction solar cell, characterized in that: The following steps are involved: Providing a silicon wafer with metal seed layers deposited on the front and back sides; Forming a mask layer on the front and back sides of the silicon wafer, wherein the width of the mask layer is smaller than the width of the silicon wafer, and the distance between the edge of the mask layer and the edge of the silicon wafer is 0.1 mm to 0.5 mm; exposing the silicon wafer; Etching edge copper regions on the front and back sides of the silicon wafer where the mask layer is not formed; Developing the silicon wafer, then removing the unexposed areas on the front and back sides of the silicon wafer, and forming groove pattern layers on the front and back sides of the silicon wafer; Etching the edge ITO regions on the front and back sides of the silicon wafer where the mask layer is not formed; forming a copper gate line layer on the groove pattern layer, and forming an anti-oxidation metal layer on the copper gate line layer; The mask layer and the metal seed layer on the front and back sides of the silicon wafer are removed to obtain copper grid lines.

2. The method according to claim 1, characterized in that: The steps of forming a mask layer on the front and back sides of the silicon wafer specifically include: Coating a photosensitive material with a thickness of 5um-50um on the front and back of the silicon wafer, and curing the photosensitive material by drying at 80°C-200°C for 5min-30min to form a mask layer; The width of the mask layer is smaller than the width of the silicon wafer, and the distance between the edge of the mask layer and the edge of the silicon wafer is 0.1 mm to 0.45 mm.

3. The method according to claim 1, characterized in that The distance between the edge of the mask layer and the edge of the silicon wafer is 0.1 mm to 0.4 mm.

4. The method according to claim 1, characterized in that The distance between the edge of the mask layer and the edge of the silicon wafer is 0.1 mm to 0.3 mm.

5. The method according to claim 1, characterized in that: The step of etching the areas on the front and back sides of the silicon wafer where the mask layer is not formed specifically includes: Etching the edges of the front and back sides of the silicon wafer using a first etching solution to remove the metal seed layer at the edges of the front and back sides of the silicon wafer that are not protected by the mask layer; The first etching solution includes persulfate composite salt and dilute sulfuric acid, the concentration of the persulfate composite salt is 10 g / L to 20 g / L, and the concentration of the dilute sulfuric acid is 11 g / L to 18.4 g / L.

6. The method according to claim 5, characterized in that Using ITO etching solution or dry etching to etch the edge ITO areas on the front and back sides of the silicon wafer where the mask layer is not formed; Wherein, the ITO etching solution is hydrochloric acid with a mass concentration of 3% to 22%; or a mixture of oxalic acid, hydrochloric acid, water, a metal complexing agent, polymethyl hydrogen siloxane and vinyl glycol ether; The dry etching method comprises: overlapping a plurality of battery cells, using at least one of SF6, CF4, and CHF3 to dissociate free radicals, and bombarding the battery side with Ar ions to perform dry etching.

7. The method according to claim 1, characterized in that The thickness of the anti-oxidation metal layer is 50nm-10000nm, and the anti-oxidation metal layer includes at least one of tin and silver.

8. A copper grid line of a silicon heterojunction solar cell, characterized in that: The method is prepared by any one of claims 1 to 7.

9. A method for preparing a silicon heterojunction solar cell, characterized in that: The copper grid line of the heterojunction battery is prepared by the method described in any one of claims 1 to 7.

10. A silicon heterojunction solar cell, characterized in that: The method according to claim 9 is used to prepare the product.

Images