Semiconductor wafer device
By designing a multi-layer trace structure intermediary board and decoupling circuit in a semiconductor chip device, the problems of high circuit transmission impedance and unstable power supply in die-to-die packaging technology are solved, and a more stable power supply and lower circuit impedance are achieved.
Patent Information
- Application Number
- CN202311237485.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-25
- Publication Date
- 2025-03-25
AI Technical Summary
In the context of the development of high-performance computing and artificial intelligence technology, in three-dimensional chip and small chip technology, the packaging technology of die-to-die chips has problems such as high circuit transmission impedance and unstable power supply.
By designing the multi-layer trace structure of the intermediary board, multiple power traces and ground traces are set up, and decoupling circuits are used to reduce the impedance of the circuit transmission and improve the stability of the power supply.
It realizes the reduction of impedance during circuit transmission, improves the stability of power supply, and ensures the stability of power supply under high-frequency operation of the semiconductor chip device.
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Figure CN119695027A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor structure, and more particularly to a semiconductor wafer device. Background Art
[0002] With the development of high performance computing (HPC) and artificial intelligence (AI) technology, the demand for three-dimensional chips and chiplet technology is increasing. Among them, die-to-die is one of the important technologies for semiconductor chip packaging, which can package the system on chip (System On Chip) into multiple small modules to form a multi-chip module. Summary of the invention
[0003] The present disclosure relates to a semiconductor chip device, comprising a first bare die, a second bare die, a decoupling circuit and an interposer. The interposer has a plurality of power traces and a plurality of ground traces. The first bare die and the second bare die are arranged on a first side of the interposer in a configuration direction, and couple the plurality of power traces and the plurality of ground traces. The decoupling circuit is arranged on a second side of the interposer, and couples the plurality of power traces and the plurality of ground traces. The plurality of power traces and the plurality of ground traces are arranged in an interlaced manner, and the extension direction of the plurality of ground traces and the plurality of power traces is the same as the configuration direction.
[0004] In one embodiment, the interposer has a plurality of routing layers, and at least one of the plurality of routing layers is provided with the plurality of power routing lines and the plurality of ground routing lines.
[0005] In one embodiment, the interposer further includes a power transmission line and a ground transmission line. The power transmission line runs through the plurality of routing layers, is coupled to one of the plurality of power routing lines, and is coupled to the first die or the second die. The ground transmission line runs through the plurality of routing layers, is coupled to one of the plurality of ground routing lines, and is coupled to the first die or the second die.
[0006] In one embodiment, one of the plurality of power lines comprises a plurality of power coupling portions and a plurality of power connecting portions. At least one of the plurality of power coupling portions is coupled to a power transmission line. The power connecting portion is coupled between the plurality of power coupling portions, and a width of each of the plurality of power connecting portions is smaller than a width of each of the plurality of power coupling portions.
[0007] In one embodiment, one of the plurality of grounding traces comprises a plurality of grounding coupling portions and a plurality of grounding connecting portions. At least one of the plurality of grounding coupling portions is coupled to the grounding transmission line. A plurality of grounding connecting portions are coupled between the plurality of grounding coupling portions. A width of each of the plurality of grounding connecting portions is smaller than a width of each of the plurality of grounding coupling portions.
[0008] In one embodiment, the plurality of ground coupling portions are disposed between the plurality of power connection portions corresponding to two adjacent ones of the plurality of power traces.
[0009] In one embodiment, an isolation gap is formed between the plurality of ground coupling portions and the corresponding plurality of power connection portions, and the isolation gap is greater than or equal to 15 micrometers.
[0010] In one embodiment, the plurality of power coupling portions are disposed between the plurality of ground connection portions corresponding to two adjacent ones of the plurality of ground traces.
[0011] In one embodiment, an isolation gap is formed between the power coupling portions and the corresponding ground connection portions, and the isolation gap is greater than or equal to 15 micrometers.
[0012] In one embodiment, the power transmission line and the plurality of power traces are disposed in directions substantially perpendicular to each other.
[0013] In one embodiment, the ground transmission line and the plurality of ground traces are disposed in directions substantially perpendicular to each other.
[0014] In one embodiment, the decoupling circuit includes a plurality of ground contacts and a plurality of power contacts, wherein the plurality of ground contacts and the plurality of power contacts are arranged alternately with each other, and an arrangement direction of the plurality of ground contacts and the plurality of power contacts is the same as an arrangement direction of the plurality of power lines and the plurality of ground lines.
[0015] Accordingly, by arranging the wiring structure in the interposer in the shortest manner and using a decoupling circuit, the impedance during circuit transmission can be reduced and the stability of power supply can be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 is a schematic diagram of a semiconductor wafer device according to some embodiments of the present disclosure;
[0017] Figure 2 is a partial structural schematic diagram of a semiconductor wafer device according to some embodiments of the present disclosure;
[0018] Figure 3 is a schematic diagram of an equivalent circuit of a local circuit of a semiconductor chip device according to some embodiments of the present disclosure;
[0019] Figure 4 Shown is a schematic diagram of an interposer wiring structure according to some embodiments of the present disclosure;
[0020] Figure 5 Shown is a schematic diagram of an interposer wiring structure according to some embodiments of the present disclosure;
[0021] Figure 6 FIG. 1 is a schematic diagram showing local features of a routing layer according to some embodiments of the present disclosure.
[0022]
Explanation of symbols
[0023] 100:Semiconductor chip device
[0024] 110: Circuit board
[0025] 120:Packaging substrate
[0026] 130:Intermediary board
[0027] 130P: Power supply wiring
[0028] 130G: Ground routing
[0029] 140: Decoupling circuit
[0030] 140P:Contact
[0031] 140G: Contact
[0032] 300: Decoupling area
[0033] 611: power supply coupling portion
[0034] 612: Power connection part
[0035] 621: ground coupling portion
[0036] 622: ground connection part
[0037] A-A': hatch line
[0038] BP: Bump
[0039] Cd: decoupling capacitor
[0040] D10: First Bare Die
[0041] D11: First connection interface
[0042] D20: Second die
[0043] D21: Second connection interface
[0044] Vdd: first power input terminal
[0045] Vss: Second power input terminal
[0046] PL: Power Line
[0047] GL: Grounded Transmission Line
[0048] PDN1: First distribution network
[0049] PDN2: Second distribution network
[0050] VN1, VN2: voltage noise
[0051] L1: Inductor
[0052] L2: Inductor
[0053] M1-M5: routing layer
[0054] CX: Diameter
[0055] PX: Center distance DETAILED DESCRIPTION
[0056] The following will disclose multiple embodiments of the present invention with the accompanying drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is, in some embodiments of the present invention, these practical details are not necessary. In addition, in order to simplify the drawings, some conventional structures and elements will be depicted in a simple schematic manner in the drawings.
[0057] In this document, when an element is referred to as "connected" or "coupled", it may refer to "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although the terms "first", "second", etc. are used in this document to describe different elements, the terms are only used to distinguish between elements or operations described by the same technical terms. Unless the context clearly indicates otherwise, the terms do not specifically refer to or imply an order or sequence, nor are they used to limit the present invention.
[0058] Figure 1Schematic diagram of a semiconductor chip device 100 according to some embodiments of the present disclosure. The semiconductor chip device 100 includes a first die D10 and at least one second die D20. In one embodiment, the first die D10 may be a main die (Main Die, or System on a Chip), and the second die D20 may be a chiplet or another slave die in a dual main die architecture. The first die D10 and the second die D20 have a first connection interface D11 and a second connection interface D21, respectively. The first connection interface D11 and the second connection interface D21 are used to transmit data between the first die D10 and the second die D20 to form a package interconnection transmission network between semiconductor chips.
[0059] The first connection interface D11 and the second connection interface D21 are input / output interface circuits (Transmitter / Receiver interface, Transmitter / Receiver interface phy) in the bare chip. Figure 1 In the embodiment, each bare die has multiple connection interfaces, but in other embodiments, the bare die can also be connected to other bare dies through only one connection interface. In one embodiment, the semiconductor chip device 100 is provided with a decoupling area 300. In one embodiment, the decoupling area 300 is located between the two connection interfaces D11 and D21. In another embodiment, the vertical projection of the decoupling area 300 toward the connection interfaces D11 and D21 covers (includes) the connection interfaces D11 and D21. By configuring the decoupling capacitor on the decoupling area 300, the power integrity and power supply quality of the semiconductor chip device 100 can be improved.
[0060] Figure 2 is a partial structural diagram of a semiconductor wafer device 100 according to some embodiments of the present disclosure, corresponding to Figure 1 For ease of explanation, Figure 2 Only the first connection interface D11 on the first die D10 and the second connection interface D21 on the second die D20 are disclosed for illustration.
[0061] See also Figure 1 and Figure 2The semiconductor chip device 100 is mounted on a circuit board 110, and includes a first bare chip D10, a second bare chip D20, a package substrate 120, an interposer 130, and a decoupling circuit 140. The circuit board 110 is electrically connected to a first power input terminal Vdd and a second power input terminal Vss (e.g., a ground terminal), wherein the first power input terminal Vdd is used to supply power to the first bare chip D10 and the second bare chip D20 in the semiconductor chip device 100. It should be particularly mentioned here that the first power input terminal Vdd and the second power input terminal Vss refer to nodes connected to specific potentials.
[0062] In one embodiment, the interposer 130 is connected to the bare die D10 / D20 and the package substrate 120 through bumps BP. Specifically, the interposer 130 is connected to the bare die D10 / D20 through micro bumps (μBumps), and is connected to the package substrate 120 through "C4 Bumps". In addition, the package substrate 120 and the circuit board 110 are connected to each other through ball grid array package solder balls (BGA balls).
[0063] The first side surface of the intermediate board 130 (eg: Figure 2 The upper side shown in FIG. 1 is used for arranging and coupling the first die D10 and the second die D20 (as described above, Figure 2 Only the first connection interface D11 of the first die D10 and the second connection interface D21 of the second die D20 are shown. The second side surface of the interposer 130 (eg: Figure 2 The lower side surface shown in the figure is used to set and couple the package substrate 120. The first bare chip D10 and the second bare chip D20 are respectively electrically connected to the first power input terminal Vdd through the intermediate board 130, the package substrate 120 and the circuit board 110 to receive the supply power. The first bare chip D10 and the second bare chip D20 perform data transmission through the first connection interface D11, the intermediate board 130 and the second connection interface D21.
[0064] Specifically, the material of the interposer 130 may be a silicon interposer, in which multiple layers of wires are arranged. The wires are used to connect the electronic signals between the bare chips, and can be connected to the external bumps through silicon vias (TSV) and the wire carrier to achieve a close connection between the bare chip and the package substrate. The wiring structure of the interposer 130 will be described in detail in the subsequent paragraphs.
[0065] The decoupling circuit 140 is disposed on the interposer 130 at a position corresponding to the decoupling region 300. In one embodiment, the second side surface of the interposer 130 is coupled to the decoupling circuit 140. In other embodiments, the decoupling circuit 140 may be located in a vertical projection area of the first connection interface D11 and the second connection interface D21, or between the first die D10 and the second die D20. The "vertical projection area" mentioned herein refers to the area of the first connection interface D11 and the second connection interface D21 projected to the second side surface of the interposer 130.
[0066] In one embodiment, the decoupling circuit 140 includes at least one decoupling capacitor Cd. The first connection interface D11 / the second connection interface D21 are respectively connected to the decoupling capacitor Cd, the first power input terminal Vdd and the second power input terminal Vss through the wiring of the intermediate board 130 to form a power distribution network (PDN). In other embodiments, one or more additional decoupling capacitors Cd may also be disposed on the package substrate 120, and the location is not limited to the decoupling area 300.
[0067] When the semiconductor chip device 100 operates at high frequency, the inductive wiring of the interposer 130 will increase the impedance of the power distribution network and generate a high voltage drop in the power distribution network, thereby affecting the power supply stability of the semiconductor chip device 100. Through the decoupling effect of the decoupling circuit 140, the impedance of the power distribution network generated by high frequency operation can be reduced, thereby ensuring the stability of the power supply of the semiconductor chip device 100.
[0068] In addition to utilizing decoupling capacitors to ensure power supply quality, in some embodiments of the present disclosure, the wiring structure of the intermediate board 130 may be designed to shorten the inductive wiring distance of “connecting the first connection interface D11 or the second connection interface D21 to the decoupling circuit 140”, thereby reducing the impedance of the power distribution network. Figure 3 FIG. 1 is a schematic diagram of an equivalent circuit of a local circuit of a semiconductor wafer device 100 according to some embodiments of the present disclosure. Figure 3 As shown, the first bare chip D10, the inductor L1, the first power input terminal Vdd, the decoupling circuit 140 (eg: Figure 2The decoupling capacitor Cd) and the second power input terminal Vss shown form a first power distribution network PDN1, wherein the inductor L1 represents the first wiring of the interposer 130. The second die D20, the inductor L2, the first power input terminal Vdd, the decoupling circuit 140 and the second power input terminal Vss form a second power distribution network PDN2, wherein the inductor L2 represents the second wiring of the interposer 130. Thereby, the first power input terminal Vdd supplies power to the first die D10 through the first power distribution network PDN1, and supplies power to the second die D20 through the second power distribution network PDN2.
[0069] The present disclosure utilizes the wiring structure design of the interposer 130 to reduce the inductance L1 in the first power distribution network PDN1, and effectively reduce the voltage noise VN1 caused by the inductance L1 during high-frequency operation, thereby ensuring the power supply stability of the first bare chip D10. Similarly, by reducing the inductance L2 in the second power distribution network PDN2, the voltage noise VN2 caused by the inductance L2 can be effectively reduced during high-frequency operation, thereby ensuring the power supply stability of the second bare chip D20.
[0070] Thus, in order to ensure stable power supply, in the semiconductor chip device 100, the wiring structure design of the interposer 130 is used to reduce the inductance L1 and L2, and the usage of the decoupling circuit 140 can be further reduced accordingly (e.g., reducing the capacitance value or reducing the number of configurations). Accordingly, the volume of the semiconductor chip device 100 can be simplified and the circuit cost can be reduced.
[0071] Please refer to Figure 1 , Figure 2 and Figure 4 Here, the wiring structure of the intermediate board 130 is described. Figure 2 As shown, in one embodiment, the interposer 130 includes one or more power transmission lines PL, one or more ground transmission lines GL and one or more signal transmission lines SL. The signal transmission line SL is used to couple to the first die D10 and the second die D20 for data transmission. The power transmission line PL runs through the interposer 130 to couple to the first die D10 or the second die D20. The ground transmission line GL runs through the interposer 130 to couple to the first die D10 or the second die D20. In addition, the power transmission line PL and the ground transmission line GL are electrically coupled to the first power input terminal Vdd and the second power input terminal Vss respectively through the packaging substrate 120 and the circuit board 110, as the power supply path for the first die D10 and the second die D20.
[0072] Figure 4FIG. 1 is a schematic diagram of the wiring structure of the interposer 130 according to some embodiments of the present disclosure. The interposer 130 further includes a plurality of power traces 130P and a plurality of ground traces 130G. Each power trace 130P is coupled to at least one power transmission line PL and coupled to the decoupling circuit 140. Similarly, each ground trace 130G is coupled to at least one ground transmission line GL and coupled to the decoupling circuit 140. Figure 2 and Figure 4 , the power transmission line PL and the power trace 130P are arranged in directions substantially perpendicular to each other, and the ground transmission line GL and the ground trace 130G are arranged in directions substantially perpendicular to each other. In other words, the arrangement directions of the power trace 130P and the ground trace 130G can be Figure 2 The direction of the section line A-A'.
[0073] In one embodiment, the intermediate board 130 has a plurality of routing layers M1 to M5, and the first routing layer M1 is the top layer of the intermediate board 130, which is used to couple to the first bare chip D10 and the second bare chip D20. The fifth routing layer M5 is the bottom layer of the intermediate board 130, which is used to couple to the packaging substrate 120. In this embodiment, the ground routing 130G and the power routing 130P are arranged on the fifth routing layer M5, and may be exposed on the side of the intermediate board 130 facing the packaging substrate 120 (such as the second side in the aforementioned embodiment). However, the wiring structures of each routing layer M1 to M5 in the intermediate board 130 may be different, and the wiring structures of each routing layer M1 to M5 may be interchangeable. In other words, Figure 4 The wiring structure shown may also be changed to be disposed in any layer of the routing layers M1 - M5 .
[0074] The power transmission line PL and the ground transmission line GL penetrate and couple at least one of the wiring layers M1-M5 (e.g., through vias). The power transmission line PL will be coupled to at least one power wiring 130P. The ground transmission line GL will be coupled to at least one ground wiring 130G. In addition, the decoupling circuit 140 is coupled to at least one power wiring 130P and at least one ground wiring 130G.
[0075] In one embodiment, the extending direction of the ground trace 130G and the power trace 130P is the same as the configuration direction of the first die D10 and the second die D20 disposed on the interposer 130 (eg, Figure 1 and Figure 4 The ground traces 130G and the power traces 130P are arranged in an interlaced manner. In other words, every two power traces 130P are separated by at least one ground trace 130G.
[0076] The decoupling circuit 140 is provided with a plurality of grounding contacts 140G and a plurality of power contacts 140P for coupling to the grounding trace 130G and the power trace 130P respectively. The grounding contacts 140G and the power contacts 140P are arranged alternately, and the arrangement direction of the grounding contacts 140G and the power contacts 140P (e.g.: Figure 4 The arrangement direction of the ground trace 130G and the power trace 130P is the same as that of the ground trace 130G and the power trace 130P.
[0077] like Figure 4 As shown, in one embodiment, the extension directions of the ground trace 130G and the power trace 130P do not substantially have a large turn, such as a turn of more than 90 degrees, thereby maintaining the connection distance between the connection interface D11 / D21 and the decoupling circuit 140 to the shortest.
[0078] Figure 5 FIG. 1 is a schematic diagram of the wiring of the wiring layer M5 in the interposer 130 according to some embodiments of the present disclosure. In this embodiment, the power wiring 130P in the wiring layer M5 is respectively coupled to at least one power transmission line PL (eg Figure 2 and Figure 4 The ground trace 130G in the trace layer M5 is divided into a plurality of parts to couple to the decoupling circuit 140 and at least one ground transmission line GL (as shown in FIG. Figure 2 and Figure 4 In addition, the power wiring 130P and the ground wiring 130G in the wiring layer M5 can be connected to other wiring layers M1 to M4 through the power transmission line PL and the ground transmission line GL respectively.
[0079] See also Figure 2 and Figure 5 As shown, each power line 130P also includes a plurality of power coupling portions 611 and a power connecting portion 612. The power coupling portion 611 is used to couple to at least one power transmission line PL, or to set a bump BP to couple to the packaging substrate 120 or to couple to the decoupling circuit 140. In addition, the two corresponding power coupling portions 611 on two adjacent power lines 130P are arranged side by side. The power connecting portion 612 on each power line 130P is coupled between the two power coupling portions 611, and the width of each power connecting portion 612 is smaller than the width of each power coupling portion 611. In this way, there is a gap between the power connecting portions 612 of two adjacent power lines 130P. In some embodiments, the width is along Figure 5 Horizontal measurement in .
[0080] Similarly, each ground trace 130G also includes a plurality of ground coupling portions 621 and ground connection portions 622. The ground coupling portion 621 is used to couple to at least one ground transmission line GL, or to set a bump BP to couple to the package substrate 120 or to couple to the decoupling circuit 140. In addition, the two ground coupling portions 621 on two adjacent ground traces 130G are arranged side by side, and the ground connection portion 622 on each ground trace 130G is coupled between the two ground coupling portions 621, and the width of each ground connection portion 622 is smaller than the width of each ground coupling portion 621. In this way, there is a gap between the ground connection portions 622 of two adjacent ground traces 130G.
[0081] In the present embodiment, the ground coupling portion 621 of the ground trace 130G is disposed in the gap between the multiple power connection portions 612 corresponding to each other on two adjacent power traces 130P. The power coupling portion 611 of the power trace 130P is disposed in the gap between the two ground connection portions 622 corresponding to each other on two adjacent ground traces 130G. In this way, the power trace 130P and the ground trace 130G can be staggered, and the power trace 130P (or the ground trace 130G) will not have an excessively large turn (e.g., the turning angle exceeds 30 degrees, or exceeds 90 degrees) in the extension direction, so as to keep the connection distance between the connection interface D11 / D21 and the decoupling circuit 140 as short as possible.
[0082] Furthermore, the staggered power traces 130P and ground traces 130G do not contact each other. That is, there is an isolation gap between the ground coupling portion 621 and the corresponding / adjacent power connection portion 612, and there is an isolation gap between the ground connection portion 622 and the corresponding / adjacent power coupling portion 611. In one embodiment, the isolation gap between the power trace 130P and the ground trace 130G is between 10 and 20 microns. In other embodiments, the isolation gap between the power trace 130P and the ground trace 130G is greater than or equal to 15 microns.
[0083] Figure 6 The following is a schematic diagram of the local features of the routing layer according to some embodiments of the present disclosure. Figure 2 , Figure 5 and Figure 6 In one embodiment, the power coupling portion 611 and the ground coupling portion 621 are used to connect to the power transmission line PL and the ground transmission line GL respectively, or to set a bump BP on the wiring layer. Therefore, the area of the power coupling portion 611 and the ground coupling portion 621 will correspond to the area of the bump or the connection hole (via), for example Figure 6 The circle shown.
[0084] As mentioned above, since an isolation gap must be maintained between the power trace 130P and the ground trace 130G to avoid mutual coupling, in some embodiments, the layout widths of the power trace 130P and the ground trace 130G may be varied so that the power trace 130P and the ground trace 130G do not have excessive turns in the extension direction, thereby maintaining the connection distance between the connection interface D11 / D21 and the decoupling circuit 140 to the shortest.
[0085] Here, the power coupling portion 611 is used as an example for explanation: the diameter of the power coupling portion 611 is CX, and the "center spacing" of two adjacent power coupling portions 611 is PX. In one embodiment, the isolation gap between the power trace 130P and the ground trace 130G needs to be at least "15 microns", so the "width of the ground connection portion 622" that can be set between two adjacent power coupling portions 611 will be "PX-CX-(15×2)".
[0086] like Figure 5 In the two adjacent power traces 130P shown, the width of the power coupling portion 611 is wider than the power connection portion 612, and the distance between the two adjacent power connection portions 612 is greater than the distance between the two adjacent power connection portions 612. Therefore, the ground coupling portion 621 can be accommodated between the two adjacent power connection portions 612, so that the power trace 130P and the ground trace 130G do not have too large a turn in the extension direction, that is, the center line of the power trace 130P and the ground trace 130G basically remains a straight line.
[0087] The various elements, method steps or technical features in the aforementioned embodiments may be combined with each other and are not limited to the order of textual description or the order of presentation of the drawings in the present disclosure.
[0088] Although the present disclosure has been disclosed in the above implementation mode, it is not intended to limit the present disclosure. Anyone familiar with this technology can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure should be determined by the attached claims.
Claims
1. A semiconductor wafer device, characterized in that: Include: a first bare chip; a second bare chip; a decoupling circuit; An interposer having a plurality of power traces and a plurality of ground traces, wherein the first die and the second die are disposed on a first side of the interposer in a configuration direction and coupled to the plurality of power traces and the plurality of ground traces, and the decoupling circuit is disposed on a second side of the interposer and coupled to the plurality of power traces and the plurality of ground traces; The plurality of power lines and the plurality of ground lines are arranged in an interlaced manner, and an extending direction of the plurality of ground lines and the plurality of power lines is the same as the configuration direction.
2. The semiconductor wafer device according to claim 1, wherein: The intermediate board has a plurality of wiring layers, and at least one of the plurality of wiring layers is provided with the plurality of power wirings and the plurality of ground wirings.
3. The semiconductor wafer device according to claim 2, wherein: The interposer board also includes: a power transmission line, running through the plurality of routing layers, coupled to one of the plurality of power routing lines, and coupled to the first die or the second die; and A ground transmission line runs through the plurality of routing layers, is coupled to one of the plurality of ground routing lines, and is coupled to the first bare chip or the second bare chip.
4. The semiconductor wafer device according to claim 3, wherein: One of the plurality of power supply lines comprises: a plurality of power coupling portions, wherein at least one of the plurality of power coupling portions is coupled to the power transmission line; as well as A plurality of power connection portions are coupled between the plurality of power coupling portions, wherein a width of each of the plurality of power connection portions is smaller than a width of each of the plurality of power coupling portions.
5. The semiconductor wafer device according to claim 4, wherein: One of the plurality of ground traces comprises: a plurality of ground coupling portions, wherein at least one of the plurality of ground coupling portions is coupled to the ground transmission line; as well as A plurality of ground connection portions are coupled between the plurality of ground coupling portions, wherein a width of each of the plurality of ground connection portions is smaller than a width of each of the plurality of ground coupling portions.
6. The semiconductor wafer device according to claim 5, wherein: The plurality of ground coupling portions are disposed between the plurality of power connection portions corresponding to two adjacent ones of the plurality of power traces.
7. The semiconductor wafer device according to claim 6, wherein: An isolation gap is formed between the plurality of ground coupling portions and the corresponding plurality of power connection portions, and the isolation gap is greater than or equal to 15 micrometers.
8. The semiconductor wafer device according to claim 5, wherein: The plurality of power coupling portions are disposed between the plurality of ground connection portions corresponding to two adjacent ones of the plurality of ground traces.
9. The semiconductor wafer device according to claim 8, wherein: An isolation gap is provided between the plurality of power coupling portions and the corresponding plurality of ground connection portions, and the isolation gap is greater than or equal to 15 micrometers.
10. The semiconductor wafer device according to claim 3, wherein: The power transmission line and the plurality of power lines are arranged in directions substantially perpendicular to each other.
11. The semiconductor wafer device according to claim 3, wherein: The ground transmission line and the plurality of ground routing lines are arranged in directions substantially perpendicular to each other.
12. The semiconductor wafer device according to claim 1, wherein: The decoupling circuit includes a plurality of grounding contacts and a plurality of power contacts, wherein the plurality of grounding contacts and the plurality of power contacts are arranged alternately, and an arrangement direction of the plurality of grounding contacts and the plurality of power contacts is the same as an arrangement direction of the plurality of power lines and the plurality of grounding lines.