Voltage converter with inductor or transformer between stacked dies

Abstract

The invention relates to a voltage converter with an inductor or transformer between stacked dies. Embodiments herein relate to a voltage regulator (VR) formed of dies stacked on a package substrate layer. The dies may include a load die stacked on the VR die with an intermediate layer between the two dies. The VR may include an inductor or transformer as a charge transfer component formed between the dies. For example, an inductor or transformer winding may be wound around an intermediate layer and include VR and portions of a top metal layer of a load die, where the load die is inverted in the stack. The intermediate layer may be magnetic or non-magnetic to the inductor, or may be magnetic to the transformer. Optionally, the VR may be divided into two dies. The VR die may have a gallium nitride substrate to cope with higher input voltages, while the load die includes a silicon substrate.

Description

Technical Field

[0001] The present application relates generally to the field of voltage converters. Background Art

[0002] Computing devices often rely on voltage converters, also known as voltage regulators, to obtain power. For example, a direct current (DC) to DC voltage converter can convert a power supply at one DC voltage to another, usually lower DC voltage. The voltage converter can step down the main supply voltage (e.g., 12V) of the computing device to a lower voltage (e.g., 5V, 3.3V, or 1.8V). The lower voltage can be used by various components in the computing device, such as a Universal Serial Bus (USB) interface, a memory such as a dynamic random access memory (DRAM), and a processing resource such as a central processing unit (CPU). However, it is challenging to supply power in an efficient and economical manner. Summary of the invention

[0003] According to one aspect of the present application, a device is provided, comprising: a first die, the first die comprising a substrate and a plurality of metal layers above the substrate, including a first top metal layer; a second die, the second die comprising a substrate and a plurality of metal layers above the substrate, including a second top metal layer, wherein the second die forms a stack with the first die and is in an inverted position relative to the first die; and a voltage regulator, the voltage regulator comprising an input path in the first die, an output path in the second die, and an inductor coupled to the input path and the output path, wherein the inductor comprises at least one of a portion of the first top metal layer or a portion of the second top metal layer.

[0004] According to another aspect of the present application, a device is provided, comprising: a first die; a second die stacked on the first die and in an inverted position relative to the first die; a magnetic material between the first die and the second die; and a voltage regulator, the voltage regulator comprising an input path in the first die, an output path in the second die, a primary winding of a transformer surrounding the magnetic material, and a secondary winding of the transformer surrounding the magnetic material, wherein the primary winding is coupled to the input path and the secondary winding is coupled to the output path.

[0005] According to another aspect of the present application, a voltage regulator is provided, comprising: a magnetic material between a first die and a second die; and a conductive coil wound around the magnetic material, wherein the conductive coil comprises some portions of the metal layer of the first die and some portions of the metal layer of the second die, and the second die is in an inverted direction relative to the first die in a stack formed with the first die. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The embodiments of the present disclosure will be more fully understood through the detailed description given below and through the drawings of various embodiments of the present disclosure, however the detailed description and drawings should not be understood as limiting the present disclosure to specific embodiments but are only for illustration and understanding.

[0007] Figure 1 Depicted is a cross-sectional view of a stack 100 including a package substrate layer 110 , a voltage regulator (VR) die 120 , and a load die 130 , wherein an inductor 140 or 141 of the VR is located on or within the package substrate layer, according to various embodiments.

[0008] Figure 2 Depicted is a cross-sectional view of a stack 200 including a package substrate layer 210 , a VR die 220 , and a load die 230 , wherein an inductor 240 of the VR is located between the dies, according to various embodiments.

[0009] Figure 3 A cross-sectional view of a stack 300 is depicted, the stack including a package substrate layer 310 , VR dies 320 , an intermediate layer 330 , and a load die 340 , wherein a transformer 350 of the VR is located between the dies, according to various embodiments.

[0010] Figure 4A A perspective view of a stack 400 is depicted according to various embodiments, the stack including a package substrate layer 410, a VR die 420, an intermediate layer 430, and a load die 440, wherein an example spiral inductor 450 is formed in a portion of a top metal layer of the VR die, and an example coil 460 of an inductor or transformer is formed in portions of the top metal layers of the VR die and the load die, with the winding surrounding a portion of the intermediate layer.

[0011] Figure 4B Depicted are various embodiments Figure 4A 4 is a top view of a package showing magnetic material 431 in the middle layer 430, wherein the inductor 460 includes windings around the magnetic material.

[0012] Figure 5 Depicted is a cross-sectional view of a stack 500 according to various embodiments, the stack comprising Figure 4AA VR die 420, an intermediate layer 430, and a load die 440 are provided, wherein the metal layers of the VR die 420 and the load die 440 are included, wherein the load die is in an inverted position relative to the VR die, and the inductor 460 includes some portions of the top metal layers of the VR die and the load die.

[0013] Figure 6 A cross-sectional view of a stack 600 is depicted, the stack including a package substrate layer 610, a VR die 620, a magnetic interlayer 630, and a load die 640, wherein a buck VR 650, a boost VR 660, and a single-input multiple-output (SIMO) VR 670 are formed with inductors 651, 661, and 671, respectively, located between the die, according to various embodiments.

[0014] Figure 7 Depicted is a cross-sectional view of a stack 700 including a package substrate layer 710 , a VR die 720 , a magnetic interlayer 730 , and a load die 740 , with a transformer 750 of a flyback VR 790 located between the dies, according to various embodiments.

[0015] Figure 8 A cross-sectional view of a stack 800 is depicted according to various embodiments, the stack including a package substrate layer 810, a first VR die 820 for converting a high voltage Vin to an intermediate voltage Vout1, a magnetic intermediate layer 830, a second VR die 840, and a load die 850, wherein a transformer 750 is located between the first and second VR dies, and an additional VR 795 in the second VR die 840 is used to step down convert Vout1 to a low voltage Vout2.

[0016] Fig. 9 Depicted according to various embodiments, as Figure 8 Circuit diagram of an example implementation of VR 795 for a 2:1 switched capacitor based VR.

[0017] Fig.10 Depicted is a cross-sectional view of a stack 1000 including a package substrate layer 1010 , VR dies 1020 , an intermediate layer 1030 , and a load die 1040 , wherein an example forward VR 1050 is formed with a transformer 1060 between the dies, according to various embodiments.

[0018] Fig.11 Illustrations illustrate examples of components that may be present in a computing system 1150 for implementing the techniques (eg, operations, processes, methods, and approaches) described herein. DETAILED DESCRIPTION

[0019] Compared to linear regulators, inductor-based power converters, also called voltage regulators (VRs), can provide very efficient power conversion through the transformer effect over a wide output voltage range. However, it is very important to use a high-quality factor (Q) inductor with a small DC resistance, because otherwise the losses associated with the inductor may dominate and impair the efficiency of the VR. In addition, the location of the inductor is also important, because it should be as close as possible to the power stage circuit and the receiving end to minimize the direct current (DC) resistance losses through metal traces and vias in the high-current power path. Especially in vertically stacked systems where multiple dies are stacked vertically, in addition to the package vias, the power path may also include through-silicon vias (TSVs) to reach the top load die. These paths can seriously affect efficiency and impair signal routing.

[0020] One approach is to place the inductor on the board or die side of the package. However, in this approach, the power path from both the VR die and the load die to the inductor includes TSVs, lateral package routing, and package vias through the VR die, which may incur significant ohmic losses. Another approach is to integrate the inductor into the package substrate layer. This approach may eliminate lateral package routing, but still uses package vias and TSVs, which may compromise efficiency.

[0021] To overcome the above and other problems, the inductor or transformer of the VR can be placed between the VR die and the load die in the stack to minimize the wiring resistance. The input terminals of the inductor or transformer can be connected to the VR die, while the output terminals of the inductor or transformer are connected to the load die. The inductor or transformer can be built using the GM layer (top metal layer) of each die. An intermediate layer can be placed between the VR die and the load die, with or without a magnetic core.

[0022] In another solution, a second VR die is stacked on the first VR die, and a load die is stacked on the second die. The first VR die converts the input voltage down to an intermediate voltage, and the second VR die converts the intermediate voltage down to a final output voltage for use by the load die.

[0023] The stacked die may be provided on a package substrate layer, wherein the substrate layer and the die form a stack, which is enclosed in a package.

[0024] In one option, both the VR die and the load die include a silicon substrate.

[0025] In another option, the VR die includes a substrate material such as gallium nitride (GaN) and is capable of handling higher input voltages than the load die, while the load die includes a silicon substrate, which operates at a lower voltage.

[0026] VR can be of various types. For example, inductor-based VR includes buck, boost, and single-input, multiple-output (SIMO), while transformer-based VR includes flyback and forward VR.

[0027] These and other features will become further apparent from the discussion below.

[0028] Figure 1 A cross-sectional view of a stack 100 is depicted according to various embodiments, the stack including a package substrate layer 110, a voltage regulator (VR) die 120, and a load die 130, wherein an inductor 140 or 141 of the VR is located on or within the package substrate layer. The stack or stack structure includes a substrate layer, referred to as the package substrate layer 110, on which a number of dies are stacked, one on top of another. The package substrate layer can be mounted on a board such as a motherboard or other printed circuit board and includes conductive dots, such as a ball grid array, on its underside for communicating with circuits on the board. The package substrate layer can include conductive paths, such as through-holes, to couple the conductive dots to the VR, for example, to input a voltage or to ground the VR.

[0029] As previously described, one option is to position inductor 140 on the top surface of the package substrate layer. Inductor 140 is part of the VR of the VR die and includes conductive paths 143 and 144 that extend laterally and vertically. These conductive paths are coupled to other conductive paths and circuits in the VR die, such as switches. For example, the conductive paths in the VR die may include paths in metal layers and TSVs. These conductive paths may extend all the way to the load die. Another option is to position inductor 141 within the package substrate layer. In this case, conductive paths 145 and 146 are used to communicate with the VR die. As previously described, in such vertical power delivery applications, the conductive paths on or in the package substrate layer can result in significant resistive losses.

[0030] The control circuit 111 can communicate with the stack and can include a sensor 112, a processor 113, and a memory 114. The memory stores instructions to be executed by the processor. The sensor can sense the output voltage of the VR and implement a control loop to regulate the output voltage. The control circuit can be external to the package, such as on a board to which the package is attached, or in a low voltage domain, such as in a load die. Providing the control circuit on the load die may be a good choice for integration because the load die is a low voltage die and the control circuit typically operates at a low voltage. Other options are also possible.

[0031] Figure 2 A cross-sectional view of a stack 200 is depicted according to various embodiments, the stack including a package substrate layer 210, a VR die 220, and a load die 230, wherein an inductor 240 of the VR is located between the die. Positioning the inductor between the die brings advantages such as reduced resistance losses. Specifically, by placing the inductor between two stacked die, the power path resistance is significantly improved because this approach reduces or eliminates the need for TSVs through package vias, lateral package routing, or through the die and package substrate layers. This improves end-to-end power conversion efficiency, extends battery operating time, and / or reduces cooling requirements. In addition, this approach can also free up more area on the die stack for routing, which may be used for power TSVs, thereby enabling denser input / output or higher throughput die-to-die communication channels.

[0032] In some cases, an intermediate layer is provided between the first die 220 and the second die 230. The inductor of the VR can be wound around the intermediate layer, and the intermediate layer can include magnetic material to increase the magnetic field. Various VR designs can include one or more inductors.

[0033] Figure 3 A cross-sectional view of a stack 300 is depicted according to various embodiments, the stack including a package substrate layer 310, a VR die 320, an intermediate layer 330, and a load die 340, wherein a transformer 350 of the VR is located between the dies. As in the example of the inductor, in some cases, an intermediate layer is provided between the dies 320 and 340. The transformer of the VR may include primary and / or secondary windings around the intermediate layer, which may include magnetic material to increase the magnetic field.

[0034] Figure 4AA perspective view of a stack 400 is depicted according to various embodiments, the stack including a package substrate layer 410, a VR die 420, an intermediate layer 430, and a load die 440, wherein an example spiral inductor 450 is formed in a portion of a top metal layer of the VR die, and an example coil 460 of an inductor or transformer is formed in portions of the top metal layers of the VR die and the load die, with the winding wrapping around a portion of the intermediate layer. The inductor 450 is in the shape of a planar spiral and is formed in the top metal layer of the VR die 420. The input end 451 of the inductor can be in the top metal layer of the VR die, while the output end 452 of the inductor extends to a portion of the top metal layer of the load die. In this example, the load die is inverted so that its top metal layer faces the top metal layer of the VR die. See also Figure 5 In another option, a spiral inductor is provided in the top metal layer of the load die. In another option, both the VR die and the load die include a spiral shape / conductive path to create the inductance. The spiral shape creates a magnetic field that can be used to store and release energy when the VR converts the input voltage to a different output voltage.

[0035] In another option, the inductor 460 is a coil and includes a winding (or vertical turns) around the middle layer 430, where the winding includes some portions of the top metal layer of the tube cores 420 and 440. Specifically, the laterally extending portion of the inductor can be in some portions of the top metal layer, and the vertically extending portion can include TSVs or other vias extending between some portions of the top metal layer of the two tube cores. In one approach, the TSV can include metal. The inductor includes a coil wrapped around a portion of the middle layer. The input end 461 of the inductor 460 can be in the top metal layer of the VR tube core, and the output end 462 of the inductor is in the top metal layer of the load tube core.

[0036] Die 420 is a first die and die 440 is a second die.

[0037] Figure 4B Depicted are various embodiments Figure 4AA top view of a package of , showing magnetic material 431 in the middle layer 430, wherein the inductor 460 includes a winding around the magnetic material. When the inductor is a coil, in order to increase the magnetic field, the winding of the inductor is wound around the magnetic material in the middle layer. The magnetic material can be a metal-based material, such as Fe (iron), Ni (nickel), Cu (copper), Mo (molybdenum), Mn (manganese), Cr (chromium), etc., or can be an iron oxide-based material, i.e., ferrite, such as MnFe2O3, CuFe2O3, ZnFe2O3, NiFe2O3, etc. Other example materials include amorphous cobalt alloys, such as CoZrTa, CoFeHfO, CoAlO, FeSiO, CoFeAlO, CoNbTa and CoZr.

[0038] The magnetic material may be elongated, such as rod-shaped, and formed, for example, in a surrounding dielectric material 465 of an intermediate layer.

[0039] The intermediate layer may alternatively comprise a non-magnetic material, as a so-called air core, which is not necessarily air, but a material with very low magnetic properties. In one possible implementation, the intermediate layer may be sandwiched between the VR die and the load die.

[0040] Figure 5 Depicted is a cross-sectional view of a stack 500 according to various embodiments, the stack comprising Figure 4A The VR die 420, the middle layer 430 and the load die 440 are provided, wherein the metal layers of the VR die 420 and the load die 440 are included, wherein the load die is in an inverted position relative to the VR die, and the inductor 460 includes some portions of the top metal layers of the VR die and the load die. By inverting the load die on top of the VR die, the top metal layers of the two dies face each other, and the distance between these layers is minimized, thereby minimizing the resistance loss of the conductive path between these layers.

[0041] In a VR die, a substrate 421 (e.g., silicon or GaN) includes a transistor layer 422, e.g., the top portion of the substrate where transistors are fabricated to create a circuit. Above the substrate are alternating dielectric and metal layers. For example, dielectric layers VR_D0-VR_D7 and metal layers VR_M0-VR_M7 are depicted, where VR_M7 is the topmost metal layer (first top metal layer). For example, the metal layers may include aluminum or copper, and the dielectric layers may include oxides.

[0042] In the load die, a substrate 441 (e.g., silicon) includes a transistor layer 442. Above the substrate are alternating dielectric and metal layers, such as dielectric layers L_D0-L_D7 and metal layers L_M0-L_M7, where L_M7 is the topmost metal layer (the second top metal layer). The metal layers get thicker the further away from the substrate. When the load die is inverted, the alternating dielectric and metal layers are below the substrate. Eight metal layers are depicted for example only.

[0043] and Figure 4A and Figure 4B As in FIG. 4 , inductor 460 comprises a coil having windings around intermediate layer 430. The inductor is shown in a cross-sectional view and comprises a portion 471 of VR_M7 and a portion 472 of L_M7, and further comprises a vertically extending portion 473, such as a via extending through the intermediate layer.

[0044] In some implementations, Figure 8 As in FIG. 4 , the second VR die is on the first VR die. In this case, die 440 may represent the second die. The load die may be stacked on the second die in an inverted or non-inverted orientation.

[0045] Figure 6 A cross-sectional view of a stack 600 is depicted according to various embodiments, the stack including a package substrate layer 610, a VR die 620, a magnetic intermediate layer 630, and a load die 640, wherein a buck VR 650, a boost VR 660, and a single-input multiple-output (SIMO) VR 670 are formed with inductors 651, 661, and 671 located between the die, respectively. A buck VR, or step-down converter, is a DC to DC converter that steps down voltage from its input (supply) to its output (load) while stepping up current. A boost converter, or step-up converter, is a DC to DC power converter that steps up voltage from its input (supply) to its output (load) while stepping down current. As shown here, a SIMO VR acts as a buck or boost converter with multiple outputs. For convenience, different types of VRs are depicted together in the same package here. In general, one or more VRs may be used.

[0046] Buck VR 650 includes an inductor 651 having an input terminal 652 and an output terminal 653. Input terminal 652 is coupled to an input path 654 receiving Vin through a high-side switch Shs, and is coupled to a ground path G through a low-side switch Sls. The switch can be a transistor controlled by a signal from a control circuit. In one embodiment, when Sls is open (non-conducting), Shs is closed (conducting); and when Sls is closed, Shs is open. Shs is closed according to the duty cycle, so that the larger the duty cycle, the larger Vout. A diode 656 is coupled between the ground and the point between the switch. The output terminal 653 of the inductor is coupled to an output path 655 to provide Vout to a current sink 657 (a load in a load die), which in turn is coupled to ground through a ground path 658. The load may include one or more circuits in the load die that draw power from the output of the VR. The input 652 of the inductor may be in the top metal layer of the VR die, while the output 653 is in the top metal layer of the load die.

[0047] Boost VR 660 includes an inductor 661 having an input 662 and an output 663. Input 662 is coupled to an input path 664 that receives Vin. Output 663 of the inductor is coupled to a ground path via a ground switch Sgnd and to an output path 665 via an output switch Sout to provide Vout to a current sink 667, which in turn is coupled to ground via a ground path 668. Both the input and output of the inductor may be in the top metal layer of the VR die.

[0048] SIMO VR 670 includes an inductor 671 having an input 672 and an output 673. The input 672 is coupled to an input path 674 receiving Vin via a high-side switch Shs, and is coupled to a ground path via a low-side switch Sls. The output 673 of the inductor is coupled to ground via a ground switch Sgnd, and is coupled to an output path 675 via respective output switches S0, S1, S2 to provide respective output voltages Vout0, Vout1, Vout2 to respective current sinks 677, which in turn are coupled to ground via respective ground paths 678. The input and output of the inductor may both be in the top metal layer of the VR die. This example depicts three outputs, but any number N>1 may also be provided. Switches S0, S1, S2 are controlled according to respective control signals so that only one switch is closed at a time. Thus, only one output path is coupled to the inductor at a time. Each output may therefore be provided at a different level according to the duty cycle of its respective switch. An output capacitor (not shown) may also be provided for each output path, connected in parallel with the corresponding current sink.

[0049] Generally speaking, a buck converter can be implemented with an inductor, where the high-side and low-side switches (Shs and Sls) are on the VR die. A boost converter can be implemented similarly, and the output switch can be on the VR die or the load die. SIMO converters can be formed with most of the power switches on the VR die, while the output switch can be placed on the VR die or the load die. In these scenarios, since the inductor does not isolate the input and output, both the VR die and the load die should have similar voltage ratings.

[0050] Die 620 is a first die and die 640 is a second die.

[0051] Figure 7 Depicted is a cross-sectional view of a stack 700 including a package substrate layer 710 , a VR die 720 , a magnetic interlayer 730 , and a load die 740 , with a transformer 750 of a flyback VR 790 located between the dies, according to various embodiments.

[0052] Transformer-based VRs allow the input and output paths to be completely isolated from each other so that they can operate at different voltages, allowing high voltage ratio conversions to be achieved. For example, Figure 7 and Figure 8 An example of a flyback converter is provided, while Fig. 9 An example of a forward converter is provided. In one approach, a 12V input is provided to the VR, and the input GaN power switch is implemented in a 12V compliant GaN VR die, while the other output switches on the secondary winding are implemented in a low voltage load die. This can open up a wide range of vertical integration in higher voltage scenarios (e.g., 48V) because it allows separation between dies at different voltage levels, benefits from extremely small path resistance through vertical vias only, and eliminates any high current lateral wiring.

[0053] Forward and flyback converters can be used to step up or down an input voltage, or to convert a single voltage to multiple output voltages.

[0054] A transformer typically includes two magnetically coupled coils. An alternating current in one coil (i.e., the primary coil or winding) causes a changing magnetic field that induces a current in the other coil (i.e., the secondary coil or winding). The transformer provides voltage transformation and isolation. An input voltage is provided to the input of the primary winding, and an output voltage is obtained from the output of the secondary winding. When the primary to secondary turns ratio of the winding is N:1, the output voltage can be lower than the input voltage by a ratio of 1 / N. The windings can be wound on a magnetic material. The windings can extend over a common length of the magnetic intermediate layer, or over different lengths as shown here.

[0055] Generally speaking, using magnetic materials, a transformer can be built between two dies. Since the input and output are isolated, the input side can be built with a high voltage process and the output side with a low voltage process. Figure 7 and Fig. 9 In the dual-die configuration shown in , the VR die receives a relatively high input voltage, such as 12-48V, and outputs a relatively low output voltage, such as 1V. In the three-die configuration, Figure 8 As shown, the first VR die receives a relatively high input voltage, such as 24-48V, and outputs an intermediate voltage, such as 4V, to the second VR die. The second VR die converts the intermediate voltage to a low voltage, such as 1V, for use by the load die.

[0056] Transformer 750 includes a primary winding 751 and a secondary winding 752 wound around a magnetic material of an intermediate layer. An input voltage Vin is provided to an input terminal 761 of the primary winding on an input path 760. An output terminal 762 of the primary winding is coupled to a ground path G through a switch 763. The magnetic field generated by the primary winding in the magnetic material causes the secondary winding to provide an output voltage Vout between its input terminal 765 and output terminal 766. Vout is provided on an output path 764 in the load die and is provided to a current sink 768 representing the load through a diode 767. An output capacitor Cout is coupled in parallel with the load. A ground path 769 is coupled to the capacitor and the current sink.

[0057] In the flyback VR, when the switch 763 is closed, the first current flows through the primary winding to store energy in the transformer. The windings are two coupled inductors of the transformer, which store energy when the switch 763 is closed. In addition, the second current flows from Cout to the current sink. When the switch is open, the current flows from the secondary winding to the current sink through the diode 767.

[0058] Die 720 is a first die and die 740 is a second die.

[0059] Figure 8A cross-sectional view of a stack 800 is depicted according to various embodiments, the stack including a package substrate layer 810, a first VR die 820 for converting a high voltage Vin to an intermediate voltage Vout1, a magnetic intermediate layer 830, a second VR die 840, and a load die 850, wherein a transformer 750 is located between the first and second VR dies, and an additional VR 795 in the second VR die 840 is used to convert Vout1 down to a low voltage Vout2. In this case, the output voltage on path 764 in the second VR die is the intermediate voltage Vout1. Vout1 passes through a diode 767 and is provided as an input voltage to the additional VR 795, which in turn provides an output Vout2 on path 770 to a current sink 768 of the load die. An output capacitor Cout is coupled in parallel with the load. In this example, Cout is in the second VR die. A ground path 769 is coupled to VR 795, and a ground path 779 is coupled to the capacitor and the current sink.

[0060] Various types of VRs may be used for VR 795. One example uses a switched capacitor VR such as Fig. 9 shown.

[0061] One advantage of this implementation is that the voltage reduction occurs in two stages, in the first and second VRs of the cascade arrangement.In theory, more than two VR dies and VRs can be used.

[0062] In general, various designs of magnetics-based power converters can be realized in conjunction with the solutions provided in this article.

[0063] Fig. 9 Depicted according to various embodiments, as Figure 8 795 is a circuit diagram of an example implementation of a 2:1 switched capacitor based VR. This example VR is configured as a single stage charge pump with a single flying capacitor. A charge pump generally refers to a switching voltage converter that employs an intermediate capacitive storage element, which is sometimes referred to as a flying capacitor or charge transfer capacitor. One or more flying capacitors may be used. In this example, the charge pump is configured to provide Vout2 <Vout1。

[0064] Input node 901 receives input voltage Vout1. A set of switches SW1-SW4 is controlled by a control circuit to transfer charge from the input node to Cf, and from Cf to an output node 902. Vout2 is the voltage generated at the output node, and Iload is the current drawn by the load. The switch may be, for example, a MOSFET, a BJT, or a relay switch. SW1 and SW2 are closed (conducting) at the same time, while SW3 and SW4 are disconnected (non-conducting). Similarly, SW1 and SW2 are disconnected at the same time, while SW3 and SW4 are closed. When closed, SW1 connects the top conductor of Cf to the input node 901 to receive charge from Vout1, and SW2 connects the bottom conductor of Cf to the output node 902 to transfer its charge to the output node. When closed, SW4 connects the bottom conductor of Cf to the ground node, and SW3 connects the top conductor of Cf to the output node 902 to transfer its charge to the output node.

[0065] The control circuit provides appropriate control signals to the switches to provide Vout2 at the desired level. The control circuit may include sensors (see also Figure 1 ), which monitors Vout2 at the output node via a feedback path. CC can adjust the on / off time (duty cycle) of the switch to regulate Vout2 to the target level.

[0066] Fig.10 A cross-sectional view of a stack 1000 is depicted according to various embodiments, the stack including a package substrate layer 1010, a VR die 1020, an intermediate layer 1030, and a load die 1040, wherein an example forward VR 1050 is formed with a transformer 1060 located between the die. The VR includes a transformer 1060 including a primary winding 1061, a reset winding 1062, and a secondary winding 1063. The reset winding is used to prevent the magnetic field of the transformer from collapsing. The primary winding has an input terminal 1065 that receives Vin via an input path 1066. An output terminal 1067 of the primary winding is coupled to ground via a switch 1068. The reset winding has an input terminal 1070 coupled to the input path 1066 and an output terminal 1071 coupled to a diode 1072. The secondary winding has an input 1073 coupled to an output path 1074 to provide an intermediate voltage Vint to an input 1078 of the inductor 1064 via a diode 1075. The diode 1075 is coupled to an output 1076 of the secondary winding via a diode 1077. The output 1079 of the inductor is coupled to a path 1080 to provide Vout to a current sink 1081. The current sink is coupled in parallel with Cout and in series with a ground path 1082.

[0067] In a forward VR, when switch 1068 is closed, a first current flows through the primary winding to store energy in the transformer. In addition, a second current flows from the secondary winding to the current sink through diode 1075 and inductor 1064. When switch 1068 is closed, current flows through capacitor Cout. The output voltage of the forward converter is controlled by the input voltage, the turns ratio between the primary and secondary windings, and the duty cycle. An active clamp circuit can be used to eliminate the need for a reset winding 1062.

[0068] Die 1020 is a first die and die 1040 is a second die.

[0069] Fig.11 1100 may provide a voltage Vout to one or more components of the computing system 1150. The VR may be controlled by a control signal provided by the processor circuit 1152. The VR may include any VR discussed herein, including Figure 6-Figure 10 Those in .

[0070] The memory circuit 1154 may store instructions, and the processor circuit 1152 may execute the instructions to perform the functions described herein.

[0071] The computing system 1150 may include any combination of the hardware or logic components mentioned herein. These components may be implemented as ICs, portions thereof, discrete electronic devices, or other modules, instruction sets, programmable logic or algorithms, hardware, hardware accelerators, software, firmware, or a combination thereof adapted in the computing system 1150, or as components otherwise contained within a housing of a larger system. For one embodiment, at least one processor 1152 may be packaged together with the computing logic 1182 and configured to implement aspects of the various example embodiments described herein to form a system-in-package (SiP) or a system-on-chip (SoC).

[0072] System 1150 includes a processor circuit in the form of one or more processors 1152. Processor circuit 1152 includes circuits such as (but not limited to): one or more processor cores and one or more of the following: cache memory, low drop-out (LDO) voltage regulator, interrupt controller, serial interface such as SPI, I2C or general programmable serial interface circuit, real time clock (RTC), timer-counter including interval and watchdog timer, general I / O, memory card controller such as secure digital / multi-media card (SD / MMC) or similar interface, mobile industry processor interface (MIPI) interface and joint test access group (JTAG) test access port. In some implementations, processor circuit 1152 may include one or more hardware accelerators (e.g., the same or similar to acceleration circuit 1164), which may be microprocessors, programmable processing devices (e.g., FPGA, ASIC, etc.), etc. The one or more accelerators may include, for example, computer vision and / or deep learning accelerators. In some implementations, the processor circuit 1152 may include on-chip memory circuitry, which may include any suitable volatile and / or non-volatile memory, such as DRAM, SRAM, EPROM, EEPROM, flash memory, solid-state memory, and / or any other type of memory device technology, such as those discussed herein.

[0073] The processor circuit 1152 may include, for example, one or more processor cores (CPUs), application processors, GPUs, RISC processors, Acorn RISC Machine (ARM) processors, CISC processors, one or more DSPs, one or more FPGAs, one or more PLDs, one or more ASICs, one or more baseband processors, one or more radio-frequency integrated circuits (RFICs), one or more microprocessors or controllers, multi-core processors, multi-threaded processors, ultra-low voltage processors, embedded processors, or any other known processing elements, or any suitable combination of these. The processor (or core) 1152 may be coupled to or may include a memory / storage device, and may be configured to execute instructions stored in the memory / storage device to enable various applications or operating systems to run on the platform 1150. The processor (or core) 1152 is configured to operate application software to provide specific services to users of the platform 1150. In some embodiments, the (one or more) processors 1152 may be (or may be configured to) be (one or more) dedicated processors / controllers configured to operate according to various embodiments herein.

[0074] As an example, the processor(s) 1152 may include Core based architecture TM Processors such as i3, i5, i7, i9 based processors; Microcontroller-based processors such as Quark TM 、Atom TM Or other MCU-based processors; (one or more) Processor(s), processor, or available from Santa Clara, California However, any number of other processors may be used, such as one or more of the following: Advanced Micro Devices (AMD) Architecture, such as (one or more) or Processor, Accelerated Processing Unit (APU), MxGPU, (one or more) processor, etc.; from The company's (one or more) A5-A12 and / or S1-S4 processors, from Snapdragon(s) from technology companies TM or Centriq TM Processor, Texas Instruments, (One or more) Open Multimedia Applications Platform (OMAP) TM Processors; MIPS-based designs from MIPS Technologies Inc., such as the MIPS Warrior M-class, Warrior I-class, and Warrior P-class processors; ARM-based designs licensed from ARM Holdings plc, such as the ARM Cortex-A, Cortex-R, and Cortex-M series processors; and processors manufactured by Cavium TM Provided by the company In some implementations, the processor(s) 1152 may be part of a system on a chip (SoC), a system-in-Package (SiP), a multi-chip package (MCP), etc., where the processor(s) 1152 and other components are formed as a single integrated circuit, or a single package, such as from Edison TM or Galileo TM SoC Board. Other examples of processor(s) 1152 are mentioned elsewhere in this disclosure.

[0075] The system 1150 may include or be coupled to an acceleration circuit 1164, which may be implemented by one or more AI / ML accelerators, neural compute sticks, neuromorphic hardware, FPGAs, arrangements of GPUs, one or more SoCs (including programmable SoCs), one or more CPUs, one or more digital signal processors, dedicated ASICs (including programmable ASICs), PLDs (such as complex PLDs (CPLDs) or high complexity PLDs (HCPLDs)), and / or other forms of specialized processors or circuits designed to implement one or more specialized tasks. These tasks may include AI / ML processing (e.g., including training, inference, and classification operations), visual data processing, network data processing, object detection, rule analysis, and the like. In an FPGA-based implementation, the acceleration circuit 1164 may include logic blocks or logic architectures and other interconnected resources that may be programmed (configured) to perform various functions, such as the processes, methods, functions, and the like of the various embodiments discussed herein. In such an implementation, the acceleration circuit 1164 may also include a memory unit (e.g., EPROM, EEPROM, flash memory, static memory (e.g., SRAM, antifuse, etc.) for storing logic blocks, logic architectures, data, etc. in a LUT, etc.

[0076] In some implementations, the processor circuit 1152 and / or the acceleration circuit 1164 may include hardware elements specifically customized for machine learning and / or artificial intelligence (AI) functions. In these implementations, the processor circuit 1152 and / or the acceleration circuit 1164 may be or may include an AI engine chip that, once loaded with appropriate weighting and training code, can run many different kinds of AI instruction sets. Additionally or alternatively, the processor circuit 1152 and / or the acceleration circuit 1164 may be or may include (one or more) AI accelerators, which may be one or more of the above-mentioned hardware accelerators designed for hardware acceleration of AI applications. As an example, these processors or accelerators may be a cluster of the following: artificial intelligence (AI) GPU, The company developed the tensor processing unit (TPU), The Real AI Processor (RAP TM ), Nervana provided by the company TM Neural Network Processor (NNP), Movidius TM Myriad TM XVision Processing Unit (VPU), based on PX TM GPU, General Provided NM500 chip, Hardware provided by the company 3. Provided by Epiphany TM In some embodiments, the processor circuit 1152 and / or the acceleration circuit 1164 and / or the hardware accelerator circuit may be implemented as (one or more) AI acceleration coprocessors, such as Hexagon 685DSP, Imagination Technologies PowerVR 2NX Neural Net Accelerator (NNA) provided, The Neural Engine core inside the A11 or A12 Bionic SoC, The neural processing unit (NPU) within the HiSilicon Kirin 970 provided, etc. In some hardware-based implementations, the individual subsystems of the system 1150 can be operated by various AI acceleration coprocessors, AI GPUs, TPUs or hardware accelerators (e.g., FPGAs, ASICs, DSPs, SoCs, etc.), etc., which are configured with appropriate logic blocks, (one or more) bitstreams, etc. to perform their respective functions.

[0077] The system 1150 also includes a system memory 1154. Any number of memory devices may be used to provide a fixed amount of system memory. As an example, the memory 1154 may be or may include volatile memory, such as random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), Dynamic Random Access Memory (DRAM) Dynamic Random Access Memory, ), and / or any other desired type of volatile memory device. Additionally or alternatively, the memory 1154 may be or may include a non-volatile memory, such as a read-only memory (ROM), an erasable programmable ROM (EPROM), an electrically erasable programmable (EEPROM), flash memory, a non-volatile RAM, a ferroelectric RAM, a phase-change memory (PCM), flash memory, and / or any other desired type of non-volatile memory device. Access to the memory 1154 is controlled by a memory controller. Individual memory devices may have any number of different package types, such as a single die package (SDP), a dual die package (DDP), or a quad die package (Q17P). Any number of other memory implementations may be used, such as different types of dual inline memory modules (DIMMs), including but not limited to microDIMMs or MiniDIMMs.

[0078] Storage circuitry 1158 provides persistent storage of information such as data, applications, operating systems, and the like. In one example, storage 1158 may be implemented via a solid-state disk drive (SSDD) and / or a high-speed electrically erasable memory (commonly referred to as "flash memory"). Other devices that may be used for storage 1158 include flash memory cards, such as SD cards, microSD cards, XD picture cards, and the like, and USB flash drives. In one example, the memory device may be or may include a memory device using chalcogenide glass, a multi-threshold level NAND flash memory, a NOR flash memory, a single-level or multi-level phase change memory (PCM), a resistive memory, a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), an antiferroelectric memory, a magnetoresistive random access memory (MRAM) memory including memristor technology, a phase change RAM (PRAM), a resistive memory including a metal oxide substrate, an oxygen vacancy substrate and a conductive bridge random access memory (CB-RAM), or a spin transfer torque (STT)-MRAM, a device based on a spin electronic magnetic junction memory, a device based on a magnetic tunneling junction (MTJ), a device based on a domain wall (DW) and a spin orbit transfer (SOT), a semiconductor thyristor-based memory device, a hard disk drive (HDD) drive, HDD), micro HDD, or a combination of these, and / or any other memory. Memory circuit 1154 and / or storage circuit 1158 may also include and Three-dimensional (3D) cross-point (XPOINT) memory.

[0079] The memory circuit 1154 and / or the storage circuit 1158 are configured to store computing logic 1183 in the form of software, firmware, microcode, or hardware-level instructions to implement the techniques described herein. The computing logic 1183 may be employed to store a working copy and / or permanent copy of programming instructions, or data used to create programming instructions, for use with various components of the operating system 1150 (e.g., drivers, libraries, application programming interfaces (APIs), etc.), the operating system of the system 1150, one or more applications, and / or for implementing the embodiments discussed herein. The computing logic 1183 may be stored or loaded into the memory circuit 1154 as instructions 1182 or data used to create instructions 1182, and then accessed by the processor circuit 1152 for execution to implement the functions described herein. The processor circuit 1152 and / or the acceleration circuit 1164 access the memory circuit 1154 and / or the storage circuit 1158 via the interconnect (IX) 1156. The instructions 1182 direct the processor circuit 1152 to perform a particular sequence of actions or flow, for example, as described with reference to the previously depicted flowchart(s) and block diagram(s) of operations and functions. The various elements may be implemented by assembly instructions or a high-level language supported by the processor circuit 1152, which may be compiled into instructions 1188, or data used to create instructions 1188, for execution by the processor circuit 1152. A permanent copy of the programming instructions may be placed into a persistent storage device of the storage circuit 1158 at the factory or in the field, for example, via a distribution medium (not shown), via a communication interface (e.g., from a distribution server (not shown)), over the air (OTA), or any combination of these.

[0080] IX 1156 couples processor 1152 to communication circuitry 1166 for communication with other devices, such as a remote server (not shown), etc. Communication circuitry 1166 is a hardware element, or a collection of hardware elements, for communicating over one or more networks 1163 and / or communicating with other devices. In one example, communication circuitry 1166 is or includes transceiver circuitry configured to implement wireless communications using any number of frequencies and protocols, such as Institute of Electrical and Electronics Engineers (IEEE) 802.11 (and / or variants thereof), IEEE 802.23.4, and / or Low energy ( low energy, BLE), LoRaWAN TM(Long Range Wide Area Network), cellular protocols such as 3GPP LTE and / or Fifth Generation (5G) / New Radio (NR), etc. Additionally or alternatively, the communication circuit 1166 is or includes one or more network interface controllers (NICs) to enable wired communications using, for example, an Ethernet connection, a Controller Area Network (CAN), a Local Interconnect Network (LIN), DeviceNet, ControlNet, Data Highway+, or PROFINET, etc.

[0081] IX 1156 also couples processor 1152 to interface circuitry 1170 for connecting system 1150 to one or more external devices 1172. External devices 1172 may include, for example, sensors, actuators, positioning circuits (e.g., global navigation satellite system (GNSS) / Global Positioning System (GPS) circuits), client devices, servers, network appliances (e.g., switches, hubs, routers, etc.), integrated photonics devices (e.g., optical neural network (ONN) integrated circuits (ICs), etc.), and / or other similar devices.

[0082] In some optional examples, various input / output (I / O) devices may be present in or connected to the system 1150, which are referred to as input circuits 1186 and output circuits 1184. The input circuits 1186 and output circuits 1184 include one or more user interfaces designed to enable a user to interact with the platform 1150, and / or peripheral component interfaces designed to enable peripheral components to interact with the platform 1150. The input circuit 1186 may include any physical or virtual device for accepting input, including, in particular, one or more physical or virtual buttons (e.g., reset buttons), physical keyboards, keypads, mice, touch pads, touch screens, microphones, scanners, headsets, and the like. The output circuit 1184 may be included to show information or otherwise convey information, such as sensor readings, (one or more) actuator positions, or other similar information. Data and / or graphics may be displayed on one or more user interface components of the output circuit 1184. Output circuitry 1184 may include any number and / or combination of audio or visual displays, including, in particular, one or more simple visual outputs / indicators (e.g., binary status indicators (e.g., light emitting diodes (LEDs)) and multi-character visual outputs, or more complex outputs such as display devices or touch screens (e.g., liquid crystal displays (LCDs)). Display, LCD), LED display, quantum dot display, projector, etc.), where output of characters, graphics, multimedia objects, and the like is generated or produced from the operation of platform 1150. Output circuitry 1184 may also include speakers and / or other audio emitting devices, (one or more) printers, and the like. Additionally or alternatively, (one or more) sensors may be used as input circuitry 1184 (e.g., image capture devices, motion capture devices, and the like) and one or more actuators may be used as output device circuitry 1184 (e.g., actuators to provide tactile feedback or the like). Peripheral component interfaces may include, but are not limited to, non-volatile memory ports, USB ports, audio jacks, power interfaces, and the like. In some embodiments, in the context of the present system, display or console hardware may be used to provide output and receive input to an edge computing system; manage components or services of an edge computing system; identify the status of an edge computing component or service; or perform any other number of management or administrative functions or service use cases.

[0083] The components of the system 1150 may communicate via the IX 1156. The IX 1156 may include any number of technologies including ISA, extended ISA, I2C, SPI, point-to-point interface, power management bus (PMBus), PCI, PCIe, PCIx, UPI, Accelerator Link, CXL, CAPI, OpenCAPI, QPI, UPI, OPA IX, RapidIO TM System IX, CCIX, Gen-Z Consortium IX, HyperTransport Interconnect, NVLink, a Time-Trigger Protocol (TTP) system, a FlexRay system, PROFIBUS, and / or any number of other IX technologies provided. IX 1156 can be a proprietary bus used, for example, in a SoC-based system.

[0084] The number, capabilities, and / or capacity of the elements of the system 1150 may vary, depending on whether the computing system 1150 is used as a fixed computing device (e.g., a server computer in a data center, a workstation, a desktop computer, etc.) or a mobile computing device (e.g., a smart phone, a tablet computing device, a laptop computer, a gaming console, an IoT device, etc.). In various implementations, the computing device system 1150 may include one or more components of a data center, a desktop computer, a workstation, a laptop computer, a smart phone, a tablet device, a digital camera, a smart home appliance, a smart home hub, a network appliance, and / or any other device / system that processes data.

[0085] The techniques described herein may be performed in part or in whole by software or other instructions provided in a machine-readable storage medium (e.g., memory). The software is stored as processor-executable instructions (e.g., instructions that implement any other process discussed herein). The instructions associated with the flow charts (and / or various embodiments) and executed to implement embodiments of the disclosed subject matter may be implemented as part of an operating system or a specific application, component, program, object, module, routine, or other sequence of instructions or organization of sequences of instructions.

[0086] The storage medium may be a tangible, non-transitory machine-readable medium, such as read only memory (ROM), random access memory (RAM), flash memory devices, floppy disks and other removable disks, magnetic storage media, optical storage media (e.g., Compact Disk Read-Only Memory (CD ROMS), Digital Versatile Disk (DVD)), and the like.

[0087] The storage medium may be included in, for example, a communication device, a computing device, a network device, a personal digital assistant, a manufacturing tool, a mobile communication device, a cellular phone, a notebook computer, a tablet device, a game console, a set-top box, an embedded system, a TV (television), or a personal desktop computer.

[0088] Some non-limiting examples of various embodiments are given below.

[0089] Example 1 includes a device comprising: a first die comprising a substrate and a plurality of metal layers above the substrate, including a first top metal layer; a second die comprising a substrate and a plurality of metal layers above the substrate, including a second top metal layer; wherein the second die is stacked with the first die and is in an inverted position relative to the first die; and a voltage regulator comprising an input path in the first die, an output path in the second die, and an inductor coupled to the input path and the output path, wherein the inductor comprises at least one of a portion of the first top metal layer or a portion of the second top metal layer.

[0090] Example 2 includes the apparatus of Example 1, wherein the inductor has a planar spiral shape.

[0091] Example 3 includes the apparatus of Example 1 or 2, wherein the inductor comprises a plurality of vertical turns including the portion of the first top metal layer and the portion of the second top metal layer.

[0092] Example 4 includes the apparatus of Example 3, further comprising a magnetic material between the first die and the second die, wherein the plurality of vertical turns surround the magnetic material.

[0093] Example 5 includes the apparatus of Example 3, further comprising a non-magnetic material between the first die and the second die, wherein the plurality of vertical turns surround the non-magnetic material.

[0094] Example 6 includes the apparatus of any one of Examples 1-5, wherein the voltage regulator is a buck converter and includes a first switch and a second switch on the first die, the first switch being used to couple the input path to an input end of the inductor, and the second switch being used to couple the input end of the inductor to ground.

[0095] Example 7 includes the apparatus of any one of Examples 1-6, wherein the voltage regulator is a boost converter and includes a first switch and a second switch on the first die, the first switch being used to couple the output end of the inductor to ground, and the second switch being used to couple the output end of the inductor to the output path.

[0096] Example 8 includes an apparatus as described in any one of Examples 1-7, wherein: the voltage regulator is a single-input multiple-output converter; the output path is among a plurality of output paths in the second die; and the voltage regulator includes a first switch and a second switch on the first die, the first switch being used to couple the input path to an input end of the inductor, and the second switch being used to couple the input end of the inductor to ground.

[0097] Example 9 includes the apparatus of any one of Examples 1 to 8. Also included is at least one of an integrated circuit, a system on a chip, a system-in-package, or a computing device in which the first die, the second die, and the voltage regulator are disposed, wherein the computing device includes at least one of the following: a processor circuit, a memory circuit, a storage circuit, an acceleration circuit, a communication circuit, an input circuit, an output circuit, an interface circuit, or an external device.

[0098] Example 10 includes a device comprising: a first die; a second die stacked on the first die in an inverted position relative to the first die; a magnetic material between the first die and the second die; and a voltage regulator comprising an input path in the first die, an output path in the second die, a primary winding of a transformer surrounding the magnetic material, and a secondary winding of the transformer surrounding the magnetic material, wherein the primary winding is coupled to the input path and the secondary winding is coupled to the output path.

[0099] Example 11 includes the apparatus of Example 10, wherein the second die is a load die including circuitry to be powered by the output path.

[0100] Example 12 includes the apparatus of Example 10, further comprising a load die stacked on the second die, wherein the second die includes an additional voltage regulator to step down the voltage at the output path to a step-down converted output voltage for use by the load die.

[0101] Example 13 includes an apparatus as described in any of Examples 10-12, wherein: the first die includes a substrate and a plurality of metal layers above the substrate, including a first top metal layer; the second die includes a substrate and a plurality of metal layers above the substrate, including a second top metal layer; the primary winding includes portions of the first top metal layer and portions of the second top metal layer; and the secondary winding includes portions of the first top metal layer and portions of the second top metal layer.

[0102] Example 14 includes the apparatus of any of Examples 10-13, wherein the voltage regulator is a flyback converter and includes one or more switches on the first die coupled to the primary winding.

[0103] Example 15 includes the apparatus of any of Examples 10-14, wherein: the voltage regulator is a forward converter and includes an inductor coupled to the secondary winding; and the inductor includes a winding surrounding the magnetic material.

[0104] Example 16 includes the apparatus of any of Examples 10-15, wherein the substrate of the first die includes gallium nitride and the substrate of the second die includes silicon.

[0105] Example 17 includes a voltage regulator comprising: a magnetic material between a first die and a second die; and a conductive coil wound around the magnetic material, wherein the conductive coil comprises portions of a metal layer of the first die and portions of a metal layer of the second die, and the second die is in an inverted orientation relative to the first die in a stack formed with the first die.

[0106] Example 18 includes the voltage regulator of Example 17, wherein the conductive coil comprises an inductor in an inductor-based voltage regulator.

[0107] Example 19 includes the voltage regulator of Example 17, wherein the conductive coil comprises a winding of a transformer in a transformer-based voltage regulator.

[0108] Example 20 includes a voltage regulator as described in any of Examples 17-19, wherein: the second die is inverted relative to the first die; and the conductive coil includes a portion of a top metal layer of the first die and a portion of a top metal layer of the second die.

[0109] Example 21 includes a method comprising: receiving an input voltage at an input path of a voltage regulator and at an inductor coupled to the input path; and receiving an output voltage of the inductor at an output path of the voltage regulator, wherein: the input path is in a first die; the output path is in a second die; the first die includes a substrate and a plurality of metal layers above the substrate, including a first top metal layer; the second die includes a substrate and a plurality of metal layers above the substrate, including a second top metal layer; the second die forms a stack with the first die and is in an inverted position relative to the first die; and the inductor includes at least one of a portion of the first top metal layer or a portion of the second top metal layer.

[0110] Example 22 includes a non-transitory machine-readable storage device including machine-readable instructions that, when executed, cause a processor or other circuit or computing device to implement the method as described in Example 21.

[0111] Example 23 includes a computer program comprising instructions, which, when executed by a computer, cause the computer to perform the method as described in Example 21.

[0112] Various operations may be described in turn as a plurality of discrete actions or operations in a manner that is most helpful for understanding the claimed subject matter. However, the order of description should not be interpreted as meaning that these operations must be dependent on the order. Specifically, these operations may not be performed in the order presented. The operations described may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the operations described may be omitted in additional embodiments.

[0113] The terms "substantially," "close," "roughly," "approximately," and "about" generally refer to within + / -10% of a target value. Unless otherwise indicated, the use of ordinal adjectives "first," "second," and "third," etc., to describe common objects simply indicates that different instances of similar objects are referenced, and is not intended to imply that the objects so described must be in a given sequence in time, space, ranking, or in any other manner.

[0114] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0115] The description may use the phrases "in one embodiment" or "in an embodiment", each of which may refer to one or more identical or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in embodiments of the present disclosure are synonymous.

[0116] As used herein, the term "circuitry" may refer to, be a part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), a combinational logic circuit, and / or other suitable hardware components that provide the described functionality. As used herein, a "computer-implemented method" may refer to any method performed by one or more processors, a computer system having one or more processors, a mobile device such as a smart phone (which may include one or more processors), a tablet device, a laptop computer, a set-top box, a game console, and the like.

[0117] The terms "coupled," "communicatively coupled," and their derivatives are used herein. The term "coupled" may mean that two or more elements are in direct physical or electrical contact with each other, may mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and / or may mean that one or more other elements are coupled or connected between the elements allegedly coupled to each other. The term "directly coupled" may mean that two or more elements are in direct contact with each other. The term "communicatively coupled" may mean that two or more elements are in contact with each other by means of communication, including by wires or other interconnections, by wireless communication channels or links, and the like.

[0118] References in the specification to "an embodiment", "one embodiment", "some embodiments" or "other embodiments" mean that the particular features, structures or characteristics described in connection with these embodiments are included in at least some embodiments, but not necessarily in all embodiments. The various appearances of "an embodiment", "one embodiment" or "some embodiments" do not necessarily all refer to the same embodiment. If the specification states that a component, feature, structure or characteristic "may", "might" or "could" be included, that particular component, feature, structure or characteristic is not required to be included. If the specification or claims refer to "an" element, it does not mean that there is only one of that element. If the specification or claims refer to "an additional" element, it does not exclude that there is more than one of that additional element.

[0119] In addition, in one or more embodiments, specific features, structures, functions or characteristics can be combined in any appropriate manner. For example, the first embodiment can be combined with the second embodiment at any place where the specific features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

[0120] Although the present disclosure has been described in conjunction with its specific embodiments, many alternatives, modifications and variations of such embodiments will be apparent to those skilled in the art from the foregoing description. The embodiments of the present disclosure are intended to encompass all such alternatives, modifications and variations falling within the broad scope of the appended claims.

[0121] In addition, for simplicity of illustration and discussion, and in order not to obscure the present disclosure, known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the given figures. In addition, the arrangement may be shown in block diagram form to avoid obscuring the present disclosure, and also taking into account the fact that the specific details of the implementation of such block diagram arrangements are highly dependent on the platform in which the present disclosure is to be implemented (i.e., such specific details should be fully within the scope of those skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the present disclosure, it should be clear to those skilled in the art that the present disclosure may be implemented without these specific details, or with variations of these specific details. The specification should therefore be considered illustrative, not restrictive.

[0122] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. A device comprising: a first die comprising a substrate and a plurality of metal layers over the substrate including a first top metal layer; a second die including a substrate and a plurality of metal layers above the substrate, including a second top metal layer, wherein the second die is stacked with the first die and is in an inverted position relative to the first die; and A voltage regulator comprising an input path in the first die, an output path in the second die, and an inductor coupled to the input path and the output path, wherein the inductor comprises at least one of a portion of the first top metal layer or a portion of the second top metal layer.

2. The device according to claim 1, wherein: The inductor has a planar spiral shape.

3. The device according to claim 1 or 2, wherein: The inductor includes a plurality of vertical turns including the portion of the first top metal layer and the portion of the second top metal layer. 4 . The apparatus of claim 3 , further comprising a magnetic material between the first die and the second die, wherein the plurality of vertical turns surround the magnetic material. 5 . The apparatus of claim 3 , further comprising a non-magnetic material between the first die and the second die, wherein the plurality of vertical turns surround the non-magnetic material.

6. The device according to claim 1 or 2, wherein: The voltage regulator is a buck converter and includes on the first die a first switch for coupling the input path to an input terminal of the inductor and a second switch for coupling the input terminal of the inductor to ground.

7. The device according to claim 1 or 2, wherein: The voltage regulator is a boost converter and includes on the first die a first switch for coupling an output terminal of the inductor to ground and a second switch for coupling the output terminal of the inductor to the output path.

8. The device according to claim 1 or 2, wherein: The voltage regulator is a single-input multiple-output converter; The output path is among a plurality of output paths in the second die; and The voltage regulator includes a first switch and a second switch on the first die, the first switch being used to couple the input path to an input terminal of the inductor, the second switch being used to couple the input terminal of the inductor to ground.

9. The apparatus of claim 1 or 2, further comprising at least one of an integrated circuit, a system on chip, a system in package, or a computing device, wherein the first die, the second die, and the voltage regulator are disposed in the at least one, wherein: The computing device includes at least one of: a processor circuit, a memory circuit, a storage circuit, an acceleration circuit, a communication circuit, an input circuit, an output circuit, an interface circuit, or an external device.

10. An apparatus comprising: a first tube core; a second die stacked on the first die in an inverted position relative to the first die; a magnetic material between the first tube core and the second tube core; as well as A voltage regulator comprising an input path in the first die, an output path in the second die, a primary winding of a transformer surrounding the magnetic material, and a secondary winding of the transformer surrounding the magnetic material, wherein the primary winding is coupled to the input path and the secondary winding is coupled to the output path.

11. The device of claim 10, wherein: The second die is a load die that includes circuitry to be powered by the output path.

12. The apparatus of claim 10 or 11, further comprising a load die stacked on the second die, wherein: The second die includes an additional voltage regulator for stepping down the voltage at the output path to a step-down converted output voltage for use by the load die.

13. The device according to claim 10 or 11, wherein: The first die includes a substrate and a plurality of metal layers above the substrate, including a first top metal layer; The second die includes a substrate and a plurality of metal layers above the substrate, including a second top metal layer; the primary winding comprising portions of the first top metal layer and portions of the second top metal layer; and The secondary winding includes portions of the first top metal layer and portions of the second top metal layer.

14. The device according to claim 10 or 11, wherein: The voltage regulator is a flyback converter and includes one or more switches on the first die coupled to the primary winding.

15. The device according to claim 10 or 11, wherein: The voltage regulator is a forward converter and includes an inductor coupled to the secondary winding; and The inductor includes a winding surrounding the magnetic material.

16. The device according to claim 10 or 11, wherein: The substrate of the first die comprises gallium nitride and the substrate of the second die comprises silicon.

17. A voltage regulator comprising: a magnetic material between the first die and the second die; as well as A conductive coil is wound around the magnetic material, wherein the conductive coil includes some portions of the metal layer of the first tube core and some portions of the metal layer of the second tube core, and the second tube core is in an inverted orientation relative to the first tube core in a stack formed with the first tube core.

18. The voltage regulator of claim 17, wherein: The conductive coil comprises an inductor in an inductor based voltage regulator.

19. The voltage regulator of claim 17, wherein: The conductive coil comprises a winding of a transformer in a transformer based voltage regulator.

20. The voltage regulator of claim 17 or 18, wherein: The second die is inverted relative to the first die; and The conductive coil includes a portion of a top metal layer of the first die and a portion of a top metal layer of the second die.

21. A method comprising: receiving an input voltage at an input path of a voltage regulator and at an inductor coupled to the input path; and The output voltage of the inductor is received at an output path of the voltage regulator, wherein: The input path is in the first die; The output path is in the second die; The first die includes a substrate and a plurality of metal layers above the substrate, including a first top metal layer; The second die includes a substrate and a plurality of metal layers above the substrate, including a second top metal layer; The second die forms a stack with the first die and is in an inverted position relative to the first die; and The inductor includes at least one of a portion of the first top metal layer or a portion of the second top metal layer.

22. The method of claim 21, wherein: The inductor has a planar spiral shape.

23. The method of claim 21 or 22, wherein: The inductor includes a plurality of vertical turns including the portion of the first top metal layer and the portion of the second top metal layer.

24. A non-transitory machine-readable storage device comprising machine-readable instructions which, when executed, cause a processor or other circuit or computing device to implement the method of claim 21.

25. A computer program comprising instructions, which, when executed by a computer, cause the computer to perform the method of claim 21.

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