Voltage converter based on input side packaged inductor

Abstract

The invention relates to a voltage converter based on an input side packaged inductor. Embodiments herein relate to a voltage regulator (VR) formed from a first die stacked on a package substrate layer. The VR may have an inductor antecedent design in which an inductor is in a package substrate layer and an active circuit, such as a switch, is in a first die. The inductor receives an input voltage Vin directly from the package substrate layer, which does not first enter the first die. In some embodiments, the VR may include a kappa VR that includes first and second inductors in an encapsulation substrate layer. The inductor may have an asymmetric inductance to improve efficiency. The VR may be cascaded with a set of current multipliers or continuously scalable conversion ratio (CSCR) capacitive regulators. Another example implementation includes a switched inductor capacitor converter cascaded with a set of switched capacitor current multipliers.

Description

Technical Field

[0001] The present application relates generally to the field of voltage converters. Background Art

[0002] Computing devices often rely on voltage converters, also known as voltage regulators, to obtain power. For example, a direct current (DC) to DC voltage converter can convert a power source at one DC voltage to another, usually lower DC voltage. The voltage converter can step down the main supply voltage (e.g., 12-48V) of the computing device to a lower voltage (e.g., about 1V). The lower voltage can be used by various components in the computing device, such as Universal Serial Bus (USB) interfaces, memories such as dynamic random access memory (DRAM), and processing resources such as central processing units (CPUs). However, supplying power in an efficient and economical manner is challenging. Summary of the invention

[0003] According to one aspect of the present application, a device is provided, comprising: a packaging substrate layer; a first tube core stacked on the packaging substrate layer; and a voltage converter, which includes a first inductor, an input node and an input path in the packaging substrate layer, and an active circuit in the first tube core, wherein the input path is used to couple the input node to the input end of the first inductor without entering the first tube core, and the active circuit is coupled to the output end of the first inductor.

[0004] According to another aspect of the present application, a device is provided, comprising: a packaging substrate layer; a first tube core stacked on the packaging substrate layer; and an inductor-first voltage converter, wherein the inductor-first voltage converter comprises a first inductor in the packaging substrate layer and an active circuit in the first tube core, the first inductor is coupled to an input node of the packaging substrate layer, and the active circuit is coupled to the first inductor.

[0005] According to another aspect of the present application, a device is provided, comprising: a first inductor in a stacked packaging substrate layer; and an active circuit in one or more tube cores in the stack, wherein: the one or more tube cores are above the packaging substrate layer in the stack; the input end of the first inductor is coupled to a voltage input node of the packaging substrate layer through a switch-free path in the packaging substrate layer; and the output end of the first inductor is coupled to the active circuit through a switch-free path in the packaging substrate layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The embodiments of the present disclosure will be more fully understood through the detailed description given below and through the drawings of various embodiments of the present disclosure, however the detailed description and drawings should not be understood as limiting the present disclosure to specific embodiments but are only for illustration and understanding.

[0007] Figure 1A A cross-sectional view of an example implementation of a stack 100 according to various embodiments is depicted, the stack 100 including a package substrate layer 110 (including an inductor L of a voltage regulator (VR) 125), a first die 120 (including an active circuit 121 of the VR), and a second die 130 (including a load 131 powered by the VR), wherein a voltage input Vin is provided from the package substrate layer to the active circuit and from the active circuit to the inductor.

[0008] Figure 1B Depicted are various embodiments Figure 1A An example circuit diagram of the VR 125.

[0009] Figure 2A A cross-sectional view of an example implementation of a stack 200 is depicted according to various embodiments, the stack 200 including a package substrate layer 210 (including an inductor L of a voltage regulator (VR) 225), a first die 220 (including active circuits 221 of the VR), and a second die 230 (including a load 231 powered by the VR), wherein a voltage input Vin is provided directly to the inductor in the package substrate layer without first passing through the first die.

[0010] Figure 2B Depicted according to various embodiments, Figure 2A A cross-sectional view of an example implementation of stack 250 similar to stack 200 , where capacitors 222 represent deep trench capacitors or other embedded capacitors that are part of active circuit 221 of VR 225 .

[0011] Figure 3 Depicted according to various embodiments, as Figure 2A A circuit diagram of a Kappa VR 300 of an example implementation of the VR 225 .

[0012] Figure 4 Depicted are according to various embodiments, Figure 3 A graph of the efficiency of a Kappa VR versus load current is shown, where inductors L1 and L2 have the same inductance (graph 400) and the inductance of L1 is greater than the inductance of L2 by a ratio of 3:1 (graph 410).

[0013] Figure 5A Depicted according to various embodiments, as Figure 2A Another example implementation of VR 225 is a circuit diagram of VR 500, which includes Figure 3 The Kappa VR 300 and a set of current multipliers 510 thereafter.

[0014] Figure 5B Depicted is a switched capacitor buck converter according to various embodiments. Figure 5A A circuit diagram of an example implementation of a current multiplier.

[0015] Figure 5C Depicted are according to various embodiments, Figure 5A 0046] An example set of control signals for current multiplier 510 is shown in FIG.

[0016] Figure 6 Depicted are according to various embodiments, Figure 3 and Figure 5A Example plots of efficiency versus load current for various implementations of Kappa VR.

[0017] Figure 7 Depicted according to various embodiments, as Figure 2A 2 is a circuit diagram of another example implementation of VR 700 that includes VR 750 as a switched inductor capacitor converter cascaded with a set of 3:1 switched capacitor current multipliers 730.

[0018] Fig. 8A Depicted according to various embodiments, as Figure 2A A circuit diagram of another example implementation of VR 225 is a VR 800, the VR 800 comprising Figure 3 The Kappa VR 300 and the subsequent continuously scalable switching ratio (CSCR) capacitive regulator 810.

[0019] Figure 8B Depicted are various embodiments Fig. 8A 8 is a circuit diagram of an example implementation of a CSCR capacitive regulator 810.

[0020] Fig. 9 Illustrations illustrate examples of components that may be present in a computing system 950 for implementing the techniques (eg, operations, processes, methods, and approaches) described herein. DETAILED DESCRIPTION

[0021] As workloads and power demands of large computing complexes continue to increase, the industry is moving toward 3D integration of integrated voltage regulators (VRs).

[0022] In one possible approach, the VR is placed directly below the load. This approach is more advantageous for area and power. For example, a vertical power delivery architecture using a buck converter might include active circuitry on the substrate die, combined with a high quality factor (Q) inductor in the package substrate layer below the substrate die. In this configuration, power flows into the substrate die, returns down to the inductor in the package substrate layer, and then returns up through the substrate die to the load on the top die. See also Figure 1A The circuitous route that power takes from the package substrate to the load can result in excessive conduction losses, which is made worse by the need to partition vertical conduction resources such as through-silicon vias (TSVs), package through-holes, and bumps between various upward and downward paths. In addition, the input current of the buck converter is discontinuous, resulting in the need for large decoupling capacitors at the package substrate and / or on the die.

[0023] Generally speaking, inductors in VR can be integrated on the top metal layer of the base die, with or without a magnetic core, which keeps the power flow unidirectional. However, on-chip inductors are much worse in terms of current density and losses, due to the relatively low permeability of the magnetic materials available for integration, and the fact that even the top metal layer on the die is relatively thin, increasing resistance.

[0024] Alternatively, switched capacitor based topologies can be used on substrate die power converters using integrated capacitors. However, hard switched capacitive topologies are usually limited in terms of current density because the converter losses increase with the depth of discharge during the switching cycle, which increases with current. In addition, integrated capacitors with higher voltage ratings usually have very low capacitance density, which limits the capacitive VR to lower input voltages to maintain reasonable current density.

[0025] The solution provided herein addresses the above disadvantages and others. In one aspect, a step-down converter topology is equipped with an inductor on the input side of the VR. High-Q inductors can be implemented inside the package substrate layer, for example, coaxial, horizontal or vertical solenoids, with or without magnetic material, and power flows upward into the active converter circuit on the substrate die and continues to flow to the load die on the top. These converters can be cascaded with downstream current multiplier stages (e.g., N:1 unregulated switched capacitor converters) integrated on either die, thereby alleviating the burden of step-down conversion on the inductor-first VR on the substrate die. In addition, in such a topology with inductors on both the input (Vin) and return (Vss) paths, called a Kappa converter, the asymmetry between the inductors can be used to improve efficiency at high conversion ratios.

[0026] These solutions offer several advantages. For example, regarding inductor size, since the input current is lower than the output current in a voltage step-down converter, moving the inductor to the input side reduces the inductor current, thereby reducing the inductor size and cost, and reducing losses. In addition, adding a current multiplier stage on the output side further reduces the current conduction losses through the inductor.

[0027] In addition, electromagnetic interference (EMI) and radio frequency interference (RMI), as well as cost, can be reduced. Since there is a clear inductor on the input side, the parasitic inductance on the input of the converter can be easily absorbed into its operation, which can reduce costs by allowing higher parasitic effects and / or smaller decoupling capacitors. In addition, the converter with an inductor on the input side has a continuous input current, which improves the EMI / RFI generated by the converter. These advantages also allow the converter to be directly connected to a battery or other main energy source of the system.

[0028] Another advantage is unidirectional power flow. Specifically, power flows vertically from the package substrate layer through the VRs on the substrate die to the top die, reducing losses and reducing the need for high-density, low-resistance vertical conduction paths, such as TSV arrays through the substrate die.

[0029] These and other features will become further apparent from the discussion below.

[0030] Figure 1A A cross-sectional view of an example implementation of a stack 100 according to various embodiments is depicted, the stack 100 including a package substrate layer 110 (including an inductor L of a voltage regulator (VR) 125), a first die 120 (including an active circuit 121 of the VR), and a second die 130 (including a load 131 powered by the VR), wherein a voltage input Vin is provided from the package substrate layer to the active circuit and from the active circuit to the inductor.

[0031] Active circuits may include, for example, switches that interact with passive devices such as capacitors and / or inductors as charge storage elements. VR controller 140 (control circuit) is configured to control the VR, for example by specifying a duty cycle for the switch. The VR controller includes a sensor 141, a processor 142, and a memory 143. The memory stores instructions to be executed by the processor. The sensor is capable of sensing the output voltage of the VR and implementing a control loop to regulate the output voltage. The VR controller can then communicate with a power management unit (PMU). The PMU can be provided as a microcontroller that manages various power functions, such as charging a battery, controlling power to other integrated circuits, shutting down unnecessary system components when they are idle, and controlling sleep and power functions. The PMU 125 can communicate with one or more VRs to, for example, coordinate dynamic voltage and frequency scaling (DVFS) and other efficiency measures. DVFS involves adjusting the power and speed settings on the processor, controller chip, and peripherals of a computing device to optimize resource allocation for tasks and maximize power savings when these resources are not needed. In one possible approach, the PMU may be provided on a system-on-a-chip (SoC) external to the stack.

[0032] In this example, VR uses an inductor L in the package substrate layer to transfer charge from the input voltage Vin to provide an output voltage Vout for use by the load. The inductor can be embedded inside the package substrate layer. In one embodiment, the inductor is formed by a conductive trace in the package substrate layer. Vin can be provided on a conductive path 111 extending upward in the package substrate layer to the VR active circuit in the first tube core 120. The VR active circuit performs functions such as switching to couple Vin to the input end 156 of the inductor via a conductive path 112 extending downward from the first tube core to the package substrate layer. Then, the output end 157 of the inductor is coupled to a conductive path 113, which extends upward in the package substrate layer back to the active circuit. The active circuit performs functions such as switching to couple the charge stored in the inductor to the output node to provide Vout to the load. The input end of the inductor is generally the end that receives the input voltage, and the output end of the inductor is the end that provides the output voltage. In the case of a buck converter, the output voltage is less than the input voltage. The output voltage may be set based on the duty cycle of a control signal that turns one or more switches on or off.

[0033] As described above, in this configuration, power flows into the base die (first die), returns down to the inductor in the package base layer, and then returns up through the base die to the load on the top die. The circuitous route that power takes from the package base layer to the load can result in excessive conduction losses.

[0034] Figure 1B Depicted are various embodiments Figure 1A 1 is an example circuit diagram of VR 125. In this example, VR includes a first portion in the package substrate layer and a second portion in the first tube core. The two portions are connected by nodes / conductive points 151 and 152 (e.g., microbumps between the package substrate layer and the tube core). The first tube core includes two switches, including a high-side switch SHS and a low-side switch SLS in this example. Inductor L has an input terminal 156 and an output terminal 157. Input terminal 156 is coupled to node 151 via SHS, and node 151 receives Vin via input node 150 and path 111. Input terminal 156 is also coupled to ground nodes 152 and 153 via SLS. Diode 154 is coupled between ground and the input terminal of the inductor. The output terminal 157 of the inductor is coupled to the output node 158 of the VR via conductive point 155 to provide Vout to the load 131 via node 160, and node 160 is further coupled to the ground node 152 via node 161 and ground path 159. Nodes / conductive points 160 and 161 are between the first and second dies.

[0035] When SHS is closed, SLS is open and charge is stored in the inductor. When SHS is open, SLS is closed and charge is transferred from the inductor to ground. SHS and SLS are controlled according to the duty cycle, so that the larger the duty cycle, the larger Vout.

[0036] Vin may be provided by a power source on the package substrate layer or outside the package substrate layer.

[0037] The package substrate layer can be mounted on a circuit board such as a motherboard or other printed circuit board and include conductive points on its underside, such as a ball grid array, for communicating with the circuits on the board. The package substrate layer can include conductive paths, such as through holes, to couple the conductive points to the first tube core above, for example, to input voltage or to ground the VR. Each tube core can then similarly include conductive points on its underside to connect to the layer / tube core below. The package substrate layer itself can be considered a high-density circuit board.

[0038] Figure 2AA cross-sectional view of an example implementation of a stack 200 is depicted according to various embodiments, the stack 200 including a package substrate layer 210 (including an inductor L of a voltage regulator (VR) 225), a first die 220 (including active circuits 221 of the VR), and a second die 230 (including a load 231 powered by the VR), wherein a voltage input Vin is provided directly to the inductor in the package substrate layer without first passing through the first die.

[0039] Vin is provided directly to the first end 156 of the inductor on an input path 211, where the input path does not enter the first die, but remains entirely within the package substrate layer. The output end 157 of the inductor is coupled to the active circuit 221 via a path 212 extending from the inductor upward to the first die. As previously described, by coupling the input voltage directly to the input end of the inductor, several advantages can be achieved.

[0040] Dies 220 and 230 may include different materials. For example, die 220 may include a gallium nitride (GaN) substrate that can handle relatively high voltage domains, while die 230 may include a silicon substrate that can handle relatively low voltage domains. Thus, in addition to standard complementary metal-oxide semiconductor (CMOS) semiconductor technology, the first die may be modified to use GaN or other high voltage compatible process nodes, which allows the first stage of the converter with an inductor at the input to operate from a higher input voltage. This is beneficial, for example, if the system is to be directly interfaced to a 2S / 3S battery (two or three batteries arranged in series) that can be as high as 20V, and the switch needs to block such voltages without compromising performance.

[0041] Figure 2B Depicted according to various embodiments, Figure 2A FIG. 2 is a cross-sectional view of an example implementation of a stack 250 similar to the stack 200 of FIG. 2, wherein capacitor 222 represents a deep trench capacitor or other embedded capacitor that is part of the active circuit 221 of VR 225. Various capacitor options are possible for the 3D integrated input inductor first VR. For example, in addition to package components or on-die capacitors, the various flying capacitor options in the converter topologies described herein may include embedded package capacitors or deep-trench capacitors (DTCs). In this example, capacitor 222 is provided in the first die, but may also be located in other locations.

[0042] Figure 3 Depicted according to various embodiments, as Figure 2AFIG. 2 is a circuit diagram of a Kappa VR 300 of an example implementation of a VR 225. In general, a Kappa VR can be configured for step-down (buck), step-up (boost), or buck-boost operation. The Kappa converter circuit exhibits lower electromagnetic interference (EMI) and higher power handling capabilities relative to other buck, boost, or buck-boost topologies. The Kappa VR includes isolation inductors at its input and ground nodes to reduce signal bounce.

[0043] The converter includes two inductors L1 and L2, which can be integrated in the base package layer 210; a flying capacitor Cfly in the first die; and first and second switches 320 and 322, which are respectively implemented as n-type metal oxide semiconductor field effect transistors or nMOSFETs in this example. In general, the switches can be MOSFETs, BJTs or relay switches, for example. These switches can work out of phase, which means that when the second switch is open (non-conducting), the first switch is closed (conducting), and when the second switch is closed, the first switch is open.

[0044] The flying capacitor can be integrated in the first die 220 on the chip, or it can be a packaged capacitor off the chip. The conversion ratio of VR is defined as: Vout / Vin=D, where D is the duty cycle of the pulse-width modulation (PWM) signal that controls the first switch. Due to the small number of switches, such as two, the Kappa converter can be implemented with the same area as a traditional buck converter, while also maintaining the benefit of reducing the conduction losses from the input inductor. The rated voltage on both switches is Vin, the same as the buck converter.

[0045] In more detail, an input voltage Vin at an input node 301 is coupled to an input terminal 303 of L1 on a conductive path 302, and an output terminal 304 of L1 is coupled to a node 306 between the package substrate layer and the first die on a conductive path 305. Node 306 is coupled to a first side 340 of Cfly and a drain side of an nMOS switch 320. A second side 341 of Cfly is coupled to a drain side of an nMOS switch 322 and a node 307. Node 307 is coupled to an input terminal 309 of L2 via a conductive path 308, and an output terminal 310 of L2 is coupled to a ground node 312 via a conductive ground path 311.

[0046] The source side of nMOS switch 320 is coupled to the output node 321 of VR, and the source side of nMOS switch 322 is coupled to the ground node 323. Optionally, the ground node 323 can be coupled to the ground node of the package substrate layer. A first load capacitor or output capacitor Cload1 is coupled between nodes 321 and 323, wherein a first side 342 of Cload1 is coupled to node 321, and a second side 343 of Cload1 is coupled to node 323. The output node 321 is coupled to the load 131 in the second die 230 via node 330, and the load is also coupled to the ground node 323 via node 331.

[0047] Nodes / conductive points 306 and 307 are between the package substrate layer and the first die, while nodes / conductive points 330 and 331 are between the first die and the second die.

[0048] The Kappa VR is an inductor-first VR because the first inductor L1 receives the input voltage Vin directly from a conductive path 302 in the package substrate layer, which does not enter the first die. In addition, in some cases, there is no switch between the input node and the first inductor, so that the path 302 is a switchless path. The second inductor L2 is directly coupled to the ground node 312 via a conductive ground path 311 in the package substrate layer, which does not enter the first die. In addition, in some cases, there is no switch between the ground node and the second inductor, so that the path 311 is a switchless path.

[0049] In one example implementation, the input of the first inductor is coupled to a voltage input node 301 of the package substrate layer through a switchless path 302 in the package substrate layer, and the output of the first inductor is coupled to an active circuit through a switchless path 305 in the package substrate layer. Additionally, the output of the second inductor is coupled to a ground node 312 of the package substrate layer through a switchless path 311 in the package substrate layer, and the input of the second inductor is coupled to the active circuit through a switchless path 308 in the package substrate layer.

[0050] Figure 4 Depicted are according to various embodiments, Figure 3 Graphs of efficiency of a kappa VR versus load current are shown, where inductors L1 and L2 have the same inductance (graph 400) and the inductance of L1 is greater than the inductance of L2 by a ratio of 3:1 (graph 410). For a single-phase input, graph 400 represents the case where L1 = L2 = 4 nH and 10 mΩ. Graph 410 represents the case where L1 = 6 nH, 20 mΩ and L2 = 2 nH, 10 mΩ, so that the inductance ratio of L1 to L2 is 3:1.

[0051] The graph shows that the performance of the Kappa converter can be optimized by introducing asymmetry in the two inductors. In the Kappa converter, the average DC current flowing through each inductor can be expressed as: D*Iload for the top inductor L1 and (1-D)*Iload for the bottom inductor L2. Iload is the load current of the converter. In high conversion ratio scenarios, the duty cycle D may be very small, which leads to the following situation: the bottom inductor conducts most of the output current and causes most of the total inductor losses. In addition, packaged integrated inductors tend to have low inductance (e.g., single-digit nH), resulting in high losses due to current ripple. In the Kappa converter, both inductors have the same peak-to-peak AC inductor current. Given the small DC current through L1 caused by the smaller duty cycle, the inductor losses in L1 are dominated by alternating current (AC) losses. Therefore, given a fixed amount of package real estate split between the two inductors L1 and L2, it may be more beneficial to design L1 with a larger inductance at the expense of a larger DC resistance to reduce ripple current and AC losses, and vice versa for L2. This assumes that the VR provides step-down conversion.

[0052] Plot 410 shows the results of introducing an asymmetry between the two inductors. In this example, the inductors are formed coaxially by package vias and the total via count is fixed. In the first scenario (plot 400), the two inductors have equal inductance and equal DC resistance. The second scenario (plot 410) uses a larger inductance and higher DC resistance for the top inductor and a smaller inductance and lower DC resistance for the bottom inductor that carries most of the DC current. The results show that the second scenario achieves better peak efficiency by reducing inductor conduction losses. The same idea can be applied to a similar situation of implementing a Kappa converter with integrated planar inductors where the total inductor area is limited.

[0053] In one approach, when the voltage converter provides a step-down conversion of a voltage at an input node at a ratio of at least 2:1 (e.g., Vin / Vout1), the inductance of the first inductor can be configured to be greater than the inductance of the second inductor. For example, the inductance of the first inductor can be greater than the inductance of the second inductor at a ratio of at least 2:1 or at least 3:1.

[0054] Figure 5A Depicted according to various embodiments, as Figure 2A Another example implementation of VR 225 is a circuit diagram of VR 500, which includes Figure 3The capa VR 300 and a set of current multipliers 510 thereafter. The current multipliers divide the voltage while multiplying the current. The set of current multipliers includes example current multipliers 511, 512, ..., 513. The outputs of the different current multipliers are provided to an output node 520, which in turn is coupled to a load 131 via a node 530. The load is also coupled to a ground node 532 via a node 531. A second load capacitor Cload2 is coupled between nodes 520 and 532, wherein a first side 533 of Cload2 is coupled to node 520, and a second side 534 of Cload2 is coupled to node 532. Nodes / conductive points 530 and 531 are between the first and second dies.

[0055] Generally speaking, the set of current multipliers is cascaded with and downstream of the VR and its active circuitry. Downstream current multipliers are based on a strategy to mitigate inductor losses caused by high conversion ratios and high output currents. This scheme adds a current multiplier stage at the output of the Kappa converter. Figure 5B In one scheme depicted in , a cascaded 2:1 switched-capacitor (SC) output stage is added to the Kappa converter. Both stages perform step-down conversion. For example, the Kappa converter of the first stage can convert the input voltage Vin (e.g., 3.6V) to an intermediate voltage Vout1 (e.g., 1.4V) with a duty cycle of 44% and an efficiency of 88%. The current multiplier can step down the intermediate voltage to a final lower voltage Vout2, for example, 0.7V. This keeps the DC current on the two inductors balanced and reduces losses. In addition, because the SC stage provides 2x current multiplication and step-down conversion, the current provided by the Kappa converter is halved, further reducing inductor losses.

[0056] The current multiplier may operate at a higher clock frequency than the VR (eg, Kappa VR 300) and its active circuits. In one approach, a first control loop is used to regulate Vout1 and a second control loop is used to regulate Vout2.

[0057] Figure 5B Depicted is a switched capacitor buck converter according to various embodiments. Figure 5A1 is a circuit diagram of an example implementation of a current multiplier of . The current multiplier 511 includes switches (e.g., nMOSFETs) 521 and 522 coupled in series between the input node 321 of Vout1 and the output node 520 of Vout2. In addition, switches 523 and 524 are coupled in series between the input node 321 and the output node 520. The flying capacitor Cfly2 is coupled on a first side 542 to a node 540 between the switches 521 and 522, and on a second side 543 to a node 541 between the switches 523 and 524.

[0058] As previously mentioned, in this example, each current multiplier can provide a 2:1 voltage reduction. The switch of each current multiplier can be controlled so that only one current multiplier is active at a time. The current multipliers are thus phase-interleaved. When a current multiplier is selected by the control signal (see Figure 5C ), which outputs current to the output node 520. As the current multipliers are selected successively, a relatively stable current is output. Therefore, the load capacitor Cload1 can be made relatively small or even removed while the circuit maintains a stable output.

[0059] Figure 5C Depicted are according to various embodiments, Figure 5A 1 and 2. Example control signals for a set of current multipliers 510 of FIG. 5. Control signals 550, 551, 552, and 553 are used for the first to fourth current multipliers, respectively. When the signal is high, the switch of each current multiplier is turned on, so that charge is transferred from the input node 321 to the flying capacitor Cfly2, and from Cfly2 to the output node 520. This example includes four current multipliers as a simplification, but in practice many more current multipliers can be provided to ensure a stable output at the node 520.

[0060] Figure 6 Depicted are according to various embodiments, Figure 3 and Figure 5A Example graphs of efficiency versus load current for various implementations of Kappa VR. Graph 601 shows a single-stage Kappa VR (e.g., Figure 5A The Kappa VR 300) converts 3.6V to 0.7V without the following set of current multipliers 510. In this case, the peak efficiency is relatively low because the step-down conversion ratio is relatively high. Graph 602 shows Figure 5A602 is based on multiplying the values ​​of graph 603, which is the efficiency of the kappa VR alone in the two-stage design, and graph 604, which is the efficiency of the group of current multipliers alone in the two-stage design. When the step-down conversion ratio of the kappa VR is reduced, it is more efficient.

[0061] The plots show the efficiency of each stage, as well as the combined efficiency compared to a single-stage design. The efficiency of the kappa converter stage itself is improved because the current distribution is less skewed and the total current through the inductor is lower. The 2x current multiplier stage can often be integrated on chip with high efficiency, significantly improving the efficiency of the cascade design.

[0062] Since the switched capacitor converter at the output is fully integrated on the base die (first die) or the top die (second die), it can be divided into multiple phases with phase interleaving and switched at a much higher effective frequency, providing a nearly continuous current drawn from the first stage. This can help reduce or eliminate the decoupling capacitors Cload1 between the converter stages and at the output (Cload2). Compared to a single-stage Kappa converter, a major portion of the output capacitor budget can now be allocated to the flying capacitor (Cfly2) of the 2:1 switched capacitor divider.

[0063] Figure 7 Depicted according to various embodiments, as Figure 2A 2 is a circuit diagram of another example implementation of VR 700 that includes VR 750 as a switched inductor capacitor converter cascaded with a set of 3:1 switched capacitor current multipliers 730.

[0064] These solutions can be further extended to other input inductor first topologies. This example describes a switched-inductor-capacitor (SIC) converter (e.g., VR 750) cascaded with a 3:1 switched capacitor converter (e.g., a set of 3:1 switched capacitor current multipliers 730). The SIC converter includes an input inductor L, a first flying capacitor Cf1, and three switches SW1-SW3. The first load capacitor Cload1 acts as a decoupling capacitor between each stage. In one embodiment, all components except the inductor L are integrated on the chip. The SIC converter operates by controlling the PWM signal through a duty cycle, which is divided into two phases. In the charging phase, SW1 and SW3 are turned on to charge the inductor and Cf1. In the discharging phase, SW2 is turned on by an out-of-phase PWM signal to discharge Cf1 to the output. The conversion ratio of the SIC stage is 1 / (2-D), where D is the duty cycle of the PWM signal in the charging phase.

[0065] The 3:1SC converter can be operated with a separate clock signal, which is typically at a higher frequency than the clock signal of VR 750. The overall conversion ratio is 1 / 3 (2-D), which enables this converter to have conversion ratios between 1 / 3 and 1 / 6 and is suitable for the 3.6V-0.7V conversion application outlined in the previous example. The frequency of each stage can be optimized individually to reduce switching losses and improve efficiency. The on-chip integrated 3:1SC converter can also be divided into multiple phase-interleaved units, which can provide nearly continuous output current to the SIC and minimize the need for inter-stage decoupling capacitors Cload1.

[0066] In more detail, an input voltage Vin at an input node 701 is coupled to an input end 703 of an inductor L1 on a conductive path 702, and an output end 704 of the inductor is coupled to a node 706 between a package substrate layer and a first die on a conductive path 705. Node 706 is in turn coupled to a first side 710 of a first flying capacitor Cf1 and a switch SW1, for example, coupled to the drain side of an nMOS switch. A second side 711 of Cf1 is coupled to a switch SW3, for example, coupled to the drain side of the nMOS switch SW3, and to a switch SW2, for example, coupled to the drain side of the nMOS switch SW2. SW3 is used to control whether the second side of Cf1 is grounded. The source sides of SW1 and SW2 are coupled to an output node 712 at a voltage Vout1. A first load capacitor Cload1 is coupled between node 712 and a ground node 715, wherein a first side 713 of Cload1 is coupled to node 712, and a second side 714 of Cload1 is coupled to node 715.

[0067] Nodes 712 and 715 are coupled to a set of current multipliers 730, which include current multipliers 731, 732, ..., 733. Each current multiplier includes two flying capacitors Cf2 and Cf3, and switches for coupling charge to and from the flying capacitors. A first side 721 of Cf2 is coupled to a node 716 between switches SW4 and SW7. A second side 722 of Cf2 is coupled to a node 717 and SW5, which is between nodes 715 and 717. A first side 724 of Cf3 is coupled to a node 718 between switches SW10 and SW9. A second side 723 of Cf3 may be coupled to node 717 via SW6. An output node 720 is coupled to SW7 and SW9 of each current multiplier to receive an output voltage Vout2. Vout2 is provided to a load 131 via a node 740. The load is coupled to a ground node 743 via a path 744. In operation, SW4, SW6 and SW9 are turned on in half of the cycle, and SW5, SW7, SW8 and SW10 are turned on in the other half of the cycle. As previously mentioned, the switching frequency can be higher for the current doubler compared to VR 750.

[0068] Nodes / conductive points 740 and 741 are between the first and second dies.

[0069] In one approach, a set of current multipliers is cascaded with and downstream of the active circuit of the VR, wherein the set of current multipliers is in one or more dies and comprises a plurality of switched capacitor buck converters interleaved in phase. In addition, the set of current multipliers operates at a clock frequency higher than the clock frequency of the active circuit.

[0070] Fig. 8A Depicted according to various embodiments, as Figure 2A A circuit diagram of another example implementation of VR 225 is a VR 800, the VR 800 comprising Figure 3 The Kappa VR 300 is followed by a continuously scalable conversion ratio (CSCR) capacitive regulator 810. The CSCR capacitive voltage regulator 810 is coupled to the output node 321 at Vout1 and to the ground node 323, for example, at 0V.

[0071] Figure 8B Depicted are various embodiments Fig. 8AFIG. 8 is a circuit diagram of an example implementation of a CSCR capacitive regulator 810. The CSCR capacitive regulator uses multi-phase soft charging of capacitor C to provide a continuously scalable conversion ratio with high efficiency. The basic idea is to maximize the voltage variation of the flying capacitor (s) by swinging them back and forth between about Vin and 0V, regardless of the output voltage. Opening up the voltage of the capacitors, so that they do not have a fixed bias voltage, dramatically increases the number of topologies, especially when many phases are also used. To minimize design complexity, a single capacitor topology is depicted. For simplicity, it is assumed that the capacitor polarity remains the same throughout the cycle.

[0072] The regulator includes several (e.g., 65) phase-shifted cores 820, 821, ..., 822. Each core includes transistor groups 830, .., 831 and 832 associated with top-side nodes T1 to T16, and transistor groups 833, .., 834 and 835 associated with bottom-side nodes B1 to B16. There are M soft-charge phases on the top side (nodes T1 to TM) and N soft-charge phases on the bottom side, corresponding to nodes B1-BN. The example topology is implemented with N, M = 32. In order to realize direct charge transfer between capacitors through the soft-charge nodes, the converter is divided into 1+N+M = 65 phase-shifted cores. Due to the phase shifting, only 16 top and bottom nodes need to be implemented.

[0073] All switches are implemented using two stacked thin oxide transistors to achieve a wide Vout range, with Vin up to, for example, 2V. In addition, to maximize its conductance over the entire range, four 3-pF bootstrap capacitors 840, 841, 842, and 843 are used for each core, each of which generates voltage rails T Pp / T Pm and B Pp / B Pm relative to the top / bottom plates, which are charged each time the plate is connected to Vout using external Voutp and Voutm rails. These external voltage rails are at fixed voltages of 1V and -0.85V relative to Vout. All transistors connected to the soft charge nodes need to block positive and negative voltages between their drain-source and are therefore driven by tri-state buffers. The external frequency reference Fclk is divided into 130 phases using a non-overlapping clock generator 813, which are then distributed to the local decoders of each core, such as decoder 850 of core 820. Fclk is input to AND gate 812 and variable delay circuit 811, where the delay is set by Vdelay. The output of the decoder is provided to the gate driver and level shifter circuit 851.

[0074] Vss, which connects the transistors with the clock generator and other logic, is supplied by Vcontrol = 1.1 V. Vcontrol, Voutp and Voutm are provided externally for flexibility and measurement purposes, but their peak current consumption allows their generation with a classic charge pump and limited on-chip overhead.

[0075] Thus, instead of a current multiplier at the output of the input inductor converter, a linear or capacitive regulator, such as a continuously scalable conversion ratio (CSCR) capacitive regulator or a digital or analog linear regulator, can be added at the output. In this implementation, the upstream input inductor converter can act as an unregulated fixed ratio converter, and the task of voltage regulation is pushed to the downstream stage. Having a fully on-chip integrable capacitive or linear downstream stage also provides the following advantages: combining multiple small rails to be fed by a single upstream stage, each rail has its own dedicated downstream regulator, which can be all capacitive, linear, or a combination of both.

[0076] In one approach, a CSCR capacitive regulator is cascaded with and downstream of an active circuit of a voltage converter, wherein the CSCR capacitive regulator is in at least one of a first die or a second die stacked on the first die.

[0077] Fig. 9 950 for implementing the techniques (e.g., operations, processes, methods, and approaches) described herein. Voltage regulator 900 can provide voltage Vout to one or more components of computing system 950. Voltage regulator 900 can be external to computing system 950, or can be part of computing system 950. VR can be controlled by control signals provided by processor circuit 952. VR can include any VR discussed herein, including Figure 2A-Figure 3 , Figure 5A-Figure 5C and Figure 7-8B Those in .

[0078] The memory circuit 954 may store instructions, and the processor circuit 952 may execute the instructions to perform the functions described herein.

[0079] The computing system 950 may include any combination of the hardware or logic components mentioned herein. These components may be implemented as ICs, parts thereof, discrete electronic devices, or other modules, instruction sets, programmable logic or algorithms, hardware, hardware accelerators, software, firmware, or combinations thereof adapted in the computing system 950, or as components otherwise contained within a housing of a larger system. For one embodiment, at least one processor 952 may be packaged with computing logic 982 and configured to implement aspects of the various example embodiments described herein to form a system-in-package (SiP) or system-on-chip (SoC).

[0080] The system 950 includes a processor circuit in the form of one or more processors 952. The processor circuit 952 includes circuits such as (but not limited to): one or more processor cores and one or more of the following: cache memory, low drop-out (LDO) voltage regulator, interrupt controller, serial interface such as SPI, I2C or general programmable serial interface circuit, real time clock (RTC), timer-counter including interval and watchdog timer, general I / O, memory card controller such as secure digital / multi-media card (SD / MMC) or something similar, interface, mobile industry processor interface (MIPI) interface and joint test access group (JTAG) test access port. In some implementations, the processor circuit 952 may include one or more hardware accelerators (e.g., the same or similar to the acceleration circuit 964), which may be microprocessors, programmable processing devices (e.g., FPGA, ASIC, etc.), etc. The one or more accelerators may include, for example, computer vision and / or deep learning accelerators. In some implementations, processor circuit 952 may include on-chip memory circuitry, which may include any suitable volatile and / or nonvolatile memory, such as DRAM, SRAM, EPROM, EEPROM, flash memory, solid-state memory, and / or any other type of memory device technology, such as those discussed herein.

[0081] The processor circuit 952 may include, for example, one or more processor cores (CPUs), application processors, GPUs, RISC processors, Acorn RISC Machine (ARM) processors, CISC processors, one or more DSPs, one or more FPGAs, one or more PLDs, one or more ASICs, one or more baseband processors, one or more radio-frequency integrated circuits (RFICs), one or more microprocessors or controllers, multi-core processors, multi-threaded processors, ultra-low voltage processors, embedded processors, or any other known processing elements, or any suitable combination of these. The processor (or core) 952 may be coupled to or may include a memory / storage device, and may be configured to execute instructions stored in the memory / storage device to enable various applications or operating systems to run on the platform 950. The processor (or core) 952 is configured to operate application software to provide specific services to users of the platform 950. In some embodiments, the (one or more) processors 952 may be (or may be configured to) be (one or more) dedicated processors / controllers configured to operate according to various embodiments herein.

[0082] As an example, the processor(s) 952 may include Core based architecture TM Processors such as i3, i5, i7, i9 based processors; Microcontroller-based processors such as Quark TM 、Atom TM Or other MCU-based processors; (one or more) Processor(s), processor, or available from Santa Clara, California However, any number of other processors may be used, such as one or more of the following: Advanced Micro Devices (AMD) Architecture, such as (one or more) or Processor, Accelerated Processing Unit (APU), MxGPU, (one or more) processor, etc.; from The company's (one or more) A5-A12 and / or S1-S4 processors, from Snapdragon(s) from technology companies TM or Centriq TM Processor, Texas Instruments, (One or more) Open Multimedia Applications Platform (OMAP) TM Processors; MIPS-based designs from MIPS Technologies Inc., such as the MIPS Warrior M-class, Warrior I-class, and Warrior P-class processors; ARM-based designs licensed from ARM Holdings plc, such as the ARM Cortex-A, Cortex-R, and Cortex-M series processors; and processors manufactured by Cavium TM Provided by the company In some implementations, the processor(s) 952 may be part of a system on a chip (SoC), a system-in-Package (SiP), a multi-chip package (MCP), etc., where the processor(s) 952 and other components are formed as a single integrated circuit, or a single package, such as from Edison TM or Galileo TM SoC Board. Other examples of processor(s) 952 are mentioned elsewhere in this disclosure.

[0083] The system 950 may include or be coupled to an acceleration circuit 964, which may be implemented by one or more AI / ML accelerators, neural compute sticks, neuromorphic hardware, FPGAs, arrangements of GPUs, one or more SoCs (including programmable SoCs), one or more CPUs, one or more digital signal processors, dedicated ASICs (including programmable ASICs), PLDs (such as complex PLDs (CPLDs) or high complexity PLDs (HCPLDs)), and / or other forms of specialized processors or circuits designed to implement one or more specialized tasks. These tasks may include AI / ML processing (e.g., including training, inference, and classification operations), visual data processing, network data processing, object detection, rule analysis, and the like. In an FPGA-based implementation, the acceleration circuit 964 may include logic blocks or logic architectures and other interconnected resources that may be programmed (configured) to perform various functions, such as the processes, methods, functions, and the like of the various embodiments discussed herein. In such an implementation, the acceleration circuit 964 may also include a memory unit (e.g., EPROM, EEPROM, flash memory, static memory (e.g., SRAM, antifuse, etc.) for storing logic blocks, logic architectures, data, etc. in a LUT, etc.

[0084] In some implementations, the processor circuit 952 and / or the acceleration circuit 964 may include hardware elements specifically customized for machine learning and / or artificial intelligence (AI) functions. In these implementations, the processor circuit 952 and / or the acceleration circuit 964 may be or may include an AI engine chip that, once loaded with appropriate weighting and training code, can run many different kinds of AI instruction sets. Additionally or alternatively, the processor circuit 952 and / or the acceleration circuit 964 may be or may include (one or more) AI accelerators, which may be one or more of the above-mentioned hardware accelerators designed for hardware acceleration of AI applications. As an example, these processors or accelerators may be a cluster of the following: artificial intelligence (AI) GPU, The company developed the tensor processing unit (TPU), The Real AI Processor (RAP TM ), Nervana provided by the company TM Neural Network Processor (NNP), MovidiusTM Myriad TM XVision Processing Unit (VPU), based on PX TM GPU, General Provided NM500 chip, Hardware provided by the company 3. Provided by Epiphany TM In some embodiments, the processor circuit 952 and / or the acceleration circuit 964 and / or the hardware accelerator circuit can be implemented as (one or more) AI acceleration coprocessors, such as Hexagon 685DSP, Imagination Technologies PowerVR 2NX Neural Net Accelerator (NNA) provided, The Neural Engine core inside the A11 or A12 Bionic SoC, The neural processing unit (NPU) within the HiSilicon Kirin 970 provided, etc. In some hardware-based implementations, the individual subsystems of the system 950 can be operated by various AI acceleration coprocessors, AI GPUs, TPUs or hardware accelerators (e.g., FPGAs, ASICs, DSPs, SoCs, etc.), etc., which are configured with appropriate logic blocks, (one or more) bitstreams, etc. to perform their respective functions.

[0085] The system 950 also includes a system memory 954. Any number of memory devices may be used to provide a fixed amount of system memory. As an example, the memory 954 may be or may include a volatile memory such as a random access memory (RAM), a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), Dynamic Random Access Memory (DRAM) Dynamic Random Access Memory, ), and / or any other desired type of volatile memory device. Additionally or alternatively, the memory 954 may be or may include a non-volatile memory, such as a read-only memory (ROM), an erasable programmable ROM (EPROM), an electrically erasable programmable (EEPROM), a flash memory, a non-volatile RAM, a ferroelectric RAM, a phase-change memory (PCM), a flash memory, and / or any other desired type of non-volatile memory device. Access to the memory 954 is controlled by a memory controller. Individual memory devices may have any number of different package types, such as a single die package (SDP), a dual die package (DDP), or a quad die package (Q17P). Any number of other memory implementations may be used, such as different types of dual inline memory modules (DIMMs), including but not limited to microDIMMs or MiniDIMMs.

[0086] The storage circuit 958 provides persistent storage of information such as data, applications, operating systems, etc. In one example, the storage device 958 can be implemented via a solid-state disk drive (SSDD) and / or a high-speed electrically erasable memory (commonly referred to as "flash memory"). Other devices that can be used for the storage device 958 include flash memory cards, such as SD cards, microSD cards, XD picture cards, etc., and USB flash drives. In one example, the memory device may be or may include a memory device using chalcogenide glass, a multi-threshold level NAND flash memory, a NOR flash memory, a single-level or multi-level phase change memory (PCM), a resistive memory, a nanowire memory, a ferroelectric transistor random access memory (FeTRAM), an antiferroelectric memory, a magnetoresistive random access memory (MRAM) memory including memristor technology, a phase change RAM (PRAM), a resistive memory including a metal oxide substrate, an oxygen vacancy substrate and a conductive bridge random access memory (CB-RAM), or a spin transfer torque (STT)-MRAM, a device based on a spin electronic magnetic junction memory, a device based on a magnetic tunneling junction (MTJ), a device based on a domain wall (DW) and a spin orbit transfer (SOT), a semiconductor thyristor-based memory device, a hard disk drive (HDD) drive, HDD), micro HDD, or a combination of these, and / or any other memory. Memory circuit 954 and / or storage circuit 958 may also include and Three-dimensional (3D) cross-point (XPOINT) memory.

[0087] The memory circuit 954 and / or the storage circuit 958 are configured to store computing logic 983 in the form of software, firmware, microcode or hardware level instructions to implement the techniques described herein. The computing logic 983 may be employed to store working copies and / or permanent copies of programming instructions, or data used to create programming instructions, for various components of the operating system 950 (e.g., drivers, libraries, application programming interfaces (APIs), etc.), the operating system of the system 950, one or more applications, and / or for implementing the embodiments discussed herein. The computing logic 983 may be stored or loaded into the memory circuit 954 as instructions 982 or data used to create instructions 982, and then accessed by the processor circuit 952 for execution to implement the functions described herein. The processor circuit 952 and / or the acceleration circuit 964 access the memory circuit 954 and / or the storage circuit 958 via the interconnect (IX) 956. The instructions 982 direct the processor circuit 952 to perform a specific sequence of actions or processes, for example, as described with reference to the (one or more) flow charts and (one or more) block diagrams of the operations and functions previously depicted. The various elements may be implemented by assembly instructions or a high-level language supported by processor circuit 952, which may be compiled into instructions 988, or data used to create instructions 988, for execution by processor circuit 952. A permanent copy of the programming instructions may be placed into a persistent storage device of storage circuit 958 at the factory or in the field, for example, via a distribution medium (not shown), via a communication interface (e.g., from a distribution server (not shown)), over the air (OTA), or any combination of these.

[0088] IX 956 couples processor 952 to communication circuitry 966 for communication with other devices, such as a remote server (not shown), etc. Communication circuitry 966 is a hardware element, or a collection of hardware elements, for communicating over one or more networks 963 and / or communicating with other devices. In one example, communication circuitry 966 is or includes transceiver circuitry configured to implement wireless communications using any number of frequencies and protocols, such as Institute of Electrical and Electronics Engineers (IEEE) 802.11 (and / or its variants), IEEE 802.23.4, and / or Low energy ( low energy, BLE), LoRaWAN TM(Long Range Wide Area Network), cellular protocols such as 3GPP LTE and / or Fifth Generation (5G) / New Radio (NR), etc. Additionally or alternatively, the communication circuit 966 is or includes one or more network interface controllers (NICs) to enable wired communications using, for example, an Ethernet connection, a Controller Area Network (CAN), a Local Interconnect Network (LIN), DeviceNet, ControlNet, Data Highway+, or PROFINET, etc.

[0089] IX 956 also couples processor 952 to interface circuitry 970 for connecting system 950 to one or more external devices 972. External devices 972 may include, for example, sensors, actuators, positioning circuits (e.g., global navigation satellite system (GNSS) / Global Positioning System (GPS) circuits), client devices, servers, network appliances (e.g., switches, hubs, routers, etc.), integrated photonics devices (e.g., optical neural network (ONN) integrated circuits (ICs), etc.), and / or other similar devices.

[0090] In some optional examples, various input / output (I / O) devices may be present in or connected to the system 950, which are referred to as input circuits 986 and output circuits 984. Input circuits 986 and output circuits 984 include one or more user interfaces designed to enable a user to interact with the platform 950, and / or peripheral component interfaces designed to enable peripheral components to interact with the platform 950. Input circuits 986 may include any physical or virtual device for accepting input, including one or more physical or virtual buttons (e.g., reset buttons), physical keyboards, keypads, mice, touch pads, touch screens, microphones, scanners, headsets, and the like. Output circuits 984 may be included to show information or otherwise convey information, such as sensor readings, (one or more) actuator positions, or other similar information. Data and / or graphics may be displayed on one or more user interface components of output circuits 984. Output circuitry 984 may include any number and / or combination of audio or visual displays, including, in particular, one or more simple visual outputs / indicators (e.g., binary status indicators (e.g., light emitting diodes (LEDs)) and multi-character visual outputs, or more complex outputs such as a display device or touch screen (e.g., a liquid crystal display (LCD)). Display, LCD), LED display, quantum dot display, projector, etc.), where output of characters, graphics, multimedia objects, and the like is generated or produced from the operation of platform 950. Output circuitry 984 may also include speakers and / or other audio emitting devices, (one or more) printers, and the like. Additionally or alternatively, (one or more) sensors may be used as input circuitry 984 (e.g., image capture devices, motion capture devices, and the like) and one or more actuators may be used as output device circuitry 984 (e.g., actuators to provide tactile feedback or the like). Peripheral component interfaces may include, but are not limited to, non-volatile memory ports, USB ports, audio jacks, power supply interfaces, and the like. In some embodiments, in the context of the present system, display or console hardware may be used to provide output and receive input to an edge computing system; manage components or services of an edge computing system; identify the state of an edge computing component or service; or perform any other number of management or administrative functions or service use cases.

[0091] The components of system 950 may communicate via IX 956. IX 956 may include any number of technologies including ISA, extended ISA, I2C, SPI, point-to-point interface, power management bus (PMBus), PCI, PCIe, PCIx, UPI, Accelerator Link, CXL, CAPI, OpenCAPI, QPI, UPI, OPA IX, RapidIO TM System IX, CCIX, Gen-Z Consortium IX, HyperTransport Interconnect, NVLink, Time-Trigger Protocol (TTP) systems, FlexRay systems, PROFIBUS, and / or any number of other IX technologies provided. IX 956 can be a proprietary bus used, for example, in a SoC-based system.

[0092] The number, capabilities, and / or capacity of the elements of system 950 may vary, depending on whether computing system 950 is used as a fixed computing device (e.g., a server computer in a data center, a workstation, a desktop computer, etc.) or a mobile computing device (e.g., a smart phone, a tablet computing device, a laptop computer, a gaming console, an IoT device, etc.). In various implementations, computing device system 950 may include one or more components of a data center, a desktop computer, a workstation, a laptop computer, a smart phone, a tablet device, a digital camera, a smart home appliance, a smart home hub, a network appliance, and / or any other device / system that processes data.

[0093] The techniques described herein may be performed in part or in whole by software or other instructions provided in a machine-readable storage medium (e.g., memory). The software is stored as processor-executable instructions (e.g., instructions that implement any other process discussed herein). The instructions associated with the flow charts (and / or various embodiments) and executed to implement embodiments of the disclosed subject matter may be implemented as part of an operating system or a specific application, component, program, object, module, routine, or other sequence of instructions or organization of sequences of instructions.

[0094] The storage medium may be a tangible, non-transitory machine-readable medium, such as read only memory (ROM), random access memory (RAM), flash memory devices, floppy disks and other removable disks, magnetic storage media, optical storage media (e.g., Compact Disk Read-Only Memory (CD ROMS), Digital Versatile Disk (DVD)), and the like.

[0095] The storage medium may be included in, for example, a communication device, a computing device, a network device, a personal digital assistant, a manufacturing tool, a mobile communication device, a cellular phone, a notebook computer, a tablet device, a game console, a set-top box, an embedded system, a TV (television), or a personal desktop computer.

[0096] Some non-limiting examples of various embodiments are given below.

[0097] Example 1 includes a device comprising: a packaging substrate layer; a first tube core stacked on the packaging substrate layer; and a voltage converter, which includes a first inductor, an input node and an input path in the packaging substrate layer, and an active circuit in the first tube core, wherein the input path couples the input node to the input end of the first inductor without entering the first tube core, and the active circuit is coupled to the output end of the first inductor.

[0098] Example 2 includes the apparatus of Example 1, wherein the load of the voltage converter is in at least one of the first die or a second die stacked on the first die.

[0099] Example 3 includes the apparatus of Example 1 or 2, wherein the load of the voltage converter is in a second die stacked on the first die, the first die includes a gallium nitride substrate, and the second die includes a silicon substrate.

[0100] Example 4 includes the apparatus of any of Examples 1-3. Also included is a set of current multipliers in cascade with and downstream of the active circuit of the voltage converter, wherein the set of current multipliers is in at least one of the first die or a second die stacked on the first die.

[0101] Example 5 includes the apparatus of Example 4, wherein the set of current multipliers comprises a plurality of switched capacitor buck converters interleaved in phase.

[0102] Example 6 includes the apparatus of any of Examples 1-5. Also included is a continuously scalable conversion ratio (CSCR) capacitive regulator cascaded with and downstream of the active circuit of the voltage converter, wherein the CSCR capacitive regulator is in at least one of the first die or a second die stacked on the first die.

[0103] Example 7 includes an apparatus as described in any one of Examples 1-6, wherein: the voltage converter includes a second inductor, a ground node, and a ground path in the package substrate layer; the ground path couples the ground node to an output of the second inductor without entering the first die; and the active circuit is coupled to an input of the second inductor.

[0104] Example 8 includes the apparatus of Example 7, wherein the voltage converter provides step-down conversion of the voltage at the input node at a ratio of at least 2:1, and the inductance of the first inductor is greater than the inductance of the second inductor.

[0105] Example 9 includes the apparatus of Example 8, wherein an inductance of the first inductor is greater than an inductance of the second inductor by a ratio of at least 2:1.

[0106] Example 10 includes the apparatus of any of Examples 7-9, wherein the active circuit comprises: a flying capacitor having a first side coupled to an output terminal of the first inductor and a second side coupled to an input terminal of the second inductor; a first switch to couple the first side of the flying capacitor to an output node of the voltage converter; and a second switch to couple the second side of the flying capacitor to a ground node.

[0107] Example 11 includes the apparatus of Example 10, wherein the flying capacitor comprises an embedded package capacitor or a deep trench capacitor.

[0108] Example 12 includes an apparatus as described in any one of Examples 1 to 11. It also includes at least one of an integrated circuit, a system on a chip, a system-level package, or a computing device in which the package substrate layer, the first die, and the voltage converter are provided, wherein the computing device includes a circuit of at least one of the following: a processor circuit, a memory circuit, a storage circuit, an acceleration circuit, a communication circuit, an input circuit, an output circuit, an interface circuit, or an external device.

[0109] Example 13 includes a device comprising: a packaging substrate layer; a first tube core stacked on the packaging substrate layer; and an inductor-first voltage converter, wherein the inductor-first voltage converter includes a first inductor in the packaging substrate layer and an active circuit in the first tube core, the first inductor is coupled to an input node of the packaging substrate layer, and the active circuit is coupled to the first inductor.

[0110] Example 14 includes the apparatus of Example 13, wherein the inductor-first voltage converter is a kappa voltage converter.

[0111] Example 15 includes an apparatus as described in Example 14, wherein: the inductor-first voltage converter further includes a second inductor in the package substrate layer; the second inductor is coupled to a ground node of the package substrate layer; and the active circuit is coupled to the second inductor.

[0112] Example 16 includes the apparatus of any of Examples 13-15, wherein the inductor-first voltage converter is a switched capacitor voltage converter.

[0113] Example 17 includes an apparatus as described in Example 16, wherein the active circuit includes: a flying capacitor having a first side coupled to the first inductor; a first switch to couple the first side of the flying capacitor to an output node of the inductor-first voltage converter; a second switch to couple the second side of the flying capacitor to the output node; and a third switch to couple the second side of the flying capacitor to a ground node.

[0114] Example 18 includes a device comprising: a first inductor in a stacked packaging substrate layer; and an active circuit in one or more tube cores of the stack, wherein: the one or more tube cores are above the packaging substrate layer in the stack; the input end of the first inductor is coupled to a voltage input node of the packaging substrate layer through a switch-free path in the packaging substrate layer; and the output end of the first inductor is coupled to the active circuit through a switch-free path in the packaging substrate layer.

[0115] Example 19 includes the apparatus of Example 18, further comprising a set of current multipliers in cascade with and downstream of the active circuit, wherein the set of current multipliers are in the one or more dies and include a plurality of switched capacitor buck converters with phases interleaved.

[0116] Example 20 includes the apparatus of Example 18 or 19, further comprising a set of current multipliers in cascade with and downstream of the active circuit, wherein the set of current multipliers is configured to operate at a clock frequency greater than a clock frequency of the active circuit.

[0117] Example 21 includes a method comprising: receiving an input voltage at an input end of an inductor of a voltage regulator in a package substrate layer; outputting an output voltage at an output end of the inductor in the package substrate layer; and coupling the output voltage to an active circuit of the voltage regulator in a first die stacked on the package substrate layer.

[0118] Example 22 includes the method of Example 21, further comprising down-converting the output voltage at the first die to provide an output voltage to a load.

[0119] Example 23 includes a non-transitory machine-readable storage device including machine-readable instructions that, when executed, cause a processor or other circuit or computing device to implement the method of Example 21 or 22.

[0120] Example 24 includes a computer program comprising instructions, which, when executed by a computer, cause the computer to perform the method as described in Example 21 or 22.

[0121] Various operations may be described in turn as a plurality of discrete actions or operations in a manner that is most helpful for understanding the claimed subject matter. However, the order of description should not be interpreted as meaning that these operations must be dependent on the order. Specifically, these operations may not be performed in the order presented. The operations described may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the operations described may be omitted in additional embodiments.

[0122] The terms "substantially," "close," "roughly," "approximately," and "about" generally refer to within + / -10% of a target value. Unless otherwise indicated, the use of ordinal adjectives "first," "second," and "third," etc., to describe common objects simply indicates that different instances of similar objects are referenced, and is not intended to imply that the objects so described must be in a given sequence in time, space, ranking, or in any other manner.

[0123] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0124] The description may use the phrases "in one embodiment" or "in an embodiment", each of which may refer to one or more identical or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in embodiments of the present disclosure are synonymous.

[0125] As used herein, the term "circuitry" may refer to, be a part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), a combinational logic circuit, and / or other suitable hardware components that provide the described functionality. As used herein, a "computer-implemented method" may refer to any method performed by one or more processors, a computer system having one or more processors, a mobile device such as a smart phone (which may include one or more processors), a tablet device, a laptop computer, a set-top box, a game console, and the like.

[0126] The terms "coupled," "communicatively coupled," and their derivatives are used herein. The term "coupled" may mean that two or more elements are in direct physical or electrical contact with each other, may mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and / or may mean that one or more other elements are coupled or connected between the elements allegedly coupled to each other. The term "directly coupled" may mean that two or more elements are in direct contact with each other. The term "communicatively coupled" may mean that two or more elements are in contact with each other by means of communication, including by wires or other interconnections, by wireless communication channels or links, and the like.

[0127] References in the specification to "an embodiment", "one embodiment", "some embodiments" or "other embodiments" mean that the particular features, structures or characteristics described in connection with these embodiments are included in at least some embodiments, but not necessarily in all embodiments. The various appearances of "an embodiment", "one embodiment" or "some embodiments" do not necessarily all refer to the same embodiment. If the specification states that a component, feature, structure or characteristic "may", "might" or "could" be included, that particular component, feature, structure or characteristic is not required to be included. If the specification or claims refer to "an" element, it does not mean that there is only one of that element. If the specification or claims refer to "an additional" element, it does not exclude that there is more than one of that additional element.

[0128] In addition, in one or more embodiments, specific features, structures, functions or characteristics can be combined in any appropriate manner. For example, the first embodiment can be combined with the second embodiment at any place where the specific features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

[0129] Although the present disclosure has been described in conjunction with its specific embodiments, many alternatives, modifications and variations of such embodiments will be apparent to those skilled in the art from the foregoing description. The embodiments of the present disclosure are intended to encompass all such alternatives, modifications and variations falling within the broad scope of the appended claims.

[0130] In addition, for simplicity of illustration and discussion, and in order not to obscure the present disclosure, known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the given figures. In addition, the arrangement may be shown in block diagram form to avoid obscuring the present disclosure, and also taking into account the fact that the specific details of the implementation of such block diagram arrangements are highly dependent on the platform in which the present disclosure is to be implemented (i.e., such specific details should be fully within the scope of those skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the present disclosure, it should be clear to those skilled in the art that the present disclosure may be implemented without these specific details, or with variations of these specific details. The specification should therefore be considered illustrative, not restrictive.

[0131] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. A device comprising: Encapsulation substrate layer; a first tube die stacked on the package substrate layer; as well as A voltage converter comprises a first inductor in the package substrate layer, an input node and an input path, and an active circuit in the first die, wherein the input path is used to couple the input node to the input end of the first inductor without entering the first die, and the active circuit is coupled to the output end of the first inductor.

2. The device according to claim 1, wherein: A load of the voltage converter is in at least one of the first die or a second die stacked on the first die.

3. The device according to claim 1 or 2, wherein: The load of the voltage converter is in a second die stacked on the first die, the first die includes a gallium nitride substrate, and the second die includes a silicon substrate.

4. The apparatus of claim 1 or 2, further comprising a set of current multipliers cascaded with and downstream of the active circuit of the voltage converter, wherein: The set of current multipliers is in at least one of the first die or a second die stacked on the first die.

5. The device according to claim 4, wherein: The set of current multipliers includes a plurality of switched capacitor buck converters interleaved in phase.

6. The apparatus of claim 1 or 2, further comprising a continuously scalable conversion ratio (CSCR) capacitive regulator cascaded with and downstream of the active circuit of the voltage converter, wherein: The CSCR capacitive regulator is in at least one of the first die or a second die stacked on the first die.

7. The device according to claim 1 or 2, wherein: The voltage converter includes a second inductor, a ground node, and a ground path in the package substrate layer; The ground path couples the ground node to an output of the second inductor without entering the first die; and The active circuit is coupled to an input terminal of the second inductor.

8. The device according to claim 7, wherein: The voltage converter is configured to provide step-down conversion of a voltage at the input node at a ratio of at least 2:1, and the inductance of the first inductor is greater than the inductance of the second inductor.

9. The device of claim 8, wherein: The inductance of the first inductor is greater than the inductance of the second inductor by a ratio of at least 2:

1.

10. The device according to claim 7, wherein: The active circuit comprises: a flying capacitor having a first side coupled to an output terminal of the first inductor and a second side coupled to an input terminal of the second inductor; a first switch for coupling a first side of the flying capacitor to an output node of the voltage converter; and A second switch is configured to couple a second side of the flying capacitor to a ground node.

11. The device of claim 10, wherein: The flying capacitor includes an embedded package capacitor or a deep trench capacitor.

12. The apparatus of claim 1 or 2, further comprising at least one of an integrated circuit, a system on chip, a system-level package, or a computing device, wherein the package substrate layer, the first die, and the voltage converter are disposed in the at least one of the integrated circuit, a system on chip, a system-level package, or a computing device, The computing device includes at least one of: a processor circuit, a memory circuit, a storage circuit, an acceleration circuit, a communication circuit, an input circuit, an output circuit, an interface circuit, or an external device.

13. An apparatus comprising: Encapsulation substrate layer; a first tube die stacked on the package substrate layer; as well as An inductor-first voltage converter, wherein the inductor-first voltage converter comprises a first inductor in the package substrate layer and an active circuit in the first die, the first inductor being coupled to an input node of the package substrate layer, and the active circuit being coupled to the first inductor.

14. The device of claim 13, wherein: The inductor-first voltage converter is a kappa voltage converter.

15. The apparatus of claim 14, wherein: The inductor-first voltage converter also includes a second inductor in the package substrate layer; The second inductor is coupled to a ground node of the package substrate layer; and The active circuit is coupled to the second inductor.

16. The device according to claim 13 or 14, wherein: The inductor-first voltage converter is a switched capacitor voltage converter.

17. The device of claim 16, wherein: The active circuit comprises: a flying capacitor having a first side coupled to the first inductor; a first switch for coupling a first side of the flying capacitor to an output node of the inductor-first voltage converter; a second switch for coupling a second side of the flying capacitor to the output node; and A third switch is configured to couple the second side of the flying capacitor to a ground node.

18. An apparatus comprising: a first inductor in the stacked package substrate layer; as well as Active circuitry in one or more dies of the stack, wherein: the one or more dies being above the package substrate layer in the stack; The input terminal of the first inductor is coupled to a voltage input node of the package substrate layer through a switch-free path in the package substrate layer; and An output of the first inductor is coupled to the active circuit through a switch-free path in the package substrate layer.

19. The apparatus of claim 18, further comprising a set of current multipliers in cascade with and downstream of the active circuit, wherein: The set of current multipliers is in the one or more dies and includes a plurality of switched capacitor buck converters interleaved in phase.

20. The apparatus of claim 18 or 19, further comprising a set of current multipliers in cascade connection with and downstream of the active circuit, wherein: The set of current multipliers is configured to operate at a clock frequency greater than a clock frequency of the active circuit.

21. A method comprising: receiving an input voltage at an input terminal of an inductor of a voltage regulator, the inductor being in a package substrate layer; outputting an output voltage at an output terminal of the inductor in the package substrate layer; The output voltage is coupled to active circuitry of the voltage regulator, the active circuitry being in a first die stacked on the package substrate layer.

22. The method of claim 21, further comprising down-converting the output voltage at the first die to provide an output voltage to a load.

23. A non-transitory machine-readable storage device comprising machine-readable instructions which, when executed, cause a processor or other circuit or computing device to implement the method of claim 21 or 22.

24. A computer program comprising instructions which, when executed by a computer, cause the computer to perform the method according to claim 21 or 22.

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