MOSFET (Metal Oxide Semiconductor Field Effect Transistor) unit, bridge circuit and preparation method

Abstract

The invention provides an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) unit, a bridge circuit and a preparation method, and the MOSFET unit comprises an MOSFET which comprises an active region, a Gate lead-out region and a Gate pad region; the RC circuit is used for eliminating the ringing signal; the RC circuit comprises a first end and a second end, the first end is connected with a grid electrode of the MOSFET, and the second end is connected with a source electrode of the MOSFET; and the RC circuit is arranged in a Gate pad region of the MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). According to the invention, the probability of simultaneous conduction of the upper and lower MOSFETs is reduced.

Description

Technical Field

[0001] The invention relates to the technical field of power MOSFET, and in particular to the technical field of bridge circuits. Background Art

[0002] Power MOSFET devices are widely used in bridge circuit topology due to their low on-resistance, fast switching speed, and increasingly miniaturized packaging. In recent years, with the rise of emerging industries such as new energy, robotics, and intelligent manufacturing, MOSFET power devices have been widely used in motor control systems composed of brushed or brushless DC motors (BLDC). Therefore, the reliability and stability of MOSFET devices are becoming increasingly important.

[0003] At present, there are many factors that cause power MOSFET devices to fail in bridge circuit topology. One of the most common and most difficult reasons for R&D engineers is the mis-conduction of the upper and lower MOSFETs, causing the entire bridge arm to be directly turned on, and eventually damaging the MOSFET.

[0004] Generally speaking, the main reason for the bridge arm shoot-through of the bridge circuit is that the dead time setting of the software control program is not reasonable, or it is affected by electromagnetic interference (EMI). Both of these situations may cause the upper and lower tubes to shoot through, thereby causing the device to burn out.

[0005] In recent years, with the continuous progress of power MOSFET technology, users have increasingly higher requirements for system performance, and are increasingly pursuing advantages such as high efficiency, high power density and high reliability. In this context, MOSFET needs to have a smaller on-resistance and faster switching speed while further reducing its conduction loss and switching loss. To achieve this goal, MOSFET devices are required to control the gate charge (Qg) within a smaller range. However, doing so will make the voltage change rate (dv / dt) very large at the moment the MOSFET is turned on.

[0006] In a bridge circuit, when the upper tube starts to conduct, the larger dv / dt will be coupled to the gate-source voltage (Vgs) of the lower tube through the Miller capacitance (Cgd), thereby interfering with the normal operation of the lower tube MOSFET and may even cause it to turn on by mistake. This undoubtedly brings extremely severe challenges to the stability and reliability of the device operation, and it is urgent to further optimize and improve the relevant technologies to deal with this problem.

[0007] In view of this, this application is filed. Summary of the invention

[0008] The present invention provides a MOSFET unit, a bridge circuit and a preparation method, which effectively solve the technical problem of misconduction of upper and lower MOSFETs in the bridge circuit.

[0009] One aspect of the present invention provides a MOSFET unit, comprising:

[0010] MOSFET, including an active region, a gate lead region, and a gate pad region; and

[0011] RC circuit, used to eliminate ringing signal;

[0012] The RC circuit comprises a first end and a second end, the first end is connected to the gate of the MOSFET, and the second end is connected to the source of the MOSFET;

[0013] The RC circuit is arranged in the Gate pad region of the MOSFET.

[0014] Further, the RC circuit includes a filtering module and a discharge module connected in parallel;

[0015] The filtering module includes a resistor and a capacitor, and the resistor and the capacitor are connected in series;

[0016] The discharge module includes an adjustable resistor.

[0017] On the other hand, the present application also provides a bridge circuit, comprising:

[0018] a first MOSFET unit and a second MOSFET unit;

[0019] The source of the first MOSFET unit is connected to the drain of the second MOSFET unit;

[0020] The source of the second MOSFET unit is grounded.

[0021] The first MOSFET unit and the second MOSFET unit both adopt the above-mentioned MOSFET unit.

[0022] Further, the gate of the first MOSFET unit is connected to the first chip;

[0023] The second MOSFET unit gate is connected to the second chip.

[0024] On the other hand, the present application also provides a method for preparing the above-mentioned MOSFET unit, comprising the following steps: including preparing an RC circuit in a Gate pad region.

[0025] Further, in step S1, a HDP filling isolation layer of a predetermined thickness is prepared in the gate pad area;

[0026] Step S2, depositing a third polysilicon layer on the HDP filling isolation layer;

[0027] Step S3: interlayer dielectric oxide deposition.

[0028] Further, in step S1, a field oxide layer is prepared in the gate pad region;

[0029] Step S2, depositing a first polysilicon layer;

[0030] Step S3, HDP filling isolation layer deposition;

[0031] Step S4, depositing a third polysilicon layer;

[0032] Step S5: interlayer dielectric oxide deposition.

[0033] Further, the third polysilicon layer forms a first resistor, a second resistor and a capacitor;

[0034] The first resistor and the capacitor are connected in series to form a filter module; the second resistor constitutes a discharge module; and the filter module and the discharge module are connected in parallel.

[0035] Compared with the prior art, the present invention has the following advantages:

[0036] The present application adds an RC circuit to the original MOSFET driving circuit, thereby reducing the coupling current of the Miller capacitor without increasing the area; for the MOSFET power device, the internal parameters Crss and Coss of the device are increased to make it more linear, thereby improving the slope of dv / dt during the MOSFET turn-on process and improving the smoothness of the device turn-on. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 It is a structural schematic diagram of a bridge circuit in the prior art;

[0039] Figure 2 It is a signal schematic diagram of a bridge circuit in the prior art;

[0040] Figure 3 A schematic diagram of a MOSFET unit provided in this embodiment;

[0041] Figure 4 A schematic diagram of a bridge circuit structure of a MOSFET unit using the present embodiment;

[0042] FIG5( a ) is a schematic diagram of a structure of a MOSFET unit;

[0043] FIG5( b ) is a schematic cross-sectional view of the MOSFET unit shown in FIG5( a );

[0044] FIG5( c ) is a schematic diagram of a manufacturing process of the MOSFET unit shown in FIG5( a );

[0045] FIG6( a ) is another schematic diagram of the structure of a MOSFET unit;

[0046] FIG6( b ) is a cross-sectional schematic diagram of the MOSFET unit shown in FIG6( a );

[0047] FIG6( c ) is a schematic diagram of the manufacturing process of the MOSFET unit shown in FIG6( a ). DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] Figure 1 It is a bridge circuit of the prior art. Figure 1 As shown, the bridge circuit includes a first MOSFET 10, a second MOSFET 20, a first chip 30 and a second chip 40, wherein the drain of the first MOSFET 10 is connected to the bus voltage, the source is respectively connected to the drain of the second MOSFET 20 and the first chip 30, and the gate is connected to the first chip 30; the drain of the second MOSFET 20 is connected to the source of the first MOSFET 10, the gate is connected to the second chip 40, and the source is connected to the ground terminal.

[0050] See again Figure 1 When the first MOSFET 10 is turned on and the second MOSFET 20 is turned off, the current flows along Figure 1 The middle line A forms a closed loop. However, in practice, in this case, the second MOSFET 20 is often mis-turned on (i.e. Figure 1 In line B, the upper and lower MOSFETs are turned on at the same time, which is not desirable.

[0051] Line B is caused by the dv / dt of the first MOSFET 10 coupling to the second MOSFET 20, thereby causing the Vgs signal of the second MOSFET 20 to be a ringing signal (such as Figure 2The amplitude of the ringing signal is close to the turn-on threshold voltage of the MOSFET, which poses a great risk of misleading turn-on.

[0052] In this regard, the present application proposes a MOSFET unit that can effectively solve the above-mentioned technical problem of misconduction.

[0053] Figure 3 FIG. 4 shows the MOSFET unit of this embodiment. Figure 3 As shown, the MOSFET unit includes an RC circuit and a MOSFET 70, and the RC circuit includes a filter module 50 and a discharge module 60 connected in parallel; wherein the filter module 50 is composed of a first resistor 501 and a capacitor 502 connected in series; and the discharge module 60 is composed of a second resistor 601. In addition, one end of the filter module 50 is connected to the gate of the MOSFET 70, and the other end is connected to the source of the MOSFET 70. Specifically, one end of the first resistor 501 is connected to the source of the MOSFET 70, and the other end is connected to one end of the capacitor 502, and the other end of the capacitor 502 is connected to the gate of the MOSFET 70; one end of the second resistor 601 of the discharge module 60 is connected to the gate of the MOSFET 70, and the other end is connected to the source of the MOSFET 70.

[0054] Figure 4 FIG. 4 shows a bridge circuit using the above-mentioned MOSFET unit.

[0055] In this embodiment, an RC circuit is added between the drain and source of the MOSFET to absorb part of the coupling current, so that the amplitude of the Vgs signal of the lower MOSFET is smaller than the turn-on threshold voltage of the MOSFET, which greatly reduces the probability of mis-turning on of the upper and lower MOSFETs.

[0056] Optionally, R is 5.1Ω and C is 10nF.

[0057] Optionally, the second resistor 601 is 100Ω.

[0058] The first resistor 501 and the second resistor 601 are both process-adjustable resistors and serve as a second-order RLC series circuit.

[0059] Fig. 5(a) shows a schematic diagram of a structure of a MOSFET unit. As shown in Fig. 5(a), the MOSFET unit includes an active region 101, a gate lead region 102 and a gate pad region 103. In this embodiment, the RC circuit is integrated in the gate pad region, thereby simplifying the circuit, reducing the cost, and the chip area does not increase.

[0060] FIG5( b ) is a schematic cross-sectional view of the MOSFET unit shown in FIG5( a ).

[0061] As shown in FIG. 5( b ), the gate pad region 103 includes, from bottom to top, a substrate 1011 , a HDP filling isolation layer 1014 , a third polysilicon layer 1017 , and an interlayer dielectric oxide layer 1016 .

[0062] In this embodiment, the third polysilicon layer 1017 can be divided into three parts: a first part 10171, a second part 10172 and a third part 10173. The first part 10171 forms the first resistor 501, the second part 10172 forms the two plates 502 of the capacitor, and the third part 10173 forms the second resistor 601. The interlayer dielectric oxide 1016 serves as an isolation insulating layer of the capacitor.

[0063] Furthermore, pins for connecting the gate are provided on the first part 10171 and the third part 10173 , and pins for connecting the source are provided on the second part 10172 and the third part 10173 .

[0064] 5( a ), in this embodiment, the first portion 10171 and the second portion 10172 constitute the plates of the capacitor, and the interlayer dielectric oxide 1016 therebetween serves as a dielectric to form a capacitor 502 , that is, a capacitor 502 is formed in the horizontal direction.

[0065] It should be noted that the capacitor in this embodiment may be in other forms and is not limited to the shapes shown in FIG. 5( a ) and FIG. 6( a ).

[0066] On the other hand, this embodiment also provides a method for preparing the MOSFET unit shown in FIG. 5( a ), including preparing an RC circuit in the Gatepad region.

[0067] Optionally, preparing an RC circuit in the Gate pad region includes the following steps:

[0068] Step S1, preparing a HDP filling isolation layer of a predetermined thickness in the gate pad area;

[0069] Step S2, depositing a third polysilicon layer on the HDP filling isolation layer;

[0070] Step S3: interlayer dielectric oxide deposition.

[0071] Generally, in addition to the gate pad region, the MOSFET also includes an active region 101 and a gate lead region 102 (not shown in FIG. 5( a)). Referring again to FIG. 5( b), it can be seen that the active region 101 includes, from bottom to top, a substrate 1011, a field oxide layer 1012, a first polysilicon layer 1013, an HDP filling isolation layer 1014, a second polysilicon layer 1015, and an interlayer dielectric oxide layer 1016; further, a pin for connecting the gate is provided on a portion of the second polysilicon layer 1015; and a pin for connecting the source is provided on the substrate 1011 and a portion of the third polysilicon layer 1017.

[0072] The gate lead-out region 102 includes, from bottom to top, a substrate 1011, a field oxide layer 1012, a first polysilicon layer 1013, an HDP filling isolation layer 1014, a second polysilicon layer 1015 and an interlayer dielectric oxide layer 1016; further, a pin for connecting the gate is provided on the second polysilicon layer 1015;

[0073] This embodiment takes the MOSFET unit shown in FIG. 5( b ) as an example to illustrate the MOSFET unit, as shown in FIG. 5( c ), including the following steps:

[0074] Step 1, preparing the EPI substrate 1011;

[0075] Step 2, growing a field oxide layer 1012 on the active area 101 of the substrate, the Gate lead-out area 102, and the GatePAD area 103;

[0076] Step 3: depositing and etching first polysilicon on the field oxide layer 1012 to obtain a first polysilicon layer 1013;

[0077] Step 4, etching the field oxide layer 1012;

[0078] Step 5, HDP filling is performed in the active area 101, the gate lead-out area 102 and the gate pad area 103;

[0079] Step 6: Mechanically polish and etch the HDP using a CMP process, so that the HDP layer on the active area 101, the Gate pad area 103 and part of the Gate lead-out area 102 reaches a preset thickness, thereby obtaining a HDP filling isolation layer 1014;

[0080] Step 7: HDP oxidation filling isolation layer etching and gate oxide growth

[0081] Step 8, depositing a second polysilicon layer 1015 on the HDP oxidation filling isolation layer 1014 of the active area 101 and a portion of the gate lead-out area 102;

[0082] Step 9, depositing a third polysilicon layer in the gate pad region to obtain a third polysilicon layer 1017;

[0083] Step 10: depositing an interlayer dielectric oxide to obtain an interlayer dielectric oxide layer 1016;

[0084] Step 11. Set the pins.

[0085] Optionally, the HDP layer filling can be replaced by oxide layer growth.

[0086] Preferably, the resistivity of the third polysilicon layer 1017 is variable and is higher than those of the second polysilicon layer 1015 and the first polysilicon layer 1013 .

[0087] The process steps of this embodiment omit conventional active area implantation steps.

[0088] Compared with the MOSFET in the prior art, the MOSFET unit obtained by the above-mentioned preparation method has the same thickness and the preparation process is not complicated.

[0089] It should be noted that this embodiment uses interdigital electrodes as capacitors for illustration, but is not limited thereto. The capacitors may also be other types such as planar capacitors.

[0090] Fig. 6(a) shows another schematic diagram of the structure of a MOSFET unit. Fig. 6(b) shows a cross-sectional schematic diagram of the MOSFET unit shown in Fig. 6(a).

[0091] The only difference between FIG. 6( a ) and FIG. 5( a ) is that the structure of the capacitor 502 in the gate pad region is different.

[0092] As shown in FIG6(b), the gate pad region 103 includes, from bottom to top, a substrate 1011, a field oxide layer 1012, a first polysilicon layer 1013, an HDP filling isolation layer 1014, a third polysilicon layer 1017, and an interlayer dielectric oxide layer 1016. The third polysilicon layer 1017 includes two first parts 10171 and a second part 10172.

[0093] In addition, pins for connecting to the source are provided on the substrate 1011 and a portion of the third polysilicon layer 1017 ; pins for connecting to the gate are provided on a portion of the first polysilicon layer 1013 , a portion of the second polysilicon layer 1015 and a portion of the third polysilicon layer 1017 .

[0094] Further, the two plates of capacitor 502 are formed by first portion 10172 and first polysilicon layer 1013, that is, capacitor 502 is formed in vertical direction. First portion 10171 forms first resistor 501 and third portion 10173 forms second resistor 601. HDP oxide layer 1014 serves as an isolation insulating layer of the capacitor.

[0095] On the other hand, this embodiment also provides a method for preparing the MOSFET unit shown in FIG. 6( b ), including preparing an RC circuit in the Gatepad region.

[0096] Optionally, preparing an RC circuit in the Gate pad region 103 includes the following steps:

[0097] Step S1, preparing a field oxide layer in the gate pad region 103;

[0098] Step S2, depositing a first polysilicon layer;

[0099] Step S3, etching the field oxide layer and the first polysilicon;

[0100] Step S4, HDP filling isolation layer deposition and etching;

[0101] Step S5, depositing and etching the third polysilicon layer;

[0102] Step S6: interlayer dielectric oxide deposition.

[0103] This embodiment takes the MOSFET unit shown in FIG. 6( b ) as an example to describe in detail the method for preparing the MOSFET unit, as shown in FIG. 6( c ), including the following steps:

[0104] Step 1, preparing the EPI substrate 1011;

[0105] Step 2, growing a field oxide layer 1012 on the active area 101, the Gate lead-out area 102 and the GatePAD area 103 of the substrate;

[0106] Step 3: depositing and etching first polysilicon on the field oxide layer 1012 to obtain a first polysilicon layer 1013;

[0107] Step 4, field oxide layer etching;

[0108] Step 5, HDP filling is performed in the active area 101, the gate lead-out area 102 and the gate pad area 103;

[0109] Step 6: Mechanically polish and etch the HDP using a CMP process, so that the HDP layer on the active area 101, the Gate pad area 103 and part of the Gate lead-out area 102 reaches a preset thickness, thereby obtaining a HDP filling isolation layer 1014;

[0110] Step 7: HDP oxidation filling isolation layer etching

[0111] Step 8: growing gate oxide on the HDP layer of the active area 101 and part of the gate lead-out area 102, depositing and etching the second polysilicon, and obtaining the second polysilicon layer 1015;

[0112] Step 9: depositing and etching a third polysilicon layer in the gate pad region to obtain a third polysilicon layer 1017;

[0113] Step 10: depositing interlayer dielectric oxide to obtain interlayer dielectric oxide 1016;

[0114] Step 11. Set the pins.

[0115] Optionally, the HDP fill layer can be replaced by an oxide layer growth.

[0116] Preferably, the resistivity of the third polysilicon layer 1017 is variable and is higher than those of the second polysilicon layer 1015 and the first polysilicon layer 1013 .

[0117] The process steps of this embodiment omit conventional active area implantation and other steps.

[0118] Compared with the MOSFET in the prior art, the MOSFET unit obtained by the above-mentioned preparation method has the same thickness and the preparation process is not complicated.

[0119] In addition, this application is not only applicable to SGT MOSFET, but also to all MOSFET products such as TRENCH / VDMOS MOSFET, IGBT, SJMOSFET, SiC MOSFET, etc.

[0120] The "equal" or "same" or "equal" disclosed in the present invention must take into account the parameter distribution of the project, and the error distribution is within ±30%; the definition of "parallel" of two line segments or two straight lines is that the angle between the two line segments or two straight lines is less than or equal to 45 degrees; the definition of "perpendicular" of two line segments or two straight lines is that the angle between the two line segments or two straight lines is within the range of [60, 120] degrees; the definition of "phase mismatch" also needs to take into account the parameter distribution of the project, and the error distribution of the degree of mismatch is within ±30%. In addition, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. Without more constraints, an element defined by the phrase "comprising a..." does not exclude the existence of other identical elements in the process, method, article or apparatus comprising the element.

[0121] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0122] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A MOSFET unit, characterized in that: include: MOSFET, including active region, gate lead region and gate pad region; and RC circuit, used to eliminate ringing signal; The RC circuit comprises a first end and a second end, the first end is connected to the gate of the MOSFET, and the second end is connected to the source of the MOSFET; The RC circuit is arranged in the Gate pad region of the MOSFET.

2. The MOSFET unit according to claim 1, wherein: The RC circuit includes a filter module and a discharge module connected in parallel; The filtering module includes a resistor and a capacitor, and the resistor and the capacitor are connected in series; The discharge module includes an adjustable resistor.

3. A bridge circuit, characterized in that: include: a first MOSFET unit and a second MOSFET unit; The source of the first MOSFET unit is connected to the drain of the second MOSFET unit; The source of the second MOSFET unit is grounded. The first MOSFET unit and the second MOSFET unit both adopt the MOSFET unit according to any one of claims 1 to 2.

4. The bridge circuit according to claim 3, characterized in that include: The gate of the first MOSFET unit is connected to the first chip; The second MOSFET unit gate is connected to the second chip.

5. A method for preparing a MOSFET unit according to any one of claims 1 to 2, characterized in that: This includes preparing an RC circuit in the Gatepad area.

6. The preparation method according to claim 5, characterized in that: The preparation of the RC circuit in the Gate pad area includes the following steps: Step S1, preparing a HDP filling isolation layer of a predetermined thickness in the gate pad area; Step S2, depositing a third polysilicon layer on the HDP filling isolation layer; Step S3: interlayer dielectric oxide deposition.

7. The preparation method according to claim 5, characterized in that: The preparation of the RC circuit in the Gate pad area includes the following steps: Step S1, preparing a field oxide layer in the gate pad region; Step S2, depositing a first polysilicon layer; Step S3, etching the field oxide layer and the first polysilicon; Step S4, HDP filling isolation layer deposition and etching; Step S5, depositing and etching the third polysilicon layer; Step S6: interlayer dielectric oxide deposition.

8. The preparation method according to any one of claims 5 to 7, characterized in that: The third polysilicon layer forms a first resistor, a second resistor and a capacitor; The first resistor and the second resistor are both process-adjustable resistors and serve as a second-order RLC circuit. The first resistor and the capacitor are connected in series to form a filter module; The second resistor constitutes a discharge module; the filter module and the discharge module are connected in parallel.

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