A MOSFET cell, a bridge circuit and a manufacturing method thereof

Abstract

The present invention provides a MOSFET unit, a bridge circuit and a manufacturing method. The MOSFET unit includes: a MOSFET, which includes an active region, a Gate lead-out region and a Gate pad region; and an RC circuit for eliminating ringing signals. The RC circuit includes a first end and a second end. The first end is connected to the gate of the MOSFET, and the second end is connected to the source of the MOSFET. The RC circuit is disposed in the Gate pad region of the MOSFET. This application reduces the probability of simultaneous conduction of the upper and lower MOSFETs.

Description

Technical Field

[0001] The present invention relates to the technical field of power MOSFETs, and particularly to the technical field of bridge circuits. Background Art

[0002] Power MOSFET devices are widely used in bridge circuit topologies due to their characteristics such as low on-resistance, fast switching speed, and increasingly miniaturized packaging. In recent years, with the rise of emerging industries such as new energy, robotics, and intelligent manufacturing, MOSFET power devices are widely used in motor control systems composed of brushed or brushless direct current motors (BLDC). Therefore, the reliable and stable operation of MOSFET devices becomes increasingly important.

[0003] Currently, there are many factors causing the failure of power MOSFET devices in bridge circuit topologies. One of the most common and troublesome reasons for R & D engineers is the mis-conduction of the upper and lower MOSFETs, resulting in the direct connection of the entire bridge arm and ultimately damaging the MOSFET.

[0004] Generally speaking, the main reason for the direct connection of the bridge arm in the bridge circuit is that the dead time setting of the software control program is not reasonable enough, or it is affected by electromagnetic interference (EMI). Both of these situations may cause the upper and lower tubes to have a direct connection phenomenon, thereby causing the device to burn out.

[0005] In recent years, with the continuous progress of power MOSFET technology, users' requirements for system performance have also been increasing day by day, and they increasingly pursue advantages such as high efficiency, high power density, and high reliability in the system. In this context, it is required that the MOSFET further reduces its conduction loss and switching loss while having a small on-resistance and a fast switching speed. To achieve this goal, it is required that the MOSFET device controls the gate charge (Qg) within a small range. However, doing so will make the voltage change rate (dv / dt) very large at the moment when the MOSFET conducts.

[0006] In the bridge circuit, when the upper tube starts to conduct, the large dv / dt will be coupled to the gate-source voltage (Vgs) of the lower tube through the Miller capacitance (Cgd), thereby interfering with the normal operation of the lower tube MOSFET and even possibly causing it to mis-turn on. This undoubtedly poses a very serious challenge to the stable and reliable operation of the device, and it is urgent for related technologies to be further optimized and improved to address this problem.

[0007] In view of this, the present application is proposed. Summary of the Invention

[0008] The present invention provides a MOSFET unit, a bridge circuit, and a preparation method, effectively solving the technical problem of mis-conduction of the upper and lower MOSFETs in the bridge circuit.

[0009] On the one hand, the present invention provides a MOSFET unit, comprising:

[0010] a MOSFET, including an active region, a Gate lead-out region, and a Gate pad region; and

[0011] an RC circuit for eliminating ringing signals;

[0012] The RC circuit includes a first end and a second end, the first end is connected to the gate of the MOSFET, and the second end is connected to the source of the MOSFET;

[0013] The RC circuit is disposed in the Gate pad region of the MOSFET.

[0014] Further, the RC circuit includes a parallel filter module and a discharge module;

[0015] The filter module includes a resistor and a capacitor, and the resistor and the capacitor are connected in series;

[0016] The discharge module includes a variable resistor.

[0017] On the other hand, the present application also provides a bridge circuit, comprising:

[0018] a first MOSFET unit and a second MOSFET unit;

[0019] The source of the first MOSFET unit is connected to the drain of the second MOSFET unit;

[0020] The source of the second MOSFET unit is grounded.

[0021] Both the first MOSFET unit and the second MOSFET unit adopt the above MOSFET unit.

[0022] Further, the gate of the first MOSFET unit is connected to a first chip;

[0023] The gate of the second MOSFET unit is connected to a second chip.

[0024] On the other hand, the present application also provides a preparation method of the above MOSFET unit, comprising the following steps: including preparing an RC circuit in the Gate pad region.

[0025] Further, step S1, preparing a HDP filling isolation layer with a predetermined thickness in the Gate pad region;

[0026] Step S2, depositing a third polysilicon layer on the HDP filling isolation layer;

[0027] Step S3: Deposit interlayer dielectric oxide.

[0028] Further, in step S1, a field oxide layer is prepared in the Gate pad region;

[0029] Step S2: Deposit the first polysilicon layer;

[0030] Step S3: Deposit an HDP-filled isolation layer;

[0031] Step S4: Deposit the third polysilicon layer;

[0032] Step S5: Deposit interlayer dielectric oxide.

[0033] Further, the third polysilicon layer forms a first resistor, a second resistor, and a capacitor;

[0034] The first resistor and the capacitor are connected in series to form a filtering module; the second resistor constitutes a discharging module; the filtering module and the discharging module are connected in parallel.

[0035] Compared with the prior art, the present invention has the following advantages:

[0036] In the present application, an RC circuit is added to the original MOSFET drive circuit. Without increasing the area, the coupling current of the Miller capacitance is reduced; for the MOSFET power device, the internal parameters Crss and Coss of the device are increased, making it more linear, thereby improving the slope of dv / dt during the MOSFET turn-on process and enhancing the smoothness of the device turn-on. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0038] Figure 1 It is a schematic structural diagram of a bridge circuit in the prior art;

[0039] Figure 2 It is a signal schematic diagram of a bridge circuit in the prior art;

[0040] Figure 3 It is a schematic diagram of a MOSFET unit provided in this embodiment;

[0041] Figure 4 It is a schematic structural diagram of a bridge circuit applying the MOSFET unit of this embodiment;

[0042] Figure 5(a) is a schematic structural diagram of a MOSFET unit;

[0043] Figure 5(b) is a schematic cross-sectional view of the MOSFET unit shown in Figure 5(a);

[0044] Figure 5(c) is a schematic diagram of the manufacturing process of the MOSFET unit shown in Figure 5(a);

[0045] Figure 6(a) is another schematic structural diagram of a MOSFET unit;

[0046] Figure 6(b) is a schematic cross-sectional view of the MOSFET unit shown in Figure 6(a);

[0047] Figure 6(c) is a schematic diagram of the manufacturing process of the MOSFET unit shown in Figure 6(a). Detailed implementation manners

[0048] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0049] Figure 1 The bridge circuit is a prior art. As Figure 1 shown, the bridge circuit includes a first MOSFET 10, a second MOSFET 20, a first chip 30, and a second chip 40. Among them, the drain of the first MOSFET 10 is connected to the bus voltage, the source is respectively connected to the drain of the second MOSFET 20 and the first chip 30, and the gate is connected to the first chip 30; the drain of the second MOSFET 20 is connected to the source of the first MOSFET 10, the gate is connected to the second chip 40, and the source is connected to the ground terminal.

[0050] Refer to again Figure 1 , when the first MOSFET 10 is turned on and the second MOSFET 20 is turned off, the current forms a closed loop along the Figure 1 line A in Figure 1 . However, in fact, in this case, the second MOSFET 20 often conducts misleadingly (that is, the

[0051] line B in Figure 2As shown, the amplitude of the ringing signal is close to the turn-on threshold voltage of the MOSFET, posing a great risk of mis-conduction.

[0052] In response, this application proposes a MOSFET unit that can effectively solve the above-mentioned technical problem of mis-conduction.

[0053] Figure 3 FIG. [FIGURE NUMBER] shows the MOSFET unit of this embodiment. As Figure 3 shown, the MOSFET unit includes an RC circuit and a MOSFET 70. The RC circuit includes a parallel-connected filtering module 50 and a discharging module 60. Among them, the filtering module 50 is composed of a series-connected first resistor 501 and a capacitor 502; the discharging module 60 is composed of a second resistor 601. Moreover, one end of the filtering module 50 is connected to the gate of the MOSFET 70, and the other end is connected to the source of the MOSFET 70. Specifically, one end of the first resistor 501 is connected to the source of the MOSFET 70, the other end is connected to one end of the capacitor 502, and the other end of the capacitor 502 is connected to the gate of the MOSFET 70; one end of the second resistor 601 of the discharging module 60 is connected to the gate of the MOSFET 70, and the other end is connected to the source of the MOSFET 70.

[0054] Figure 4 FIG. [FIGURE NUMBER] shows a bridge circuit applying the above MOSFET unit.

[0055] In this embodiment, an RC circuit is added between the drain and source of the MOSFET to absorb part of the coupled current, so that the amplitude of the Vgs signal of the lower MOSFET is less than the turn-on threshold voltage of the MOSFET, greatly reducing the probability of mis-conduction between the upper and lower MOSFETs.

[0056] Optionally, R is 5.1Ω and C is 10nF.

[0057] Optionally, the second resistor 601 is 100Ω.

[0058] Both the first resistor 501 and the second resistor 601 are process-adjustable resistors.

[0059] FIG. 5(a) shows a schematic structural diagram of a MOSFET unit. As shown in FIG. 5(a), the MOSFET unit includes an active region 101, a Gate lead-out region 102, and a Gate pad region 103. In this embodiment, the RC circuit is integrated in the Gate pad region, thus simplifying the circuit, reducing the cost, and the chip area does not increase.

[0060] FIG. 5(b) is a cross-sectional schematic diagram of the MOSFET unit shown in FIG. 5(a).

[0061] Note: Replace [FIGURE NUMBER] with the actual figure number in the original text.As shown in Figure 5(b), in the Gate pad region 103, from bottom to top, there are a substrate 1011, an HDP-filled isolation layer 1014, a third polysilicon layer 1017, and an interlayer dielectric oxide layer 1016 in sequence.

[0062] In this embodiment, the third polysilicon layer 1017 can be divided into three parts: a first part 10171, a second part 10172, and a third part 10173. The first part 10171 forms a first resistor 501, the second part 10172 forms two capacitor plates 502, and the third part 10173 forms a second resistor 601. The interlayer dielectric oxide 1016 serves as the isolation insulating layer of the capacitor.

[0063] Furthermore, pins for connecting the gate are provided on the first part 10171 and the third part 10173, and pins for connecting the source are provided on the second part 10172 and the third part 10173.

[0064] Combined with Figure 5(a), in this embodiment, the first part 10171 and the second part 10172 form the capacitor plates, and with the HDP-filled isolation layer between them as the medium, they jointly form a capacitor 502, that is, a capacitor 502 is formed in the horizontal direction.

[0065] It should be noted that the capacitor in this embodiment can be in other forms and is not limited to the shapes shown in Figures 5(a) and 6(a).

[0066] On the other hand, this embodiment also provides a method for manufacturing the MOSFET unit shown in Figure 5(a), including preparing an RC circuit in the Gate pad region.

[0067] Optionally, preparing an RC circuit in the Gate pad region includes the following steps:

[0068] Step S1: Prepare an HDP-filled isolation layer with a predetermined thickness in the Gate pad region;

[0069] Step S2: Deposit a third polysilicon layer on the HDP-filled isolation layer;

[0070] Step S3: Deposit an interlayer dielectric oxide.

[0071] Generally, in addition to the Gate pad region, a MOSFET also includes an active region 101 and a Gate lead-out region 102 (not shown in Fig. 5(a)). Referring again to Fig. 5(b), it can be seen that the active region 101 includes, from bottom to top, a substrate 1011, a field oxide layer 1012, a first polysilicon layer 1013, an HDP-filled isolation layer 1014, a second polysilicon layer 1015, and an interlayer dielectric oxide layer 1016; further, pins for connecting the gate are provided on a part of the second polysilicon layer 1015; pins for connecting the source are provided on the substrate 1011 and a part of the third polysilicon layer 1017.

[0072] The Gate lead-out region 102 includes, from bottom to top, a substrate 1011, a field oxide layer 1012, a first polysilicon layer 1013, an HDP-filled isolation layer 1014, a second polysilicon layer 1015, and an interlayer dielectric oxide layer 1016; further, pins for connecting the gate are provided on the second polysilicon layer 1015;

[0073] In this embodiment, the MOSFET unit shown in Fig. 5(b) is taken as an example to illustrate the MOSFET unit. As shown in Fig. 5(c), the following steps are included:

[0074] Step 1, fabricating the EPI substrate 1011;

[0075] Step 2, growing the field oxide layer 1012 on the active region 101, the Gate lead-out region 102, and the GatePAD region 103 of the substrate;

[0076] Step 3, depositing and etching the first polysilicon on the field oxide layer 1012 to obtain the first polysilicon layer 1013;

[0077] Step 4, etching the field oxide layer 1012;

[0078] Step 5, performing HDP filling on the active region 101, the Gate lead-out region 102, and the Gate pad region 103;

[0079] Step 6, mechanically polishing and etching the HDP using the CMP process so that the HDP layer on the active region 101, the Gate pad region 103, and a part of the Gate lead-out region 102 reaches a preset thickness, obtaining the HDP-filled isolation layer 1014;

[0080] Step 7, etching the HDP oxide-filled isolation layer and growing the gate oxide

[0081] Step 8, depositing the second polysilicon on the HDP oxide-filled isolation layer 1014 of the active region 101 and a part of the Gate lead-out region 102 to obtain the second polysilicon layer 1015;

[0082] Step 9: Deposit the third polysilicon in the Gate pad region to obtain the third polysilicon layer 1017;

[0083] Step 10: Deposit the interlayer dielectric oxide to obtain the interlayer dielectric oxide layer 1016;

[0084] Step 11: Set the pins.

[0085] Optionally, the HDP layer filling can be replaced by oxide layer growth.

[0086] Preferably, the resistivity of the third polysilicon layer 1017 is variable and higher than that of the second polysilicon layer 1015 and the first polysilicon layer 1013.

[0087] The process steps of this embodiment omit the conventional steps such as active region implantation.

[0088] The MOSFET unit obtained by the above preparation method has the same thickness as the MOSFET in the prior art, and the preparation process is not complicated.

[0089] It should be noted that in this embodiment, the interdigital electrode is taken as an example to illustrate the capacitor, but it is not limited thereto. The capacitor can also be other types such as a planar capacitor.

[0090] FIG. 6(a) shows another structural schematic diagram of the MOSFET unit. FIG. 6(b) shows a cross-sectional schematic diagram of the MOSFET unit shown in FIG. 6(a).

[0091] The difference between FIG. 6(a) and FIG. 5(a) is only that the structure of the capacitor 502 in the Gate pad region is different.

[0092] As shown in FIG. 6(b), in the Gate pad region 103, from bottom to top, it includes: a substrate 1011, a field oxide layer 1012, a first polysilicon layer 1013, an HDP filling isolation layer 1014, a third polysilicon layer 1017, and an interlayer dielectric oxide layer 1016. Among them, the third polysilicon layer 1017 includes two first parts 10171 and a second part 10172

[0093] Moreover, pins for connecting the source are provided on the substrate 1011 and part of the third polysilicon layer 1017; pins for connecting the gate are provided on part of the first polysilicon layer 1013, part of the second polysilicon layer 1015, and part of the third polysilicon layer 1017.

[0094] Further, two electrodes of the capacitor 502 are formed by the first part 10172 and the first polysilicon layer 1013. That is, the first part 10171 of the capacitor 502 is formed in the vertical direction, the third part 10173 of the first resistor 501 is formed, and the second resistor 601 is formed. The HDP oxide layer 1014 serves as the isolation insulating layer of the capacitor.

[0095] On the other hand, this embodiment also provides a method for manufacturing a MOSFET unit shown in FIG. 6(b), including preparing an RC circuit in the Gatepad area.

[0096] Optionally, preparing the RC circuit in the Gate pad area 103 includes the following steps:

[0097] Step S1: Prepare a field oxide layer in the Gate pad area 103;

[0098] Step S2: Deposit the first polysilicon layer;

[0099] Step S3: Etch the field oxide layer and the first polysilicon;

[0100] Step S4: Deposit and etch the HDP filling isolation layer;

[0101] Step S5: Deposit and etch the third polysilicon layer;

[0102] Step S6: Deposit the interlayer dielectric oxide.

[0103] This embodiment takes the MOSFET unit shown in FIG. 6(b) as an example to elaborate on the method for manufacturing a MOSFET unit. As shown in FIG. 6(c), it includes the following steps:

[0104] Step 1: Fabricate the EPI substrate 1011;

[0105] Step 2: Grow the field oxide layer 1012 on the active area 101, Gate lead-out area 102, and GatePAD area 103 of the substrate;

[0106] Step 3: Deposit and etch the first polysilicon on the field oxide layer 1012 to obtain the first polysilicon layer 1013;

[0107] Step 4: Etch the field oxide layer;

[0108] Step 5: Perform HDP filling in the active area 101, Gate lead-out area 102, and Gate pad area 103;

[0109] Step 6: Use the CMP process to mechanically polish and etch the HDP so that the HDP layer on the active area 101, Gate pad area 103, and part of the Gate lead-out area 102 reaches a preset thickness, obtaining the HDP filling isolation layer 1014;

[0110] Step 7, etching of the HDP oxide-filled isolation layer

[0111] Step 8, growing gate oxide on the HDP layer of the active region 101 and part of the Gate lead-out region 102, depositing and etching the second polysilicon to obtain the second polysilicon layer 1015;

[0112] Step 9, depositing and etching the third polysilicon in the Gate pad region to obtain the third polysilicon layer 1017;

[0113] Step 10, depositing the interlayer dielectric oxide to obtain the interlayer dielectric oxide 1016;

[0114] Step 11, setting the pins.

[0115] Optionally, the HDP filling layer can be replaced by oxide growth.

[0116] Preferably, the resistivity of the third polysilicon layer 1017 is variable and higher than that of the second polysilicon layer 1015 and the first polysilicon layer 1013.

[0117] The process steps of this embodiment omit conventional steps such as active region implantation.

[0118] The MOSFET unit obtained by the above preparation method has the same thickness as the MOSFET in the prior art, and the preparation process is not complicated.

[0119] In addition, this application is applicable not only to SGT MOSFETs, but also to all MOSFET products such as TRENCH / VDMOS MOSFETs, IGBTs, SJMOSFETs, and SiC MOSFETs.

[0120] The "equal", "same", or "equivalent" disclosed in the present invention must consider the parameter distribution of the project, with the error distribution within ±30%; the definition of "parallel" for two line segments or two straight lines is that the included angle between the two line segments or two straight lines is less than or equal to 45 degrees; the definition of "perpendicular" for two line segments or two straight lines is that the included angle between the two line segments or two straight lines is within the range of [60, 120] degrees; the definition of "phase shift" of the phase also needs to consider the parameter distribution of the project, and the error distribution of the phase shift degree is within ±30%. In addition, in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0121] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other.

[0122] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A MOSFET cell, characterized in that, Comprising: A MOSFET, including an active region, a Gate lead-out region, and a Gate pad region; And An RC circuit for eliminating ringing signals; The RC circuit includes a first end and a second end, the first end is connected to the gate of the MOSFET, and the second end is connected to the source of the MOSFET; The RC circuit is integrated in the Gate pad region of the MOSFET.

2. The MOSFET unit according to claim 1, wherein The RC circuit includes a parallel filter module and a discharge module; The filter module includes a resistor and a capacitor, and the resistor and the capacitor are connected in series; The discharge module includes a variable resistor.

3. A bridge circuit, characterized in that, Comprising: A first MOSFET unit and a second MOSFET unit; The source of the first MOSFET unit is connected to the drain of the second MOSFET unit; The source of the second MOSFET unit is grounded; Both the first MOSFET unit and the second MOSFET unit adopt the MOSFET unit according to any one of claims 1-2.

4. The bridge circuit according to claim 3, wherein Comprising: The gate of the first MOSFET unit is connected to a first chip; The gate of the second MOSFET unit is connected to a second chip.

5. A method for manufacturing a MOSFET cell according to any one of claims 1-2, characterized in that, Including fabricating an RC circuit in the Gatepad region.

6. The preparation method according to claim 5, characterized in that, Fabricating an RC circuit in the Gate pad region includes the following steps: Step S1, fabricate a HDP filling isolation layer with a predetermined thickness in the Gate pad region; Step S2, deposit a third polysilicon layer on the HDP filling isolation layer; Step S3, deposit interlayer dielectric oxide.

7. The preparation method according to claim 5, characterized in that, Fabricating an RC circuit in the Gate pad region includes the following steps: Step S1, fabricate a field oxide layer in the Gate pad region; Step S2, deposit a first polysilicon layer; Step S3, etch the field oxide layer and the first polysilicon; Step S4, deposit and etch the HDP filling isolation layer; Step S5, deposit and etch the third polysilicon layer; Step S6, deposit interlayer dielectric oxide.

8. The manufacturing method according to any one of claims 5-7, wherein The third polysilicon layer forms a first resistor, a second resistor, and a capacitor; Both the first resistor and the second resistor are process-adjustable resistors; The first resistor and the capacitor are connected in series to form a filter module; the second resistor constitutes a discharge module; the filter module and the discharge module are connected in parallel.

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