Printed circuit board and manufacturing method thereof

Abstract

The invention provides a printed circuit board and a method of manufacturing the same. The printed circuit board comprises a wiring part and a conductive part, comprising one or more insulating layers, and one or more wiring layers which are respectively arranged on the one or more insulating layers and / or in the one or more insulating layers, a first pad disposed on a lowermost insulating layer of the one or more insulating layers and a second pad disposed on an uppermost insulating layer of the one or more insulating layers; a first solder resist layer disposed on a lower side of the wiring portion to cover a portion of the first pad, the first solder resist layer having a first opening on the first pad; a second solder resist layer disposed on an upper side of the wiring portion to cover a portion of the second pad; a first surface treatment layer disposed on at least a portion of the first pad; and a barrier layer disposed on the first solder resist layer. And the thickness of the barrier layer is smaller than that of the first bonding pad.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0128292 filed on September 25, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board and a method for manufacturing the same. Background Art

[0003] Multi-chip packages (including memory chips such as high bandwidth memory (HBM), processor chips such as central processing units (CPUs), graphics processing units (GPUs), and logic chips such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs)) have been used to process data that has been growing exponentially due to the recent development of artificial intelligence (AI) technology. In particular, the number of CPU cores and GPU cores of server products is increasing rapidly, so finer chip metal pillar spacing is required. Research has been conducted to form finer pads on the board for connection between the chip and the board, and to increase the yield while improving the reliability of the connection between the chip and the board. Summary of the invention

[0004] An aspect of the present disclosure provides a printed circuit board having electronic components and semiconductor chips mounted thereon and capable of implementing metal pillars with a fine pitch, and a method of manufacturing the same.

[0005] Another aspect of the present disclosure provides a printed circuit board and a method for manufacturing the same, wherein the printed circuit board includes a pad located on the upper side of the printed circuit board, a metal column located on the pad, and a surface treatment layer located on the lower side of the printed circuit board, wherein when the metal column is provided, the printed circuit board does not have defects caused by galvanic corrosion between the pad and the surface treatment layer.

[0006] Another aspect of the present disclosure provides a printed circuit board having improved reliability and a method of manufacturing the same.

[0007] One aspect of the present disclosure provides a printed circuit board, the printed circuit board comprising: a wiring portion, including one or more insulating layers, one or more wiring layers respectively arranged on the one or more insulating layers and / or in the one or more insulating layers, a first pad arranged on the lowest insulating layer of the one or more insulating layers, and a second pad arranged on the highest insulating layer of the one or more insulating layers; a first solder resist layer arranged on the lower side of the wiring portion to cover a portion of the first pad, the first solder resist layer having a first opening located on the first pad; a second solder resist layer arranged on the upper side of the wiring portion to cover a portion of the second pad; a first surface treatment layer arranged on at least a portion of the first pad; and a barrier layer arranged on the first solder resist layer. The thickness of the barrier layer may be less than the thickness of the first pad.

[0008] According to another aspect of the present disclosure, a printed circuit board is provided, the printed circuit board comprising: a wiring portion including one or more insulating layers, one or more wiring layers respectively arranged on the one or more insulating layers and / or in the one or more insulating layers, a first pad arranged on the lowest insulating layer of the one or more insulating layers, and a second pad arranged on the highest insulating layer of the one or more insulating layers; a first solder resist layer arranged on the lower side of the wiring portion to cover a portion of the first pad, the first solder resist layer having a first opening located on the first pad; a second solder resist layer arranged on the upper side of the wiring portion to cover a portion of the second pad; a first surface treatment layer arranged on at least a portion of the first pad; and a barrier layer arranged on the first solder resist layer. The barrier layer may include an inorganic oxide film.

[0009] According to another aspect of the present disclosure, a printed circuit board is provided, the printed circuit board comprising: a wiring portion, comprising one or more insulating layers, one or more wiring layers respectively arranged on the one or more insulating layers and / or in the one or more insulating layers, a first pad arranged on the lowest insulating layer of the one or more insulating layers, and a second pad arranged on the highest insulating layer of the one or more insulating layers; a first solder resist layer arranged on the lower side of the wiring portion to cover a portion of the first pad, the first solder resist layer having a first opening located on the first pad; a second solder resist layer arranged on the upper side of the wiring portion to cover a portion of the second pad; a first surface treatment layer arranged on at least a portion of the first pad; and a barrier layer arranged on the first solder resist layer. The barrier layer may be a film having a thickness of less than 100 nm.

[0010] According to another aspect of the present disclosure, a method for manufacturing a printed circuit board is provided, the method comprising: preparing a wiring portion, the wiring portion comprising one or more insulating layers, one or more wiring layers respectively arranged on the one or more insulating layers and / or in the one or more insulating layers, a first solder pad arranged on the lowest insulating layer among the one or more insulating layers, and a second solder pad arranged on the highest insulating layer among the one or more insulating layers; forming a first solder resist layer and a second solder resist layer on the lower side and the upper side of the wiring portion, respectively; forming a first opening in the first solder resist layer to expose at least a portion of the first solder pad; forming a first surface treatment layer on the at least a portion of the first solder pad; arranging a blocking layer on the first solder resist layer; forming a second opening in the second solder resist layer to expose at least a portion of the second solder pad; and forming a metal column on the at least a portion of the second solder pad.

[0011] According to example embodiments of the present disclosure, a printed circuit board on which electronic components and semiconductor chips are mounted may implement metal pillars having a fine pitch.

[0012] According to an example embodiment of the present disclosure, a printed circuit board includes a solder pad located on an upper side of the printed circuit board, a metal column located on the solder pad, and a surface treatment layer located on a lower side of the printed circuit board. When the metal column is provided, the printed circuit board will not have defects caused by galvanic corrosion between the solder pad and the surface treatment layer.

[0013] A printed circuit board according to example embodiments of the present disclosure may have improved reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a schematic block diagram of an example of an electronic device system; Figure 2 is a schematic perspective view of an example of an electronic device; Figure 3A and Figure 3B is a schematic cross-sectional view of a printed circuit board according to an example; Figure 4A and Figure 4B is a schematic cross-sectional view of a printed circuit board according to another example; and Figures 5 to 15 is a schematic cross-sectional view of a method of manufacturing a printed circuit board according to an example. DETAILED DESCRIPTION

[0015] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. For clearer description, the shapes and sizes of elements in the drawings may be exaggerated or reduced.

[0016] Electronic Devices Figure 1 A schematic block diagram of an example of an electronic device system is shown.

[0017] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to the mainboard 1010. Such components may be connected to other electronic components to be described below via various signal lines 1090.

[0018] The chip-related components 1020 may include: a memory chip, such as a volatile memory (e.g., a dynamic random access memory (DRAM)), a non-volatile memory (e.g., a read-only memory (ROM) or a flash memory); an application processor chip, such as a central processing unit (e.g., a central processing unit (CPU)), a graphics processor (e.g., a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor or a microcontroller; and a logic chip, such as an analog-to-digital converter or an application-specific integrated circuit (ASIC). However, the chip-related components 1020 are not limited thereto and may include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips or electronic components.

[0019] The network-related components 1030 may include components compatible with or operating according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), Third Generation Mobile Communication Technology (3G) Protocol, Fourth Generation Mobile Communication Technology (4G) Protocol, and Fifth Generation Mobile Communication Technology (5G) Protocol, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, and may also include components compatible with or operating according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 described above.

[0020] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto and may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0021] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. The other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. However, the other electronic components are not limited thereto, and may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), etc. Depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0022] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device for processing data.

[0023] Figure 2 is a schematic perspective view of an example of an electronic device.

[0024] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various electronic components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. A portion of the electronic component 1120 may be the above-mentioned chip-related component, for example, a component package 1121, but the present disclosure is not limited thereto. The component package 1121 may be in the form of a printed circuit board on which an electronic component (including an active component and / or a passive component) is surface-mounted. The electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0025] Printed Circuit Board Figure 3A and Figure 3B is a schematic cross-sectional view of an example of a printed circuit board.

[0026] Reference Figure 3AAccording to the example, the printed circuit board may include a wiring portion 100, the wiring portion 100 includes: one or more insulating layers 110; one or more wiring layers 120, respectively disposed on the one or more insulating layers 110 and / or in the one or more insulating layers 110; a first pad 141, disposed on the lowest insulating layer of the one or more insulating layers 110; and a second pad 142, disposed on the highest insulating layer of the one or more insulating layers 110. In addition, the printed circuit board according to the example may further include: a first solder resist layer 171, disposed on the lower side of the wiring portion 100 to cover a portion of the first pad 141, the first solder resist layer 171 having a first opening 1710; a first surface treatment layer 161, disposed on at least a portion of the first pad 141; a barrier layer 180, disposed on the first solder resist layer 171; a second solder resist layer 172, disposed on the upper side of the wiring portion 100; and a metal column 150, disposed on the second pad 142. The printed circuit board according to the example may further include a second surface treatment layer 162 disposed on the metal pillar 150. In this case, the barrier layer 180 may include an inorganic oxide film. The thickness of the barrier layer 180 may be less than the thickness of the first pad 141, and may be less than the thickness of the first surface treatment layer 161.

[0027] The printed circuit board according to the example may include a barrier layer 180 on the first solder resist layer 171 so that the first surface treatment layer 161 disposed on the first pad 141 may be covered by the barrier layer 180. The first surface treatment layer 161 may be covered by the barrier layer 180 so that galvanic corrosion caused by etching may not occur in an operation of disposing the metal pillar 150 on the second pad 142.

[0028] When two metals with different electrochemical properties (such as different standard reduction potentials) are exposed to a corrosive solution in a state of being electrically connected to each other, galvanic corrosion may occur. A metal that is more active or has a lower standard reduction potential may be corroded during galvanic corrosion. The first surface treatment layer 161 may include gold (Au) located at its outermost side, and the second pad 142 may include copper (Cu). In the operation of pre-treating the second pad 142 through the second opening 1720 of the second solder resist layer 172 to set the metal column 150 on the second pad 142, the second pad 142 and the first surface treatment layer 161 may be simultaneously exposed to an etching solution for soft etching. Therefore, the second pad 142 including copper (Cu) with a relatively low standard reduction potential may act as an anode, and the first surface treatment layer 161 including gold (Au) with a relatively high standard reduction potential may act as a cathode, resulting in galvanic corrosion between the second pad 142 and the first surface treatment layer 161. More specifically, galvanic corrosion may occur in the second pad 142, resulting in defects in the second pad 142 and defects in the metal pillar 150 disposed on the second pad 142. The metal material of the first surface treatment layer 161 and the metal material of the second pad 142 are not necessarily limited to gold (Au) and copper (Cu), respectively, and may include all cases where galvanic corrosion may occur between the first surface treatment layer 161 and the second pad 142 due to different standard reduction potentials.

[0029] However, in the printed circuit board according to the example, after the first surface treatment layer 161 is disposed on the first pad 141, a barrier layer 180 may be disposed on the first solder resist layer 171, thereby preventing the second pad 142 and the first surface treatment layer 161 from being simultaneously exposed to the etching solution during the operation of pre-treating the second pad 142. More specifically, the barrier layer 180 may be conformally disposed along the lower surface of the first surface treatment layer 161, the inner wall of the first opening 1710 disposed in the first solder resist layer 171, and the lower surface of the first solder resist layer 171, thereby preventing galvanic corrosion of the second pad 142. The barrier layer 180 may include a thin oxide film, but the present disclosure is not necessarily limited thereto.

[0030] The printed circuit board according to the example can prevent galvanic corrosion of the second pad 142 so that no defect occurs when the second pad 142 and the metal pillar 150 are designed to have a fine pitch. Therefore, it is convenient to connect components with a fine pitch (such as a semiconductor chip, etc.) to the upper side of the wiring portion 100.

[0031] The insulating layer 110 may include one or more insulating layers. For example, the insulating layer 110 may include a first insulating layer 111 as a core layer and a second insulating layer 112 as a stacked insulating layer. The insulating layer 110 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler and / or glass fiber (such as glass fabric with glass cloth as an example) and the above resin. The insulating material may have a photosensitive property or a non-photosensitive property. For example, the insulating material of the insulating layer 110 may be an Ajinomoto stacked film (ABF), but the present disclosure is not limited thereto, and may include a prepreg (PPG), a copper-clad resin (RCC), a photosensitive dielectric (PID), FR-4, bismaleimide triazine (BT), etc. However, the present disclosure is not limited thereto, and other materials with excellent rigidity, such as a glass material, etc., may be used as needed.

[0032] The wiring layer 120 may include one or more wiring layers, and may include a first wiring layer 121 disposed on and / or in the first insulating layer 111 and a second wiring layer 122 disposed on and / or in the second insulating layer 112 as a stacked wiring layer.

[0033] The wiring layer 120 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, the metal material may include copper (Cu), but the present disclosure is not limited thereto, and the first wiring layer 121 and the second wiring layer 122 may include different metal materials. The wiring layer 120 may perform various functions according to its design. For example, the wiring layer 120 may include a signal pattern, a power pattern, a ground pattern, etc., but the present disclosure is not limited thereto, and may be used as a pad on which electronic components and chips are mounted, or may be used as a stopper for forming a cavity. Each of the above patterns may have various forms such as lines, surfaces, pads, etc. The wiring layer 120 may have different pitches according to its function. When the wiring layer 120 requires a high-density fine pitch for connection to a connection structure or a semiconductor chip, the pitch between the wiring layers 120 may be reduced. When the wiring layer 120 performs signal connection, the pitch between the wiring layers 120 may be increased.

[0034] The wiring layer 120 may be provided using one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a via sealing (TT) process, and a subtractive process, but the present disclosure is not limited thereto. The wiring layer 120 may include an electroless plating layer (e.g., a chemical copper plating layer) as a seed layer and an electrolytic plating layer (e.g., an electrolytic copper plating layer) as a plating layer, but the present disclosure is not limited thereto. A sputtering layer may be provided instead of the electroless plating layer (e.g., a chemical copper plating layer). The wiring layer 120 may further include a copper foil as needed.

[0035] The wiring portion 100 of the printed circuit board according to the example may further include a via layer 130 connecting the wiring layers 120 to each other. The via layer 130 may include one or more via layers, and may include a first via layer 131 (as a through via layer passing through the first insulating layer 111) and a second via layer 132 (as a built-up via layer passing through at least a portion of the second insulating layer 112).

[0036] The first via layer 131 may include a metal layer disposed on the wall surface of the through hole passing through the first insulating layer 111 and a plug filling the space between the metal layers. The metal layer may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof, and preferably, may include copper (Cu), but the present disclosure is not limited thereto. The plug may include ink having a component including an insulating material. The metal layer may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. A sputtering layer may be provided instead of the electroless plating layer, or a sputtering layer may be provided in addition to the electroless plating layer. The first via layer 131 may perform various functions according to its design. For example, the first via layer 131 may include a ground via, a power via, a signal via, etc.

[0037] The second via layer 132 may include micro vias. The micro vias may be filled vias that fill the via holes, or conformal vias that are arranged along the wall surface of the via holes. The micro vias may be arranged as stacked vias and / or staggered vias. The second via layer 132 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys, and preferably, copper (Cu) may be included, but the present disclosure is not limited thereto. The second via layer 132 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. A sputtering layer may be provided instead of the electroless plating layer, or a sputtering layer may be provided in addition to the electroless plating layer. The second via layer 132 may perform various functions according to its design. For example, the second via layer 132 may include a ground via, a power via, a signal via, and the like.

[0038] The printed circuit board according to the example may further include a first pad 141 located at the lower side of the wiring portion 100. The first pad 141 may be disposed on and / or in the lowermost insulating layer of the second insulating layer 112. Figure 3A, it is shown that the first pad 141 is disposed on the second insulating layer 112 and protrudes from the lower side of the second insulating layer 112, but the present disclosure is not necessarily limited thereto. The first pad 141 may have a structure in which the first pad 141 is embedded in the lower side of the second insulating layer 112. The first pad 141 may be connected to at least a portion of the second wiring layer 122 through one of the second via layers 132.

[0039] The first pad 141 may include a metal material, and the metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof, and preferably, may include copper (Cu), but the present disclosure is not limited thereto. The first pad 141 may be disposed at the lowermost side of the wiring portion 100, and may be used as a connection pad so that the lower surface of the printed circuit board is connected to other components such as a main board. However, the present disclosure is not limited thereto, and the first pad 141 may be used as a component for connecting to a component having a fine pitch (such as a semiconductor chip), and the pitch may be designed in various ways according to its function. The first pad 141 may perform various functions according to its design. For example, the first pad 141 may include a ground pad, a power pad, a signal pad, and the like. Here, the signal pad may include a pad for transmission of various signals (e.g., a data signal, etc.) other than a ground signal, a power signal, and the like.

[0040] The printed circuit board according to the example may further include a second pad 142 located at the upper side of the wiring portion 100. The second pad 142 may be disposed on and / or in the uppermost insulating layer of the second insulating layers 112. Figure 3A , it is shown that the second pad 142 is disposed on the second insulating layer 112 and protrudes toward the upper side of the second insulating layer 112. However, the present disclosure is not necessarily limited thereto, and the second pad 142 may also be embedded in the second insulating layer 112. In this case, the second pad 142 may have a pad structure having a finer pitch than that of the first pad 141. As a non-limiting example, a structure in which the second pad 142 is embedded in the second insulating layer 112 may be more preferred than a structure in which the first pad 141 is embedded in the second insulating layer 112. The second pad 142 may be connected to at least a portion of the second wiring layer 122 through one of the second via layers 132.

[0041] The second pad 142 may include a metal material, and the metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys, and preferably, may include copper (Cu), but the present disclosure is not limited thereto. The second pad 142 may be disposed on the uppermost side of the wiring portion 100, may be used to mount electronic components and chips, and may be connected to a circuit pattern to perform signal transmission with other pads. The second pad 142 may perform various functions according to its design. For example, the second pad 142 may include a ground pad, a power pad, a signal pad, etc. The signal pad may include a pad for the transmission of various signals (e.g., data signals, etc.) other than a ground signal, a power signal, etc. When the second pad 142 requires a high-density fine pitch to mount a semiconductor chip, etc., the spacing between the second pads 142 may be reduced. When the electronic components are mounted, the spacing between the second pads 142 may be increased. In addition, the interval between the second pads 142 in a region where a semiconductor chip or the like is mounted through other components such as the connection structure 200 or the like may be reduced.

[0042] The first and second pads 141 and 142 may be formed using one of SAP, MSAP, a TT process, and a subtractive process, but the present disclosure is not limited thereto and may be formed using other methods that may be used by those skilled in the art.

[0043] The printed circuit board according to the example may further include a first solder resist layer 171 disposed on the lower side of the wiring portion 100 and a second solder resist layer 172 disposed on the upper side of the wiring portion 100. The first solder resist layer 171 is disposed on the lowermost insulating layer of the second insulating layers 112, and the second solder resist layer 172 is disposed on the uppermost insulating layer of the second insulating layers 112.

[0044] The first solder resist layer 171 and the second solder resist layer 172 may be respectively disposed at the outermost side of the printed circuit board to protect the printed circuit board externally. The first solder resist layer 171 and the second solder resist layer 172 may use a known solder resist. The first solder resist layer 171 and the second solder resist layer 172 may both include an insulating resin (e.g., a thermosetting resin) and a filler dispersed in the insulating resin, but may not include glass fiber. The insulating resin may also be a photosensitive insulating resin, and the filler may be an inorganic filler and / or an organic filler, but the present disclosure is not limited thereto, and other polymer materials may be used. For example, the first solder resist layer 171 and the second solder resist layer 172 may both include a photosensitive insulating resin. When a photosensitive insulating resin is used as a solder resist layer, it may be advantageous to set a fine opening, but the present disclosure is not limited thereto, and a fine opening may also be formed with an ultraviolet (UV) laser when the solder resist layer includes a non-photosensitive insulating resin.

[0045] The first solder resist layer 171 may have a first opening 1710, and at least a portion of the first pad 141 may be exposed through the first opening 1710. Exposing at least a portion of the first pad 141 through the first opening 1710 may mean that, in addition to the case where the first pad 141 is exposed to the outside of the printed circuit board, at least a portion of the first pad 141 may be connected to other components because the first solder resist layer 171 does not cover the at least a portion of the first pad 141.

[0046] exist Figure 3A , although it is shown that the first opening 1710 of the first solder resist layer 171 exposes a portion of the lower surface of the first pad 141, the first solder resist layer 171, the first opening 1710 and the first pad 141 are not limited to being aligned in a solder mask defined (SMD) form, and may be aligned in a non-solder mask defined (NSMD) form, etc. The relationship between the first pad 141 and the first solder resist layer 171 is not limited to the relationship shown in the drawings. When aligned in the NSMD form, the width of the first opening 1710 of the first solder resist layer 171 may be formed to be wider than the width of the first pad 141, the lower surface of the first pad 141 may be exposed through the first opening 1710 of the first solder resist layer 171, and the side surface of the first pad 141 may also be exposed through the first opening 1710 of the first solder resist layer 171.

[0047] The second solder resist layer 172 may cover a portion of the second pad 142. In addition, the metal pillar 150 may pass through a portion of the second solder resist layer 172 and may protrude from the second solder resist layer 172. The protrusion of the metal pillar 150 from the second solder resist layer 172 may mean that the upper surface of the metal pillar 140 may be positioned higher than the upper surface of the second solder resist layer 172.

[0048] The second solder resist layer 172 may also expose at least a portion of the second pad 142 through the second opening 1720, and the second opening 1720 may be filled with the metal pillar 150. In this case, in the region where the metal pillar 150 and the second pad 142 contact each other, the width of the lower end of the metal pillar 150 may be formed to be narrower than the width of the second pad 142. As described above, similar to the width of the first opening 1710, the width of the second opening 1720 formed in the second solder resist layer 172 may also have various widths, for example, the width of the second opening 1720 may be wider than the width of the second pad 142, so that the width of the metal pillar 150 may be formed to be wider than the width of the second pad 142.

[0049] The printed circuit board according to the example may further include a first surface treatment layer 161 disposed on at least a portion of the first pad 141. The first surface treatment layer 161 may include one metal of nickel (Ni), palladium (Pd), and gold (Au), and may be implemented as a plurality of metal layers, the metal of each metal layer may be any one metal of nickel (Ni), palladium (Pd), and gold (Au). For example, the first surface treatment layer 161 may be at least a portion of an electroless nickel electroless palladium immersion gold (ENEPIG) structure, or may be at least a portion of an electroless nickel immersion gold (ENIG) structure. In this case, the first surface treatment layer 161 may include a gold (Au) plating layer located at its outermost side. The gold (Au) plating layer may be formed by performing electroless plating, and preferably, may be formed by performing displacement plating. The first surface treatment layer 161 may improve adhesion and signal transmission between the first pad 141 and the connecting member. In Figure 3A , it is shown that the first surface treatment layer 161 is implemented as a single layer, but the present disclosure is not limited thereto, and as described above, the first surface treatment layer 161 may be implemented as a plurality of metal layers. However, the plurality of metal layers may not have clear boundaries therebetween.

[0050] The first surface treatment layer 161 may cover at least a portion of the first pad 141. The first surface treatment layer 161 may cover a portion of the first pad 141 exposed through the first opening 1710 of the first solder resist layer 171. In this case, the first surface treatment layer 161 may be provided after the first opening 1710 is formed in the first solder resist layer 171. Therefore, when the shape of the first opening 1710 has the same Figure 3A When the NSMD structure is different from the SMD structure shown in FIG. 1 , the first surface treatment layer 161 may be disposed to cover the side surface of the first pad 141 .

[0051] The first surface finish layer 161 may include a gold (Au) plating layer at the outermost side thereof. Galvanic corrosion may occur in the second pad 142 .

[0052] The printed circuit board according to the example may further include a barrier layer 180 disposed on the first solder resist layer 171. Figure 3A , the barrier layer 180 may be disposed on the lower surface of the first solder resist layer 171, and may cover the inner wall of the first opening 1710 and the first surface treatment layer 161. Since the barrier layer 180 is disposed to cover the first surface treatment layer 161, the first surface treatment layer 161 is not exposed to the outside. That is, since the barrier layer 180 covers the first surface treatment layer 161, galvanic corrosion may be prevented from occurring during a process of pre-treating the second pad 142 before the metal column 150 is disposed. In particular, the barrier layer 180 may cover the outermost gold (Au) plating layer disposed on the first surface treatment layer 161.

[0053] The barrier layer 180 may include an oxide film including an inorganic oxide. The oxide film may be an aluminum oxide film, for example, an oxide film including Al2O3, but the present disclosure is not limited thereto, and may be an oxide film including at least one of Al2O3, TiO2, ZnO, SiO2, etc. The barrier layer 180 may be a coating layer provided using a thin film deposition method such as an atomic layer deposition (ALD) method or a molecular vapor deposition (MVD) method. In this case, a thin oxide film may be provided using a deposition method. As a non-limiting example, the barrier layer 180 may be a film having a thickness of less than 100 nm (for example, a thickness of about 1 nm to about 10 nm). The thickness of the barrier layer 180 may be less than the thickness of the first pad 141, and may be less than the thickness of the first surface treatment layer 161. The barrier layer 180 may have a nanometer-level thickness, while the first pad 141 and the first surface treatment layer 161 may have a micrometer-level thickness. Therefore, the thickness of the barrier layer 180 may be thinner than the thickness of the first pad 141 and the thickness of the first surface treatment layer 161. When the thickness of the barrier layer 180 is thinner than the thickness of the first pad 141 and / or the thickness of the first surface treatment layer 161 , the barrier layer 180 may have excellent step coverage to better achieve the effect of preventing galvanic corrosion.

[0054] Since the barrier layer 180 includes a thin inorganic oxide film, the first pad 141 and the first surface treatment layer 161 can be electrically disconnected from other components connected to the lower part of the printed circuit board. For example, when the printed circuit board is mounted on the main board through the connection metal, the barrier layer 180 can be positioned between the first pad 141 and the first surface treatment layer 161 and the connection metal. However, when the oxide film included in the barrier layer 180 includes a metal oxide, a connection metal including a metal material having the same element as that of the metal oxide of the barrier layer 180 can be used. For example, when the barrier layer 180 includes Al2O3, a connection metal including aluminum (Al) can be selected. In this case, in the operation of setting the connection metal, the aluminum (Al) element in Al2O3 of the barrier layer 180 can diffuse, so a portion of the oxide film of the barrier layer 180 is removed from the portion of the barrier layer 180 that contacts the connection metal. As a result, the first pad 141 and the first surface treatment layer 161 can be electrically connected to other components through the connection metal. Therefore, in the case where the printed circuit board is electrically connected to other components such as a main board through a connecting metal, even if the material constituting the barrier layer 180 is not identified in the area where the connecting metal and the barrier layer 180 contact each other, such a phenomenon is caused by the above-mentioned diffusion and therefore also falls within the scope of the present disclosure.

[0055] The printed circuit board according to the example may further include a metal column 150 disposed on at least a portion of the second pad 142. The metal column 150 may be disposed on the second pad 142 to pass through at least a portion of the second solder resist layer 172. The metal column 150 may include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), lead (Pb), titanium (Ti) and / or an alloy thereof. Preferably, the metal material may include copper (Cu), but the present disclosure is not limited thereto. The metal column 150 may be used to mount electronic components and chips, and may be a component that protrudes to facilitate smooth connection when the electronic components and chips are mounted on the second pad 142. Depending on the design of the second pad 142, the metal column 150 may perform various functions. The metal column 150 may electrically exchange signals with the second pad 142.

[0056] When the second pads 142 require a high-density fine pitch to mount a semiconductor chip or the like, the spacing between the second pads 142 and / or the spacing between the metal pillars 150 can be reduced. Since the metal pillars 150 are disposed on the second pads 142, even when a semiconductor chip having a fine pitch is mounted, a short circuit is less likely to occur in the connection member 400 disposed between the semiconductor chip and the metal pillars 150, and a defect of detachment of the semiconductor chip can be reduced. In addition, since the metal pillars 150 are disposed on the second pads 142, adhesion can be ensured by the metal pillars 150 rather than a structure in which the connection member 400 is directly disposed on the second pads 142, thereby improving the reliability of the printed circuit board.

[0057] The metal pillar 150 may be disposed using one of SAP, MSAP, TT process, and subtractive process, but the present disclosure is not limited thereto and may be disposed using other methods available to those skilled in the art.

[0058] The printed circuit board according to the example may further include a second surface treatment layer 162 disposed on at least a portion of the metal pillar 150. The second surface treatment layer 162 may include one metal of nickel (Ni), palladium (Pd), and gold (Au), and a plurality of layers including the above metals may be implemented. For example, the second surface treatment layer 162 may be at least a portion of an electroless nickel electroless palladium immersion gold (ENEPIG) structure, or may be at least a portion of an electroless nickel immersion gold (ENIG) structure. The second surface treatment layer 162 is not limited thereto, and may include an organic solderability preservative (OSP) structure including an organic material. The second surface treatment layer 162 may improve adhesion and signal transmission between the metal pillar 150 and the connecting member. Figure 3A , it is shown that the second surface treatment layer 162 is implemented as a single layer, but the present disclosure is not limited thereto, and as described above, the second surface treatment layer 162 may be implemented as a plurality of metal layers.

[0059] The second surface treatment layer 162 may cover at least a portion of the metal pillar 150. Figure 3A , the second surface treatment layer 162 is shown to cover the upper surface of the metal pillar 150 , but is not necessarily limited thereto, and may be provided to further cover the exposed side surface of the metal pillar 150 .

[0060] The printed circuit board according to the example may further include a connection structure 200 and an adhesive layer 210. The connection structure 200 may be connected to an electronic component such as a semiconductor chip. For example, the connection structure 200 may have a bridge structure. The connection structure 200 may include a body having a pattern implemented on an insulating material, and may include a connection portion 201 for connecting to the wiring portion 100. The connection structure 200 may be an organic substrate, or may be a silicon bridge having a circuit implemented on a silicon wafer. The present disclosure is not limited thereto, and the connection structure 200 may be a single semiconductor chip embedded in the wiring portion 100 of the printed circuit board.

[0061] The connection structure 200 may be disposed in a cavity passing through at least a portion of the second insulating layer 112 and may be embedded in the second insulating layer 112. The connection structure 200 may further include an adhesive layer 210 so that the connection structure 200 is installed in the cavity. The structure of the connection structure 200 and the installation method of the connection structure 200 may be a structure and an installation method that can be used by those skilled in the art.

[0062] Reference Figure 3B The printed circuit board according to the example may further include: semiconductor chips 301 and 302 disposed on the metal pillar 150 ; and a connection member 400 connecting the metal pillar 150 and the semiconductor chips 301 and 302 to each other.

[0063] Semiconductor chips 301 and 302 may be integrated circuits (ICs) in which hundreds to millions of circuits are integrated into a single chip. Each of the ICs may be a processor chip, specifically, an application processor (AP), such as a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, but the present disclosure is not limited thereto. For example, each of the ICs may be: a logic chip, such as a field programmable gate array (FPGA), an analog-to-digital converter, an application specific integrated circuit (ASIC), or a memory controller (MC) chip; or each of the ICs may be: a memory chip, such as a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, a phase change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, a resistive random access memory (RRAM) chip, an electrically erasable programmable read-only memory (EEPROM) chip, or a high bandwidth memory (HBM) chip. The above chips may be provided in combination with each other.

[0064] Semiconductor chips 301 and 302 may include a body and a connection pad. The surface of semiconductor chips 301 and 302 on which connection pads for connecting to metal pillars 150 are provided may be an effective surface, and the surface of semiconductor chips 301 and 302 opposite to the effective surface may be an invalid surface, but the present disclosure is not limited thereto. For example, electrical connection may be performed by both the effective surface and the invalid surface. In some cases, semiconductor chips 301 and 302 may have a three-dimensional structure. Semiconductor chips 301 and 302 may be formed based on an effective wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as a matrix material included in the body. Various circuits may be formed in semiconductor chips 301 and 302, and at least some of the above circuits may be connected to the connection pads.

[0065] The connecting member 400 may be made of a conductive material (e.g., solder), but the material of the connecting member 400 is not particularly limited thereto. In addition, the connection method of the connecting member 400 is not limited thereto, and may include a pad, a solder ball, a pin, etc. In addition, the connecting member 400 may be made of a multilayer or a single layer. When made of a multilayer, the connecting member 400 may include a copper column and solder. When made of a single layer, the connecting member 400 may include tin-silver solder or copper, but the present disclosure is not limited thereto.

[0066] exist Figure 3B , it is shown that two semiconductor chips 301 and 302 are arranged on a printed circuit board, but the present disclosure is not limited thereto. In particular, it is shown that the semiconductor chips 301 and 302 are connected to each other in a die-to-die manner, and the connection structure 200 is interposed between the semiconductor chips 301 and 302, but the present disclosure is not necessarily limited thereto. The number and arrangement of the semiconductor chips 301 and 302, the number and arrangement of the connection members 400, and the distance between the connection members 400 are not specifically limited, and can be fully modified by those skilled in the art according to their design.

[0067] The printed circuit board according to the example is not limited to Figure 3A and Figure 3B The components shown in the figure may also include other components in some cases. That is, the printed circuit board may also include components that can be used by those skilled in the art.

[0068] Figure 4A and Figure 4B is a schematic cross-sectional view of a printed circuit board according to another example.

[0069] Reference Figure 4A and Figure 4B In a printed circuit board according to another example, the barrier layer 180 may have a different arrangement compared to the printed circuit board according to the example.

[0070] The barrier layer 180 of the printed circuit board according to another example may not be disposed in the first opening 1710, and may not be disposed on the first surface treatment layer 161. This may be because: after the operation of disposing the metal pillar 150 using the barrier layer 180 to prevent galvanic corrosion, an operation of removing a portion of the barrier layer 180 is performed. The operation of performing the removal of a portion of the barrier layer 180 may be: performing an operation (such as dry etching) of selectively removing a portion of the barrier layer 180 so that the barrier layer 180 does not cover the first opening 1710 and the first surface treatment layer 161. The barrier layer 180 may include an oxide film. Therefore, in the case where the barrier layer 180 is not disposed on the first surface treatment layer 161, when the printed circuit board and other components are combined with each other, the first pad 141 can be more easily connected to other components through the first surface treatment layer 161.

[0071] Here, in the final product of the printed circuit board, those skilled in the art may choose to retain the entire barrier layer 180 or remove at least a portion of the barrier layer 180 according to needs (eg, the need for electrical connection with external components). Figure 3A and 3B As shown in FIG. 1 , in the final product of the printed circuit board, the barrier layer 180 covers the lower surface of the first solder resist layer 171, the inner wall of the first opening 1710, and the lower surface of the first surface treatment layer 161. Figure 4A and 4B As shown in , in the final product of the printed circuit board, the barrier layer 180 covers the lower surface of the first solder resist layer 171, but does not cover the inner wall of the first opening 1710 and the first surface treatment layer 161. For example, although not shown, in the final product of the printed circuit board, the barrier layer 180 covers at least a portion of the inner wall of the first opening 1710 and / or at least a portion of the first surface treatment layer 161.

[0072] The configuration of the printed circuit board according to the example (except for the arrangement of the barrier layer 180 ) may be applied to the printed circuit board according to another example, and thus repeated descriptions thereof will be omitted.

[0073] Method for manufacturing printed circuit board Figures 5 to 15 is a schematic cross-sectional view of a method of manufacturing a printed circuit board according to an example.

[0074] The method of manufacturing a printed circuit board according to an example may include an operation of preparing a wiring portion 100, an operation of disposing a first solder resist layer 171 on a lower side of the wiring portion 100, an operation of disposing a second solder resist layer 172 on an upper side of the wiring portion 100, an operation of disposing a first opening 1710 in the first solder resist layer 171 so that at least a portion of the first pad 141 is exposed, an operation of disposing a first surface treatment layer 161 on the exposed portion of the first pad 141, an operation of disposing a barrier layer 180 on the first solder resist layer 171, and an operation of disposing a metal pillar 150 on the second pad 142. In this case, the method of manufacturing a printed circuit board according to an example may not include an operation of removing the barrier layer 180, and the barrier layer 180 may remain on the first solder resist layer 171 in the printed circuit board.

[0075] Reference Figure 5 , the wiring portion 100 may include one or more insulating layers 110, one or more wiring layers 120 disposed on and / or in the one or more insulating layers 110, a first pad 141 disposed on the lowest insulating layer in the one or more insulating layers 110, and a second pad 142 disposed on the highest insulating layer in the one or more insulating layers 110. The operation of preparing the wiring portion 100 may include: an operation of disposing the first wiring layer 121 on the first insulating layer 111; and an operation of disposing the second insulating layer 112 on the first insulating layer 111 and disposing the second wiring layer 122. The operation of preparing the wiring portion 100 may also include: an operation of disposing the first pad 141 and the second pad 142 on the second insulating layer 112 disposed on the outermost side of the one or more insulating layers 110, respectively. In this case, the operation of disposing the insulating layer 110 and the wiring layer 120 may be performed using a known deposition process. In addition, the operation of preparing the wiring portion 100 may further include an operation of forming a via layer 130 in one or more insulating layers 110 , for example, an operation of forming a first via layer 131 in the first insulating layer 111 and an operation of forming a second via layer 132 in the second insulating layer 112 .

[0076] The method of manufacturing a printed circuit board according to an example may further include forming a cavity through at least a portion of the second insulating layer 112 , attaching and mounting the connection structure 200 using the adhesive layer 210 , and embedding the connection structure 200 in the second insulating layer 112 , but the present disclosure is not necessarily limited thereto.

[0077] The method may further include: an operation of providing a first solder resist layer 171 on the lower side of the wiring portion 100, and an operation of providing a second solder resist layer 172 on the upper side of the wiring portion 100. The solder resist layers may be provided at the same time, but the present disclosure is not necessarily limited thereto. Any known method of providing the first solder resist layer 171 and the second solder resist layer 172 may be used without limitation.

[0078] Reference Figure 6 , an operation of forming a first opening 1710 in the first solder resist layer 171 may be performed. The first opening 1710 may be formed on the first pad 141, and at least a portion of the first pad 141 may be exposed through the first opening 1710. The shape of the first opening 1710 is not limited to Figure 6 , and may have a NSMD structure as described above in conjunction with the printed circuit board. Any known method of forming the first opening 1710 in the first solder resist layer 171 may be used without limitation.

[0079] Reference Figure 7 , an operation of disposing a first surface treatment layer 161 on at least a portion of the first pad 141 may be performed. The first surface treatment layer 161 including a plurality of metal layers may be formed by repeatedly performing electroless plating as described above in conjunction with the printed circuit board, and the first surface treatment layer 161 may include a gold (Au) plating layer located at the outermost side thereof.

[0080] Reference Figure 8 , an operation of disposing a barrier layer 180 on the first solder resist layer 171 may be performed. The operation of disposing the barrier layer 180 may be performed using a thin film deposition method such as an ALD method or an MVD method. The deposition method may be a method having excellent step coverage, so that the barrier layer 180 may cover the lower surface of the first solder resist layer 171, the inner wall of the first opening 1710, and the first surface treatment layer 161.

[0081] Reference Fig. 9 , an operation of setting the second opening 1720 in the second solder resist layer 172 may be performed. In this case, the second pad 142 may be exposed through the second opening 1720. The method of forming the opening in the second solder resist layer 172 may be performed using UV laser processing or the like, but the present disclosure is not necessarily limited thereto, and any known method of forming the second opening 1720 in the second solder resist layer 172 may be used without limitation. In this case, the second opening 1720 may be set using a physical method, and may have a downwardly tapered shape, but the present disclosure is not necessarily limited thereto.

[0082] Subsequently, a pretreatment may be performed to set the metal pillar 150. As a pretreatment, a desmear process for removing the residue on the second solder resist layer 172 may be performed, and soft etching may be performed to process the exposed surface of the second pad 142. When the printed circuit board is exposed to an etching solution to perform soft etching, an oxidation / reduction reaction may occur between the second pad 142 including copper (Cu) and the first surface treatment layer 161 including gold (Au), so that galvanic corrosion may occur in the second pad 142. However, the method of manufacturing a printed circuit board according to an example may include an operation of providing a barrier layer 180 to cover the first surface treatment layer 161 before performing pretreatment to set the metal pillar 150, so that the first surface treatment layer 161 may not be exposed to the etching solution. Therefore, the second pad 142 may be protected from galvanic corrosion. As described above in conjunction with the printed circuit board, the metal material included in the second pad 142 and the metal material included in the first surface treatment layer 161 are not limited to copper (Cu) and gold (Au), respectively.

[0083] Reference Figures 10 to 15 , an operation of disposing a metal pillar 150 and a second surface treatment layer 162 on the second pad 142 may be performed.

[0084] Reference Fig.10 , a seed layer 150' may be provided. The seed layer 150' may be provided by performing electroless plating, and may be provided by performing chemical copper plating, but the present disclosure is not limited thereto, and may also be provided by performing a sputtering method.

[0085] Reference Fig.11 , a dry film resist DFR may be provided. Before performing plating, a dry film resist DFR may be provided.

[0086] Reference Fig.12 , a plating layer 150 ″ may be provided. The plating layer 150 ″ may be provided by performing electroplating using the seed layer 150 ′.

[0087] Reference Fig.13 , a second surface treatment layer 162 may be disposed on the plating layer 150 ″.

[0088] Reference Fig.14 , the dry film resist DFR can be removed.

[0089] Reference Fig.15 , the metal pillar 150 may be completed by removing a portion of the seed layer 150 ′.

[0090] The operation of providing the metal pillar 150 is not limited thereto and can be provided using a method that can be used by those skilled in the art. The operation of providing the metal pillar 150 and the second surface treatment layer 162 is not necessarily limited to Figures 10 to 15In some cases, the operation of providing the second surface treatment layer 162 may also be performed after the metal pillar 150 is completed. In this case, the operation of providing the second surface treatment layer 162 may be performed last. Fig.13 The corresponding operation.

[0091] The method of manufacturing a printed circuit board according to the example is not necessarily limited to Figures 5 to 15 The method shown in , and can be appropriately modified and changed as needed.

[0092] The method of manufacturing a printed circuit board according to another example may further include an operation of removing at least a portion of the barrier layer 180 to expose the first surface treatment layer 161. Preferably, the operation of removing at least a portion of the barrier layer 180 may be performed after the operation of providing the metal pillar 150 and the second surface treatment layer 162, but the present disclosure is not necessarily limited thereto.

[0093] As used herein, a cross-sectional shape may refer to the cross-sectional shape of an object when the object is cut vertically, or the cross-sectional shape of an object when the object is viewed from a side view. In addition, a planar shape may refer to the shape of an object when the object is cut horizontally, or the planar shape of an object when the object is viewed from a top view or an upward view.

[0094] As used herein, for convenience, upper side, upper part, upper surface, etc. are used to refer to the direction toward the surface on which the electronic components can be mounted based on the cross section of the drawings, and lower side, lower part, lower surface, etc. are used to refer to the opposite direction. However, the above directions are defined for the convenience of description. Therefore, it should be understood that the scope of the claims is not specifically limited by the above directions.

[0095] As used herein, the term "connection" may refer not only to "direct connection" but also to "indirect connection" via an adhesive layer or the like. The term "electrical connection" may include a case where components are "physically connected" and a case where components are "not physically connected." In addition, the terms "first," "second," and the like may be used to distinguish a component from another component, and may not limit the order and / or importance associated with the components, etc. In some cases, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the example embodiments.

[0096] As used herein, the term "substantially" may include a process error, positional deviation, measurement error, etc. that occurs in a manufacturing process. For example, "substantially vertical" may include not only "completely vertical" but also "approximately vertical". In addition, "substantially coplanar" may include not only "completely coplanar" but also "approximately coplanar".

[0097] As used herein, the same insulating material may refer not only to the same insulating material, but also to the same type of insulating material. Therefore, the composition of the insulating material may be substantially the same, but its specific composition ratio may vary slightly.

[0098] As used herein, the terms "exemplary embodiment" and "example" are provided to emphasize specific features, structures, or characteristics, and do not necessarily refer to the same exemplary embodiment. In addition, specific features or characteristics may be combined in any suitable manner in one or more exemplary embodiments. For example, unless described as being contrary to or inconsistent with content in other exemplary embodiments, content described in a particular exemplary embodiment may also be used in other exemplary embodiments even if not described in other exemplary embodiments.

[0099] The terms used herein are intended to describe only particular example embodiments, and the present disclosure is not limited thereby.As used herein, unless the context clearly indicates otherwise, the singular forms are intended to include the plural forms as well.

[0100] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: A wiring portion, comprising one or more insulating layers, one or more wiring layers respectively arranged on the one or more insulating layers and / or in the one or more insulating layers, a first pad arranged on a lowermost insulating layer among the one or more insulating layers, and a second pad arranged on an uppermost insulating layer among the one or more insulating layers; a first solder resist layer provided on a lower side of the wiring portion to cover a portion of the first pad, the first solder resist layer having a first opening located on the first pad; a second solder resist layer provided on an upper side of the wiring portion to cover a portion of the second pad; a first surface treatment layer disposed on at least a portion of the first pad; as well as a barrier layer disposed on the first solder resist layer, Wherein, the thickness of the barrier layer is smaller than the thickness of the first pad.

2. The printed circuit board according to claim 1, wherein: The barrier layer is disposed on a lower surface of the first solder resist layer.

3. The printed circuit board according to claim 2, wherein: The barrier layer covers at least a portion of an inner wall of the first opening and / or at least a portion of the first surface treatment layer.

4. The printed circuit board according to claim 1, wherein: The first solder resist layer covers a portion of a lower surface of the first pad.

5. The printed circuit board according to claim 1, wherein The second solder resist layer has a second opening provided on the second pad.

6. The printed circuit board according to claim 5, further comprising: A metal column is disposed in the second opening, and the metal column is disposed on at least a portion of the second pad.

7. The printed circuit board according to claim 6, further comprising: The second surface treatment layer is arranged on the metal column.

8. The printed circuit board according to claim 6, further comprising: A first semiconductor chip is disposed on the metal pillar; as well as A connecting member connects the metal pillar and the first semiconductor chip to each other.

9. The printed circuit board according to claim 1, wherein: The thickness of the barrier layer is smaller than the thickness of the first surface treatment layer.

10. The printed circuit board according to claim 9, wherein: The thickness of the barrier layer is less than 100 nm.

11. A printed circuit board, comprising: A wiring portion, comprising one or more insulating layers, one or more wiring layers respectively arranged on the one or more insulating layers and / or in the one or more insulating layers, a first pad arranged on a lowermost insulating layer among the one or more insulating layers, and a second pad arranged on an uppermost insulating layer among the one or more insulating layers; a first solder resist layer provided on a lower side of the wiring portion to cover a portion of the first pad, the first solder resist layer having a first opening located on the first pad; a second solder resist layer provided on an upper side of the wiring portion to cover a portion of the second pad; a first surface treatment layer disposed on at least a portion of the first pad; as well as a barrier layer disposed on the first solder resist layer, Wherein, the barrier layer comprises an inorganic oxide film.

12. The printed circuit board according to claim 11, wherein The barrier layer includes at least one of Al2O3, TiO2, ZnO and SiO2.

13. The printed circuit board according to claim 11, wherein The barrier layer is disposed on a lower surface of the first solder resist layer.

14. The printed circuit board according to claim 13, wherein: The barrier layer covers at least a portion of an inner wall of the first opening and / or at least a portion of the first surface treatment layer.

15. The printed circuit board according to claim 12, further comprising: The metal column is disposed on at least a portion of the second pad.

16. The printed circuit board according to claim 11, wherein The thickness of the barrier layer is smaller than the thickness of the first pad.

17. The printed circuit board according to claim 11, wherein The second solder resist layer has a second opening provided on the second pad.

18. The printed circuit board according to claim 11, wherein The first solder resist layer and the second solder resist layer each include an insulating resin and a filler dispersed in the insulating resin.

19. The printed circuit board according to claim 11, wherein The first solder resist layer and the second solder resist layer each include a photosensitive insulating resin.

20. A printed circuit board, comprising: A wiring portion, comprising one or more insulating layers, one or more wiring layers respectively arranged on the one or more insulating layers and / or in the one or more insulating layers, a first pad arranged on a lowermost insulating layer among the one or more insulating layers, and a second pad arranged on an uppermost insulating layer among the one or more insulating layers; a first solder resist layer provided on a lower side of the wiring portion to cover a portion of the first pad, the first solder resist layer having a first opening located on the first pad; a second solder resist layer provided on an upper side of the wiring portion to cover a portion of the second pad; a first surface treatment layer disposed on at least a portion of the first pad; as well as The barrier layer is disposed on the first solder resist layer.

21. The printed circuit board according to claim 20, wherein The barrier layer is a film with a thickness of less than 100 nm.

22. The printed circuit board according to claim 21, wherein The thickness of the barrier layer is greater than 1 nm and less than 10 nm.

23. A method for manufacturing a printed circuit board, comprising: preparing a wiring portion, the wiring portion comprising one or more insulating layers, one or more wiring layers respectively arranged on the one or more insulating layers and / or in the one or more insulating layers, a first pad arranged on a lowermost insulating layer among the one or more insulating layers, and a second pad arranged on an uppermost insulating layer among the one or more insulating layers; forming a first solder resist layer and a second solder resist layer on a lower side and an upper side of the wiring portion, respectively; forming a first opening in the first solder resist layer to expose at least a portion of the first pad; forming a first surface treatment layer on the at least a portion of the first pad; providing a barrier layer on the first solder resist layer; forming a second opening in the second solder resist layer to expose at least a portion of the second pad; as well as A metal pillar is formed on the at least a portion of the second pad.

24. The method for manufacturing a printed circuit board according to claim 23, further comprising: After the step of forming the metal pillar, a portion of the barrier layer is removed to expose the first surface treatment layer.

Images