Corrugated capacitor

Abstract

The embodiment of the invention relates to a corrugated capacitor. In an example, an IC (100) includes a first corrugated conductive layer (124), a second corrugated conductive layer (128), and a corrugated dielectric layer (126). The first corrugated conductive layer (124) and the second corrugated conductive layer (128) are over a semiconductor substrate (102). The corrugated dielectric layer (126) is located between the first corrugated conductive layer (124) and the second corrugated conductive layer (128). For a given lateral footprint of the capacitor, various examples may achieve a larger surface area of a respective plate of the capacitor.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to ripple capacitors. Background Art

[0002] Capacitors have a wide range of applications, such as use in combination with other components in integrated circuits. Capacitors used to implement large capacitance occupy a large area on the die. This increases the die area and / or may require each die to be larger, thereby reducing the number of dies that can be manufactured from a single wafer. Summary of the invention

[0003] This summary is provided to introduce a brief selection of the disclosed concepts in a simplified form, which concepts are further described in the following detailed description including the provided figures. Various disclosed devices and methods can be advantageously applied in the context of semiconductor processing, where capacitors can be manufactured in integrated circuits (ICs). Some examples described herein can be applied to capacitor stacks for manufacturing corrugated capacitors in ICs. Although such examples can be expected to achieve a larger capacitor plate surface area relative to the lateral footprint of the capacitor, no specific result is required unless explicitly recited in a particular claim.

[0004] The example described herein is an IC. The IC includes a first corrugated conductive layer, a second corrugated conductive layer and a corrugated dielectric layer. The first corrugated conductive layer and the second corrugated conductive layer are located above a semiconductor substrate. The corrugated dielectric layer is located between the first corrugated conductive layer and the second corrugated conductive layer.

[0005] Another example described herein is an IC. The IC includes a parallel plate capacitor located above a semiconductor substrate. The parallel plate capacitor includes a first corrugated conductive layer, a second corrugated conductive layer, and a corrugated dielectric layer. The first corrugated conductive layer and the second corrugated conductive layer are located above the semiconductor substrate. The corrugated dielectric layer is located between the first corrugated conductive layer and the second corrugated conductive layer.

[0006] Another example described herein is a method of manufacturing an IC. A corrugated dielectric structure is formed over a semiconductor substrate. A first conductive layer is conformally formed over the corrugated dielectric structure. The first conductive layer includes a corrugated upper surface. A dielectric layer is conformally formed over the first conductive layer. A second conductive layer is conformally formed over the dielectric layer.

[0007] The foregoing summary of the invention has been quite extensively summarized various features of examples of the present disclosure so that the following detailed description may be better understood. Additional features and advantages of such examples will be described below. The described examples may be readily used as a basis for modifying or designing other examples within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to understand the above features in detail, reference is made to the following detailed description in conjunction with the accompanying drawings.

[0009] Figure 1 is a cross-sectional view of an integrated circuit (IC) including a ripple capacitor according to some examples.

[0010] Figure 2 is a cross-sectional view of an IC including a ripple capacitor according to some examples.

[0011] Figure 3 is a cross-sectional view of an IC including a ripple capacitor according to some examples.

[0012] Figure 4 , 5 6 are corresponding layout views of the surface of a corrugated capacitor according to some examples.

[0013] Figure 7 , 8 , 9, 10, 11, 12, 13 and 14 are based on some examples Figure 1 Cross-sectional views of an IC during corresponding manufacturing stages.

[0014] Fig.15 , 16 , 17, 18, 19, 20 and 21 are based on some examples Figure 3 Cross-sectional views of an IC during corresponding manufacturing stages.

[0015] The drawings and accompanying detailed description are provided for understanding the features of the various examples and do not limit the scope of the appended claims. The examples illustrated in the drawings and described in the accompanying detailed description can be easily used as a basis for modifying or designing other examples within the scope of the appended claims. Where possible, the same reference numerals may be used to refer to the same elements that are common in the drawings. The drawings are drawn to clearly illustrate the relevant elements or features and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0016] Various features are described below with reference to the drawings. The illustrated examples may not have all aspects or advantages shown. An aspect or advantage described in conjunction with a particular example is not necessarily limited to that example and may be practiced in any other example, even if not so illustrated or not explicitly described. In addition, the methods described herein may be described in a particular order of operations, but other methods according to other examples may be implemented with various other orders of more or fewer operations (e.g., including different serial or parallel executions of various operations).

[0017] The present disclosure relates to a corrugated capacitor in an integrated circuit (IC). In some examples, the IC includes a corrugated dielectric structure located above a semiconductor substrate. A first conductive layer is conformally located above the corrugated dielectric structure. A dielectric layer is conformally located above the first conductive layer. A second conductive layer is conformally located above the dielectric layer. For a given lateral footprint of the capacitor, various examples can achieve a larger surface area of ​​the corresponding plates of the capacitor. A larger surface area can result in a larger capacitance of the capacitor that can be achieved for a given lateral footprint. Other benefits or advantages can be achieved through various examples.

[0018] Figure 1 is a cross-sectional view of an IC 100 including a capacitor according to some examples. The capacitor in IC 100 is or includes a ripple capacitor. Generally, a ripple capacitor can have an effective capacitor area (eg, from which a capacitance value is derived) that is larger than a lateral footprint of the ripple capacitor.

[0019] IC 100 includes semiconductor substrate 102 having top surface 103. Semiconductor substrate 102 may be or include a bulk wafer, a semiconductor-on-insulator (SOI) substrate, etc. Semiconductor substrate 102 may be or include any semiconductor material, and may include bulk material (e.g., bulk silicon) and / or one or more epitaxial layers of semiconductor material. IC 100 may include one or more active devices (e.g., transistor 104) formed in, on, and / or over top surface 103 of semiconductor substrate 102.

[0020] A first interconnect dielectric layer 106 is located above the semiconductor substrate 102. The first interconnect dielectric layer 106 may be a pre-metal dielectric (PMD), an inter-layer dielectric (ILD), an inter-metal dielectric (IMD), or the like. The first interconnect dielectric layer 106 may include a conformal dielectric layer (e.g., an etch stop layer) located above (e.g., possibly on) the top surface 103 of the semiconductor substrate 102 and the active device (e.g., the transistor 104), and may include a dielectric layer located above the conformal dielectric layer. In some examples, the conformal dielectric layer may be or include silicon nitride, silicon oxynitride, or the like, or a combination thereof, and the dielectric layer may be or include silicon oxide (e.g., phosphosilicate glass (PSG) or tetraethyl orthosilicate (TEOS) oxide), or the like, or a combination thereof.

[0021] Conductive contacts 108, 110 pass through the first interconnect dielectric layer 106. The conductive contacts 108, 110 contact active regions of transistors 104 in the semiconductor substrate 102. For example, the conductive contact 108 may contact a source region of the transistor 104 in the semiconductor substrate 102, and the conductive contact 110 may contact a drain region of the transistor 104 in the semiconductor substrate 102. The conductive contacts 108, 110 may each include one or more barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or a combination thereof) conformally located in respective openings through the first interconnect dielectric layer 106, and a fill metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc., or a combination thereof) located above and / or on the (one or more) barrier and / or adhesion layers.

[0022] Conductive layer 114 and conductive lines 116, 118 are located over first interconnect dielectric layer 106. Conductive line 116 is located over and contacts conductive contact 108, and conductive line 118 is located over and contacts conductive contact 110. In some examples, conductive layer 114 and conductive lines 116, 118 are located in an interconnect metal layer of an interconnect structure of IC 100. Conductive layer 114 and conductive lines 116, 118 may each include one or more barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or a combination thereof) located over first interconnect dielectric layer 106, and a fill metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc., or a combination thereof) located over and / or on the (one or more) barrier and / or adhesion layers.

[0023] The corrugated dielectric structure 122 is located above at least a portion of the conductive layer 114. The conductive layer 114 extends laterally from the corrugated dielectric structure 122. The corrugated dielectric structure 122 has a corrugated upper surface with crests and troughs. The upper surface of the corrugated dielectric structure 122 is away from the conductive layer 114. In some examples, the crests and troughs of the upper surface of the corrugated dielectric structure 122 along a lateral direction (e.g., one lateral direction or two lateral directions) are periodic. More specifically, as Figure 1 , the upper surface of the corrugated dielectric structure 122 has a curved shape or follows a curved wave function in the lateral direction, such as being similar to or following a sine wave function. The upper surface of the corrugated dielectric structure 122 may be discontinuous (e.g., at a valley), and / or the corrugated dielectric structure 122 may have one or more openings therethrough to the conductive layer 114. In some examples, the corrugated dielectric structure 122 may be or include silicon oxide (e.g., PSG or TEOS oxide), silicon nitride, silicon oxynitride, etc., or a combination thereof.

[0024] The capacitor stack is located above the corrugated dielectric structure 122 (e.g., located above the upper surface of the corrugated dielectric structure 122). The capacitor stack includes a lower capacitor conductive layer 124 located above the corrugated dielectric structure 122, a capacitor dielectric layer 126 located above the lower capacitor conductive layer 124, and an upper capacitor conductive layer 128 located above the capacitor dielectric layer 126. The lower capacitor conductive layer 124 is conformally located above and on the upper surface of the corrugated dielectric structure 122. The capacitor dielectric layer 126 is conformally located above and on the upper surface of the lower capacitor conductive layer 124, and the upper capacitor conductive layer 128 is conformally located above and on the upper surface of the capacitor dielectric layer 126. The conformal nature of the capacitor conductive layers 124, 128, and the capacitor dielectric layer 126 generally causes the corrugation structure of the corrugated dielectric structure 122 to propagate through the capacitor conductive layers 124, 128, and the capacitor dielectric layer 126. Each of the capacitor conductive layers 124, 128 and the capacitor dielectric layer 126 has a respective upper surface, at least a portion of which generally replicates the upper surface of the corrugated dielectric structure 122, which in some instances may result in, for example, the respective upper surface being periodic in a lateral direction and / or having a curved shape or following a curved wave function, such as being similar to or following a sinusoidal wave function.

[0025] The respective upper surfaces of the capacitor conductive layers 124, 128 and the capacitor dielectric layer 126 have peaks 150 and valleys 152 that correspond to the peaks and valleys of the upper surface of the corrugated dielectric structure 122. Thus, the capacitor conductive layers 124, 128 and the capacitor dielectric layer 126 can each have a corrugated structure and a corrugated upper surface and can at least partially form the corrugated capacitor 120. The upper surfaces of the capacitor conductive layers 124, 128 and the capacitor dielectric layer 126 have respective peak-to-valley heights 160 ( Figure 1 128 for the upper surface of the upper capacitor conductive layer 128). The peak-to-trough height 160 is the height from a valley 152 of a given surface to an adjacent peak 150. In some examples, the peak-to-trough height 160 is at least 50 nm. The capacitor conductive layers 124, 128 and the capacitor dielectric layer 126 may form a parallel plate or parallel film corrugated capacitor.

[0026] Compared to a planar capacitor having the same lateral footprint, the corrugated capacitor 120 permits a greater capacitance based on the area, lateral footprint, of the corrugated capacitor 120. The "lateral footprint" or "lateral area" refers to the area of ​​the IC 100 parallel to the top surface 103 that is covered by the corrugated capacitor 120. The corrugated structure of the surfaces of the capacitor conductive layers 124, 128 has a larger surface area than the lateral footprint of the corrugated structure of the corrugated capacitor 120, which permits the corrugated capacitor 120 to achieve a greater capacitance. In some examples, the respective surface areas of the corrugated portions of the upper surface of the lower capacitor conductive layer 124 and the lower surface of the upper capacitor conductive layer 128 are at least 1.5 times (e.g., at least two or three times) the lateral footprint of the respective corrugated portions of those surfaces on which the corrugated portions are located.

[0027] In the illustrated example, the ripple capacitor 120 is periodic. A period 162 of the ripple capacitor 120 is shown between adjacent peaks 150 of the ripple capacitor 120 (e.g., between corresponding peaks 150 of the upper surface of the capacitor conductive layer 124, 128 and the capacitor dielectric layer 126). In the lateral direction parallel to the top surface 103, throughout the period (e.g., period 162) between adjacent peaks 150, the radius of curvature R of the upper surface of the lower capacitor conductive layer 124 may not be less than 500 nm, may not include a bend with a radius of curvature less than 500 nm, and / or the minimum radius of curvature may be 500 nm. The lower surface of the upper capacitor conductive layer 128 may also have similar characteristics. In such examples, such a geometry may be beneficial to the reliability of the ripple capacitor 120. Too small a radius of curvature of the surface of the capacitor conductive layers 124 , 128 (eg, such as forming an acute angle > 85°) may otherwise generate a large electric field at such points, which may result in a shorter time dependent dielectric breakdown (TDDB).

[0028] Additionally, the smaller period 162 and / or increased peak-to-trough height 160 may increase the surface area of ​​the upper surface of the lower capacitor conductive layer 124 and the lower surface of the upper capacitor conductive layer 128 to increase capacitance. Figure 1 A full width at half maximum (FWHM) 164 is shown, which is the width between the upper surface of the upper capacitor conductive layer 128 (as illustrated) or the lower capacitor conductive layer 124 at a height from the valley 152 (or peak 150) that is half of the peak-to-valley height 160. According to some examples, the ratio of the peak-to-valley height 160 to the FWHM 164 is at least 10%. Increasing this ratio may result in a smaller period and / or an increased peak-to-valley height to increase the capacitance of the ripple capacitor 120.

[0029] In the illustrated example, the upper surface of the corrugated dielectric structure 122 is discontinuous at the valleys, such that the lower capacitor conductive layer 124 contacts the conductive layer 114 at the valleys. Additionally, the lower capacitor conductive layer 124 extends laterally beyond the corrugated dielectric structure 122, wherein the lower capacitor conductive layer 124 is also located above and contacts the conductive layer 114. In the illustrated example, the lower capacitor conductive layer 124, the capacitor dielectric layer 126, and the upper capacitor conductive layer 128 are laterally coextensive, and therefore, the capacitor dielectric layer 126 and the upper capacitor conductive layer 128 also extend laterally beyond the corrugated dielectric structure 122. Respective portions 154 of the lower capacitor conductive layer 124, the capacitor dielectric layer 126, and the upper capacitor conductive layer 128 that extend laterally beyond the corrugated dielectric structure 122 are planar. The conductive layer 114 extends laterally beyond the capacitor conductive layers 124, 128, and the capacitor dielectric layer 126. Conductive layer 114 may include a pad or plate underlying capacitor conductive layers 124 , 128 and capacitor dielectric layer 126 and extending at least laterally coextensively or beyond capacitor conductive layers 124 , 128 and capacitor dielectric layer 126 .

[0030] The capacitor conductive layers 124, 128 may be or include any suitable conductive material, such as metals (including metal alloys), doped semiconductors, metal-semiconductor compounds, and the like, or combinations thereof. Examples include metals such as aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), tantalum (Ta), alloys thereof, metal compounds such as titanium nitride (TiN) and tantalum nitride (TaN), or combinations thereof. Example doped semiconductors include doped silicon (e.g., doped polysilicon), doped silicon germanium, doped germanium, and the like, or combinations thereof. Example metal-semiconductor compounds include silicides (e.g., NiSi, TiSi, and the like), germanides, and the like. The capacitor dielectric layer 126 may be or include silicon oxide, silicon nitride, hafnium oxide, and the like, or combinations thereof.

[0031] The second interconnect dielectric layer 132 is located above the conductive layer 114, the conductive lines 116, 118, the capacitor stack, and the first interconnect dielectric layer 106. The second interconnect dielectric layer 132 may be an ILD, an IMD, or the like. The second interconnect dielectric layer 132 may include a conformal dielectric layer (e.g., an etch stop layer) located above (e.g., possibly located on) the top surface of the first interconnect dielectric layer 106, the conductive layer 114, the conductive lines 116, 118, and the sidewall surfaces and upper surfaces of the upper capacitor conductive layer 128, and the sidewall surfaces of the lower capacitor conductive layer 124 and the capacitor dielectric layer 126. The second interconnect dielectric layer 132 may further include a dielectric layer located above the conformal dielectric layer. In some examples, the conformal dielectric layer may be or include silicon nitride, silicon oxynitride, or the like, or a combination thereof, and the dielectric layer may be or include silicon oxide (e.g., PSG or TEOS oxide), or the like, or a combination thereof.

[0032] Conductive vias 134, 136, 138 extend through the second interconnect dielectric layer 132. Conductive via 134 extends through the second interconnect dielectric layer 132 to the upper capacitor conductive layer 128. Conductive via 136 extends through the second interconnect dielectric layer 132 to the conductive layer 114. Conductive via 138 extends through the second interconnect dielectric layer 132 to the conductive line 116. The ripple capacitor 120 may be electrically connected to the transistor 104 in the circuit through the conductive vias 136, 138. An overlying interconnect metal layer may electrically connect the conductive vias 136, 138. The conductive vias 134, 136, 138 may each include one or more barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or a combination thereof) conformally positioned in respective openings through the second interconnect dielectric layer 132, and a fill metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc., or a combination thereof) positioned above and / or on the (one or more) barrier and / or adhesion layers.

[0033] Additional interconnect dielectric layers and interconnect metal layers may be formed over the second interconnect dielectric layer 132. The first interconnect dielectric layer 106, the second interconnect dielectric layer 132, the additional dielectric layers, and the interconnect metal layers therein may form an interconnect structure. Conductive lines in adjacent interconnect metal layers may be electrically coupled by vias, which may interconnect various devices including the transistor 104 and the ripple capacitor 120 in a circuit. In various examples, the ripple capacitor 120 may be formed at any level of the interconnect structure. For example, any number of interconnect dielectric layers (with corresponding interconnect metal layers) may be located between the semiconductor substrate 102 and the ripple capacitor 120.

[0034] Figure 2 is a cross-sectional view of an IC 200 including a capacitor according to some examples. The capacitor in the IC 200 is or includes Figure 1 The ripple capacitor 120 in FIG. Figure 2 The IC 200 contains Figure 1 Components included in the IC 100 are indicated by the same reference numerals. For the sake of brevity, descriptions of such components are omitted.

[0035] IC 200 includes a conductive layer 214 (similar to Figure 1 Conductive layer 214 is located over first interconnect dielectric layer 106 and conductive contacts 108. In some examples, conductive layer 214 is located in an interconnect metal layer of an interconnect structure of IC 200. Conductive layer 214 may include material(s) as described above with respect to conductive layer 114.

[0036] The corrugated dielectric structure 122 is located above a portion of the conductive layer 214. The conductive layer 214 extends laterally from the corrugated dielectric structure 122 to contact the conductive contacts 108. In the illustrated example, the upper surface of the corrugated dielectric structure 122 is discontinuous at the valleys so that the lower capacitor conductive layer 124 contacts the conductive layer 214 at the valleys. In addition, the lower capacitor conductive layer 124 extends laterally beyond the corrugated dielectric structure 122, wherein the lower capacitor conductive layer 124 is also located above and contacts the conductive layer 214. The conductive layer 214 extends laterally beyond the capacitor conductive layers 124, 128, and the capacitor dielectric layer 126 to contact the conductive contacts 108. The conductive layer 214 may include a pad or plate located below the capacitor conductive layers 124, 128, and the capacitor dielectric layer 126, which pad or plate extends at least laterally coextensively or beyond the capacitor conductive layers 124, 128, and the capacitor dielectric layer 126. In Figure 2 In the illustrated example, conductive layer 214 is directly connected to via 108 , thereby providing a conductive electrical connection to transistor 104 , which at least partially forms a circuit.

[0037] Figure 3 is a cross-sectional view of an IC 300 including a capacitor 320 according to some examples. The capacitor in the IC 300 is or includes a capacitor similar to Figure 1 The ripple capacitor 120 of the ripple capacitor 320. Figure 3 IC 300 contains Figure 1 Components included in the IC 100 are indicated by the same reference numerals. For the sake of brevity, descriptions of such components are omitted.

[0038] The corrugated dielectric structure 322 is located above and on the first interconnect dielectric layer 106. The corrugated dielectric structure 322 may be similar to Figure 1 1. The conductive layer 324 is conformally located above and on the upper surface of the corrugated dielectric structure 322 and extends laterally from the corrugated dielectric structure 322. In some examples, the conductive layer 324 is located in an interconnect metal layer of an interconnect structure of the IC 100 including the conductive lines 116, 118. The conductive layer 324 can be or include the material(s) described above with respect to the conductive layer 114. In some examples, the conductive layer 324 can be located above and in contact with the conductive contacts 108 (e.g., similar to Figure 2 214 in the conductive layer 214). Capacitor dielectric layer 126 is conformally located above and on conductive layer 324, and upper capacitor conductive layer 128 is conformally located above and on capacitor dielectric layer 126.

[0039] In the illustrated example, the capacitor dielectric layer 126 and the upper capacitor conductive layer 128 are laterally coextensive, and the capacitor dielectric layer 126 and the upper capacitor conductive layer 128 extend laterally beyond the corrugated dielectric structure 322. The respective portions of the conductive layer 324, the capacitor dielectric layer 126, and the upper capacitor conductive layer 128 that extend laterally beyond the corrugated dielectric structure 322 are planar. The conductive layer 324 also extends laterally beyond the capacitor dielectric layer 126 and the upper capacitor conductive layer 128.

[0040] In the illustrated example, the capacitor stack includes a conductive layer 324, a capacitor dielectric layer 126, and an upper capacitor conductive layer 128. The capacitor stack is located above the corrugated dielectric structure 322 (eg, located above an upper surface of the corrugated dielectric structure 322).

[0041] The second interconnect dielectric layer 132 is located above the conductive layer 324, the conductive lines 116, 118, the capacitor stack, and the first interconnect dielectric layer 106. Conductive vias 134, 136, 138 extend through the second interconnect dielectric layer 132. Conductive via 136 extends through the second interconnect dielectric layer 132 to the conductive layer 324. In some examples, the ripple capacitor 320 can be electrically connected to the transistor 104 in the circuit through the conductive vias 136, 138. In some examples, the conductive layer 324 can be directly electrically connected to the conductive contact 108 to provide a conductive electrical connection to the transistor 104. Additional interconnect dielectric layers and interconnect metal layers can be formed above the second interconnect dielectric layer 132, which can form an interconnect structure. In various examples, the ripple capacitor 320 can be formed at any level of the interconnect structure.

[0042] Figure 4 is a layout view of a surface 400 of a corrugated capacitor according to some examples. Figure 1 , 2 3 may be along cross section 402. Surface 400 may correspond to any or each of the upper or lower surfaces of lower capacitor conductive layer 124, conductive layer 324, capacitor dielectric layer 126, and upper capacitor conductive layer 128. Additionally, surface 400 may correspond to the upper surface of corrugated dielectric structure 122, 322.

[0043] Surface 400 has crests 410 and troughs 412 that may correspond to crests 150 and troughs 152, respectively. Crests 410 and troughs 412 radiate laterally outward from a center, much like ripples. Surface 400 has a period 422 between adjacent crests 410 (or adjacent troughs 412), which may correspond to period 162. Around the periphery, surface 400 has a planar portion 414, which may correspond to planar portion 154. As shown by Figure 4As shown in FIG. 4A and FIG. 4B , the corrugated capacitor can be periodic in two lateral directions. The period 422 can be along any lateral radial direction starting from the center of the surface 400 .

[0044] Figure 5 is a layout view of a surface 500 of a corrugated capacitor according to some examples. Figure 1 , 2 3 may be along cross section 502. Surface 500 may correspond to any or each of the upper or lower surfaces of lower capacitor conductive layer 124, conductive layer 324, capacitor dielectric layer 126, and upper capacitor conductive layer 128. Additionally, surface 500 may correspond to the upper surface of corrugated dielectric structure 122, 322.

[0045] Surface 500 has peaks 510 and troughs 512 that may correspond to peaks 150 and troughs 152, respectively. Peaks 510 may form or be individual hillocks, wherein peaks 410 form a lateral array. Surface 500 has a period 522 between adjacent peaks 510 (or adjacent troughs 512), which may correspond to period 162. Around the periphery, surface 500 has a planar portion 514, which may correspond to planar portion 154. As shown by Figure 5 As shown in surface 500 of FIG. 5 , the corrugated capacitor can be periodic in two lateral directions. Period 522 can be along two or more lateral directions.

[0046] Figure 6 is a layout view of a surface 600 of a corrugated capacitor according to some examples. Figure 1 , 2 3 may be along cross section 602. Surface 600 may correspond to any or each of the upper or lower surfaces of lower capacitor conductive layer 124, conductive layer 324, capacitor dielectric layer 126, and upper capacitor conductive layer 128. Additionally, surface 600 may correspond to the upper surface of corrugated dielectric structure 122, 322.

[0047] Surface 600 has peaks 610 and troughs 612 that may correspond to peaks 150 and troughs 152, respectively. Surface 600 has a period 622 between adjacent peaks 610 (or adjacent troughs 612), which may correspond to period 162. At the periphery, surface 600 has a planar portion 614, which may correspond to planar portion 154. Figure 6 As shown in surface 600, the corrugation capacitor can be periodic in one lateral direction.

[0048] Figures 7 to 14 Based on some examples Figure 1cross-sectional views of IC 100 during corresponding stages of the manufacturing method. Figure 1 The method is described in the context of an IC 100, but the method may be implemented to manufacture Figure 2 IC 200, as described subsequently.

[0049] refer to Figure 7 , a semiconductor substrate 102 is provided. Semiconductor substrate 102 includes one or more active devices (e.g., transistor 104) formed in, on, and / or over a top surface 103 of semiconductor substrate 102. The (one or more) active devices may be formed using any suitable front end of line (FEOL) process. A first interconnect dielectric layer 106 is formed over and on semiconductor substrate 102. First interconnect dielectric layer 106 may be or include any material described above with respect to first interconnect dielectric layer 106, and may be deposited by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), or any other deposition process. First interconnect dielectric layer 106 may have a planar top surface, such as by planarizing first interconnect dielectric layer 106 by chemical mechanical polishing (CMP).

[0050] refer to Figure 8 , forming conductive contacts 108, 110, conductive layer 114, and conductive lines 116, 118. Appropriate photolithography and etching processes may be used to form openings through first interconnect dielectric layer 106 to, for example, semiconductor substrate 102. The metal(s) of conductive contacts 108, 110, conductive layer 114, and conductive lines 116, 118 are deposited in the openings and above and on first interconnect dielectric layer 106. The metal(s) may be deposited using appropriate deposition processes (e.g., CVD, physical vapor deposition (PVD), etc.). The metal(s) above first interconnect dielectric layer 106 are patterned into conductive layer 114 and conductive lines 116, 118 using appropriate photolithography and etching processes. In the manufacturing Figure 2 In the example of IC 200 , the metal(s) over the first interconnect dielectric layer 106 are patterned into a conductive layer 214 and conductive lines 118 .

[0051] refer to Fig. 9 , an intermediate dielectric layer 902 is formed above and on the first interconnect dielectric layer 106, the conductive layer 114 and the conductive lines 116, 118 (or the conductive layer 214 and the conductive line 118). As described later, the intermediate dielectric layer 902 will be patterned into a corrugated dielectric structure 122. The intermediate dielectric layer 902 can be or include any material described above for the corrugated dielectric structure 122, and can be deposited by CVD, PECVD, LPCVD, or any other deposition process.

[0052] Photoresist 904 is deposited above and on the intermediate dielectric layer 902. Photoresist 904 may be deposited using spin coating or another suitable deposition technique. Next, grayscale photolithography is used to pattern photoresist 904. Fig. 9 As illustrated in FIG. 1 , grayscale lithography uses a grayscale lithography mask 906 and transmits electromagnetic radiation 908 (eg, light) through the grayscale lithography mask 906 to expose the photoresist 904 to the pattern of the grayscale lithography mask 906. Fig.10 , after developing and curing the photoresist 904 after exposure, the photoresist 904 is patterned into a patterned photoresist 1002 by grayscale lithography. The patterned photoresist 1002 corresponds to the corrugated dielectric structure 122 to be formed in lateral position and three-dimensional shape. In an example, any suitable grayscale lithography technique may be implemented. For example, i-line grayscale lithography may be implemented. In other examples, KrF grayscale technology may be implemented. In other examples, maskless digital grayscale lithography may be implemented.

[0053] refer to Fig.11 , the corrugated dielectric structure 122 is formed by the intermediate dielectric layer 902. Using the patterned photoresist 1002 as a mask, the intermediate dielectric layer 902 is etched to transfer the pattern of the patterned photoresist 1002 to the intermediate dielectric layer 902, thereby forming the corrugated dielectric structure 122. The etching may be anisotropic and may etch or consume both the patterned photoresist 1002 and the intermediate dielectric layer 902. In some examples, the etching rate of the intermediate dielectric layer 902 is substantially equal to the etching rate of the patterned photoresist 1002.

[0054] refer to Fig.12 , forming blanket capacitor conductive layers 1204, 1208 and blanket capacitor dielectric layer 1206. Blanket lower capacitor conductive layer 1204 is conformally deposited over and on the upper surface of corrugated dielectric structure 122, the upper surface and sidewall surfaces of conductive layer 114 and conductive lines 116, 118, and the upper surface of first interconnect dielectric layer 106. Blanket capacitor dielectric layer 1206 is conformally deposited over and on the upper surface of blanket lower capacitor conductive layer 1204, and blanket upper capacitor conductive layer 1208 is conformally deposited over and on the upper surface of blanket capacitor dielectric layer 1206. Blanket capacitor conductive layers 1204, 1208 and blanket capacitor dielectric layer 1206 may be any of the materials described above for capacitor conductive layers 124, 128 and capacitor dielectric layer 126, respectively, and may be deposited using PECVD, atomic layer deposition (ALD), or the like.

[0055] The blanket capacitor conductive layers 1204, 1208 and the blanket capacitor dielectric layer 1206 are patterned into capacitor conductive layers 124, 128 and capacitor dielectric layer 126, respectively. The patterning can be performed by using appropriate photolithography and etching processes. For example, a photoresist 1210 is deposited (e.g., by spin coating) over the blanket upper capacitor conductive layer 1208 and patterned using photolithography corresponding to the lateral footprint of the corrugated capacitor. Using the photoresist 1210 as a mask, the blanket capacitor conductive layers 1204, 1208 and the blanket capacitor dielectric layer 1206 are etched to pattern the blanket capacitor conductive layers 1204, 1208 and the blanket capacitor dielectric layer 1206 into capacitor conductive layers 124, 128 and capacitor dielectric layer 126, as shown in FIG. Fig.13 Any remaining photoresist 1210 is removed, such as by ashing.

[0056] Further references Fig.13 , a second interconnect dielectric layer 132 is formed above and on the first interconnect dielectric layer 106, the conductive layer 114, the conductive lines 116, 118, and the upper capacitor conductive layer 128. The second interconnect dielectric layer 132 may be or include any material as described above for the second interconnect dielectric layer 132, and may be deposited by CVD, PECVD, LPCVD, or any other deposition process. After deposition, the topography of the upper surface of the second interconnect dielectric layer 132 may be close to or correspond to the topography of the conductive layer 114, the conductive lines 116, 118, and the corrugated capacitor 120. By CMP, the topography of the second interconnect dielectric layer 132 may be removed, and the second interconnect dielectric layer 132 may be planarized, such as Fig.14 As shown in .

[0057] refer to Figure 1 , forming conductive vias 134, 136, 138. Using appropriate photolithography and etching processes, corresponding openings can be formed through the second interconnect dielectric layer 132 to the conductive layer 114, the conductive line 116, and the upper capacitor conductive layer 128. The metal(s) of the conductive vias 134, 136, 138 are deposited in the openings. The metal(s) described above can be deposited using appropriate deposition processes such as CVD, PVD, etc.

[0058] Figures 15 to 21 Based on some examples Figure 3 300 during a corresponding stage of the manufacturing method. Figure 7 In the embodiment, a semiconductor substrate 102 is provided. A first interconnect dielectric layer 106 is formed above and on the semiconductor substrate 102.

[0059] refer to Fig.15, forming conductive contacts 108, 110. Appropriate photolithography and etching processes may be used to form openings through the first interconnect dielectric layer 106 to, for example, the semiconductor substrate 102. The metal(s) of the conductive contacts 108, 110 are deposited in the openings. The metal(s) may be deposited using appropriate deposition processes (e.g., CVD, PVD, etc.). Any excess metal above the first interconnect dielectric layer 106 may be removed by CMP.

[0060] refer to Fig.16 , an intermediate dielectric layer 1602 is formed above and on the first interconnect dielectric layer 106. As described later, the intermediate dielectric layer 1602 will be patterned into the corrugated dielectric structure 322. The intermediate dielectric layer 1602 can be or include any material described above for the corrugated dielectric structure 322, and can be deposited by CVD, PECVD, LPCVD, or any other deposition process.

[0061] Photoresist 1604 is deposited above and on the intermediate dielectric layer 1602. Photoresist 1604 may be deposited using spin coating or another suitable deposition technique. Next, photoresist 1604 is patterned using grayscale lithography. Fig.16 As illustrated in FIG. 1 , grayscale lithography uses a grayscale lithography mask 1606 and transmits electromagnetic radiation 1608 (eg, light) through the grayscale lithography mask 1606 to expose the photoresist 1604 to the pattern of the grayscale lithography mask 1606. Fig.17 , after developing and curing the photoresist 1604 after exposure, the photoresist 1604 is patterned into a patterned photoresist 1702 by grayscale lithography. The patterned photoresist 1702 corresponds to the corrugated dielectric structure 322 to be formed in lateral position and three-dimensional shape. In an example, any suitable grayscale lithography technique may be implemented. For example, i-line grayscale lithography may be implemented. In other examples, KrF grayscale technology may be implemented. In other examples, maskless digital grayscale lithography may be implemented.

[0062] refer to Fig.18 , the corrugated dielectric structure 322 is formed by the intermediate dielectric layer 1602. Using the patterned photoresist 1702 as a mask, the intermediate dielectric layer 1602 is etched to transfer the pattern of the patterned photoresist 1702 to the intermediate dielectric layer 1602, thereby forming the corrugated dielectric structure 322. The etching can be anisotropic and can etch or consume both the patterned photoresist 1702 and the intermediate dielectric layer 1602. In some examples, the etching rate of the intermediate dielectric layer 1602 is substantially equal to the etching rate of the patterned photoresist 1702.

[0063] refer to Fig.19, forming a conductive layer 324 and conductive lines 116, 118. The metal(s) of the conductive layer 324 and the conductive lines 116, 118 are conformally deposited over and on the first interconnect dielectric layer 106 and the corrugated dielectric structure 322. The metal(s) may be deposited using appropriate deposition processes (e.g., CVD, ALD, etc.). The metal(s) over the first interconnect dielectric layer 106 and the corrugated dielectric structure 322 are patterned into the conductive layer 324 and the conductive lines 116, 118 using appropriate photolithography and etching processes. In some examples, the metal(s) may be patterned so that the conductive layer 324 extends to contact the conductive contacts 108.

[0064] refer to Fig. 20 , forming a blanket capacitor dielectric layer 2006 and a blanket upper capacitor conductive layer 2008. The blanket capacitor dielectric layer 2006 is conformally deposited over and on the upper surface and sidewall surfaces of the conductive layer 324 and the conductive lines 116, 118 and the upper surface of the first interconnect dielectric layer 106. The blanket upper capacitor conductive layer 2008 is conformally deposited over and on the upper surface of the blanket capacitor dielectric layer 2006. The blanket capacitor dielectric layer 2006 and the blanket upper capacitor conductive layer 2008 can be any of the materials described above for the capacitor dielectric layer 126 and the upper capacitor conductive layer 128, respectively, and can be deposited using PECVD, ALD, etc.

[0065] The blanket capacitor dielectric layer 2006 and the blanket upper capacitor conductive layer 2008 are patterned into the capacitor dielectric layer 126 and the upper capacitor conductive layer 128, respectively. The patterning can be performed by using appropriate photolithography and etching processes. For example, a photoresist 2010 is deposited (e.g., by spin coating) over the blanket upper capacitor conductive layer 2008 and patterned using photolithography corresponding to the lateral footprint of the corrugated capacitor. Using the photoresist 2010 as a mask, the blanket upper capacitor conductive layer 2008 and the blanket capacitor dielectric layer 2006 are etched to pattern the blanket upper capacitor conductive layer 2008 and the blanket capacitor dielectric layer 2006 into the upper capacitor conductive layer 128 and the capacitor dielectric layer 126, as shown in FIG. Fig.21 Any remaining photoresist 2010 is removed, such as by ashing.

[0066] Further references Fig.21 , the second interconnect dielectric layer 132 is formed above and on the first interconnect dielectric layer 106, the conductive layer 324, the conductive lines 116, 118 and the upper capacitor conductive layer 128, as described with respect to Fig.13 and 14 Described. Reference Figure 3 , forming conductive vias 134, 136, 138, as described with respect to Figure 1 described.

[0067] Although various examples have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope defined by the appended claims.

Claims

1. An integrated circuit IC, comprising: a first corrugated conductive layer and a second corrugated conductive layer disposed above the semiconductor substrate; and A corrugated dielectric layer is located between the first corrugated conductive layer and the second corrugated conductive layer.

2. The IC of claim 1 , further comprising a corrugated dielectric structure between the semiconductor substrate and the first corrugated conductive layer, the corrugated dielectric structure having a first surface located on a planar top surface of the semiconductor substrate and a second surface contacting the first corrugated conductive layer. 3 . The IC of claim 2 , further comprising a third conductive layer between the semiconductor substrate and the first corrugated conductive layer, the first corrugated conductive layer contacting the third conductive layer through valleys of the corrugated dielectric structure.

4. The IC of claim 3, further comprising: an interconnect dielectric layer located above the third conductive layer and the second corrugated conductive layer; a first conductive via penetrating the interconnect dielectric layer to the third conductive layer; and A second conductive via passes through the interconnect dielectric layer to the second corrugated conductive layer.

5. The IC of claim 1 , wherein the first corrugated conductive layer has a corrugated upper surface, the corrugated dielectric layer is located above the corrugated upper surface, and wherein, In the transverse direction, the corrugated upper surface follows a sinusoidal wave function.

6. The IC of claim 1 , wherein the first corrugated conductive layer has a corrugated upper surface, the corrugated dielectric layer is located above the corrugated upper surface, and wherein, In the lateral direction from a peak to an adjacent peak, the corrugated upper surface has no radius of curvature less than 500 nm.

7. The IC of claim 1 , wherein the first corrugated conductive layer has a corrugated upper surface, the corrugated dielectric layer is located above the corrugated upper surface, and wherein the surface area of ​​the corrugated upper surface is at least 1.5 times the lateral footprint of the corrugated upper surface.

8. The IC of claim 1 , wherein the first corrugated conductive layer has a corrugated upper surface, the corrugated dielectric layer is located above the corrugated upper surface, and wherein the corrugated upper surface has peaks and valleys adjacent to the peaks, the height from the peaks to the valleys being at least 50 nm.

9. The IC of claim 1, wherein: The first corrugated conductive layer has a corrugated upper surface, the corrugated dielectric layer is located above the corrugated upper surface; The corrugated upper surface has a first crest, a trough, and a second crest, wherein the second crest is adjacent to the first crest, and the trough is located between the first crest and the second crest; The height is from said trough to said first crest; The width is between the upper surfaces of the corrugations between the first crest and the second crest at half the height from the trough; and A ratio of the height to the width is at least 10%.

10. The IC of claim 1, further comprising a transistor, wherein the first corrugated conductive layer, the corrugated dielectric layer, and the second corrugated conductive layer form a capacitor, the transistor being connected in circuit to the capacitor.

11. The IC of claim 10, wherein the first corrugated conductive layer is implemented by an interconnect metal layer, the interconnect metal layer providing a conductive connection to the transistor.

12. The IC of claim 1, wherein the corrugated dielectric layer comprises silicon oxide, silicon nitride, hafnium oxide, or a combination thereof.

13. An integrated circuit IC, comprising: A parallel plate capacitor disposed above a semiconductor substrate, the parallel plate capacitor comprising: A first corrugated conductive layer and a second corrugated conductive layer located above the semiconductor substrate; and A corrugated dielectric layer is located between the first corrugated conductive layer and the second corrugated conductive layer.

14. The IC of claim 13, further comprising A third conductive layer located above the semiconductor substrate; and A corrugated dielectric structure is located above the third conductive layer, the corrugated dielectric structure has a corrugated upper surface, the first corrugated conductive layer is located above the corrugated upper surface of the corrugated dielectric structure, and the first corrugated conductive layer contacts the third conductive layer through the valleys of the corrugated upper surface of the corrugated dielectric structure.

15. The IC of claim 14, further comprising: an interconnect dielectric layer located above the third conductive layer and the second corrugated conductive layer; a first conductive via penetrating the interconnect dielectric layer to the third conductive layer; and A second conductive via passes through the interconnect dielectric layer to the second corrugated conductive layer.

16. The IC of claim 13, wherein: In the lateral direction, the upper surface of the first corrugated conductive layer follows a sinusoidal wave shape.

17. The IC of claim 13, wherein: Along the lateral direction from the first crest through the trough to the second crest, the upper surface of the first corrugated conductive layer does not include a curved portion with a radius of curvature less than 500 nm.

18. The IC of claim 13, wherein a surface area of ​​an upper surface of the first corrugated conductive layer is at least 1.5 times a lateral area over which the surface area of ​​the upper surface of the first corrugated conductive layer is located.

19. A method for manufacturing an integrated circuit IC, the method comprising: forming a corrugated dielectric structure over a semiconductor substrate; conformally forming a first conductive layer over the corrugated dielectric structure, the first conductive layer comprising a corrugated upper surface; conformally forming a dielectric layer over the first conductive layer; and A second conductive layer is conformally formed over the dielectric layer.

20. The method of claim 19, wherein forming the corrugated dielectric structure comprises: depositing an intermediate dielectric layer over the semiconductor substrate; forming a photoresist over the interlayer dielectric layer, including patterning the photoresist using grayscale lithography; and The intermediary dielectric layer is etched into the corrugated dielectric structure using the patterned photoresist as a mask.

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