Silicon capacitor and manufacturing method and manufacturing equipment thereof

Abstract

The embodiment of the invention provides at least one silicon capacitor and a manufacturing method and manufacturing equipment thereof, and the manufacturing method comprises the steps: forming a groove network on a substrate along a preset direction through etching, so as to enable the substrate to form an integrated structure, the preset direction is a vertical direction extending from the top surface of the substrate to the bottom surface of the substrate, and the groove network is arranged on the substrate. The groove network comprises at least one groove, and the at least one groove is surrounded by an integrated structure; at least one layer of MIM structure is formed on the substrate through deposition, and the at least one layer of MIM structure comprises a single-layer MIM structure, a double-layer MIM structure and a multi-layer MIM structure.

Description

Technical Field

[0001] The present invention relates to, in particular to, a silicon capacitor and a manufacturing method and manufacturing equipment thereof. Background Art

[0002] In order to achieve higher capacitance density, current silicon capacitor technology usually increases the area of ​​the electrode structure by etching grooves on the silicon substrate while keeping the dielectric material and dielectric withstand voltage unchanged, and then forms a metal-insulator-metal (MIM) capacitor structure through a deposition process, thereby effectively improving the capacitance density. When the area is fixed, the capacitance density improvement of silicon capacitors usually depends on deepening the depth-to-width ratio of the trench and increasing the number of trenches.

[0003] However, in the prior art, as the trench aspect ratio and the number of trenches increase, the gaps between the trenches are compressed, the depth increases, and the structural stability between the trenches decreases. There is a risk of fracture in the subsequent deposition process of the trenches, leading to capacitor reliability issues. In addition, the increase in the trench aspect ratio and the increase in the number of trenches will also lead to an increase in stress concentration at the bottom and sidewalls of the trenches, which will not only affect the mechanical strength of the trench structure, but may also introduce unnecessary defects in electrical performance, such as an increase in leakage paths, thereby affecting the reliability and stability of the capacitor device of the overall device. Summary of the invention

[0004] The present invention provides one or more silicon capacitors and their manufacturing methods and manufacturing equipment, aiming to solve at least the following technical problems: as the groove aspect ratio and the number of grooves increase, the gap between the grooves is compressed, the depth is deepened, the structural stability is reduced, the deposition process has the risk of breakage, and the capacitor reliability deteriorates.

[0005] Specifically, the embodiment of the present invention provides the following technical solutions: In a first aspect, an embodiment of the present invention provides a method for manufacturing a silicon capacitor, comprising: By etching, a groove network is formed on the substrate along a predetermined direction to form the substrate into an integral structure, wherein the predetermined direction is a vertical direction extending from the top surface to the bottom surface of the substrate, the groove network includes at least one groove, and the at least one groove is surrounded by the integral structure; By deposition, a bottom electrode is formed on the groove bottom surface and the groove side surface of the groove network and the top surface of the integrated structure, wherein the bottom electrode covers the groove bottom surface and the groove side surface of the groove network and the top surface of the integrated structure; Forming a dielectric layer on the top surface of the bottom electrode by deposition, wherein the dielectric layer covers the bottom electrode; A top electrode is formed on the top surface of the dielectric layer by deposition, and the top electrode is configured to fill each groove in the groove network so that the top surface of the top electrode is parallel to the bottom surface of the substrate, and the bottom electrode, the dielectric layer and the top electrode together constitute a single-layer MIM structure.

[0006] Furthermore, the method further comprises: The groove network is configured as at least one of a cylinder, a cone, a frustum, a prism, a frustum, and a pyramid; The material of the substrate is silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, silicon on insulator, germanium on insulator, glass or quartz; The etching includes dry etching or wet etching; The deposition includes physical vapor deposition, chemical vapor deposition and atomic layer deposition.

[0007] In a second aspect, an embodiment of the present invention further provides a method for manufacturing a silicon capacitor, comprising: By etching, a groove network is formed on the substrate along a predetermined direction to form the substrate into an integral structure, wherein the predetermined direction is a vertical direction extending from the top surface to the bottom surface of the substrate, the groove network includes at least one groove, and the at least one groove is surrounded by the integral structure; By deposition, a bottom electrode is formed on the groove bottom surface and the groove side surface of the groove network and the top surface of the integrated structure, wherein the bottom electrode covers the groove bottom surface and the groove side surface of the groove network and the top surface of the integrated structure; Forming a first dielectric layer on the top surface of the bottom electrode by deposition, wherein the first dielectric layer covers the bottom electrode; forming an intermediate electrode layer on the top surface of the first dielectric layer by deposition, wherein the intermediate electrode layer covers the first dielectric layer; forming a second dielectric layer on the top surface of the intermediate electrode layer by deposition, wherein the second dielectric layer covers the intermediate electrode layer; A top electrode is formed on the top surface of the second dielectric layer by deposition, and the top electrode is configured to fill each groove in the groove network so that the top surface of the top electrode is parallel to the bottom surface of the substrate, and the bottom electrode, the first dielectric layer, the middle electrode layer, the second dielectric layer and the top electrode together constitute a double-layer MIM structure.

[0008] Furthermore, the method further comprises: The groove network is configured as at least one of a cylinder, a frustum, a cone, a prism, a frustum, and a pyramid; The material of the substrate is silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, silicon on insulator, germanium on insulator, glass or quartz; The etching includes dry etching or wet etching; The deposition includes physical vapor deposition, chemical vapor deposition and atomic layer deposition.

[0009] In a third aspect, an embodiment of the present invention further provides a method for manufacturing a silicon capacitor, comprising: By etching, a groove network is formed on the substrate along a predetermined direction to form the substrate into an integral structure, wherein the predetermined direction is a vertical direction extending from the top surface to the bottom surface of the substrate, the groove network includes at least one groove, and the at least one groove is surrounded by the integral structure; By deposition, at least one MIM structure is formed on the substrate, wherein the at least one MIM structure includes a single-layer MIM structure and a double-layer MIM structure. The single-layer MIM structure comprises a bottom electrode, a dielectric layer, and a top electrode in sequence, wherein the bottom electrode is formed on the bottom surface and the side surface of the grooves of the groove network and the top surface of the integrated structure by deposition, the dielectric layer is formed on the bottom electrode by deposition, and the top electrode is formed on the dielectric layer by deposition, the bottom electrode covers the bottom surface and the side surface of the grooves of the groove network and the top surface of the integrated structure, the dielectric layer covers the bottom electrode, and the top electrode is configured to fill each groove in the groove network so that the top surface of the top electrode is parallel to the bottom surface of the substrate, The double-layer MIM structure includes a bottom electrode, a first dielectric layer, an intermediate electrode, a second dielectric layer, and a top electrode in sequence. The bottom electrode is formed on the bottom surface and the side surface of the grooves of the groove network and the top surface of the integrated structure by deposition. The first dielectric layer is formed on the bottom electrode by deposition. The intermediate electrode is formed on the first dielectric layer by deposition. The second dielectric layer is formed on the intermediate electrode by deposition. The top electrode is formed on the second dielectric layer by deposition. The bottom electrode covers the bottom surface and the side surface of the grooves of the groove network and the top surface of the integrated structure. The first dielectric layer covers the bottom electrode, the intermediate electrode layer covers the first dielectric layer, the second dielectric layer covers the intermediate electrode layer, and the top electrode is constructed to fill each groove in the groove network so that the top surface of the top electrode is parallel to the bottom surface of the substrate.

[0010] Furthermore, the method further comprises: The groove network is configured as at least one of a cylinder and a prism; The material of the substrate is silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, silicon on insulator, germanium on insulator, glass or quartz; The etching includes dry etching or wet etching; The deposition includes physical vapor deposition, chemical vapor deposition and atomic layer deposition.

[0011] Furthermore, in a fourth aspect, an embodiment of the present invention also provides a silicon capacitor manufacturing device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned silicon capacitor manufacturing method when executing the program to manufacture the silicon capacitor.

[0012] Furthermore, in a fifth aspect, an embodiment of the present invention also provides a silicon capacitor, which is manufactured according to the manufacturing method of the silicon capacitor as described above and based on the manufacturing equipment of the silicon capacitor as described above, and the silicon capacitor has a single-layer MIM structure.

[0013] Furthermore, in a sixth aspect, an embodiment of the present invention also provides a silicon capacitor, which is manufactured according to the manufacturing method of the silicon capacitor as described above and based on the manufacturing equipment of the silicon capacitor as described above, and the silicon capacitor has a double-layer MIM structure.

[0014] Furthermore, in the seventh aspect, an embodiment of the present invention also provides a silicon capacitor, which is manufactured according to the manufacturing method of the silicon capacitor as mentioned above and based on the manufacturing equipment of the silicon capacitor as mentioned above, and the silicon capacitor has at least one layer of MIM structure.

[0015] It can be seen from the above technical solutions that one or more silicon capacitors and their manufacturing methods and manufacturing equipment provided in the embodiments of the present invention form a highly stable silicon capacitor structure through an independent groove network and an integrated structure design using MEMS process processing means, and increase the surface area of ​​the capacitor by designing the groove network, thereby further improving the capacitance density of the silicon capacitor, and aiming to at least solve the following technical problems: as the groove aspect ratio and the number of grooves increase, the gap between the grooves is compressed, the depth is deepened, the structural stability is reduced, there is a risk of breakage in the deposition process, and the capacitor reliability is deteriorated. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic diagram of a trench structure of a silicon capacitor provided by an embodiment of the present invention; Figure 2A schematic diagram of a structure of a silicon capacitor provided by an embodiment of the present invention in which the groove structure is a cylinder from different viewing angles; Figure 3 A schematic diagram of a structure from different viewing angles in which the trench structure of a silicon capacitor provided by an embodiment of the present invention is a truncated cone; Figure 4 A schematic diagram of a structure of a silicon capacitor provided by an embodiment of the present invention in which the trench structure is a cone at different viewing angles; Figure 5 A schematic diagram of a structure from different viewing angles in which the trench structure of a silicon capacitor provided by an embodiment of the present invention is a prism; Figure 6 A schematic diagram of a structure of a silicon capacitor provided by an embodiment of the present invention in which the groove structure is a prism at different viewing angles; Figure 7 A schematic diagram of a structure of a silicon capacitor provided by an embodiment of the present invention in which the trench structure is a pyramid at different viewing angles; Figure 8 A flow chart of one of the methods for manufacturing a silicon capacitor provided in the first embodiment of the present invention; Fig. 9 A schematic diagram of the structure of one of the silicon capacitors provided in the first embodiment of the present invention; Fig.10 A flow chart of one of the methods for manufacturing a silicon capacitor provided in the second embodiment of the present invention; Fig.11 A schematic diagram of the structure of one of the silicon capacitors provided in the second embodiment of the present invention; Fig.12 A flow chart of one of the methods for manufacturing a silicon capacitor provided in the third embodiment of the present invention; Fig.13 A schematic diagram of an electronic device provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] The various terms or phrases used in the present invention have the general meanings known to those of ordinary skill in the art. Even so, the present invention still hopes to provide a more detailed description and explanation of these terms or phrases. If the terms and phrases involved in this article are inconsistent with the commonly known meanings, the meanings expressed in the present invention shall prevail; and if not defined in this application, they have the meanings commonly understood by those of ordinary skill in the art.

[0020] In the prior art, there are many problems including but not limited to the following: as the aspect ratio of the grooves and the number of grooves increase, the gaps between the grooves are compressed, the depth increases, the structural stability decreases, there is a risk of fracture in the deposition process, and the capacitor reliability deteriorates.

[0021] Combine the following Figure 1 A trench structure involved in a method for manufacturing a silicon capacitor of the present invention is described.

[0022] Figure 1 A schematic diagram of a trench structure of a silicon capacitor provided by an embodiment of the present invention.

[0023] Specifically, Figure 1 As shown, at least one groove is formed on the top surface of the substrate along the D direction, each groove is independent of each other, and an integrated structure is formed between all the grooves, and a closed loop area formed by the integrated structure completely surrounds all the grooves.

[0024] What needs to be explained is that in the spatial sense, Figure 1 , the D direction as the predetermined direction may refer to a vertical direction extending from the top surface of the substrate to the bottom surface of the substrate.

[0025] It needs to be explained that, in terms of structural relationship, the groove network formed by the groove structure can be constructed as at least one of a cylinder and a prism, such as a cylinder, a triangular prism, a quadrangular prism, etc., or a cross prism.

[0026] It should be explained that, in terms of structural relationship, the integrated structure may refer to the overall structure of the substrate after being etched.

[0027] It should be explained that, in terms of structural relationship, since an integrated structure with at least one groove is obtained by etching the substrate, Figure 1 The spatial closed loop region formed by the integrated structure (i.e., each side of the corresponding groove) surrounds all the grooves, and each groove is separated from each other by the integrated structure.

[0028] MIM capacitors are formed using semiconductor technology. Since the integrated structure is connected as a whole, the structural rigidity is increased, which can effectively enhance the stability and load-bearing capacity of the integrated structure formed by the deep groove network. The risk of fracture of the integrated structure is reduced during the manufacturing process. Finally, the groove network is completely covered by the top electrode, that is, the top electrode completely fills the gap between the integrated structures, further improving the structural stability. The capacitor formed by the integrated structure design and semiconductor processing technology has high capacitance density and high structural stability.

[0029] Specifically, the groove structure proposed in the embodiment of the present invention is described as follows: since the integrated structure is connected as a whole, the structural rigidity is increased, the stability and load-bearing ability of the integrated structure formed by the deep groove network are effectively enhanced, and the risk of fracture of the integrated structure during the manufacturing process is reduced. The groove network is completely covered by the topmost electrode, that is, the top electrode completely fills the gap between the integrated structures, thereby further improving the structural stability.

[0030] Specifically, referring to the figures, it should be noted that the manufacturing method of the silicon capacitor may also include: the integrated structure may include but is not limited to at least one of a cylinder, a cone, a frustum, a prism, a prism and a pyramid.

[0031] Figure 2 Schematic diagram of the structure of the silicon capacitor provided by one embodiment of the present invention when the trench structure is a cylinder at different viewing angles.

[0032] Reference Figure 2 , in the case where the trench structure of the silicon capacitor is a cylinder, the trench structure in the substrate can be seen from different viewing angles.

[0033] Of course, the embodiments of the present invention are not limited thereto, and the trench structure of the silicon capacitor may also include a column-like pillar.

[0034] Figure 3 Schematic diagram of the structure at different viewing angles when the trench structure of the silicon capacitor provided by one embodiment of the present invention is a truncated cone.

[0035] Reference Figure 3 , when the trench structure of the silicon capacitor is a truncated cone, the trench structure in the substrate can be seen from different viewing angles.

[0036] Of course, the embodiments of the present invention are not limited thereto, and in the case where the bottom surface of the truncated cone (whose area is smaller than the top surface) is located on the side close to the bottom surface of the substrate, the trench structure of the silicon capacitor may also include a table body similar to the truncated cone.

[0037] Figure 4 Schematic diagram of the structure of the silicon capacitor provided by one embodiment of the present invention when the trench structure is a cone at different viewing angles.

[0038] Reference Figure 4 , in the case where the trench structure of the silicon capacitor is a cone, the trench structure in the substrate can be seen from different viewing angles.

[0039] Of course, the embodiments of the present invention are not limited thereto. In the case where the apex of the cone is located on a side close to the bottom surface of the substrate, the trench structure of the silicon capacitor may also include a cone-like body.

[0040] Figure 5 Schematic diagram of the structure at different viewing angles when the trench structure of the silicon capacitor provided by one embodiment of the present invention is a prism.

[0041] Reference Figure 5 , in the case where the trench structure of the silicon capacitor is a prism, the trench structure in the substrate can be seen from different viewing angles.

[0042] Of course, the embodiments of the present invention are not limited thereto, and the trench structure of the silicon capacitor may also include a prism-like column.

[0043] Figure 6 Schematic diagram of the structure at different viewing angles when the trench structure of the silicon capacitor provided by one embodiment of the present invention is a prism.

[0044] Reference Figure 6 , when the trench structure of the silicon capacitor is a prism, the trench structure in the substrate can be seen from different viewing angles.

[0045] Of course, the embodiments of the present invention are not limited thereto, and in the case where the bottom surface of the pyramid (whose area is smaller than the top surface) is located close to the bottom surface of the substrate, the trench structure of the silicon capacitor may also include a pyramid-like platform.

[0046] Figure 7 Schematic diagram of the structure at different viewing angles when the trench structure of the silicon capacitor provided by one embodiment of the present invention is a pyramid.

[0047] Reference Figure 7 , when the trench structure of the silicon capacitor is a pyramid, the trench structure in the substrate can be seen from different viewing angles.

[0048] Of course, the embodiments of the present invention are not limited thereto. In the case where the apex of the pyramid is located on a side close to the bottom surface of the substrate, the trench structure of the silicon capacitor may also include a pyramid-like cone.

[0049] In view of this, in a first aspect, a first embodiment of the present invention provides a method for manufacturing a silicon capacitor.

[0050] Combine the following Figure 2 A method for manufacturing a silicon capacitor of the present invention is described.

[0051] Figure 2 This is a flow chart of one of the methods for manufacturing a silicon capacitor provided in the first embodiment of the present invention.

[0052] In a first aspect, an embodiment of the present invention provides a method for manufacturing a silicon capacitor, comprising: S110: forming a groove network on the substrate along a predetermined direction by etching to form the substrate into an integrated structure, wherein the predetermined direction is a vertical direction extending from the top surface to the bottom surface of the substrate, the groove network includes at least one groove, and the at least one groove is surrounded by the integrated structure; S120: forming a bottom electrode on the groove bottom surface and groove side surface of the groove network and the top surface of the integrated structure by deposition, wherein the bottom electrode covers the groove bottom surface and groove side surface of the groove network and the top surface of the integrated structure; S130: forming a dielectric layer on the top surface of the bottom electrode by deposition, wherein the dielectric layer covers the bottom electrode; S140: A top electrode is formed on the top surface of the dielectric layer by deposition, and the top electrode is configured to fill each groove in the groove network so that the top surface of the top electrode is parallel to the bottom surface of the substrate, and the bottom electrode, the dielectric layer and the top electrode together constitute a single-layer MIM structure.

[0053] Specifically, the trench contact network involved in the method for manufacturing the silicon capacitor according to the first embodiment of the present invention can be referred to above. Figure 1 Refer to the previous article and will not be repeated here.

[0054] In the first embodiment, it should be noted that the method for manufacturing the silicon capacitor may further include: etching may include but is not limited to dry etching using plasma or wet etching using a chemical solution to remove a material layer. Through the etching process, a desired microstructure, i.e., a groove network, may be formed on the substrate.

[0055] In the first embodiment, it should be noted that the method for manufacturing the silicon capacitor may further include: the groove network is constructed as at least one of a cylinder and a prism, such as a cylinder, a triangular prism, a quadrangular prism, a cross prism, etc.

[0056] In the first embodiment, it should be noted that the method for manufacturing the silicon capacitor may further include: the material of the substrate may include but is not limited to silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, silicon on insulator, germanium on insulator, glass or quartz.

[0057] In the first embodiment, it should be noted that the method for manufacturing the silicon capacitor may further include: deposition may include but is not limited to physical vapor deposition, chemical vapor deposition and atomic layer deposition.

[0058] In the first embodiment, through the manufacturing method of the silicon capacitor, the manufactured silicon capacitor is based on a single-layer MIM structure, and while the capacitance density is improved through the trench structure, the capacitance stability is further guaranteed, laying a solid foundation for subsequent processes.

[0059] It can be seen from the above technical scheme that the manufacturing method of the silicon capacitor provided by the first embodiment of the present invention forms a high-stability silicon capacitor structure through an independent groove network and an integrated structure design using MEMS processing means, and increases the surface area of ​​the capacitor by designing the groove network, thereby further improving the capacitance density of the silicon capacitor, and at least solves the following technical problems: as the groove aspect ratio and the number of grooves increase, the gap between the grooves is compressed, the depth is deepened, the structural stability is reduced, there is a risk of breakage in the deposition process, and the capacitor reliability is deteriorated.

[0060] Based on the same inventive concept, on the other hand, an embodiment of the present invention provides a silicon capacitor.

[0061] Combine the following Figure 3 The silicon capacitor provided by the present invention is described. The silicon capacitor described below and the method for manufacturing the silicon capacitor provided by the first embodiment of the present invention described above can be referred to each other.

[0062] Figure 3 A schematic diagram of the structure of one of the silicon capacitors provided in one embodiment of the present invention.

[0063] like Figure 2 and Figure 3 As shown, a method for manufacturing a silicon capacitor is proposed in combination with the first embodiment of the present invention, which can further clarify the specific structure and process flow of the silicon capacitor manufactured by the method for manufacturing a silicon capacitor proposed based on the first embodiment of the present invention, and the silicon capacitor has a single-layer MIM structure.

[0064] Since the manufacturing process flow of the first embodiment has been described in detail above, it will not be repeated here. However, it needs to be emphasized again that the manufacturing method of the silicon capacitor provided by the first embodiment of the present invention, through an independent groove network and an integrated structure design, utilizes MEMS processing means to form a high-stability silicon capacitor structure, and increases the surface area of ​​the capacitor by designing the groove network, thereby further improving the capacitance density of the silicon capacitor, and at least solves the following technical problems: as the groove aspect ratio and the number of grooves increase, the gap between the grooves is compressed, the depth is deepened, the structural stability is reduced, there is a risk of breakage in the deposition process, and the capacitor reliability is deteriorated.

[0065] Based on the same inventive concept, on the other hand, a second embodiment of the present invention provides a method for manufacturing a silicon capacitor.

[0066] In view of this, in a second aspect, a second embodiment of the present invention provides a method for manufacturing a silicon capacitor.

[0067] Combine the following Figure 4 A method for manufacturing a silicon capacitor of the present invention is described.

[0068] Figure 4 The present invention is a flowchart of a method for manufacturing a silicon capacitor according to a second embodiment of the present invention.

[0069] In a second aspect, an embodiment of the present invention provides a method for manufacturing a silicon capacitor, comprising: S210: forming a groove network on the substrate along a predetermined direction by etching to form the substrate into an integrated structure, wherein the predetermined direction is a vertical direction extending from the top surface to the bottom surface of the substrate, the groove network includes at least one groove, and the at least one groove is surrounded by the integrated structure; S220: forming a bottom electrode on the groove bottom surface and groove side surface of the groove network and the top surface of the integrated structure by deposition, wherein the bottom electrode covers the groove bottom surface and groove side surface of the groove network and the top surface of the integrated structure; S230: forming a first dielectric layer on the top surface of the bottom electrode by deposition, wherein the first dielectric layer covers the bottom electrode; S240: forming an intermediate electrode layer on the top surface of the first dielectric layer by deposition, wherein the intermediate electrode layer covers the first dielectric layer; S250: forming a second dielectric layer on the top surface of the intermediate electrode layer by deposition, wherein the second dielectric layer covers the intermediate electrode layer; S260: A top electrode is formed on the top surface of the second dielectric layer by deposition, and the top electrode is configured to fill each groove in the groove network so that the top surface of the top electrode is parallel to the bottom surface of the substrate, and the bottom electrode, the first dielectric layer, the middle electrode layer, the second dielectric layer and the top electrode together constitute a double-layer MIM structure.

[0070] Specifically, the trench connection network involved in the method for manufacturing the silicon capacitor according to the second embodiment of the present invention can be referred to the above Figure 1 Refer to the previous article and will not be repeated here.

[0071] In the second embodiment, it should be noted that the method for manufacturing the silicon capacitor may further include: etching may include but is not limited to dry etching using plasma or wet etching using a chemical solution to remove a material layer. Through the etching process, a desired microstructure, i.e., a groove network, may be formed on the substrate.

[0072] In the second embodiment, it should be noted that the method for manufacturing the silicon capacitor may further include: the groove network is constructed as at least one of a cylinder and a prism, such as a cylinder, a triangular prism, a quadrangular prism, a cross prism, etc.

[0073] In the second embodiment, it should be noted that the manufacturing method of the silicon capacitor may further include: the material of the substrate may include but is not limited to silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, silicon on insulator, germanium on insulator, glass or quartz.

[0074] In the second embodiment, it should be noted that the method for manufacturing the silicon capacitor may further include: deposition may include but is not limited to physical vapor deposition, chemical vapor deposition and atomic layer deposition.

[0075] In the second embodiment, through the manufacturing method of the silicon capacitor, the manufactured silicon capacitor is based on a double-layer MIM structure. While the capacitance density is improved through the groove structure, more specifically, compared with the first embodiment, the capacitance density is further doubled, and the capacitance stability is further guaranteed, laying a solid foundation for subsequent processes.

[0076] It can be seen from the above technical solution that the manufacturing method of the silicon capacitor provided by the second embodiment of the present invention uses an independent groove network and an integrated structure design, and uses MEMS processing means to form a high-stability silicon capacitor structure, and increases the surface area of ​​the capacitor by designing the groove network, thereby further improving the capacitance density of the silicon capacitor, and at least solves the following technical problems: as the groove aspect ratio and the number of grooves increase, the gap between the grooves is compressed, the depth is deepened, the structural stability is reduced, there is a risk of breakage in the deposition process, and the capacitor reliability is deteriorated.

[0077] Based on the same inventive concept, on the other hand, an embodiment of the present invention provides a silicon capacitor.

[0078] Combine the following Figure 5 The silicon capacitor provided by the present invention is described. The silicon capacitor described below and the method for manufacturing the silicon capacitor provided by the first embodiment of the present invention described above can be referred to each other.

[0079] Figure 5 A schematic diagram of the structure of one of the silicon capacitors provided in one embodiment of the present invention.

[0080] like Figure 4 and Figure 5 As shown, a method for manufacturing a silicon capacitor is proposed in combination with the second embodiment of the present invention, which can further clarify the specific structure and process flow of the silicon capacitor manufactured by the method for manufacturing a silicon capacitor proposed based on the second embodiment of the present invention, and the silicon capacitor has a double-layer MIM structure.

[0081] Since the manufacturing process flow of the second embodiment has been described in detail above, it will not be repeated here. However, it needs to be emphasized again that the manufacturing method of the silicon capacitor provided by the second embodiment of the present invention, through an independent groove network and an integrated structure design, utilizes MEMS processing means to form a high-stability silicon capacitor structure, and increases the surface area of ​​the capacitor by designing the groove network, thereby further improving the capacitance density of the silicon capacitor, and at least solves the following technical problems: as the groove aspect ratio and the number of grooves increase, the gap between the grooves is compressed, the depth is deepened, the structural stability is reduced, there is a risk of breakage in the deposition process, and the capacitor reliability is deteriorated.

[0082] Based on the same inventive concept, on the other hand, a third embodiment of the present invention provides a method for manufacturing a silicon capacitor.

[0083] In view of this, in a third aspect, a third embodiment of the present invention provides a method for manufacturing a silicon capacitor.

[0084] Combine the following Figure 6 A method for manufacturing a silicon capacitor of the present invention is described.

[0085] Figure 6 The present invention is a flowchart of a method for manufacturing a silicon capacitor according to a third embodiment of the present invention.

[0086] In a third aspect, an embodiment of the present invention provides a method for manufacturing a silicon capacitor, comprising: S310: forming a groove network along a predetermined direction on the substrate by etching to form the substrate into an integrated structure, wherein the predetermined direction is a vertical direction extending from the top surface to the bottom surface of the substrate, the groove network includes at least one groove, and the at least one groove is surrounded by the integrated structure; S320: at least one MIM structure is formed on the substrate by deposition, the at least one MIM structure includes a single-layer MIM structure and a double-layer MIM structure, the single-layer MIM structure includes a bottom electrode, a dielectric layer, and a top electrode in sequence, the bottom electrode is formed on the bottom surface and the side surface of the groove of the groove network and the top surface of the integrated structure by deposition, the dielectric layer is formed on the bottom electrode by deposition, the top electrode is formed on the dielectric layer by deposition, the bottom electrode covers the bottom surface and the side surface of the groove of the groove network and the top surface of the integrated structure, the dielectric layer covers the bottom electrode, the top electrode is constructed to fill each groove in the groove network so that the top surface of the top electrode is parallel to the bottom surface of the substrate, and the double-layer MIM structure includes the bottom electrode in sequence , a first dielectric layer, an intermediate electrode, a second dielectric layer, and a top electrode, the bottom electrode is formed on the bottom surface and the side surface of the grooves of the groove network and the top surface of the integrated structure by deposition, the first dielectric layer is formed on the bottom electrode by deposition, the intermediate electrode is formed on the first dielectric layer by deposition, the second dielectric layer is formed on the intermediate electrode by deposition, and the top electrode is formed on the second dielectric layer by deposition, the bottom electrode covers the bottom surface and the side surface of the grooves of the groove network and the top surface of the integrated structure, the first dielectric layer covers the bottom electrode, the intermediate electrode layer covers the first dielectric layer, the second dielectric layer covers the intermediate electrode layer, and the top electrode is constructed to fill each groove in the groove network so that the top surface of the top electrode is parallel to the bottom surface of the substrate.

[0087] It should be noted that, in a further embodiment, the at least one layer of MIM structure may include a multi-layer MIM structure, that is, a MIM structure with more than two layers.

[0088] Specifically, the trench contact network involved in the method for manufacturing the silicon capacitor according to the third embodiment of the present invention can be referred to above. Figure 1 Refer to the previous article and will not be repeated here.

[0089] In the third embodiment, it should be noted that the method for manufacturing the silicon capacitor may further include: etching may include but is not limited to dry etching using plasma or wet etching using a chemical solution to remove a material layer. Through the etching process, a desired microstructure, i.e., a groove network, may be formed on the substrate.

[0090] In the third embodiment, it should be noted that the method for manufacturing the silicon capacitor may further include: the groove network is constructed as at least one of a cylinder and a prism, such as a cylinder, a triangular prism, a quadrangular prism, a cross prism, etc.

[0091] In the third embodiment, it should be noted that the manufacturing method of the silicon capacitor may further include: the material of the substrate may include but is not limited to silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, silicon on insulator, germanium on insulator, glass or quartz.

[0092] In the third embodiment, it should be noted that the method for manufacturing the silicon capacitor may further include: deposition may include but is not limited to physical vapor deposition, chemical vapor deposition and atomic layer deposition.

[0093] In the third embodiment, through the manufacturing method of the silicon capacitor, the manufactured silicon capacitor is based on at least one MIM structure, while the capacitance density is improved through the trench structure, and the capacitance stability is further guaranteed, laying a solid foundation for subsequent processes.

[0094] It can be seen from the above technical solutions that the manufacturing method of the silicon capacitor provided in the third embodiment of the present invention uses an independent groove network and an integrated structure design, and uses MEMS processing means to form a high-stability silicon capacitor structure. The surface area of ​​the capacitor is increased by designing the groove network, thereby further improving the capacitance density of the silicon capacitor, and at least solves the following technical problems: as the groove aspect ratio and the number of grooves increase, the gap between the grooves is compressed, the depth is deepened, the structural stability is reduced, there is a risk of breakage in the deposition process, and the capacitor reliability is deteriorated.

[0095] On the other hand, based on the same inventive concept, another embodiment of the present invention provides a manufacturing device for a silicon capacitor.

[0096] Figure 7 A schematic diagram of a silicon capacitor manufacturing device provided by an embodiment of the present invention.

[0097] In this embodiment, it should be noted that the manufacturing equipment may include: a processor 1310, a communications interface 1320, a memory 1330 and a communication bus 1340, wherein the processor 1310, the communications interface 1320, and the memory 1330 communicate with each other through the communication bus 1340. The processor 1310 can call the logic instructions in the memory 1330 to execute S110 in the manufacturing method in the first embodiment: by etching, a groove network is formed on the substrate along a predetermined direction to form the substrate into an integrated structure, the predetermined direction is a vertical direction extending from the top surface of the substrate to the bottom surface, the groove network includes at least one groove, and at least one groove is surrounded by the integrated structure; S120: by deposition, a bottom electrode is formed on the groove bottom surface and groove side surface of the groove network and the top surface of the integrated structure, and the bottom electrode covers the groove bottom surface and groove side surface of the groove network and the top surface of the integrated structure; S130: by deposition, a dielectric layer is formed on the top surface of the bottom electrode, and the dielectric layer covers the bottom electrode; S140: by deposition, a top electrode is formed on the top surface of the dielectric layer, the top electrode is constructed to fill each groove in the groove network, so that the top surface of the top electrode is parallel to the bottom surface of the substrate, and the bottom electrode, the dielectric layer and the top electrode together constitute a single-layer MIM structure.

[0098] In addition, the processor 1310 can call the logic instructions in the memory 1330 to execute S210 in the manufacturing method in the second embodiment: by etching, a groove network is formed on the substrate along a predetermined direction to form the substrate into an integrated structure, the predetermined direction is a vertical direction extending from the top surface of the substrate to the bottom surface, the groove network includes at least one groove, and at least one groove is surrounded by the integrated structure; S220: by deposition, a bottom electrode is formed on the groove bottom surface and groove side surface of the groove network and the top surface of the integrated structure, and the bottom electrode covers the groove bottom surface and groove side surface of the groove network and the top surface of the integrated structure; S230: by deposition , forming a first dielectric layer on the top surface of the bottom electrode, the first dielectric layer covering the bottom electrode; S240: forming an intermediate electrode layer on the top surface of the first dielectric layer by deposition, the intermediate electrode layer covering the first dielectric layer; S250: forming a second dielectric layer on the top surface of the intermediate electrode layer by deposition, the second dielectric layer covering the intermediate electrode layer; S260: forming a top electrode on the top surface of the second dielectric layer by deposition, the top electrode being configured to fill each groove in the groove network so that the top surface of the top electrode is parallel to the bottom surface of the substrate, and the bottom electrode, the first dielectric layer, the intermediate electrode layer, the second dielectric layer and the top electrode together constitute a double-layer MIM structure.

[0099] In addition, the processor 710 can call the logic instructions in the memory 730 to execute S310 in the manufacturing method in the third embodiment: by etching, a groove network is formed on the substrate along a predetermined direction to form the substrate into an integrated structure, the predetermined direction is a vertical direction extending from the top surface of the substrate to the bottom surface, the groove network includes at least one groove, and at least one groove is surrounded by the integrated structure; S320: by deposition, at least one layer of MIM structure is formed on the substrate, the at least one layer of MIM structure includes a single-layer MIM structure and a double-layer MIM structure, the single-layer MIM structure includes a bottom electrode, a dielectric layer, and a top electrode in sequence, the bottom electrode is formed on the groove bottom surface and groove side surface of the groove network and the top surface of the integrated structure by deposition, the dielectric layer is formed on the bottom electrode by deposition, and the top electrode is formed on the dielectric layer by deposition, the bottom electrode covers the groove bottom surface and groove side surface of the groove network and the top surface of the integrated structure The double-layer MIM structure comprises a bottom electrode, a first dielectric layer, an intermediate electrode, a second dielectric layer, and a top electrode in sequence. The bottom electrode is formed on the bottom surface and the side surface of the grooves of the groove network and the top surface of the integrated structure by deposition. The first dielectric layer is formed on the bottom electrode by deposition. The intermediate electrode is formed on the first dielectric layer by deposition. The second dielectric layer is formed on the intermediate electrode by deposition. The top electrode is formed on the second dielectric layer by deposition. The bottom electrode covers the bottom surface and the side surface of the grooves of the groove network and the top surface of the integrated structure. The first dielectric layer covers the bottom electrode, the intermediate electrode layer covers the first dielectric layer, and the second dielectric layer covers the intermediate electrode layer. The top electrode is constructed to fill each groove in the groove network so that the top surface of the top electrode is parallel to the bottom surface of the substrate.

[0100] In addition, the logic instructions in the above-mentioned memory 1330 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0101] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0102] In addition, in the present invention, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0103] In addition, in the present invention, the description with reference to the terms "embodiment", "present embodiment", "another embodiment", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a silicon capacitor, characterized in that: include: By etching, a groove network is formed on the substrate along a predetermined direction to form the substrate into an integral structure, wherein the predetermined direction is a vertical direction extending from the top surface to the bottom surface of the substrate, the groove network includes at least one groove, and the at least one groove is surrounded by the integral structure; By deposition, a bottom electrode is formed on the groove bottom surface and the groove side surface of the groove network and the top surface of the integrated structure, wherein the bottom electrode covers the groove bottom surface and the groove side surface of the groove network and the top surface of the integrated structure; Forming a dielectric layer on the top surface of the bottom electrode by deposition, wherein the dielectric layer covers the bottom electrode; A top electrode is formed on the top surface of the dielectric layer by deposition, and the top electrode is configured to fill each groove in the groove network so that the top surface of the top electrode is parallel to the bottom surface of the substrate, and the bottom electrode, the dielectric layer and the top electrode together constitute a single-layer MIM structure.

2. The method for manufacturing a silicon capacitor according to claim 1, wherein: The groove network is configured as at least one of a cylinder, a truncated cone, a cone, a prism, a truncated cone, and a pyramid; The material of the substrate is silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, silicon on insulator, germanium on insulator, glass or quartz; The etching includes dry etching or wet etching; The deposition includes physical vapor deposition, chemical vapor deposition and atomic layer deposition.

3. A method for manufacturing a silicon capacitor, characterized in that: include: By etching, a groove network is formed on the substrate along a predetermined direction to form the substrate into an integral structure, wherein the predetermined direction is a vertical direction extending from the top surface to the bottom surface of the substrate, the groove network includes at least one groove, and the at least one groove is surrounded by the integral structure; By deposition, a bottom electrode is formed on the groove bottom surface and the groove side surface of the groove network and the top surface of the integrated structure, wherein the bottom electrode covers the groove bottom surface and the groove side surface of the groove network and the top surface of the integrated structure; Forming a first dielectric layer on the top surface of the bottom electrode by deposition, wherein the first dielectric layer covers the bottom electrode; forming an intermediate electrode layer on the top surface of the first dielectric layer by deposition, wherein the intermediate electrode layer covers the first dielectric layer; forming a second dielectric layer on the top surface of the intermediate electrode layer by deposition, wherein the second dielectric layer covers the intermediate electrode layer; A top electrode is formed on the top surface of the second dielectric layer by deposition, and the top electrode is configured to fill each groove in the groove network so that the top surface of the top electrode is parallel to the bottom surface of the substrate, and the bottom electrode, the first dielectric layer, the middle electrode layer, the second dielectric layer and the top electrode together constitute a double-layer MIM structure.

4. The method for manufacturing a silicon capacitor according to claim 3, wherein: The groove network is configured as at least one of a cylinder, a cone, a frustum, a prism, a frustum, and a pyramid; The material of the substrate is silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, silicon on insulator, germanium on insulator, glass or quartz; The etching includes dry etching or wet etching; The deposition includes physical vapor deposition, chemical vapor deposition and atomic layer deposition.

5. A method for manufacturing a silicon capacitor, characterized in that: include: By etching, a groove network is formed on the substrate along a predetermined direction to form the substrate into an integral structure, wherein the predetermined direction is a vertical direction extending from the top surface to the bottom surface of the substrate, the groove network includes at least one groove, and the at least one groove is surrounded by the integral structure; By deposition, at least one MIM structure is formed on the substrate, wherein the at least one MIM structure includes a single-layer MIM structure and a double-layer MIM structure. The single-layer MIM structure comprises a bottom electrode, a dielectric layer, and a top electrode in sequence, wherein the bottom electrode is formed on the bottom surface and the side surface of the grooves of the groove network and the top surface of the integrated structure by deposition, the dielectric layer is formed on the bottom electrode by deposition, and the top electrode is formed on the dielectric layer by deposition, the bottom electrode covers the bottom surface and the side surface of the grooves of the groove network and the top surface of the integrated structure, the dielectric layer covers the bottom electrode, and the top electrode is configured to fill each groove in the groove network so that the top surface of the top electrode is parallel to the bottom surface of the substrate, The double-layer MIM structure includes a bottom electrode, a first dielectric layer, an intermediate electrode, a second dielectric layer, and a top electrode in sequence. The bottom electrode is formed on the bottom surface and the side surface of the grooves of the groove network and the top surface of the integrated structure by deposition. The first dielectric layer is formed on the bottom electrode by deposition. The intermediate electrode is formed on the first dielectric layer by deposition. The second dielectric layer is formed on the intermediate electrode by deposition. The top electrode is formed on the second dielectric layer by deposition. The bottom electrode covers the bottom surface and the side surface of the grooves of the groove network and the top surface of the integrated structure. The first dielectric layer covers the bottom electrode, the intermediate electrode layer covers the first dielectric layer, the second dielectric layer covers the intermediate electrode layer, and the top electrode is constructed to fill each groove in the groove network so that the top surface of the top electrode is parallel to the bottom surface of the substrate.

6. The method for manufacturing a silicon capacitor according to claim 5, wherein: The groove network is configured as at least one of a cylinder, a truncated cone, a cone, a prism, a truncated cone, and a pyramid; The material of the substrate is silicon, silicon carbide, gallium arsenide, gallium nitride, germanium, silicon on insulator, germanium on insulator, glass or quartz; The etching includes dry etching or wet etching; The deposition includes physical vapor deposition, chemical vapor deposition and atomic layer deposition.

7. A manufacturing device for silicon capacitors, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the processor implements the steps of the method for manufacturing a silicon capacitor according to any one of claims 1 to 6 to manufacture the silicon capacitor.

8. A silicon capacitor, characterized in that: The silicon capacitor is manufactured according to the method for manufacturing a silicon capacitor according to claim 1 or 2 and based on the silicon capacitor manufacturing equipment according to claim 7, and the silicon capacitor has a single-layer MIM structure.

9. A silicon capacitor, characterized in that: The silicon capacitor is manufactured according to the method for manufacturing a silicon capacitor according to claim 3 or 4 and based on the silicon capacitor manufacturing equipment according to claim 7, and the silicon capacitor has a double-layer MIM structure.

10. A silicon capacitor, characterized in that: The silicon capacitor is manufactured according to the method for manufacturing a silicon capacitor according to claim 5 or 6 and based on the silicon capacitor manufacturing equipment according to claim 7, and the silicon capacitor has at least one MIM structure.

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