GaN HEMT device with high gate reliability and preparation method thereof

Abstract

The invention discloses a GaN HEMT (High Electron Mobility Transistor) device with high gate reliability and a preparation method thereof. The preparation method comprises the following steps: providing a basic structure; sequentially forming a p-type GaN layer, a gate material layer, a dielectric mask layer and a metal mask layer; patterning etching is carried out; carrying out wet etching on the metal mask structure, and meanwhile, generating a corrosion effect on the side surface of the grid precursor to form a grid; performing dry etching to form a p-type GaN structure; performing plasma treatment on the side surface; and respectively manufacturing and forming a source electrode and a drain electrode. Dry etching is replaced by wet etching to form a structure that the p-type GaN structure extends to the source and drain sides, grid self-alignment etching is achieved, the uniformity and controllability of an extension area are improved, the technological process is simplified, the repeatability of device structure preparation is guaranteed, meanwhile, plasma is used for treating and passivating the side wall, and the device structure is more stable in performance. Current leakage caused by a surface state and surface roughness is suppressed, off-state leakage of the device is greatly reduced, and reliability is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of GaN devices, and in particular to a GaN HEMT device with high gate reliability and a preparation method thereof. Background Art

[0002] Group III nitrides belong to the third generation of semiconductor materials. They have the characteristics of large bandgap, high electron saturation velocity, high thermal conductivity, high voltage resistance, and radiation resistance. They are ideal materials that meet the performance requirements of the next generation of power electronic devices. AlGaN / GaN heterojunction is the basic structure of GaN-based HEMT devices. Due to the spontaneous polarization and piezoelectric polarization effects of GaN materials, a high concentration of two-dimensional electron gas (2DEG) is generated in the heterojunction. Therefore, traditional HEMT devices are in the on state when the gate is not biased, and the threshold voltage is negative, which is a depletion-type device. When existing HEMT devices are used as power switching devices, enhancement-mode HEMT devices meet the requirements of high safety, low loss and simplification of circuit design better than depletion-mode devices.

[0003] There are currently four main solutions for achieving enhanced HEMT, including: cascode structure, groove gate structure, p-type cap layer and F injection technology. Among these four solutions for achieving enhanced HEMT, HEMT devices based on p-type gate have excellent performance and stable turn-on voltage. They have been successfully commercialized and have shown broad development prospects. Existing p-type gate HEMT devices are mainly realized by selective etching, selective epitaxy or H plasma passivation, but these methods all have defects.

[0004] For the selective epitaxial p-type GaN method, the device performance is affected by many factors such as the mask material and the conditions in the growth reaction chamber, resulting in high interface states in the device. The process is cumbersome, difficult to implement, and has poor process repeatability. For the H plasma passivation method, the thermal stability of the device is poor. The H plasma will diffuse under thermal stress, resulting in the drift of the device turn-on voltage, and the process is difficult to control. At present, the production and preparation of commercial P-GaN HEMT devices are mostly completed by P-GaN etching. The high gate off-state leakage caused by etching damage affects the reliability of the device. Therefore, in order to minimize the impact of the etching process on the device performance, the industry currently usually adopts the method of expanding the width of the P-GaN under the gate to both sides of the source and drain compared to the gate metal to form an etching damage buffer zone, avoiding direct contact between the etched sidewall and the gate metal to reduce the gate off-state leakage. The process for preparing such devices is relatively complicated, and the improvement of gate leakage is not obvious. The surface roughness caused by multiple etchings and the barrier layer damage caused by over-etching greatly affect the saturation current and breakdown voltage of the device.

[0005] It can be seen that the current preparation of p-type gate HEMT devices still has more or less problems such as etching damage, poor repeatability, high interface state, and poor thermal stability. Summary of the invention

[0006] In view of the deficiencies of the prior art, an object of the present invention is to provide a GaN HEMT device with high gate reliability and a preparation method thereof.

[0007] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention includes: In a first aspect, the present invention provides a method for preparing a GaN HEMT device with high gate reliability, comprising: providing a base structure, the base structure comprising a channel layer; forming a p-type GaN layer, a gate material layer, a dielectric mask layer and a metal mask layer in sequence on the surface of the base structure; Performing patterned etching to remove the gate material layer, the dielectric mask layer and the metal mask layer in the non-gate region, and the remaining portions are used as a gate precursor, a dielectric mask structure and a metal mask structure respectively; The metal mask structure is wet-etched by using an etching liquid, and the etching liquid simultaneously etches the side of the gate precursor, so as to reduce the width of the gate precursor and form a gate; Using the dielectric mask structure with two sides protruding from the gate as a shield, dry-etching the p-type GaN layer to remove the p-type GaN layer in the non-gate region to form a p-type GaN structure; Performing plasma treatment on at least a side surface of the p-type GaN structure; And, on the surface of the base structure, a source electrode and a drain electrode are respectively formed on both sides of the gate region.

[0008] In a second aspect, the present invention further provides a GaN HEMT device with high gate reliability obtained by the above-mentioned preparation method, which comprises a base structure, a gate structure, a source electrode and a drain electrode; The base structure includes a channel layer, the gate structure is formed on the surface of the base structure and has a p-type GaN structure and a gate which are stacked in sequence in a direction away from the base structure, and on both sides of the gate, the p-type GaN structure has an extension area protruding from the gate, and the extension area or the side wall of the extension area is plasma treated; the source and the drain are respectively arranged on both sides of the gate structure.

[0009] Based on the above technical solution, compared with the prior art, the beneficial effects of the present invention at least include: The technical solution provided by the present invention forms a structure in which a p-type GaN structure extends to both sides of the source and drain by wet etching instead of dry etching, so that self-aligned etching of the gate can be realized, and the uniformity and controllability of the extension area of ​​the p-type GaN structure on both sides of the gate are improved, the process flow is simplified, and the repeatability of device structure preparation is ensured. At the same time, plasma treatment is used to passivate the side wall of the p-type GaN structure to suppress current leakage caused by surface states and surface roughness. While simplifying the device preparation process, the off-state leakage of the device is greatly reduced, and the reliability of the device is improved.

[0010] The above description is only an overview of the technical solution of the present invention. In order to enable those skilled in the art to more clearly understand the technical means of the present application and implement them according to the contents of the specification, the following is a description of the preferred embodiments of the present invention in conjunction with detailed drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a structural schematic diagram of a GaN HEMT device provided by a typical implementation case of the present invention; Figure 2 It is a schematic diagram of some process states of a preparation process of a GaN HEMT device provided by a typical implementation case of the present invention; Figure 3 It is a schematic diagram of some process states of a preparation process of a GaN HEMT device provided by a typical implementation case of the present invention; Figure 4 It is a schematic diagram of some process states of a preparation process of a GaN HEMT device provided by a typical implementation case of the present invention; Figure 5 It is a schematic diagram of some process states of a preparation process of a GaN HEMT device provided by a typical implementation case of the present invention; Figure 6 It is a schematic diagram of some process states of a preparation process of a GaN HEMT device provided by a typical implementation case of the present invention; Figure 7 It is a schematic diagram of some process states of a preparation process of a GaN HEMT device provided by a typical implementation case of the present invention; Figure 8 It is a schematic diagram of some process states of a preparation process of a GaN HEMT device provided by a typical implementation case of the present invention; Fig. 9 It is a schematic diagram of some process states of a preparation process of a GaN HEMT device provided by a typical implementation case of the present invention; Fig.10 It is a schematic diagram of some process states of a preparation process of a GaN HEMT device provided by another typical embodiment of the present invention; Fig.11It is a microphotograph of the photoresist residue during the wet etching process provided by a typical comparative case of the present invention; Fig.12 This is a micrograph of the photoresist residue during the wet etching process provided by a typical embodiment of the present invention; Fig.13 This is a transfer curve test diagram of a GaN HEMT device provided by a typical implementation case of the present invention; Fig.14 This is an output curve test diagram of a GaN HEMT device provided by a typical implementation case of the present invention; Fig.15 This is a gate leakage test diagram of a GaN HEMT device provided by a typical implementation example of the present invention; Fig.16 This is a cross-sectional electron microscope photograph of a GaN HEMT device cut by FIB according to a typical embodiment of the present invention; Fig.17 It is a schematic diagram of the process of forming an extension area by dry etching provided by a typical comparative case of the present invention. DETAILED DESCRIPTION

[0012] In view of the deficiencies in the prior art, the inventor of this case has proposed the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.

[0013] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0014] Moreover, relational terms such as “first” and “second” are merely used to distinguish one component or method step from another with the same name, but do not necessarily require or imply any such actual relationship or order between these components or method steps.

[0015] An embodiment of the present invention provides a method for preparing a GaN HEMT device with high gate reliability, which comprises the following steps: providing a base structure, the base structure comprising a channel layer; forming a p-type GaN layer (hereinafter referred to as P-GaN), a gate material layer, a dielectric mask layer and a metal mask layer in sequence on the surface of the base structure; Performing patterned etching to remove the gate material layer, the dielectric mask layer and the metal mask layer in the non-gate region, and the remaining portions are used as a gate precursor, a dielectric mask structure and a metal mask structure respectively; The metal mask structure is wet-etched by using an etching liquid, and the etching liquid simultaneously etches the side of the gate precursor, so as to reduce the width of the gate precursor and form a gate; Using the dielectric mask structure with two sides protruding from the gate as a shield, dry-etching the p-type GaN layer to remove the p-type GaN layer in the non-gate region to form a p-type GaN structure; Performing plasma treatment on at least a side surface of the p-type GaN structure; And, on the surface of the base structure, a source electrode and a drain electrode are respectively formed on both sides of the gate region.

[0016] An important implementation detail of the present invention is that when patterned etching is performed, the etching stops at the upper surface of the p-type GaN layer, and only the gate material layer, dielectric mask layer and metal mask layer in the non-gate area are removed. This is because if a multi-layer etching method is adopted to directly etch to the lower surface of the p-type GaN layer, for example, in the implementation case shown below, three plasma etchings are performed successively, using Cl2 to etch metal chromium, SF6 to etch SiO2 and TiN, and Cl2 / Ar / O2 to etch p-GaN. After all three plasma etchings are completed. When cleaning the photoresist, it is found that the densely adhered photoresist on the side wall cannot be effectively removed due to multiple etchings, which will cause the TiN side wall to affect the effect of wet etching due to the adhered photoresist. For example, in the specific experimental case, Fig.11 As shown, a large amount of photoresist residue that cannot be removed can be seen.

[0017] Therefore, the technical solution provided by the present invention adopts the implementation sequence of cleaning and removing the photoresist after the etching of the gate material layer, the dielectric mask layer and the metal mask layer is completed, and then the p-type GaN layer is etched, so that the photoresist is prevented from repeated plasma bombardment, and the photoresist adhering to the side wall can be effectively removed, so that the gate material layer can be effectively and fully contacted with the etching liquid to complete the patterned etching, forming a side wall with excellent morphology. The etching effect in specific applications can be seen in Fig.12 shown.

[0018] In some embodiments, the plasma treatment process specifically includes the following steps: After removing the dielectric mask structure, plasma is used to treat the protrusions on both sides of the p-type GaN structure and part of the material of the gate.

[0019] Or in some embodiments, the dielectric mask structure is used as a shielding body and both sides of the p-type GaN structure are treated with plasma without removing the dielectric mask structure.

[0020] In some embodiments, the etching solution includes a base solution and a catalyst, the base solution is corrosive to the metal mask layer, and the catalyst is used to increase the reaction rate of the etching solution and the gate precursor.

[0021] In some embodiments, the gate material layer is made of TiN, and the catalyst includes a Cr element introduced by dissolving the metal mask layer in the base solution.

[0022] The proportion of the etching solution can be referred to the content of the examples of the present invention below. In the application, the inventors of the present invention found that when the metal mask layer contains or is entirely composed of Cr elements, the dissolved Cr elements promote the corrosion of TiN.

[0023] In the preferred embodiment of the present invention, the topmost Cr metal mask layer not only plays a role of patterned covering, but also serves as a catalyst for the corrosion reaction. While Cr corrosion is being carried out, the pH value of the solution gradually increases, thereby achieving the effect of catalytic corrosion of TiN. In addition, the etching solution containing the Cr element has strong oxidizing properties, which is another factor that promotes TiN corrosion.

[0024] Of course, the above situation belongs to the preferred situation based on the basic inventive concept provided by the present invention, and does not mean that the present invention can only be implemented through the above situation; in fact, quite a number of wet etching solutions can achieve the synchronous corrosion reaction of the metal mask layer and the gate material layer, and those skilled in the art are fully capable of appropriately referring to the existing technical literature to select the appropriate formula or obtain the optimal composition and ratio through a limited number of experiments.

[0025] In some embodiments, the patterned etching process specifically includes the following steps: Covering the surface of the metal mask layer with a photoresist layer; Performing patterned illumination and development on the photoresist layer to form a photoresist layer; The photoresist layer is used as a shield, and the gate material layer, the dielectric mask layer and the metal mask layer are etched using a first plasma, wherein the gas used to generate the first plasma includes a chlorine-based gas and a fluorine-based gas.

[0026] In some embodiments, the dry etching specifically includes: using a second plasma to etch the p-type GaN layer, and the gas generating the second plasma includes any one of chlorine, oxygen, and argon, or a combination of two or more thereof. As some typical examples, the embodiments of the present invention generally use the above three gases to form a mixed gas for dry etching, but it does not exclude the use of other plasma gases or the use of the above two or even only one of them to achieve dry etching. As long as the etching target of the p-type GaN layer can be achieved, those skilled in the art can arbitrarily replace the etching gas and find suitable etching conditions on the basis of achieving this function, and are not limited to the limited number of implementation cases specifically exemplified in the present invention.

[0027] In the above technical solution, inductively coupled plasma of Cl2 / Ar / O2 mixed gas is used for etching. This etching method is an etching method that combines chemical reaction etching and physical bombardment, so that the etching process can effectively stop at the p-type GaN layer, achieving precise etching.

[0028] In some embodiments, the dielectric mask layer has a thickness of 100-300 nm, with a typical thickness of 200 nm; In some embodiments, the metal mask layer has a thickness of 20-80 nm, with a typical thickness of 50 nm.

[0029] In some typical implementation cases of the present invention, for the problems existing in the preparation of P-GaN HEMT enhanced devices in the background technology, a solution is proposed to wet-etch TiN gate metal using Cr-catalyzed Cr etching solution and treat the P-GaN extension area in the gate area with in-situ masked hydrogen plasma. This solution can form a structure in which P-GaN extends to both sides of the source and drain by wet etching instead of dry etching, can realize gate self-aligned etching, improve the uniformity and controllability of the p-GaN area on both sides of TiN, simplify the process flow, ensure the repeatability of device structure preparation, and use hydrogen plasma to passivate the P-GaN sidewall after etching to suppress the current leakage path caused by surface states and surface roughness. While simplifying the device preparation process, it greatly reduces the off-state leakage of the device and improves the reliability of the device.

[0030] Specific process may include: 1. If Figure 2 As shown, a Si-based PGaN epitaxial wafer is obtained and the wafer is cleaned.

[0031] 2. If Figure 3 As shown, gate metal titanium nitride is grown on the wafer and hard mask silicon dioxide and chromium are etched in sequence.

[0032] 3. If Figure 4As shown, after HMDS pretreatment, photoresist spin coating is performed, the photoresist type is AZ5214 positive photoresist, and then photolithography, exposure, and development are performed to reveal the etching pattern.

[0033] 4. If Figure 5 As shown, chlorine-based gas and fluorine-based gas are used to perform patterned etching on the etching hard mask and gate metal titanium nitride through an inductively coupled plasma etching device.

[0034] 5. If Figure 6 As shown, firstly, organic cleaning is performed to remove the photoresist, and then the sample is immersed in a Cr etching solution to uniformly etch TiN along the source and drain direction while removing the metal chromium. In this step, the corrosion rate of TiN by the conventional Cr etching solution alone is very low. The preferred embodiment is to add Cr metal as a catalyst, which can greatly increase the corrosion rate of TiN.

[0035] 6. If Figure 7 As shown, using silicon dioxide as a hard mask, chlorine / oxygen / argon is used to etch P-GaN with high selectivity. Due to the wet etching mentioned in item 5, when the P-GaN etching is completed, the width of the P-GaN under the gate along the source and drain direction will also be greater than the width of the gate metal, thus forming an etching damaged buffer zone called the P-GaN extension in the gate area.

[0036] 7. If Figure 8 As shown, a metal stack of Ti / Al / Ni / Au is deposited using electron beam evaporation, ohmic patterning is accomplished by a lift-off process, and then rapid thermal annealing is performed.

[0037] 8. If Fig. 9 As shown, hydrogen plasma treatment of the P-GaN in the P-GaN extension portion of the gate region effectively compensates for the defect states caused by magnesium acceptors and etching damage on the P-GaN sidewalls, avoiding the concentration of the electric field peak and the sidewall leakage path.

[0038] In addition, regarding the plasma treatment, it is also possible to Fig.10 As shown, without removing the silicon dioxide mask, only the sidewall of the P-GaN is processed by plasma, which greatly reduces the processed area of ​​the surface and avoids damage.

[0039] Specifically, Fig. 9 In the embodiment shown in FIG. 1 , when H plasma treatment is performed on the gate, it is inevitable that the hole concentration under the gate will be affected, thereby affecting the threshold voltage. However, in FIG. Fig.10 The structure is treated with H plasma. Due to the shielding effect of SiO2, the hole concentration in the P-GaN in the gate area can be protected from being affected by the H plasma treatment to a certain extent; at the same time, the P-GaN sidewall can also be passivated, but the passivation range is smaller than that of Fig. 9The scheme shown will be significantly reduced, so the impact on device performance is minimized.

[0040] In the above scheme, the Cr etching solution is replaced with other etching solutions that can control the corrosion of titanium nitride; the hydrogen plasma treatment is replaced with oxygen plasma treatment or nitrogen plasma treatment, which can also achieve the purpose of the present invention as long as they play the same role.

[0041] A second aspect of an embodiment of the present invention also provides a GaN HEMT device with high gate reliability obtained by the above-mentioned preparation method, which includes a base structure, a gate structure, a source and a drain; the base structure includes a channel layer, the gate structure is formed on the surface of the base structure, and has a p-type GaN structure and a gate stacked in sequence in a direction away from the base structure, and on both sides of the gate, the p-type GaN structure has an extension area protruding from the gate, and the extension area or the side wall of the extension area is plasma treated; the source and the drain are respectively arranged on both sides of the gate structure.

[0042] In some embodiments, the basic structure includes a substrate, a buffer layer, the channel layer, and a barrier layer stacked in sequence, and the gate structure, the source electrode, and the drain electrode are formed on the surface of the barrier layer.

[0043] In some embodiments, the width of the extension region is 300-600 nm, and a typical width is 450 nm, which is equivalent to the gate precursor structure being laterally etched by 450 nm.

[0044] In some embodiments, the height of the gate is 50-200 nm, with a typical height being, for example, 100 nm.

[0045] In the above implementation scheme, the key technical features are: 1. In order to form a P-GaN extension area in the gate region and simplify the process flow and production cost of the entire device preparation, a wet etching method using a chromium etching solution is proposed to laterally etch titanium nitride along the source and drain direction, replacing the process of growing a hard mask and then performing dry etching.

[0046] 2. In order to reduce the gate off-state leakage and improve device performance, a scheme of using hydrogen plasma to treat the P-GaN extension area in the gate area is proposed, which effectively compensates for the defect states caused by the Mg acceptors and etching damage on the P-GaN sidewalls, avoids the concentration of the electric field peak and the sidewall leakage path, effectively reduces the gate off-state leakage, and improves the reliability of the gate.

[0047] 3. In order to use the best process scheme to prepare P-GaN HEMT devices with good performance, we have carefully designed and experimentally compared the sequence of process steps and specific technical indicators for the entire device preparation. The sequence of process steps for device preparation described in the present invention will have a great impact on the device yield and performance. Therefore, strictly implementing the process flow described in the present invention is an important guarantee to ensure that the device has high yield and high performance, and is compatible with industrial production.

[0048] Based on the above characteristics, the advantages of the present invention compared with the general prior art are: 1. Regarding the preparation process of the P-GaN extension area in the gate region, the preparation process of the P-GaN extension area in the gate region is usually achieved by dry etching after growing a hard mask. The introduction of a new dry etching process undoubtedly increases the complexity of the process preparation. At the same time, in order to ensure that the hard mask outside the gate area is completely etched, a certain amount of over-etching is usually required. Multiple over-etching in the process is bound to affect our control of the etching steps. Therefore, the process has high requirements on technology and equipment, and the process complexity and the variables that need to be taken into account in the process are increasing.

[0049] The present invention is different from the above method in that a low-cost and effective wet etching is used instead of the above dry etching, which can achieve the same or even better effect than dry etching. The use of wet etching to prepare the P-GaN extension region in the gate region greatly simplifies the process flow of preparing P-GaN HEMT devices by a self-aligned gate-first etching process, while ensuring the yield rate and improving the production efficiency. At the same time, the gate structure formed by wet etching has better bilateral symmetry, smoothness and steepness of the side walls than dry etching, and these indicators are key factors in improving the electrical performance of the device.

[0050] 2. In terms of methods to reduce gate off-state leakage, in order to reduce the off-state leakage of P-GaN HEMT devices and improve gate reliability, GaON, Ga2O3, etc. are usually inserted between P-GaN and the gate metal as an enhancement, or i-GaN is epitaxially grown on the surface of P-GaN. Currently, the implementation of these technologies requires the growth of a new epitaxial layer on the surface of P-GaN and a high-temperature annealing process. The impact of new epitaxial growth on the surface of P-GaN on the magnesium doping in P-GaN is difficult to control. At the same time, the high-temperature annealing process will also add additional thermal budget to the entire process manufacturing. The process technology is complex and the production cost will also increase.

[0051] The present invention is different from the above method in that the preparation of a P-GaN HEMT device with low gate off-state leakage is well achieved by utilizing hydrogen plasma treatment. By treating the extended area of ​​P-GaN with hydrogen plasma, the defect states caused by Mg acceptors and etching damage on the P-GaN sidewalls are effectively compensated, the concentration of the electric field peak and the path of sidewall leakage are avoided, the gate off-state leakage is effectively reduced, and the reliability of the gate is improved. The solution has simple process operation and high repeatability, is very suitable for industrial production, and is a low-cost and high-efficiency solution.

[0052] 3. In terms of device preparation process and good threshold voltage, P-GaN HEMT devices are currently prepared by gate-first etching technology. In order to ensure the electrical performance and gate reliability of the device, some optimization solutions are usually introduced. These technical solutions do improve the device performance to a certain extent. However, the technical difficulty is high, which increases the process complexity and the difficulty of industrial production. At the same time, P-GaN HEMT devices realized by non-etching process, although to a certain extent, avoid the impact of some etching technologies on device performance, but the problem of negative drift of threshold voltage has always affected the safe use of switching devices.

[0053] However, the device preparation scheme proposed in the present invention has good device performance, with a forward threshold voltage of 2V and an off-state leakage of 1.4E-06mA / mm, which simplifies the process flow while improving device performance, and ensures the repeatable implementation of key technologies and the advantages of compatibility with industrial production possibilities.

[0054] The technical solution of the present invention is further described in detail below through several embodiments and in conjunction with the accompanying drawings. However, the selected embodiments are only used to illustrate the present invention, and do not limit the scope of the present invention.

[0055] It should also be noted that the preparation method provided by the present invention is not limited to the process methods and conditions of a specific step, such as the conditions and methods for depositing p-GaN, the deposition methods and conditions for forming a metal chromium layer, etc., as long as various material layers with corresponding characteristics and thicknesses can be formed. The main inventive concept of the present invention is embodied in the overall preparation process.

[0056] Example 1 This embodiment illustrates a preparation process of a GaN HEMT device, which is specifically as follows: (1) AlGaN / GaN epitaxial layer and p-GaN layer are grown on the substrate by metal organic compound chemical vapor deposition, wherein the thickness of GaN is 2 μm, the thickness of AlGaN is 20 nm, the molar content of Al element is 18%, the thickness of p-GaN is 70 nm, and the Mg doping concentration is 3×10 19 Magnitude.

[0057] (2) F ion implantation isolation is used to isolate the wafer from the mesa. The mesa isolation area is determined by photolithography, and the specific steps of photolithography include pretreatment, photoresist, pre-baking, exposure and development.

[0058] (3) Titanium nitride (100 nm thick) is deposited on the entire surface of the sample using a magnetron sputtering device. A hard mask silicon dioxide (200 nm thick) is grown and etched using plasma enhanced chemical vapor deposition. The top metal etch mask chromium is deposited using a magnetron sputtering device (50 nm thick).

[0059] (4) Expose the non-gate area through post-photolithography development. After determining the etching area, first use the inductively coupled plasma etching equipment to introduce chlorine-based gas to etch chromium, and then use the inductively coupled plasma etching equipment to introduce fluorine-based gas to etch silicon dioxide and titanium nitride. The etching stops on the P-GaN surface.

[0060] (5) The sample was immersed in acetone and isopropanol solutions for ultrasonic cleaning for 10 min and 5 min respectively, to effectively remove the photoresist.

[0061] (6) The sample is immersed in a chromium etching solution (the etching solution used in this embodiment is a mixed solution of potassium chromate and sulfuric acid, and the ratio is not limited. Many existing wet etching formulas can be referred to. The wet etching process is to immerse the sample in the Cr etching solution for two minutes). While removing the chromium metal, the gate metal titanium nitride is laterally corroded. The wet etching temperature is room temperature (usually 15-35°C) and the etching time is 2 minutes.

[0062] (7) Using inductively coupled plasma etching equipment, chlorine, oxygen and argon are introduced to perform high-selectivity etching on P-GaN other than the gate, and silicon dioxide is used as an etching mask.

[0063] (8) Using a 2.38% tetramethylammonium hydroxide solution heated to 85°C, the etched AlGaN surface was damaged and repaired.

[0064] (9) Before ohmic metal deposition, SiO2 was removed by soaking in BOE (7:1) for 4 minutes, and then four layers of metal Ti / Al / Ni / Au (20nm / 130nm / 50nm / 50nm) were deposited in the source and drain regions by electron beam evaporation. After evaporation, the wafer was peeled off and annealed in a rapid annealing furnace in a nitrogen atmosphere at a temperature of 850°C for 30 seconds to form an ohmic contact as the source and drain.

[0065] (10) Using gate metal titanium nitride as a mask, the wafer is treated with hydrogen plasma for 2 minutes, and then the treated wafer is annealed in a rapid thermal annealing furnace with a nitrogen atmosphere, an annealing temperature of 350° C., and a time of 5 minutes.

[0066] Finally, we got Fig. 9 The GaN HEMT device shown.

[0067] like Fig.13 As shown, the switching ratio of the device provided in this embodiment is 10 8 In this embodiment, the off-state leakage of the device is reduced by suppressing the leakage path around the gate, thereby increasing the switching ratio of the device to 10 8 , while ensuring a positive threshold voltage of 2V. Fig.14 The device's saturation current density is 12 mA / mm and its on-resistance is 38.2 Ω·mm. Fig.15 is the gate leakage of the device, where the off-state leakage is reduced to 10 6 mA / mm. Fig.16 A schematic diagram of the FIB cross-section of the gate metal TiN patterned wet etching is shown, and it can be seen that the width of the P-GaN extension area is about 450nm.

[0068] Example 2 This embodiment is substantially the same as Embodiment 1, and the main difference is that: Step (10) is moved to before the SiO2 mask structure is removed, and the blocking effect of the SiO2 mask structure is utilized to perform plasma treatment only on the side surface of the p-GaN.

[0069] This treatment method protects the hole concentration in the P-GaN in the gate region from being affected by the H plasma treatment; at the same time, the P-GaN sidewall can also be passivated, but the passivation range will be significantly reduced compared to the solution shown in the above embodiment 1, so the impact on device performance is minimized.

[0070] Comparative Example 1 The formation flow chart of conventional P-GaN extension region is as follows Fig.17 As shown, after the hard mask is etched, SiO2 is grown again on the entire surface, and then SiO2 is etched on the entire surface and stopped at the p-GaN surface. P-GaN is then etched and finally SiO2 is cleaned off to form an extended area of ​​P-GaN.

[0071] However, multiple embodiments of the present invention can avoid the process operations of re-depositing the mask etching layer and dry etching through wet etching. The above results can be achieved by simply immersing the sample in Cr etching solution after completing the hard mask etching. Not only is the process simpler, the cost is lower, the controllability is stronger, and the impact on device performance is smaller.

[0072] Based on the above embodiments and comparative examples, it can be clearly seen that the technical solution provided in the embodiments of the present invention forms a structure in which the p-type GaN structure extends to both sides of the source and drain by replacing dry etching with wet etching, which can realize gate self-aligned etching, improve the uniformity and controllability of the extended area of ​​the p-type GaN structure on both sides of the gate, simplify the process flow, ensure the repeatability of device structure preparation, and at the same time, use plasma treatment to passivate the side walls of the p-type GaN structure to suppress current leakage caused by surface states and surface roughness. While simplifying the device preparation process, it greatly reduces the off-state leakage of the device and improves the reliability of the device.

[0073] It should be understood that the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a GaN HEMT device with high gate reliability, characterized in that: include: providing a base structure, the base structure comprising a channel layer; forming a p-type GaN layer, a gate material layer, a dielectric mask layer and a metal mask layer in sequence on the surface of the base structure; Performing patterned etching to remove the gate material layer, the dielectric mask layer and the metal mask layer in the non-gate region, and the remaining portions are used as a gate precursor, a dielectric mask structure and a metal mask structure respectively; The metal mask structure is wet-etched by using an etching liquid, and the etching liquid simultaneously etches the side of the gate precursor, so as to reduce the width of the gate precursor and form a gate; Using the dielectric mask structure with two sides protruding from the gate as a shield, dry-etching the p-type GaN layer to remove the p-type GaN layer in the non-gate region to form a p-type GaN structure; Performing plasma treatment on at least a side surface of the p-type GaN structure; And, on the surface of the base structure, a source electrode and a drain electrode are respectively formed on both sides of the gate region.

2. The preparation method according to claim 1, characterized in that: The plasma treatment specifically includes: After removing the dielectric mask structure, plasma is used to treat the protrusions on both sides of the p-type GaN structure and the material of the gate; Alternatively, in a state where the dielectric mask structure is not removed, the dielectric mask structure is used as a shielding body and both sides of the p-type GaN structure are treated by plasma.

3. The preparation method according to claim 1, characterized in that: The etching solution includes a base solution and a catalyst. The base solution is corrosive to the metal mask layer. The catalyst is used to increase the reaction rate between the etching solution and the gate precursor.

4. The preparation method according to claim 3, characterized in that: The gate material layer is made of TiN, and the catalyst includes a Cr element dissolved and introduced into the base liquid by the metal mask layer.

5. The preparation method according to claim 1, characterized in that: The process of patterned etching specifically includes: Covering the surface of the metal mask layer with a photoresist layer; Performing patterned illumination and development on the photoresist layer to form a photoresist layer; The photoresist layer is used as a shield, and the gate material layer, the dielectric mask layer and the metal mask layer are etched using a first plasma, wherein the gas used to generate the first plasma includes a chlorine-based gas and a fluorine-based gas.

6. The preparation method according to claim 1, characterized in that: The dry etching specifically includes: etching the p-type GaN layer using a second plasma, and the gas used to generate the second plasma includes any one of chlorine, oxygen, and argon, or a combination of two or more thereof.

7. The preparation method according to claim 1, characterized in that: The thickness of the dielectric mask layer is 100-300 nm; And / or, the thickness of the metal mask layer is 20-80 nm.

8. A GaN HEMT device with high gate reliability obtained by the method according to any one of claims 1 to 7, characterized in that: Including base structure, gate structure, source and drain; The base structure includes a channel layer, the gate structure is formed on the surface of the base structure and has a p-type GaN structure and a gate which are stacked in sequence in a direction away from the base structure, and on both sides of the gate, the p-type GaN structure has an extension area protruding from the gate, and the extension area or the side wall of the extension area is plasma treated; the source and the drain are respectively arranged on both sides of the gate structure.

9. The GaN HEMT device according to claim 8, characterized in that: The basic structure comprises a substrate, a buffer layer, the channel layer and a barrier layer which are stacked in sequence, and the gate structure, the source electrode and the drain electrode are formed on the surface of the barrier layer.

10. The GaN HEMT device according to claim 8, characterized in that: The width of the extended region is 300-600 nm; And / or, the height of the gate is 50-200 nm.

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