GaN HEMT device and preparation method thereof

Abstract

The invention provides a GaN HEMT device and a preparation method thereof. The GaN HEMT device comprises a first substrate, a buffer layer and a channel layer, wherein the buffer layer and the channel layer are sequentially formed in the direction away from the first substrate; a barrier layer; the barrier layer covers the surface of the channel layer; the P-GaN layer covers part of the surface of the barrier layer; wherein the thickness of the part, covered by the P-GaN layer, of the barrier layer is smaller than 10 nm, and is smaller than the thickness of the rest part, not covered by the P-GaN layer, of the barrier layer; the first dielectric layer covers the barrier layer and the P-GaN layer; wherein a grid electrode is formed on the surface of the first dielectric layer on the P-GaN layer; wherein the grid electrode, the P-GaN layer and the first dielectric layer on the P-GaN layer jointly form an MIS type grid structure; and a source electrode and a drain electrode are respectively formed at two ends of the MIS type gate structure. According to the technical scheme, the problems that an existing GaN HEMT device is low in threshold voltage, capable of bearing small gate-source voltage and low in gate reliability are solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a GaN HEMT device and a preparation method thereof. Background Art

[0002] Compared with traditional Si materials, gallium nitride has a series of advantages such as high voltage resistance, high temperature resistance, high mobility, and radiation resistance. Therefore, gallium nitride semiconductor devices are currently favored by the industry. Taking GaN HEMT power devices as an example, they are mainly divided into D-mode and E-mode. Considering the driving, safety, energy saving and other requirements in practical applications, the device needs to be normally off. In this case, the traditional technology is to seal a low-voltage Si E-mode MOSFET and a GaN D-mode HEMT level into a cascode with common source and common gate, so that the entire GaN cascode is normally off; or use a P-GaN cap layer to contact AlGaN / GaN to achieve normal depletion of 2DEG.

[0003] However, among the above two solutions, the Cascode solution needs to seal a low-voltage Si MOSFET, which increases parasitic parameters and additional costs; the P-GaN cap solution has a small threshold voltage, a small gate voltage swing, and average gate reliability and anti-interference capabilities. Generally, a special gate drive needs to be designed in the application, and the same gate drive cannot be used with Si MOS, etc. Therefore, how to avoid the defects in the above-mentioned prior art is a problem to be solved by those skilled in the art. Summary of the invention

[0004] The present invention provides a GaN HEMT device and a preparation method thereof, so as to solve the problems of low threshold voltage, small tolerable gate-source voltage and low gate reliability of the existing GaN HEMT device.

[0005] According to a first aspect of the present invention, there is provided a GaN HEMT device, comprising:

[0006] A first substrate, and a buffer layer and a channel layer sequentially formed in a direction away from the first substrate;

[0007] A barrier layer; the barrier layer covers the surface of the channel layer;

[0008] A P-GaN layer, wherein the P-GaN layer covers a portion of the surface of the barrier layer; wherein the thickness of the portion of the barrier layer covered by the P-GaN layer is less than 10 nm and is less than the thickness of the remaining portion of the barrier layer not covered;

[0009] A first dielectric layer, covering the barrier layer and the P-GaN layer; wherein a gate is formed on a surface of the first dielectric layer on the P-GaN layer;

[0010] The gate, the P-GaN layer and the first dielectric layer on the P-GaN layer together form a MIS type gate structure; and a source and a drain are formed on two sides of the MIS type gate structure respectively.

[0011] Optionally, the first dielectric layer covers the barrier layer, the P-GaN layer, the source electrode and the drain electrode, or only covers the barrier layer and the P-GaN layer.

[0012] Optionally, the thickness of the first dielectric layer is 10-50 nm.

[0013] Optionally, the GaN HEMT device further includes: a second dielectric layer; the second dielectric layer covers the surface of the first dielectric layer and the gate; and the second dielectric layer is used to isolate the gate, the source and the drain.

[0014] Optionally, the GaN HEMT device further includes: the source and the drain are both in contact with the surface of the barrier layer and the side walls of the first dielectric layer and the second dielectric layer; wherein the distance between the source and the gate is smaller than the distance between the drain and the gate.

[0015] Optionally, the material of the barrier layer is AlGaN; the material of the first dielectric layer is insitu-SiN, LPCVDSiN, Al 2 O 3 or AlN; the material of the second dielectric layer is SiN, SiO 2 , SiON or a combination thereof.

[0016] According to a second aspect of the present invention, there is further provided a method for preparing a GaN HEMT device, comprising the GaN HEMT device according to any one of the first aspects of the present invention, the method comprising:

[0017] Providing the first substrate, and sequentially forming the buffer layer and the channel layer in a direction away from the first substrate;

[0018] forming the barrier layer; the barrier layer is formed on the surface of the channel layer;

[0019] The P-GaN layer is formed; the P-GaN layer covers a portion of the surface of the barrier layer; wherein the thickness of the portion of the barrier layer covered by the P-GaN layer is less than 10 nm, and is less than the thickness of the remaining portion of the barrier layer not covered;

[0020] forming the first dielectric layer; the first dielectric layer is formed on the barrier layer and the P-GaN layer; and forming the gate on the surface of the first dielectric layer on the P-GaN layer;

[0021] The gate electrode, the P-GaN layer and the first dielectric layer on the P-GaN layer together constitute the MIS type gate structure; and the source electrode and the drain electrode are respectively formed on both sides of the MIS type gate structure.

[0022] Optionally, forming the barrier layer specifically includes:

[0023] forming a first barrier layer on the channel layer in a direction away from the first substrate;

[0024] Etching a portion of the first barrier layer to expose a portion of the channel layer;

[0025] forming a second barrier layer on a portion of the surface of the channel layer and a surface and a portion of the sidewall of the first barrier layer;

[0026] The first barrier layer and the second barrier layer constitute the barrier layer.

[0027] Optionally, forming the gate on the surface of the first dielectric layer on the P-GaN layer specifically includes:

[0028] sputtering a gate metal on the first dielectric layer;

[0029] The gate metal is etched away except for the upper region of the P-GaN layer to form the gate on the surface of the first dielectric layer on the P-GaN layer.

[0030] Optionally, before forming the source and the drain on both sides of the MIS type gate structure respectively, the method further includes:

[0031] A second dielectric layer is formed; the second dielectric layer is formed on the first dielectric layer and the gate.

[0032] Optionally, the source and the drain are formed on both sides of the MIS type gate structure, respectively, including:

[0033] Sequentially etching the second dielectric layer and the two ends of the first dielectric layer in a direction close to the first substrate to form a first mesa and a second mesa on the barrier layer; wherein the distance between the first mesa and the gate is smaller than the distance between the second mesa and the gate;

[0034] Depositing a metal layer; the metal layer covers the surfaces of the first mesa, the second mesa and the second dielectric layer;

[0035] The metal layer on the second dielectric layer is etched away to form the source electrode on the first mesa; and the drain electrode is formed on the second mesa.

[0036] Optionally, after forming the P-GaN layer, the method further includes:

[0037] forming the source electrode and the drain electrode; the source electrode and the drain electrode are formed at two ends of the surface of the barrier layer;

[0038] The first dielectric layer is formed; the first dielectric layer is formed on the barrier layer, the P-GaN layer, the source electrode and the drain electrode; and the gate electrode is formed on the surface of the first dielectric layer on the P-GaN layer.

[0039] Optionally, forming the source and the drain specifically includes:

[0040] Depositing metal; to form a metal layer on the surface of the barrier layer and the P-GaN layer;

[0041] Etching away the metal layer in the middle region of the barrier layer to form the source electrode and the drain electrode at two ends of the surface of the barrier layer respectively;

[0042] Wherein, the distance between the source electrode and the gate electrode is smaller than the distance between the drain electrode and the gate electrode.

[0043] According to a third aspect of the present invention, there is provided an electronic device, comprising the GaN HEMT device according to any one of the first aspects of the present invention.

[0044] According to a fourth aspect of the present invention, there is further provided a method for preparing an electronic device, comprising the method for preparing a GaN HEMT device according to any one of the second aspects of the present invention.

[0045] The GaN HEMT device provided by the present invention can enhance the depletion capability of the P-GaN layer for the 2DEG generated by the region below the barrier layer by arranging a P-GaN layer on the barrier layer, and making the thickness of the portion of the barrier layer covered by the P-GaN layer less than 10 nm and less than the thickness of the remaining uncovered portion of the barrier layer, so that the GaN HEMT device requires a larger gate-source voltage to form a conductive path between the source and the drain, thereby improving the threshold voltage of the GaN HEMT device. At the same time, by forming a first dielectric layer on the barrier layer and the P-GaN layer, and forming a gate on the first dielectric layer, compared with the traditional GaN HEMT device structure, the present invention enables the P-GaN layer, the gate and the first dielectric layer on the P-GaN layer to jointly form a MIS-type gate structure, which can further improve the threshold voltage of the GaN HEMT device. Compared with the traditional P-GaN gate, the MIS-type gate structure improves the withstand voltage and reliability of the gate and reduces the gate leakage. In addition, the first dielectric layer can also passivate the surface of the barrier layer to prevent the generation of surface states on the barrier layer, thereby ensuring the good performance of the GaN HEMT device.

[0046] Furthermore, by setting the thickness of the first dielectric layer to 10-50 nm, the first dielectric layer can play a role in blocking conduction, reduce the leakage of the gate, and improve the reliability of the gate.

[0047] Furthermore, in the method for preparing a GaN HEMT device provided by the present invention, a P-GaN layer covers a portion of the surface of the barrier layer; wherein the thickness of the portion of the barrier layer covered by the P-GaN layer is less than 10 nm and less than the thickness of the remaining uncovered portion of the barrier layer; and the threshold voltage of the GaN HEMT device is improved.

[0048] Furthermore, the method for preparing a GaN HEMT device provided by the present invention can ensure the stability and uniformity of the barrier layer by etching the first barrier layer and forming the second barrier layer on the first barrier layer, thereby making the GaN HEMT device more stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0050] Figure 1 It is a schematic flow chart of a method for preparing a GaN HEMT device provided by an embodiment of the present invention;

[0051] Figure 2 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 1 ;

[0052] Figure 3 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 2 ;

[0053] Figure 4 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 3 ;

[0054] Figure 5 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 4 ;

[0055] Figure 6 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 5 ;

[0056] Figure 7 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 6 ;

[0057] Figure 8 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 7 ;

[0058] Fig. 9 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 8 ;

[0059] Fig.10 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 9 ;

[0060] Fig.11 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 10 ;

[0061] Fig.12 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 10 one;

[0062] Fig.13 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 10 two;

[0063] Fig.14 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 10 three;

[0064] Fig.15 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 10 Four;

[0065] Fig.16 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 10 five;

[0066] Fig.17 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 10 six;

[0067] Fig.18 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 10 seven;

[0068] Fig.19 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 10 eight;

[0069] Fig. 20 Schematic diagram of the device structure at different process stages of the method for preparing a GaN HEMT device provided by an embodiment of the present invention Figure 10 Nine.

[0070] Reference numerals:

[0071] 1-first substrate;

[0072] 2- buffer layer;

[0073] 3-channel layer;

[0074] 4-barrier layer;

[0075] 5-P-GaN layer;

[0076] 6-first dielectric layer;

[0077] 7-gate;

[0078] 8- second dielectric layer;

[0079] 9- Source;

[0080] 10-drain;

[0081] 11- a third dielectric layer;

[0082] 12- source field plate;

[0083] 13-drain field plate;

[0084] 14-Gate field plate. DETAILED DESCRIPTION

[0085] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0086] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0087] Compared with traditional Si materials, GaN has a series of advantages such as high voltage resistance, high temperature resistance, high mobility, and radiation resistance. Therefore, GaN semiconductor devices are currently favored by the industry. Taking GaN HEMT power devices as an example, they are mainly divided into D-mode and E-mode.

[0088] However, among the above two solutions, the Cascode solution needs to seal a low-voltage Si MOSFET, which increases parasitic parameters and additional costs; the P-GaN cap solution has a small threshold voltage, small gate voltage swing, average gate reliability and anti-interference ability, and generally requires a special gate drive to be designed in the application, and cannot use the same gate drive as Si MOS.

[0089] In view of this, the inventors of the present application propose that: by arranging a P-GaN layer on the barrier layer, and making the thickness of the portion of the barrier layer covered by the P-GaN layer less than 10 nm, and less than the thickness of the remaining uncovered portion of the barrier layer, the depletion capability of the P-GaN layer for the 2DEG generated in the region below it is enhanced, thereby improving the threshold voltage of the GaN HEMT device; at the same time, by sequentially forming a P-GaN layer, a first dielectric layer and a gate on the barrier layer, the P-GaN layer, the first dielectric layer and the gate together constitute a MIS-type gate structure, thereby further improving the threshold voltage of the GaN HEMT device; compared with the traditional P-GaN cap device structure, the GaN HEMT device formed by the present invention can improve the gate's withstand voltage capability and reliability, and reduce gate leakage; in addition, the first dielectric layer can also passivate the surface of the barrier layer, prevent the generation of surface states on the barrier layer, and ensure the good performance of the GaN HEMT device.

[0090] Furthermore, by setting the thickness of the first dielectric layer to 10-50 nm, the first dielectric layer can play a role in blocking conduction, reduce the leakage of the gate, and improve the reliability of the gate.

[0091] Furthermore, the method for preparing a GaN HEMT device provided by the present invention can ensure the stability and uniformity of etching by etching the first barrier layer and forming the second barrier layer on the first barrier layer, thereby making the GaN HEMT device more stable.

[0092] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0093] Please refer to Figure 2-Figure 20 According to a first aspect of the present invention, a GaN HEMT device is provided, comprising:

[0094] A first substrate 1, and a buffer layer 2 and a channel layer 3 sequentially formed in a direction away from the first substrate 1;

[0095] The barrier layer 4 covers the surface of the channel layer 3; Figure 2 As shown;

[0096] A P-GaN layer 5, wherein the P-GaN layer 5 covers a portion of the surface of the barrier layer 4; wherein the thickness of the portion of the barrier layer 4 covered by the P-GaN layer 5 is less than 10 nm, and is less than the thickness of the remaining portion of the barrier layer 4 not covered; Figure 5 As shown;

[0097] The first dielectric layer 6 covers the barrier layer 6 and the P-GaN layer 5; wherein a gate 7 is formed on the surface of the first dielectric layer 6 on the P-GaN layer 5; Figure 8 As shown;

[0098] The gate electrode 7 , the P-GaN layer 5 and the first dielectric layer 6 on the P-GaN layer 5 together form a MIS type gate structure; a source electrode 9 and a drain electrode 10 are formed on both sides of the MIS type gate structure.

[0099] The GaN HEMT device provided by the present invention can enhance the depletion capability of the P-GaN layer for the 2DEG generated by the region below the barrier layer by arranging a P-GaN layer on the barrier layer, and making the thickness of the portion of the barrier layer covered by the P-GaN layer less than 10 nm and less than the thickness of the remaining uncovered portion of the barrier layer, so that the GaN HEMT device requires a larger gate-source voltage to form a conductive path between the source and the drain, thereby improving the threshold voltage of the GaN HEMT device. At the same time, by forming a first dielectric layer on the barrier layer and the P-GaN layer, and forming a gate on the first dielectric layer, compared with the traditional GaN HEMT device structure, the present invention enables the P-GaN layer, the gate and the first dielectric layer on the P-GaN layer to jointly form a MIS-type gate structure, which can further improve the threshold voltage of the GaN HEMT device, improve the withstand voltage capability and reliability of the gate, and reduce gate leakage. In addition, the first dielectric layer can also passivate the surface of the barrier layer to prevent the generation of surface states on the barrier layer, thereby ensuring good performance of the GaN HEMT device.

[0100] In one embodiment, the first dielectric layer 6 covers the barrier layer 4, the P-GaN layer 5, the source electrode 9 and the drain electrode 10, or only covers the barrier layer 4 and the P-GaN layer 5. Figure 6 Or as shown in 17.

[0101] In a specific embodiment, the thickness of the first dielectric layer 6 is 10-50 nm, so that the first dielectric layer can play a role in blocking conduction, reduce gate leakage, and improve gate reliability.

[0102] In a specific embodiment, the material of the barrier layer 4 is AlGaN; the material of the first dielectric layer 6 is insitu-SiN, LPCVD SiN, Al 2 O 3 or AlN; the material of the second dielectric layer 8 is SiN, SiO 2 , SiON or a combination thereof. Of course, the aforementioned structural layers may also be composed of other materials, but the present invention is not limited thereto. The implementation form of the materials of any corresponding structural layers is within the protection scope of the present invention.

[0103] The GaN HEMT device proposed in the present invention has the following two specific embodiments:

[0104] In a first specific embodiment, the first dielectric layer 6 covers the barrier layer 4 and the P-GaN layer 5. Figure 6 shown.

[0105] In one embodiment, the GaN HEMT device further includes: a second dielectric layer 8; the second dielectric layer 8 covers the surface of the first dielectric layer 6 and the gate 7; the second dielectric layer 8 is used to isolate the gate 7, the source 9 and the drain 10 to avoid possible problems such as metal residues and leakage channels. Fig. 9 In a specific embodiment, the thickness of the second dielectric layer 8 is 50-100 nm.

[0106] In one embodiment, the GaN HEMT device further includes: the source electrode 9 and the drain electrode 10 are both in contact with the surface of the barrier layer 4 and the side walls of the first dielectric layer 6 and the second dielectric layer 8; wherein the distance between the source electrode 9 and the gate electrode 7 is smaller than the distance between the drain electrode 10 and the gate electrode 7, such as Fig.11 In a specific embodiment, when the withstand voltage BV of the GaN HEMT device is greater than 650V, the distance between the source electrode 9 and the gate electrode 7 is 2um; the distance between the drain electrode 10 and the gate electrode 7 is 20um.

[0107] In one embodiment, the GaN HEMT device further includes: a third dielectric layer 11; the third dielectric layer 11 covers the second dielectric layer 8, the source electrode 9 and the drain electrode 10, such as Fig.12 As shown, the thickness of the third dielectric layer is generally determined by combining simulation and actual device performance test results. In a specific embodiment, the material of the third dielectric layer is SiN, SiO 2 , SiON or a combination thereof.

[0108] In one embodiment, the GaN HEMT device further includes: a source field plate 12 and a drain field plate 13; the source field plate 12 and the drain field plate 13 are formed on the third dielectric layer 11 and are connected to the source 9 and the gate 10, respectively. Fig.14 shown.

[0109] In another embodiment, the GaN HEMT device further includes: a source field plate 12, a drain field plate 13 and a gate field plate 14; wherein the source field plate 12 and the drain field plate 13 are formed on the third dielectric layer 11 and are respectively connected to the source 9 and the gate 10; the gate field plate 14 is formed on the gate 7, as shown in FIG. Fig.15 shown.

[0110] The third dielectric layer 11 covers the second dielectric layer 8, the source electrode 9, the drain electrode 10 and the gate field plate 14. Fig.13 shown.

[0111] In a second specific embodiment, the first dielectric layer 6 covers the barrier layer 4, the P-GaN layer 5, the source electrode 9 and the drain electrode 10. Fig.17 shown.

[0112] In one embodiment, the GaN HEMT device further includes: a third dielectric layer 11; the third dielectric layer 11 covers the first dielectric layer 6 and the gate 7, such as Fig.19 shown.

[0113] In one embodiment, the GaN HEMT device further includes: a source field plate 12 and a drain field plate 13; the source field plate 12 and the drain field plate 13 are formed on the third dielectric layer 11 and are connected to the source 9 and the gate 10, respectively. Fig. 20 shown.

[0114] Of course, it should be appreciated that the above-mentioned field plates may also be other structures, and the present invention is not limited thereto. Any field plate structure that may achieve the same effect of the present invention is within the protection scope of the present invention.

[0115] The two GaN HEMT devices provided by the present invention improve the withstand voltage and dynamic performance of the GaN HEMT device by forming a third dielectric layer on the second dielectric layer, and forming a source field plate, a drain field plate and a gate field electrode or only forming a source field plate and a drain field plate on the third dielectric layer, or by forming a third dielectric layer on the first dielectric layer, and forming a source field plate and a drain field plate on the third dielectric layer, so as to utilize the overall design of the source field plate, the drain field plate, the gate field electrode or only the source field plate, the drain field plate and the third dielectric layer.

[0116] Please refer to Figure 1 , and combined with Figure 2-Figure 20 According to another embodiment of the present invention, there is further provided a method for preparing a GaN HEMT device, comprising the GaN HEMT device according to any one of the aforementioned embodiments of the present invention, the method comprising steps S11-S15:

[0117] Step S11: providing the first substrate 1, and sequentially forming the buffer layer 2 and the channel layer 3 in a direction away from the first substrate 1;

[0118] Step S12: forming the barrier layer 4; the barrier layer 4 is formed on the surface of the channel layer 3; Figure 2 As shown;

[0119] Step S13: forming the P-GaN layer 5; the P-GaN layer 5 covers a portion of the surface of the barrier layer 4; wherein the thickness of the portion of the barrier layer 4 covered by the P-GaN layer 5 is less than 10 nm, and is less than the thickness of the remaining uncovered portion of the barrier layer 4; Figure 5 As shown;

[0120] Step S14: forming the first dielectric layer 6; the first dielectric layer 6 is formed on the barrier layer 4 and the P-GaN layer 5; and forming the gate 7 on the surface of the first dielectric layer 6 on the P-GaN layer 5; Figure 8 As shown;

[0121] Step S15: wherein the gate 7, the P-GaN layer 5 and the first dielectric layer 6 on the P-GaN layer 5 together constitute the MIS type gate structure; and the source 9 and the drain 10 are respectively formed on both sides of the MIS type gate structure.

[0122] The preparation method of the GaN HEMT device provided by the present invention can enhance the depletion capability of the P-GaN layer for the 2DEG generated by the region below the P-GaN layer, thereby improving the threshold voltage of the GaN HEMT device, by forming a P-GaN layer on the barrier layer and making the thickness of the portion of the barrier layer covered by the P-GaN layer less than 10nm and less than the thickness of the remaining uncovered portion of the barrier layer, and by forming a first dielectric layer on the barrier layer and the P-GaN layer, and forming a gate metal on a portion of the first dielectric layer, so that the P-GaN layer, the gate and the first dielectric layer on the P-GaN layer together form a MIS type gate structure, thereby further enhancing the depletion capability of the P-GaN layer for the 2DEG, making the gate able to withstand a larger gate-source voltage, and improving the gate's withstand voltage capability, and in addition, the first dielectric layer also plays a role in repairing the surface of the barrier layer, thereby preventing the generation of surface states on the barrier layer, and ensuring good performance of the GaN HEMT device.

[0123] In one embodiment, the forming of the barrier layer 4 in step S12 specifically includes steps S121-S123:

[0124] Step S121: forming a first barrier layer on the channel layer 3 in a direction away from the first substrate 1, such as Figure 2 As shown;

[0125] Step S122: etching a portion of the first barrier layer to expose a portion of the channel layer 3. Figure 3 As shown;

[0126] Step S123: forming a second barrier layer on a portion of the surface of the channel layer 3 and a portion of the sidewall of the first barrier layer, such as Figure 4 As shown;

[0127] The first barrier layer and the second barrier layer constitute the barrier layer 4. In a specific embodiment, the second barrier layer is formed on a portion of the surface of the channel layer 3 and the surface and a portion of the sidewall of the first barrier layer by MOCVD.

[0128] The method for preparing the GaN HEMT device provided by the present invention has the following two specific embodiments:

[0129] In a first specific embodiment, forming the gate 7 on the surface of the first dielectric layer 6 on the P-GaN layer 5 in step S14 specifically includes steps S141-S142:

[0130] Step S141: sputtering gate metal on the first dielectric layer 6; Figure 7 As shown;

[0131] Step S142: etching away the gate metal except for the upper region of the P-GaN layer 5 to form the gate 7 on the surface of the first dielectric layer 6 on the P-GaN layer 5. Figure 8 shown.

[0132] In one embodiment, before forming the source 9 and the drain 10 on both sides of the MIS type gate structure respectively in step S15, the step further includes:

[0133] A second dielectric layer 8 is formed; the second dielectric layer 8 is formed on the first dielectric layer 6 and the gate 7, such as Fig. 9 shown.

[0134] In one embodiment, the step S15 of forming the source 9 and the drain 10 on both sides of the MIS type gate structure respectively includes steps S151-S153:

[0135] Step S151: etching the second dielectric layer 8 and the two ends of the first dielectric layer 6 in sequence along a direction close to the first substrate 1 to form a first mesa and a second mesa on the barrier layer 4; wherein the distance between the first mesa and the gate 7 is smaller than the distance between the second mesa and the gate 7; Fig.10 As shown;

[0136] Step S152: depositing a metal layer; the metal layer covers the surface of the first mesa, the second mesa and the second dielectric layer 8;

[0137] Step S153: etching away the metal layer on the second dielectric layer 8 to form the source electrode 9 on the first mesa; forming the drain electrode 10 on the second mesa, such as Fig.11 shown.

[0138] In another embodiment, while forming the source 9 and the drain 10 on both sides of the MIS type gate structure respectively in step S15, the step further includes:

[0139] A gate field plate 14 is formed; the gate field plate 14 is formed on the gate.

[0140] In one embodiment, after forming the source 9 and the drain 10 on both sides of the MIS gate structure respectively in step S15, the step further includes:

[0141] A third dielectric layer 11 is formed; the third dielectric layer 11 is formed on the second dielectric layer 8, the source 9, the drain 10 and the gate field plate 14 or only on the second dielectric layer 8, the source 9 and the drain 10. Fig.12 Or as shown in 13.

[0142] In one embodiment, after forming the third dielectric layer 11, the method further includes:

[0143] A source field plate 12 and a drain field plate 13 are formed; the source field plate 12 and the drain field plate 13 are formed on the third dielectric layer 11 and are connected to the source 9 and the gate 10, respectively. Fig.14 shown.

[0144] In a specific embodiment, forming the source field plate 12 and the drain field plate 13 specifically includes:

[0145] Etching the third dielectric layer 11 in the region above the source electrode 9 and the drain electrode 10 to form a plurality of openings;

[0146] Depositing a metal layer; the metal layer fills the plurality of openings and covers the third dielectric layer 11;

[0147] The redundant metal layer is etched away to form the source field plate 12 on the source electrode 9; the drain field plate 13 is formed on the drain electrode 10. Fig.14 Or as shown in 15.

[0148] In a second specific embodiment, after forming the P-GaN layer 5 in step S13, the method may further include steps S131-S132:

[0149] Step S131: forming the source electrode 9 and the drain electrode 10; the source electrode 9 and the drain electrode 10 are formed at both ends of the surface of the barrier layer 4; Fig.16 As shown;

[0150] Step S132: forming the first dielectric layer 6; the first dielectric layer 6 is formed on the barrier layer 4, the P-GaN layer 5, the source electrode 9 and the drain electrode 10; and forming the gate electrode 7 on the surface of the first dielectric layer 6 on the P-GaN layer 5, such as Fig.18 shown.

[0151] In one embodiment, the forming of the source electrode 9 and the drain electrode 10 in step S15 specifically includes steps S151-S152:

[0152] Step S151: depositing metal to form a metal layer on the surface of the barrier layer 4 and the P-GaN layer 5;

[0153] Step S152: etching away the metal layer in the middle region of the barrier layer 4 to form the source electrode 9 and the drain electrode 10 at two ends of the surface of the barrier layer 4 respectively;

[0154] Wherein, the distance between the source electrode 9 and the gate electrode 10 is smaller than the distance between the drain electrode 9 and the gate electrode 7, as shown in FIG. Fig.16 shown.

[0155] In one embodiment, after forming the first dielectric layer 6 in step S132, the method further includes:

[0156] A third dielectric layer 11 is formed; the third dielectric layer 11 is formed on the first dielectric layer 6 and the gate 7. Fig.19 shown.

[0157] In one embodiment, after forming the third dielectric layer 11, the method further includes:

[0158] A source field plate 12 and a drain field plate 13 are formed; the source field plate 12 and the drain field plate 13 are formed on the source 9 and the drain 10, respectively. Fig. 20 shown.

[0159] In a specific embodiment, forming the source field plate 12 and the drain field plate 13 specifically includes:

[0160] Sequentially etching the third dielectric layer 11 and the first dielectric layer 6 above the source electrode 9 and the drain electrode 10 to form a plurality of openings;

[0161] Depositing a metal layer; the metal layer fills the plurality of openings and covers the third dielectric layer 11;

[0162] The redundant metal layer is etched away to form the source field plate 12 on the source electrode 9; the drain field plate 13 is formed on the drain electrode 10. Fig. 20 shown.

[0163] The two methods for preparing GaN HEMT devices provided by the present invention both etch the first barrier layer and epitaxially grow the second barrier layer on the first barrier layer. Compared with the traditional method of forming the barrier layer, the preparation method of the present invention utilizes the difference in etching rate between the first barrier layer and the channel layer, and can completely etch part of the first barrier layer, thereby avoiding damage to the channel, and can ensure the stability and uniformity of the barrier layer, so that the GaN HEMT device is more stable.

[0164] According to an embodiment of the present invention, an electronic device is provided, comprising the GaN HEMT device according to any one of the aforementioned embodiments of the present invention.

[0165] According to another embodiment of the present invention, there is further provided a method for preparing an electronic device, comprising the method for preparing a GaN HEMT device according to any one of the aforementioned embodiments of the present invention.

[0166] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A GaN HEMT device, characterized in that: include: A first substrate, and a buffer layer and a channel layer sequentially formed in a direction away from the first substrate; Barrier layer; The barrier layer covers the surface of the channel layer; A P-GaN layer, wherein the P-GaN layer covers a portion of the surface of the barrier layer; wherein the thickness of the portion of the barrier layer covered by the P-GaN layer is less than 10 nm and is less than the thickness of the remaining portion of the barrier layer not covered; A first dielectric layer, covering the barrier layer and the P-GaN layer; wherein a gate is formed on a surface of the first dielectric layer on the P-GaN layer; The gate, the P-GaN layer and the first dielectric layer on the P-GaN layer together form a MIS type gate structure; and a source and a drain are formed on two sides of the MIS type gate structure respectively.

2. The GaN HEMT device according to claim 1, characterized in that: The first dielectric layer covers the barrier layer, the P-GaN layer, the source electrode and the drain electrode, or only covers the barrier layer and the P-GaN layer.

3. The GaN HEMT device according to claim 2, characterized in that: The thickness of the first dielectric layer is 10-50 nm.

4. The GaN HEMT device according to claim 1, characterized in that: The GaN HEMT device further includes: a second dielectric layer; the second dielectric layer covers the surface of the first dielectric layer and the gate; the second dielectric layer is used to isolate the gate, the source and the drain.

5. The GaN HEMT device according to claim 4, characterized in that: The GaN HEMT device further includes: the source electrode and the drain electrode are both in contact with the surface of the barrier layer and the side walls of the first dielectric layer and the second dielectric layer; wherein the distance between the source electrode and the gate electrode is smaller than the distance between the drain electrode and the gate electrode.

6. The GaN HEMT device according to claim 5, characterized in that: The material of the barrier layer is AlGaN; the material of the first dielectric layer is insitu-SiN, LPCVD SiN, Al2O3 or AlN; the material of the second dielectric layer is SiN, SiO2, SiON or a combination thereof.

7. A method for preparing a GaN HEMT device, characterized in that: A GaN HEMT device comprising any one of claims 1 to 6, wherein the preparation method comprises: Providing the first substrate, and sequentially forming the buffer layer and the channel layer in a direction away from the first substrate; forming the barrier layer; the barrier layer is formed on the surface of the channel layer; The P-GaN layer is formed; the P-GaN layer covers a portion of the surface of the barrier layer; wherein the thickness of the portion of the barrier layer covered by the P-GaN layer is less than 10 nm, and is less than the thickness of the remaining portion of the barrier layer not covered; forming the first dielectric layer; the first dielectric layer is formed on the barrier layer and the P-GaN layer; and forming the gate on the surface of the first dielectric layer on the P-GaN layer; The gate electrode, the P-GaN layer and the first dielectric layer on the P-GaN layer together constitute the MIS type gate structure; and the source electrode and the drain electrode are respectively formed on both sides of the MIS type gate structure.

8. The method for preparing a GaN HEMT device according to claim 7, characterized in that: Forming the barrier layer specifically includes: forming a first barrier layer on the channel layer in a direction away from the first substrate; Etching a portion of the first barrier layer to expose a portion of the channel layer; forming a second barrier layer on a portion of the surface of the channel layer and a surface and a portion of the sidewall of the first barrier layer; The first barrier layer and the second barrier layer constitute the barrier layer.

9. The method for preparing a GaN HEMT device according to claim 8, characterized in that: Forming the gate on the surface of the first dielectric layer on the P-GaN layer specifically includes: sputtering a gate metal on the first dielectric layer; The gate metal is etched away except for the upper region of the P-GaN layer to form the gate on the surface of the first dielectric layer on the P-GaN layer.

10. The method for preparing a GaN HEMT device according to claim 9, characterized in that: Before forming the source and the drain on both sides of the MIS type gate structure respectively, the method further includes: A second dielectric layer is formed; the second dielectric layer is formed on the first dielectric layer and the gate.

11. The method for preparing a GaN HEMT device according to claim 10, characterized in that: The source and the drain are respectively formed on both sides of the MIS type gate structure, specifically comprising: Sequentially etching the second dielectric layer and the two ends of the first dielectric layer in a direction close to the first substrate to form a first mesa and a second mesa on the barrier layer; wherein the distance between the first mesa and the gate is smaller than the distance between the second mesa and the gate; Depositing a metal layer; the metal layer covers the surfaces of the first mesa, the second mesa and the second dielectric layer; The metal layer on the second dielectric layer is etched away to form the source electrode on the first mesa; and the drain electrode is formed on the second mesa.

12. The method for preparing a GaN HEMT device according to claim 8, characterized in that: After forming the P-GaN layer, the method further includes: forming the source electrode and the drain electrode; the source electrode and the drain electrode are formed at two ends of the surface of the barrier layer; The first dielectric layer is formed; the first dielectric layer is formed on the barrier layer, the P-GaN layer, the source electrode and the drain electrode; and the gate electrode is formed on the surface of the first dielectric layer on the P-GaN layer.

13. The method for preparing a GaN HEMT device according to claim 12, characterized in that: Forming the source and the drain specifically includes: Depositing metal; to form a metal layer on the surface of the barrier layer and the P-GaN layer; Etching away the metal layer in the middle region of the barrier layer to form the source electrode and the drain electrode at two ends of the surface of the barrier layer respectively; Wherein, the distance between the source electrode and the gate electrode is smaller than the distance between the drain electrode and the gate electrode.

14. An electronic device comprising the GaN HEMT device according to any one of claims 1 to 6.

15. A method for preparing an electronic device, comprising the method for preparing the GaN HEMT device according to any one of claims 7 to 13.

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