Peripheral surrounding type grid gallium oxide MOSFET power device and manufacturing method thereof

Abstract

The invention discloses a surrounding type grid electrode gallium oxide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) power device and a manufacturing method thereof, and mainly solves the problems of weak grid control capability and poor heat dissipation capability of the existing gallium oxide MOSFET device. The device comprises a substrate, an unintentionally-doped UID gallium oxide layer, a gallium oxide channel layer, an upper Al2O3 dielectric layer, a source ohmic electrode, a drain ohmic electrode and a top gate electrode, the substrate is made of a diamond material with high thermal conductivity, the Al2O3 dielectric layer and a Ni / Au metal layer are sequentially arranged between the unintentionally-doped UID gallium oxide layer and the substrate, the Al2O3 dielectric layer is connected with the upper Al2O3 dielectric layer, the source ohmic electrode is connected with the source ohmic electrode, the drain ohmic electrode is connected with the drain ohmic electrode, and the top gate electrode is connected with the drain ohmic electrode. The gallium oxide channel layer is jointly surrounded; and the Ni / Au metal layer is connected with the top gate electrode to jointly surround the upper Al2O3 dielectric layer and the upper Al2O3 dielectric layer. According to the invention, the heat dissipation capability of the gallium oxide MOSFET device and the control capability of the grid electrode on a channel can be effectively improved, and the method can be used for manufacturing a high-voltage-resistant power transistor device.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a gallium oxide MOSFET power device, which can be used to manufacture a high-voltage power transistor device. Background Art

[0002] In view of the excellent material properties of ultra-wide bandgap semiconductor gallium oxide (Ga2O3), the metal-oxide-semiconductor field-effect transistor MOSFET devices made of it are expected to become the core of the next generation of power electronic systems. However, due to the low mobility of gallium oxide materials, the output power density of gallium oxide transistors is not high. Usually, the output power density of the transistor is improved by increasing the thickness of the device channel layer, but this method will also reduce the gate control ability of the device, making its threshold voltage more negative, the off-state leakage current higher and the breakdown voltage lower, which restricts the development of gallium oxide MOSFET in high-voltage and high-power applications. Therefore, how to improve the gate control ability of gallium oxide MOSFET devices and obtain gallium oxide MOSFETs with low state leakage current and high breakdown voltage is one of the current focuses of gallium oxide power device research.

[0003] In addition, due to the extremely low thermal conductivity of gallium oxide, gallium oxide power devices have a large heat dissipation problem. To solve this problem, it is usually necessary to transfer the gallium oxide epitaxial thin film material to a high thermal conductivity substrate to reduce heat accumulation during the subsequent device operation. However, the general transfer method will cause relatively large damage to the epitaxial layer, which is not conducive to the subsequent device manufacturing.

[0004] Patent document with publication number CN115472503 A discloses a gallium oxide-based power transistor with high breakdown voltage and a manufacturing method, which obtains a high resistance region by plasma treatment in the β-Ga2O3 channel layer near the drain to increase the breakdown voltage. However, this method only improves the voltage-dividing capability of the drain region, and does not substantially improve the gate control capability. At the same time, the output current is reduced due to the presence of the high resistance region, making it difficult to be applied in the high-power field.

[0005] The patent document with publication number CN117577518 A discloses a diamond-based gallium oxide semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises a diamond substrate, a silicon carbide layer and a gallium oxide layer from bottom to top. The preparation process specifically adopts a defect ion implantation method to realize the stripping of the gallium oxide layer. This method will cause significant damage to the gallium oxide layer, which is not conducive to obtaining a high-quality gallium oxide film. Summary of the invention

[0006] The object of the present invention is to address the deficiencies of the above-mentioned prior art and provide a surrounding gate gallium oxide MOSFET power device and a manufacturing method to improve the gate control capability of the gallium oxide MOSFET, while reducing the damage caused by the peeling of the gallium oxide epitaxial film and alleviating the heat dissipation problem of the gallium oxide power device.

[0007] To achieve the above object, the technical solution of the present invention includes the following:

[0008] 1. A surrounding gate gallium oxide MOSFET power device, comprising a substrate, an unintentionally doped UID gallium oxide layer, a gallium oxide channel layer, an upper Al2O3 dielectric layer, a source ohmic electrode, a drain ohmic electrode and a top gate electrode, characterized in that:

[0009] The substrate is made of diamond material with high thermal conductivity to effectively improve the heat dissipation capacity of the gallium oxide MOSFET device; an Al2O3 dielectric layer and a Ni / Au metal layer are arranged in sequence between the unintentionally doped UID gallium oxide layer and the substrate, and the Al2O3 dielectric layer is connected to the upper Al2O3 dielectric layer to jointly surround the gallium oxide channel layer; the Ni / Au metal layer is connected to the top gate electrode to jointly surround the upper Al2O3 dielectric layer and the Al2O3 dielectric layer to improve the gate's control over the channel.

[0010] Furthermore, the unintentionally doped UID gallium oxide layer is located above the Al2O3 dielectric layer and has a thickness of 100nm to 500nm and a carrier concentration of 1×10 14 cm -3 ~1×10 16 cm -3 ;

[0011] Furthermore, the gallium oxide channel layer is located above the unintentionally doped UID gallium oxide layer and has a thickness of 200nm to 600nm and a carrier concentration of 1×10 16 cm -3 ~1×10 18 cm -3 ;

[0012] Furthermore, the upper Al2O3 dielectric layer has a thickness of 5 to 35 nm;

[0013] Furthermore, the source ohmic electrode and the drain ohmic electrode are both made of Ti / Au, with a thickness of 20-40nm / 400-600nm, and are respectively located in the ohmic regions on both sides above the gallium oxide channel layer;

[0014] Furthermore, the top gate electrode is made of Ni / Au with a thickness of 35-55nm / 350-450nm;

[0015] Furthermore, the Ni / Au metal layer has a thickness of 35-55nm / 350-450nm;

[0016] Furthermore, the Al2O3 dielectric layer has a thickness of 5 to 35 nm.

[0017] 2. A method for manufacturing a four-sided gate gallium oxide MOSFET power device, characterized in that it comprises the following steps:

[0018] 1) Select the epitaxial substrate and clean it;

[0019] 2) Using a Sputter device, a layer of iron oxide film is grown on the surface of the cleaned substrate and annealed;

[0020] 3) using ALD equipment to deposit a 5-35 nm Al2O3 dielectric layer on top of the iron oxide layer;

[0021] 4) The sample with the Al2O3 dielectric layer deposited was placed in an MOCVD reaction chamber, and a metal organic chemical vapor deposition method was used to sequentially grow a carrier concentration of 1×10 14 cm -3 ~1×10 16 cm -3 , the first layer of α-doped gallium oxide is 100nm to 500nm thick, and the carrier concentration is 1×10 16 cm -3 ~1×10 18 cm -3 , a second α-oriented gallium oxide channel layer having a thickness of 200nm to 600nm;

[0022] 5) Use a mask to determine the source and drain region locations of the sample, and perform ion implantation in the source and drain regions to form an ohmic region;

[0023] 6) depositing a Ti / Au metal stack above the source ohmic region and the drain ohmic region, and performing annealing to complete the fabrication of the source ohmic electrode and the drain ohmic electrode;

[0024] 7) Etch away the gallium oxide layer outside the source and drain regions using an ICP etcher to isolate the active region;

[0025] 8) Using an electron beam lithography machine to form a mask in the shape of a nano-strip, and then using an ICP etcher to etch to form a nano-channel;

[0026] 9) Using a mask to determine the gate dielectric region of the sample, and using an ALD device to deposit a 5-35 nm upper Al2O3 dielectric layer in the gate dielectric region;

[0027] 10) Depositing a Ni / Au metal stack on the upper Al2O3 dielectric layer to complete the upper gate electrode fabrication;

[0028] 11) using a liquid phase stripping method to strip the structure above the iron oxide layer from the epitaxial substrate;

[0029] 12) The structure above the iron oxide layer is transferred and bonded to a diamond substrate with Ni / Au laminated metal deposited on the surface by using a surface activation bonding method, and annealing is performed to complete the entire device manufacturing.

[0030] Furthermore, the Sputter device is used to grow a layer of iron oxide film on the surface of the cleaned substrate and perform annealing treatment. First, the vacuum of the device is broken, the cleaned sample is sent into its chamber, and an iron oxide target is set; then the chamber is evacuated to a vacuum, the temperature is set to room temperature, the power is 90-160W, and the O2 to Ar ratio is 1:5-1:2. Process conditions, a layer of iron oxide film with a thickness of 100nm-5μm is grown on the surface of the substrate by sputtering; finally, the sample is placed in an annealing furnace, and annealed for 20-60min in a nitrogen atmosphere at a temperature of 500-1100°C.

[0031] Furthermore, the liquid phase stripping method is used to strip the structure above the iron oxide layer from the epitaxial substrate, which is to first immerse the sample in a hydrochloric acid solution with a concentration of 0.1 to 3 mol / L to dissolve the iron oxide until the four corners of the structure above the iron oxide layer are lifted up; then the sample is placed in deionized water, and the tension of the water is used to separate the upper structure from the substrate to obtain a stripped gallium oxide MOSFET device.

[0032] Compared with the prior art, the present invention has the following advantages:

[0033] First, the gate of the gallium oxide MOSFET power device designed by the present invention surrounds the channel layer, which can effectively improve the control ability of the gate electrode over the channel, help reduce the off-state leakage current of the channel, and improve the device withstand voltage;

[0034] Secondly, since the gallium oxide MOSFET device is transferred to the diamond substrate, the high thermal conductivity of diamond can be used to effectively alleviate the heat dissipation problem of the gallium oxide MOSFET device.

[0035] Third, the present invention uses hydrochloric acid solution to dissolve iron oxide during the preparation process. By taking advantage of the fact that hydrochloric acid solution does not easily dissolve gallium oxide, low-damage stripping of gallium oxide MOSFET devices can be achieved, which is beneficial to improving the performance of gallium oxide MOSFET devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic diagram of the structure of the device of the present invention;

[0037] Figure 2 The invention is made Figure 1 Schematic diagram of the device implementation flow. DETAILED DESCRIPTION

[0038] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Reference Figure 1 The device structure of the present invention includes a diamond substrate 1, an unintentionally doped UID gallium oxide layer 2, a gallium oxide channel layer 3, an upper Al2O3 dielectric layer 4, a source ohmic electrode 5, a drain ohmic electrode 6, a top gate electrode 7, a Ni / Au metal layer 8, and an Al2O3 dielectric layer 9, wherein:

[0040] The Ni / Au metal layer 8 is located on the diamond substrate 1 and has a thickness of 35-55 nm / 350-450 nm.

[0041] The Al2O3 dielectric layer 9 is located on the Ni / Au metal layer 8 and has a thickness of 5 to 35 nm.

[0042] The unintentionally doped UID gallium oxide layer 2 is located on the Al2O3 dielectric layer 9 and has a thickness of 100nm to 500nm and a carrier concentration of 1×10 14 cm -3 ~1×10 16 cm -3 .

[0043] The gallium oxide channel layer 3 is located on the unintentionally doped UID gallium oxide layer 2 and has a thickness of 200 nm to 600 nm and a carrier concentration of 1×10 16 cm -3 ~1×10 18 cm -3 .

[0044] The upper Al 2 O 3 dielectric layer 4 has a thickness of 5 to 35 nm and is connected to the Al 2 O 3 dielectric layer 9 to surround the gallium oxide channel layer 3 .

[0045] The source ohmic electrode 5 and the drain ohmic electrode 6 are both made of Ti / Au, with a thickness of 20-40 nm / 400-600 nm, and are respectively located on the two side ohmic regions above the gallium oxide channel layer 3 .

[0046] The top gate electrode 7 is made of Ni / Au with a thickness of 35-55nm / 350-450nm, and is connected to the Ni / Au metal layer 8 to surround the upper Al2O3 dielectric layer 4 and the Al2O3 dielectric layer 9 to improve the control capability of the gate electrode over the channel.

[0047] Reference Figure 2The present invention provides the following three embodiments for manufacturing a four-sided gate gallium oxide MOSFET power device.

[0048] Example 1: A diamond-based all-around gate gallium oxide MOSFET power device is manufactured with a sapphire epitaxial substrate, a sputtered iron oxide layer with a thickness of 100 nm, a hydrochloric acid concentration of 0.1 mol / L for stripping, a gallium oxide channel layer with a width of 50 nm and a depth of 305 nm.

[0049] Step 1: Select an epitaxial substrate and clean it.

[0050] Sapphire was selected as the epitaxial substrate material, and the sapphire substrate was immersed in HF acid, acetone solution, and ethanol solution in sequence, placed in a water bath for ultrasonic treatment for 3 minutes, then rinsed with deionized water for 3 minutes, and finally dried with a nitrogen gun.

[0051] Step 2: Using a Sputter device, a 100 nm thick iron oxide film is grown on the surface of the sapphire substrate and annealed.

[0052] First, break the vacuum of the Sputter equipment, then put the cleaned substrate into it and set the iron oxide target;

[0053] The chamber was then evacuated to vacuum, the temperature was set to room temperature, the power was 90 W, the O2 to Ar gas ratio was 1:5, and a 100 nm thick iron oxide film was grown on the substrate surface by sputtering.

[0054] The sample with the iron oxide film was placed in an annealing furnace and annealed in a nitrogen atmosphere at 500° C. for 20 minutes.

[0055] Step 3: Use ALD equipment to deposit a 5 nm Al2O3 dielectric layer on the iron oxide layer.

[0056] First, place the annealed sample in the ALD chamber and set the chamber pressure to 0.1 torr and the temperature to 150°C.

[0057] Trimethylaluminum and H2O were selected as precursors, and 0.1 trimethylaluminum, nitrogen for 10s, H2O3s, and nitrogen for 10s were introduced into the chamber in sequence. The process was repeated 100 times in total, and an Al2O3 dielectric layer with a thickness of 5nm was grown on the iron oxide layer by atomic layer deposition.

[0058] Step 4: using MOCVD to sequentially grow an unintentionally doped UID gallium oxide layer and a gallium oxide channel layer on the Al2O3 dielectric layer.

[0059] The sample with Al2O3 dielectric layer is placed in the MOCVD reaction chamber, and the pipeline and chamber are pumped with a mechanical pump to reduce impurities introduced from the environment;

[0060] The reaction chamber temperature was set to 400 °C and the pressure was set to 40 mba. The oxygen source was high-purity oxygen, the gallium source was TEGa, and the carrier gas was argon. The molar flow ratio of TEGa to O2 was 1:5000. MOCVD was used to grow a carrier concentration of 1×10 14 cm -3 The first layer of α-doped UID gallium oxide layer;

[0061] After that, the reaction chamber temperature was set to 400 °C and the pressure was set to 200 mba. The oxygen source was high-purity oxygen, the gallium source was TEGa, the doping source was silane, and the carrier gas was argon. The molar flow ratio of TEGa to O2 was 1:200, and the molar flow rate of silane was 50 μmol / min. The carrier concentration of the unintentionally doped gallium oxide layer was 1×10 18 cm -3 The second layer is an α-oriented gallium oxide channel layer;

[0062] In the process of sequentially growing two layers of α-gallium oxide, the growth rate of the α-gallium oxide layer during the epitaxial process is monitored in real time by means of the reflectivity change of the sample, and the growth time is modified accordingly to achieve metal organic chemical vapor deposition growth of α-gallium oxide unintentionally doped layer with a thickness of 100nm and α-gallium oxide channel layer with a thickness of 200nm.

[0063] Step 5: Use a mask to determine the location of the source and drain regions of the sample, and perform ion implantation in the source and drain regions to form an ohmic region.

[0064] First, use a mask to determine the source and drain areas, and deposit a layer of SiO2 by sputtering in the non-source and drain areas to serve as a mask for ion implantation.

[0065] The masked sample was placed in an ion implanter, and the implantation conditions were set to Si, an injection angle of 6°, and a beam current of 15 mA. 19 cm -3 Ion implantation doping forms an ohmic region.

[0066] Step 6: deposit a Ti / Au metal stack on the source ohmic region and the drain ohmic region, and perform annealing.

[0067] Place the sample after ion implantation on the E-beam evaporation table and set the vacuum degree to 10 -6torr, the evaporated metal is Ti / Au, the temperature is 25°C, the plating rate is 1 angstrom / second, and the Ti / Au metal stack with a thickness of 20nm / 400nm is evaporated in the ohmic region;

[0068] The metal stacked sample after the Ti / Au vapor deposition was placed in an annealing furnace, and the annealing conditions were set to N2 atmosphere, 400°C, and 20s to complete the production of the source ohmic electrode and the drain ohmic electrode.

[0069] The samples with the completed drain ohmic electrode and source ohmic electrode were then immersed in a buffered oxide etching solution until SiO2 was completely removed, and then immersed in an acetone solution and an ethanol solution in turn, and placed in a water bath for ultrasonic treatment for 3 minutes, and then rinsed with deionized water for 3 minutes, and finally blown dry with a nitrogen gun.

[0070] Step 7: Etch away the gallium oxide layer outside the source and drain regions by using an ICP etcher to complete the isolation of the active region.

[0071] Using a mask plate to determine the source and drain regions and the surrounding regions of the source and drain on the cleaned sample, and using a photoresist to mask the above regions;

[0072] The masked sample was placed in an ICP etcher, and the etching process conditions were set to 200W upper power, 50W lower power, and 10mTorr pressure. The gallium oxide layer outside the source and drain regions was etched away by 300nm through the ICP etching process to complete the isolation of the active region.

[0073] The samples with active area isolation were immersed in acetone solution and ethanol solution in turn until the photoresist was completely removed, then rinsed with deionized water for 3 minutes, and finally dried with a nitrogen gun.

[0074] Step 8, using an electron beam lithography machine to form a mask in the shape of a nano-strip, and then using an ICP etcher to etch to form a nano-channel with a width of 50 nm and a depth of 305 nm.

[0075] First, a mask is used to determine the channel area on the cleaned sample, and an electron beam lithography machine is used to perform photolithography on the non-channel area to form a photoresist mask in the shape of a nano-strip;

[0076] Then, the sample with the photoresist mask on the surface was placed in an ICP etcher, and the etching process conditions were set to 200W of upper power, 50W of lower power, and 10mTorr of pressure, to etch a nanochannel with a width of 50nm and a depth of 305nm in the gallium oxide channel layer;

[0077] Finally, the sample with the nano-channel etched was immersed in acetone solution and ethanol solution in turn until the photoresist was completely removed, then rinsed with deionized water for 3 minutes, and finally dried with a nitrogen gun.

[0078] Step 9: Use a mask to determine the gate dielectric region of the sample, and use an ALD device to deposit a 5 nm upper Al2O3 dielectric layer in the gate dielectric region.

[0079] Using a mask to determine the gate dielectric region of the sample, and using a photoresist to mask the non-gate dielectric region;

[0080] The masked sample was placed in the ALD chamber, and the process conditions of the chamber pressure was set to 0.1 torr and the temperature was set to 150°C. Trimethylaluminum and H2O were selected as precursors, and trimethylaluminum was introduced into the chamber for 0.1s, nitrogen for 10s, H2O for 3s, and nitrogen for 10s in sequence. The source-passing steps were repeated 100 times in total, and an upper Al2O3 dielectric layer with a thickness of 5nm was grown in the gate dielectric region by atomic layer deposition.

[0081] Step 10, depositing a Ni / Au metal stack on the upper Al2O3 dielectric layer.

[0082] Place the sample with the upper Al2O3 dielectric layer grown on the E-beam evaporation table and set the vacuum degree to 10 -6 torr, the evaporated metal is Ni / Au, the temperature is 25°C, and the plating rate is 1 angstrom / second under the E-beam evaporation process conditions. Ni / Au metal stacks with thicknesses of 35nm / 350nm are deposited on the upper Al2O3 dielectric layer to complete the top gate electrode.

[0083] Step 11: Use a liquid phase stripping method to strip the structure above the iron oxide layer from the epitaxial substrate.

[0084] The sample was immersed in a 0.1 mol / L hydrochloric acid solution to dissolve the iron oxide until the four corners of the structure above the iron oxide layer were lifted up;

[0085] The sample is then placed in deionized water, and the upper structure is separated from the substrate by the tension of the water, thereby obtaining a stripped gallium oxide MOSFET device.

[0086] Step 12: transfer-bond the stripped gallium oxide MOSFET device to a diamond substrate with Ni / Au laminated metal deposited on the surface by using a surface activation bonding method, and perform annealing.

[0087] Depositing a layer of Ni / Au laminated metal with a thickness of 35 nm / 350 nm respectively on the diamond substrate by E-beam evaporation method, wherein the E-beam evaporation process conditions are the same as the E-beam evaporation process conditions in step 10;

[0088] Add adhesive material to the front of the temporary carrier, spin-coat at a speed of 1000 rpm for 30 seconds, and place the temporary carrier coated with adhesive material on a hot plate with the front side facing upward and bake at 90° C. for 2 minutes, so that the adhesive material is evenly and firmly attached to the temporary carrier;

[0089] The stripped gallium oxide MOSFET device is directly bonded to the front side of the temporary carrier coated with bonding material;

[0090] A 5-nanometer-thick amorphous silicon nanolayer is sputtered on the surface of the gallium oxide MOSFET device bonded with a temporary carrier and the surface of the diamond substrate on which the Ni / Au stacked metal is grown, respectively, by magnetron sputtering, and the silicon nanolayer is activated by an argon atomic beam;

[0091] The two activated surfaces are placed face to face, and then bonded in a bonding machine at a pressure of 3000mba;

[0092] The bonded sample is immersed in an adhesive material removal liquid until the temporary carrier is completely detached, completing the transfer of the peeled gallium oxide MOSFET device to the diamond substrate;

[0093] The transferred sample was placed in an annealing furnace and subjected to thermal annealing treatment in a N2 atmosphere at 300°C for 4 minutes to obtain a gallium oxide MOSFET device with a surrounding gate, thus completing the entire device manufacturing process.

[0094] Example 2: A diamond-based all-around gate gallium oxide MOSFET power device is manufactured with an epitaxial substrate of iron oxide, a sputtered iron oxide layer of 5 μm thickness, a stripping hydrochloric acid concentration of 3 mol / L, a gallium oxide channel layer of 300 nm width and a depth of 720 nm.

[0095] Step A: Select an epitaxial substrate and clean it.

[0096] Iron oxide was selected as the epitaxial substrate material, and the iron oxide substrate was immersed in acetone solution and ethanol solution in turn, placed in a water bath for ultrasonic treatment for 5 minutes, then rinsed with deionized water for 5 minutes, and finally dried with a nitrogen gun.

[0097] Step B: using a Sputter device to grow a 5 μm thick iron oxide film on the surface of the substrate, and performing annealing treatment.

[0098] B1) breaking the vacuum of the Sputter equipment, placing the cleaned substrate in it, and setting the iron oxide target;

[0099] B2) The chamber is evacuated to a vacuum state, and a 5 μm thick iron oxide film is grown on the surface of the substrate by sputtering under the process conditions of room temperature, 160 W power, and a ratio of O2 to Ar gas of 1:2.

[0100] B3) The sample with the iron oxide film was placed in an annealing furnace and annealed in a nitrogen atmosphere at 1100° C. for 60 minutes.

[0101] Step C: using ALD equipment to deposit a 35nm Al2O3 dielectric layer on the iron oxide layer.

[0102] C1) placing the annealed sample in an ALD chamber, selecting trimethylaluminum and H2O as precursors, and introducing 0.3s of trimethylaluminum, 15s of nitrogen, 5s of H2O, and 15s of nitrogen into the chamber in sequence;

[0103] C2) Repeat the source-passing process in step C1) for a total of 700 times, and grow a 35 nm thick Al2O3 dielectric layer on the iron oxide layer by atomic layer deposition under process conditions of a chamber pressure of 0.3 torr and a temperature of 300°C.

[0104] Step D: using MOCVD to deposit two layers of α-galium oxide thin films on the Al2O3 dielectric layer.

[0105] D1) placing the sample with Al2O3 dielectric layer in the MOCVD reaction chamber, and pumping the pipe and chamber with a mechanical pump to reduce impurities introduced from the environment;

[0106] D2) Under the process conditions of 600℃, 200mba, high-purity oxygen as oxygen source, TEGa as gallium source, argon as carrier gas, and 1:200 molar flow ratio of TEGa to O2, the growth rate of the α-direction gallium oxide layer during the epitaxial growth process was monitored in real time by using the reflectivity change of the sample, and the growth time was modified accordingly. The first layer with a thickness of 500nm and a carrier concentration of 1×10 14 cm -3 An α-directed unintentionally doped layer of gallium oxide;

[0107] D3) Under the process conditions of a reaction chamber temperature of 600°C and a pressure of 40 mba; an oxygen source of high purity oxygen, a gallium source of TEGa, a doping source of silane, and a carrier gas of argon; a TEGa to O2 molar flow ratio of 1:5000, and a silane molar flow of 5 μmol / min, the growth rate of the α-direction gallium oxide layer during the epitaxial growth process was monitored in real time by means of the reflectivity change of the sample, and the growth time was modified accordingly. A second layer with a thickness of 600 nm and a carrier concentration of 1×10 16 cm -3 α-oriented gallium oxide channel layer.

[0108] Step E: Use a mask to determine the source and drain region positions of the sample, and perform ion implantation in the source and drain regions to form an ohmic region.

[0109] E1) First, use a mask to determine the source and drain area, and deposit a layer of SiO2 in the non-source and drain area by sputtering to serve as a mask for ion implantation;

[0110] E2) Place the masked sample into an ion implanter and perform 10 ion implantation on the source and drain regions under the conditions of Si implantation ion, 7° implantation angle, and 20 mA beam current. 20 cm -3 The concentration of doping forms an ohmic region.

[0111] Step F, depositing a Ti / Au metal stack on the source ohmic region and the drain ohmic region, and performing annealing.

[0112] F1) Place the sample after ion implantation on the E-beam evaporation table and set the vacuum degree to 10 -7 torr, the evaporated metal is Ti / Au, the temperature is 90℃, and the plating rate is 2 angstroms / second. Under the E-beam evaporation process conditions, the Ti / Au metal stack with a thickness of 40nm / 600nm is evaporated in the ohmic region;

[0113] F2) placing the Ti / Au metal stacked sample after evaporation into an annealing furnace, and annealing the sample under the annealing conditions of N2 atmosphere, temperature 450°C, and time 40s to complete the production of the source ohmic electrode and the drain ohmic electrode;

[0114] F3) The samples with the drain ohmic electrode and the source ohmic electrode are immersed in a buffered oxide etching solution until SiO2 is completely removed, and then immersed in an acetone solution and an ethanol solution in sequence, and ultrasonically treated in a water bath for 5 minutes, and then rinsed with deionized water for 5 minutes, and finally dried with a nitrogen gun.

[0115] Step G: Etch away the gallium oxide layer outside the source and drain regions by using an ICP etcher to complete the isolation of the active region.

[0116] G1) using a mask to determine the source and drain regions and the surrounding regions of the source and drain on the cleaned sample, and using a photoresist to mask the above regions;

[0117] G2) placing the masked sample in an ICP etcher, setting the etching process conditions to 500W upper power, 150W lower power, and 20mTorr pressure, and etching 1100nm of the gallium oxide layer outside the source and drain regions through the ICP etching process to complete the isolation of the active region;

[0118] G3) The sample with active area isolation is immersed in acetone solution and ethanol solution in sequence until the photoresist is completely removed, then rinsed with deionized water for 5 minutes, and finally dried with a nitrogen gun.

[0119] Step H: etching the gallium oxide channel layer to form a nano-channel.

[0120] H1) using a mask to determine the channel region on the cleaned sample, and using an electron beam lithography machine to perform photolithography on the non-channel region to form a photoresist mask in the shape of a nano-strip;

[0121] H2) placing the sample with the photoresist mask on the surface into an ICP etcher, and etching a nanochannel with a width of 300 nm and a depth of 720 nm in the gallium oxide channel layer under the etching process conditions of 500 W upper power, 150 W lower power, and 20 mTorr pressure;

[0122] H3) The sample with the nano-channels etched therein was immersed in acetone solution and ethanol solution in sequence until the photoresist was completely removed, then rinsed with deionized water for 5 minutes, and finally dried with a nitrogen gun.

[0123] Step I: Use a mask to determine the gate dielectric region of the sample, and use ALD equipment to deposit a 35nm upper Al2O3 dielectric layer in the gate dielectric region.

[0124] I1) using a mask to determine the gate dielectric region of the sample, and using a photoresist to mask the non-gate dielectric region;

[0125] I2) Place the masked sample into the ALD chamber, set the chamber pressure to 0.5 torr, and the temperature to 450°C; select trimethylaluminum and H2O as precursors, and introduce 0.3s of trimethylaluminum, 15s of nitrogen, 8s of H2O, and 15s of nitrogen into the chamber in sequence;

[0126] I3) Repeat the source-passing step in I2) for 700 times in total, and grow an upper Al2O3 dielectric layer with a thickness of 35 nm in the gate dielectric region by atomic layer deposition.

[0127] Step J, depositing a Ni / Au metal stack on top of the upper Al2O3 dielectric layer.

[0128] The sample with the upper Al2O3 dielectric layer grown was placed on the E-beam evaporation table and the vacuum degree was 10 -6 torr, the evaporated metal is Ni / Au, the temperature is 75°C, and under the E-beam evaporation process conditions with a plating rate of 2 angstroms / second, a Ni / Au metal stack with a thickness of 55nm / 450nm is deposited on the upper Al2O3 dielectric layer to complete the top gate electrode.

[0129] Step K: Use a liquid phase stripping method to strip the structure above the iron oxide layer from the epitaxial substrate.

[0130] K1) immersing the sample in a 3 mol / L hydrochloric acid solution to dissolve the iron oxide until the four corners of the structure above the iron oxide layer are lifted up;

[0131] K2) The sample is placed in deionized water, and the upper structure is separated from the substrate by the tension of water to obtain a stripped gallium oxide MOSFET device.

[0132] Step L: transfer bonding the stripped gallium oxide MOSFET device to a diamond substrate with Ni / Au stacked metal deposited on the surface by using a surface activation bonding method, and perform annealing.

[0133] L1) depositing a layer of Ni / Au laminated metal with a thickness of 55 nm / 450 nm respectively on the diamond substrate by E-beam evaporation method, and the E-beam evaporation process conditions are the same as the E-beam evaporation process conditions in step J;

[0134] L2) dripping adhesive material on the front side of the temporary carrier, spin coating at a speed of 3000 rpm for 30 seconds, placing the temporary carrier coated with adhesive material on a hot plate with the front side facing upward and baking at a temperature of 110° C. for 5 minutes, so that the adhesive material is evenly and firmly attached to the temporary carrier;

[0135] L3) directly bonding the stripped gallium oxide MOSFET device to the front side of the temporary carrier coated with the bonding material;

[0136] L4) sputtering an amorphous silicon nanolayer with a thickness of 10 nanometers on the surface of the gallium oxide MOSFET device bonded with a temporary carrier and the surface of the diamond substrate on which the Ni / Au stacked metal is grown, respectively, by magnetron sputtering, and activating the silicon nanolayer using an argon atomic beam;

[0137] L5) facing the two surfaces after activation, and then bonding them in a bonding machine at a pressure of 5000mba;

[0138] L6) Soaking the bonded sample in a bonding material removal solution until the temporary carrier is completely detached, completing the transfer of the stripped gallium oxide MOSFET to the diamond substrate;

[0139] L7) The transferred sample is placed in an annealing furnace and subjected to thermal annealing treatment in a N2 atmosphere at 400°C for 6 minutes to obtain a diamond-based all-around gate gallium oxide MOSFET, thus completing the entire device fabrication.

[0140] Example 3: A diamond-based all-around gate gallium oxide MOSFET power device is manufactured with sapphire as the epitaxial substrate, a sputtered iron oxide layer with a thickness of 2 μm, a hydrochloric acid concentration of 1 mol / L for stripping, a gallium oxide channel layer with a width of 500 nm and a depth of 1135 nm.

[0141] Step 1: Select an epitaxial substrate and clean it.

[0142] Sapphire was selected as the epitaxial substrate material, and the sapphire substrate was immersed in HF solution, acetone solution, and ethanol solution in turn, and placed in a water bath for ultrasonic treatment for 5 minutes, then rinsed with deionized water for 5 minutes, and finally dried with a nitrogen gun.

[0143] Step 2: Using a Sputter device, a 2 μm thick iron oxide film is grown on the surface of the substrate, and then annealing is performed.

[0144] 2.1) Break the vacuum of the Sputter equipment, place the cleaned substrate in it, and set the iron oxide target;

[0145] 2.2) The chamber was evacuated to vacuum, and a 2 μm thick iron oxide film was grown on the substrate surface by sputtering under the process conditions of room temperature, 100 W power, and a ratio of O2 to Ar gas of 1:5.

[0146] 2.3) The sample with the iron oxide film was placed in an annealing furnace and annealed in a nitrogen atmosphere at 800°C for 40 minutes.

[0147] Step three: Use ALD equipment to deposit a 20nm Al2O3 dielectric layer on the iron oxide layer.

[0148] 3.1) The annealed sample was placed in an ALD chamber, trimethylaluminum and H2O were selected as precursors, and 0.2s of trimethylaluminum, 12s of nitrogen, 8s of H2O, and 12s of nitrogen were introduced into the chamber in sequence;

[0149] 3.2) Repeat the source-passing process in step 3.1) for a total of 400 times, and grow a 20 nm thick Al2O3 dielectric layer on the iron oxide layer by atomic layer deposition under the process conditions of a chamber pressure of 0.3 torr and a temperature of 300°C.

[0150] Step 4: Use MOCVD to deposit two layers of α-galium oxide films on the Al2O3 dielectric layer.

[0151] 4.1) Place the sample with Al2O3 dielectric layer in the MOCVD reaction chamber, and use a mechanical pump to pump the pipe and chamber to reduce impurities introduced from the environment;

[0152] 4.2) The first layer with a thickness of 200 nm and a carrier concentration of 1×10 16 cm -3 The α-doped gallium oxide unintentional doping layer has the following process conditions:

[0153] The reaction chamber temperature is 500°C and the pressure is 100mba;

[0154] The oxygen source is high-purity oxygen, the gallium source is TEGa, and the carrier gas is argon;

[0155] The molar flow ratio of TEGa to O2 is 1:400, and the growth rate of the α-direction gallium oxide layer during the epitaxial growth process is monitored in real time by using the reflectivity change of the sample, and the growth time is modified accordingly;

[0156] 4.3) A second layer with a thickness of 600 nm and a carrier concentration of 1×10 18 cm -3 The α-oriented gallium oxide channel layer has the following process conditions:

[0157] The reaction chamber temperature is 500°C and the pressure is 50mba;

[0158] The oxygen source is high-purity oxygen, the gallium source is TEGa, the doping source is silane, and the carrier gas is argon;

[0159] The molar flow ratio of TEGa to O2 is 1:2000, the molar flow rate of silane is 50 μmol / min, and the growth rate of the α-direction gallium oxide layer during the epitaxial growth process is monitored in real time by means of the reflectivity change of the sample, and the growth time is modified accordingly.

[0160] Step 5: Use a mask to determine the location of the source and drain regions of the sample, and perform ion implantation in the source and drain regions to form an ohmic region.

[0161] First, use a mask to determine the source and drain areas, and deposit a layer of SiO2 in the non-source and drain areas by sputtering to serve as a mask for ion implantation. Then, place the masked sample in an ion implanter and perform ion implantation in the source and drain areas for 10 21 cm -3 The concentration of doping forms an ohmic region, and the injection conditions are as follows:

[0162] The implanted ions are Si, the implantation angle is 8°, and the beam current is 25 mA.

[0163] Step six, depositing a Ti / Au metal stack on the source ohmic region and the drain ohmic region, and performing annealing.

[0164] 6.1) The sample after ion implantation was placed on an E-beam evaporation table, and Ti / Au metal stacks with thicknesses of 40nm / 600nm were evaporated in the ohmic region. The process conditions were as follows:

[0165] Vacuum degree is 10 -7 torr, the evaporated metal is Ti / Au, the temperature is 70°C, and the plating rate is 1.5 Å / s;

[0166] 6.2) The Ti / Au metal stacked sample after evaporation is placed in an annealing furnace for annealing to complete the production of the source ohmic electrode and the drain ohmic electrode. The annealing conditions are as follows:

[0167] The atmosphere is N2, the temperature is 430°C, and the annealing time is 40s;

[0168] 6.3) The samples with the drain ohmic electrode and the source ohmic electrode were immersed in a buffered oxide etching solution until SiO2 was completely removed, and then immersed in an acetone solution and an ethanol solution in turn, and ultrasonically treated in a water bath for 5 minutes, and then rinsed with deionized water for 5 minutes, and finally dried with a nitrogen gun.

[0169] Step seven: Use an ICP etcher to etch away the gallium oxide layer outside the source and drain regions to complete the isolation of the active region.

[0170] 7.1) Use a mask to determine the source and drain regions and the surrounding regions of the source and drain on the cleaned sample, and use a photoresist to mask the above regions;

[0171] 7.2) Place the masked sample in an ICP etcher, and etch away 1100nm of the gallium oxide layer outside the source and drain regions through an ICP etching process to complete the isolation of the active region. The etching process conditions are as follows:

[0172] The upper power is 400W, the lower power is 100W, and the pressure is 15mTorr;

[0173] 7.3) The samples with active area isolation were immersed in acetone solution and ethanol solution in turn until the photoresist was completely removed, then rinsed with deionized water for 5 minutes, and finally dried with a nitrogen gun.

[0174] Step eight, etching the gallium oxide channel layer to form a nano-channel.

[0175] 8.1) Using a mask to determine the channel area on the cleaned sample, and using an electron beam lithography machine to perform photolithography on the non-channel area to form a photoresist mask in the shape of a nano-strip;

[0176] 8.2) The sample with the photoresist mask on the surface is placed in an ICP etcher, and a nanochannel with a width of 500 nm and a depth of 1135 nm is etched in the gallium oxide channel layer by an ICP etching process. The etching process conditions are as follows:

[0177] The upper power is 400W, the lower power is 100W, and the pressure is 15mTorr;

[0178] 8.3) The sample with the nano-channels etched therein was immersed in acetone solution and ethanol solution in sequence until the photoresist was completely removed, then rinsed with deionized water for 5 minutes, and finally dried with a nitrogen gun.

[0179] Step nine: Use a mask to determine the gate dielectric region of the sample, and use ALD equipment to deposit a 35nm upper Al2O3 dielectric layer in the gate dielectric region.

[0180] 9.1) Using a mask to determine the gate dielectric region of the sample, and using a photoresist to mask the non-gate dielectric region;

[0181] 9.2) The masked sample is placed in an ALD chamber and an upper Al2O3 dielectric layer with a thickness of 20 nm is grown in the gate dielectric region by atomic layer deposition. The atomic layer deposition conditions are as follows:

[0182] The pressure of the chamber is 0.3 torr and the temperature is 400°C;

[0183] Trimethylaluminum and H2O were selected as precursors, and trimethylaluminum for 0.3 s, nitrogen for 15 s, H2O for 8 s, and nitrogen for 15 s were introduced into the chamber in sequence, and this source-passing step was repeated 400 times in total.

[0184] Step ten, depositing a Ni / Au metal stack on the upper Al2O3 dielectric layer.

[0185] The sample with the upper Al2O3 dielectric layer grown was placed on the E-beam evaporation table. Ni / Au metal stacks with thicknesses of 40nm / 400nm were deposited on the upper Al2O3 dielectric layer by the E-beam evaporation process to complete the top gate electrode. The E-beam evaporation process conditions are as follows:

[0186] Vacuum degree is 10 -6 torr, the evaporated metal is Ni / Au, the temperature is 75°C, and the plating rate is 1.5 Å / s.

[0187] Step eleven: Use a liquid phase stripping method to strip the structure above the iron oxide layer from the epitaxial substrate.

[0188] The sample was immersed in a 1 mol / L hydrochloric acid solution to dissolve the iron oxide until the four corners of the structure above the iron oxide layer lifted up. The sample was then placed in deionized water, and the tension of the water was used to separate the upper structure from the substrate, thus obtaining a stripped gallium oxide MOSFET device.

[0189] Step 12: transfer and bond the stripped gallium oxide MOSFET device to a diamond substrate with Ni / Au stacked metal deposited on the surface by using a surface activation bonding method, and perform annealing.

[0190] 12.1) depositing a layer of Ni / Au laminated metal with a thickness of 40 nm / 400 nm respectively on the diamond substrate by E-beam evaporation method, wherein the E-beam evaporation process conditions are the same as the E-beam evaporation process conditions in step 10;

[0191] 12.2) Add adhesive material to the front of the temporary carrier, spin-coat at a speed of 2000 rpm for 40 seconds, and place the temporary carrier coated with adhesive material on a hot plate with the front side facing upwards and bake at 100° C. for 4 minutes to ensure that the adhesive material is evenly and firmly attached to the temporary carrier;

[0192] 12.3) directly bonding the stripped gallium oxide MOSFET device to the front side of the temporary carrier coated with the bonding material; then, using magnetron sputtering, sputtering an amorphous silicon nanolayer with a thickness of 8 nanometers on the surface of the gallium oxide MOSFET device bonded to the temporary carrier and the surface of the diamond substrate on which the Ni / Au stacked metal is grown, respectively, and activating the silicon nanolayer using an argon atomic beam;

[0193] 12.4) The two surfaces after activation are placed face to face, and then bonded in a bonding machine at a pressure of 4000mba; the bonded sample is immersed in an adhesive material removal liquid until the temporary carrier is completely detached, completing the transfer of the peeled gallium oxide MOSFET to the diamond substrate;

[0194] 12.5) The transferred sample was placed in an annealing furnace and subjected to thermal annealing treatment in a N2 atmosphere at 400°C for 5 minutes to obtain a diamond-based all-around gate gallium oxide MOSFET, completing the entire device fabrication process.

[0195] The above descriptions are only three specific examples of the present invention and do not constitute any limitation to the present invention. Obviously, for professionals in this field, after understanding the content and principles of the present invention, it is possible to make various modifications and changes in form and details without departing from the principles and structures of the present invention. For example, in addition to hydrochloric acid solution, a low-concentration hydrofluoric acid solution can be used as the iron oxide dissolving solution in the liquid phase stripping method; in addition to Ti / Au metal stacks, the source and drain ohmic electrodes can also be Ti / Al / Ni / Au metal stacks. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A surrounding gate gallium oxide MOSFET power device, comprising a substrate (1), an unintentionally doped UID gallium oxide layer (2), a gallium oxide channel layer (3), an upper Al2O3 dielectric layer (4), a source ohmic electrode (5), a drain ohmic electrode (6), and a top gate electrode (7), characterized in that: The substrate (1) is made of diamond material with high thermal conductivity to effectively improve the heat dissipation capability of the gallium oxide MOSFET device; An Al2O3 dielectric layer (9) and a Ni / Au metal layer (8) are sequentially arranged between an unintentionally doped UID gallium oxide layer (2) and a substrate (1); the Al2O3 dielectric layer (9) is connected to an upper Al2O3 dielectric layer (4) and together surrounds a gallium oxide channel layer (3); the Ni / Au metal layer (8) is connected to a top gate electrode (7) and together surrounds the upper Al2O3 dielectric layer (4) and the Al2O3 dielectric layer (9) to improve the gate's ability to control the channel.

2. The structure according to claim 1, characterized in that: The unintentionally doped UID gallium oxide layer (2) is located above the Al2O3 dielectric layer (9) and has a thickness of 100nm to 500nm and a carrier concentration of 1×10 14 cm -3 ~1×10 16 cm -3 ; The gallium oxide channel layer (3) is located above the unintentionally doped UID gallium oxide layer (2) and has a thickness of 200nm to 600nm and a carrier concentration of 1×10 16 cm -3 ~1×10 18 cm -3 ; The upper Al2O3 dielectric layer (4) has a thickness of 5 to 35 nm; The source ohmic electrode (5) and the drain ohmic electrode (6) are both made of Ti / Au, with a thickness of 20-40nm / 400-600nm, and are respectively located in the ohmic regions on both sides above the gallium oxide channel layer (3); The top gate electrode (7) is made of Ni / Au and has a thickness of 35-55nm / 350-450nm; The Ni / Au metal layer (8) has a thickness of 35-55nm / 350-450nm. The Al2O3 dielectric layer (9) has a thickness of 5 to 35 nm.

3. A method for manufacturing a MOSFET power device with a surrounding gate gallium oxide, characterized in that: The steps include: 1) Select the epitaxial substrate and clean it; 2) Using a Sputter device, a layer of iron oxide film is grown on the surface of the cleaned substrate and annealed; 3) using ALD equipment to deposit a 5-35 nm Al2O3 dielectric layer on top of the iron oxide layer; 4) The sample with the Al2O3 dielectric layer deposited was placed in an MOCVD reaction chamber, and a metal organic chemical vapor deposition method was used to sequentially grow a carrier concentration of 1×10 14 cm -3 ~1×10 16 cm -3 , the first layer of α-doped gallium oxide is 100nm to 500nm thick, and the carrier concentration is 1×10 16 cm -3 ~1×10 18 cm -3 , a second α-oriented gallium oxide channel layer having a thickness of 200nm to 600nm; 5) Use a mask to determine the source and drain region locations of the sample, and perform ion implantation in the source and drain regions to form an ohmic region; 6) depositing a Ti / Au metal stack above the source ohmic region and the drain ohmic region, and performing annealing to complete the fabrication of the source ohmic electrode and the drain ohmic electrode; 7) Etch away the gallium oxide layer outside the source and drain regions using an ICP etcher to isolate the active region; 8) Using an electron beam lithography machine to form a mask in the shape of a nano-strip, and then using an ICP etcher to etch to form a nano-channel; 9) Using a mask to determine the gate dielectric region of the sample, and using an ALD device to deposit a 5-35 nm upper Al2O3 dielectric layer in the gate dielectric region; 10) Depositing a Ni / Au metal stack on the upper Al2O3 dielectric layer to complete the upper gate electrode fabrication; 11) using a liquid phase stripping method to strip the structure above the iron oxide layer from the epitaxial substrate; 12) The structure above the iron oxide layer is transferred and bonded to a diamond substrate with Ni / Au stacked metal deposited on the surface by using a surface activation bonding method, and annealing is performed to complete the entire device manufacturing.

4. The method according to claim 3, characterized in that: The epitaxial substrate in step 1) is made of sapphire or α-iron oxide, which are materials with a corundum structure; The cleaning in step 1) is to first immerse the substrate in acetone solution and ethanol solution in sequence, and then place it in a water bath. The samples were ultrasonically treated for 3 to 5 minutes, then rinsed with deionized water for 3 to 5 minutes, and finally dried with a nitrogen gun. In the step 2), a layer of iron oxide film is grown on the surface of the cleaned substrate using a Sputter device. Yes first Break the vacuum of the equipment, send the cleaned sample into its chamber, and set the iron oxide target; then evacuate the chamber to vacuum, set the temperature to room temperature, the power to 90-160W, and the process conditions of O2 to Ar ratio of 1:5-1:2, and grow a layer of iron oxide film with a thickness of 100nm-5μm on the surface of the substrate by sputtering; The annealing treatment in step 2) is performed in a nitrogen atmosphere at a temperature of 500 to 1100° C. for 20 to 60 minutes on the sample grown with the iron oxide film.

5. The method according to claim 3, characterized in that: In step 3), an Al2O3 dielectric layer of 5 to 35 nm is deposited on the iron oxide layer using an ALD device, which is implemented as follows: 3a) firstly place the annealed sample in an ALD chamber, set the chamber pressure to 0.1-0.5 torr and the temperature to 150-450°C; 3b) Trimethylaluminum and H2O are selected as precursors, and trimethylaluminum is introduced into the chamber in sequence for 0.1-0.3s, nitrogen for 10-15s, H2O for 3-8s, and nitrogen for 10-15s. 3c) Repeat the process of 3b) for 100 to 700 times, and grow an Al2O3 dielectric layer with a thickness of 5 nm to 35 nm on the iron oxide layer by atomic layer deposition.

6. The method according to claim 3, characterized in that In step 4), two α-oriented gallium oxide layers are sequentially grown on the Al2O3 dielectric layer using a metal organic chemical vapor deposition (MOCVD) method, and the process conditions are as follows: 4a) depositing a first α-doped gallium oxide layer on the Al2O3 dielectric layer, the process conditions of which are: The temperature of the reaction chamber is 400-600°C and the pressure is 40mba-200mba; The oxygen source is high-purity oxygen, the gallium source is TEGa, and the carrier gas is argon; The molar flow ratio of TEGa to O2 is 1:5000 to 1:200; 4b) The process conditions for depositing a second α-oriented gallium oxide channel layer on the first α-oriented gallium oxide layer are: The temperature of the reaction chamber is 400-600°C and the pressure is 40mba-200mba; The oxygen source is high-purity oxygen, the gallium source is TEGa, the doping source is silane, and the carrier gas is argon; The molar flow ratio of TEGa to O2 is 1:5000 to 1:200, and the molar flow rate of silane is 5 to 50 μmol / min.

7. The method according to claim 3, characterized in that In step 5), a mask is used to determine the source and drain region positions of the sample, and ion implantation is performed in the source and drain regions to form an ohmic region, which is achieved as follows: 5a) Use a mask to determine the source and drain region locations of the sample, and deposit a layer of SiO2 by sputtering in the non-source and drain regions to serve as a mask for ion implantation; 5b) Place the masked sample into an ion implanter and set the ion implantation conditions as follows: implanted ions are Si, the implantation angle is 6-8°, the beam current is 15-25 mA, and 10 19 ~10 21 cm -3 The doping concentration forms an ohmic region.

8. The method according to claim 3, characterized in that In step 6), a Ti / Au metal stack is deposited on the source ohmic region and the drain ohmic region, and annealed, to achieve the following: 6a) Place the sample after ion implantation on the E-beam evaporation table and set the E-beam evaporation process conditions to: vacuum degree 10 -6 ~10 -7 torr, the evaporated metal is Ti / Au, the temperature is 25-90°C, the plating rate is 1-2 angstroms / second, and the Ti / Au metal stack with a thickness of 20-40nm / 400-600nm is evaporated in the ohmic region; 6b) The Ti / Au metal stacked sample after vapor deposition is placed in an annealing furnace, and annealed under the annealing conditions of setting the atmosphere to N2, the temperature to 400-450°C, and the time to 20-40s to complete the production of the source ohmic electrode and the drain ohmic electrode. 6c) The samples with the drain ohmic electrode and the source ohmic electrode are immersed in a buffered oxide etching solution until SiO2 is completely removed, and then immersed in an acetone solution and an ethanol solution in turn, and ultrasonically treated in a water bath for 3 to 5 minutes, and then rinsed with deionized water for 3 to 5 minutes, and finally blown dry with a nitrogen gun.

9. The method according to claim 3, characterized in that: In the step 7), the gallium oxide layer outside the source and drain regions is etched away by an ICP etcher, as follows: 7a) using a mask to determine the source and drain regions and the surrounding regions of the source and drain on the cleaned sample, and using a photoresist to mask the above regions; 7b) placing the masked sample in an ICP etcher, setting the etching process conditions of upper power of 200-500W, lower power of 50-150W, and pressure of 10-20mTorr, and etching the gallium oxide layer outside the source and drain regions by 300-1100nm through the ICP etching process to complete the isolation of the active region; 7c) The sample with active area isolation is immersed in acetone solution and ethanol solution in sequence until the photoresist is completely removed, then rinsed with deionized water for 3 to 5 minutes, and finally dried with a nitrogen gun.

10. The method according to claim 3, characterized in that In the step 8), an electron beam lithography machine is used to form a mask in the shape of a nano-strip, and then an ICP etcher is used to etch to form a nano-channel, which is achieved as follows: 8a) using a mask to determine the channel region on the cleaned sample, and using an electron beam lithography machine to perform photolithography on the non-channel region to form a photoresist mask in the shape of a nano-strip; 8b) placing the sample with the photoresist mask on the surface into an ICP etcher, setting the etching process conditions of upper power of 200-500W, lower power of 50-150W, and pressure of 10-20mTorr, and etching a nanochannel with a width of 50-500nm and a depth of 305-1135nm; 8c) The sample with the nano-channels etched thereon is sequentially immersed in an acetone solution and an ethanol solution until the photoresist is completely removed, then rinsed with deionized water for 3 to 5 minutes, and finally dried with a nitrogen gun.

11. The method according to claim 3, characterized in that In the step 9), a mask is used to determine the gate dielectric region of the sample, and an ALD device is used to deposit a 5-35 nm upper Al2O3 dielectric layer in the gate dielectric region, which is implemented as follows: 9a) using a mask to determine the gate dielectric region of the sample, and using a photoresist to mask the non-gate dielectric region; 9b) placing the masked sample into an ALD chamber, setting the chamber pressure to 0.1-0.5 torr and the temperature to 150-450°C; selecting trimethylaluminum and H2O as precursors, and introducing trimethylaluminum for 0.1-0.3s, nitrogen for 10-15s, H2O for 3-8s, and nitrogen for 10-15s into the chamber in sequence; 9c) Repeat step 9b) for 100 to 700 times, and grow an Al2O3 dielectric layer with a thickness of 5 nm to 35 nm in the gate dielectric region by atomic layer deposition.

12. The method according to claim 3, characterized in that: In the step 10), the Ni / Au metal stack is deposited on the upper Al2O3 dielectric layer by placing the sample after the upper Al2O3 dielectric layer is grown on an E-beam evaporation table and setting the vacuum degree to 10 -6 ~10 -7 torr, the evaporated metal is Ni / Au, the temperature is 25-90℃, the plating rate is 1-2 angstroms / second under the E-beam evaporation process conditions, and a Ni / Au metal stack with a thickness of 35-55nm / 350-450nm is deposited on the upper Al2O3 dielectric layer to complete the top gate electrode. In the step 11), the structure above the iron oxide layer is peeled off from the epitaxial substrate by using a liquid phase peeling method, which is to first immerse the sample in a hydrochloric acid solution with a concentration of 0.1 to 3 mol / L to dissolve the iron oxide until the four corners of the structure above the iron oxide layer are lifted up; The sample is then placed in deionized water, and the upper structure is separated from the substrate by the tension of the water, thereby obtaining a stripped gallium oxide MOSFET device.

13. The method according to claim 3, characterized in that In the step 12), the stripped gallium oxide MOSFET device is transferred and bonded to a diamond substrate with Ni / Au laminated metal deposited on the surface by using a surface activation bonding method, and annealing is performed to achieve the following: 12a) depositing a layer of Ni / Au laminated metal with a thickness of 35-55 nm / 350-450 nm on the diamond substrate by E-beam evaporation method, wherein the E-beam evaporation process conditions are the same as the E-beam evaporation process conditions in step 10); 12b) dripping an adhesive material onto the front side of the temporary carrier, and performing spin coating at a speed of 1000 to 3000 rpm for 30 to 60 seconds, and placing the temporary carrier coated with the adhesive material with the front side facing upward on a hot plate and baking at a temperature of 90 to 110° C. for 2 to 5 minutes, so that the adhesive material is evenly and firmly attached to the temporary carrier; 12c) directly bonding the peeled gallium oxide MOSFET device to the front side of the temporary carrier coated with the adhesive material; 12d) sputtering an amorphous silicon nanolayer with a thickness of 5 to 10 nanometers on the surface of the gallium oxide MOSFET device bonded to the temporary carrier and the surface of the diamond substrate on which the Ni / Au stacked metal is grown, respectively, by magnetron sputtering, and activating the silicon nanolayer using an argon atomic beam; 12e) facing the two activated surfaces, and bonding them in a bonding machine at a pressure of 3000 to 5000 mbar; 12f) soaking the bonded sample in an adhesive material removal solution until the temporary carrier sheet is completely removed; 12g) The sample is placed in an annealing furnace and subjected to a thermal annealing treatment in a N2 atmosphere at 300-400°C for 4-6 minutes to complete the fabrication of a surrounding gate gallium oxide MOSFET device.

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