Charging and discharging type capacitive sensor measuring circuit

Abstract

The invention relates to the technical field of capacitive sensors, in particular to a charge and discharge type capacitive sensor measuring circuit which comprises a detected capacitor Cs, a stray capacitor C0, a resistor R0, an isolation capacitor C1, a first transistor Q1, a second transistor Q2, a conduction control valve, a signal acquisition resistor Rs, a signal configuration switch SW1, a signal amplifier AMP, a first linear power supply, a second linear power supply and an AC / DC converter. VC0 and VCs are picked up through a signal configuration switch SW1, and charging and discharging of the stray capacitor co and the detected capacitor CS are controlled in an upper and lower bridge mode; two groups of linear power supplies and different grounding points VSS1 and Vss2 are adopted at the same time, and compared with the prior art, the whole measuring circuit solves the problem that the signal variation is uncertain after the influence of temperature in the prior art through the same signal configuration switch SW1 and the upper and lower bridge switches on the charging and discharging of the two capacitors.

Description

Technical Field

[0001] The present invention relates to the technical field of capacitance sensors, and in particular to a charge-discharge capacitance sensor measurement circuit. Background Art

[0002] As an important sensing element, capacitive sensors have been widely used in industrial automation, environmental monitoring, consumer electronics and other fields. According to different working principles, capacitive sensors are mainly divided into two categories: self-oscillation type and charge-discharge type. Among them, the charge-discharge type capacitive sensor adopts timing pulse control technology, which can better suppress the influence of environmental stray capacitance and external electromagnetic interference, so it shows higher stability and reliability in high-precision measurement and complex environment.

[0003] However, in the process of realizing the working principle of charge-discharge capacitive sensors, the existing technology faces a series of technical challenges. Specifically, in order to realize the signal switching during the charge-discharge process, multiple electronic switches are usually used. The on and off characteristics of these electronic switches are crucial to the performance of the sensor, especially their respective on capacitance (Con) and off capacitance (Coff) parameters.

[0004] First, there are large differences in the electronic switch characteristics between different products. In order to achieve effective measurement of the detected capacitance and eliminate the influence of environmental stray capacitance, such as Figure 1 As shown, the prior art uses four groups of electronic switches to introduce the detection signal into the input of the operational amplifier for signal amplification. However, each electronic switch has different Con and Coff parameters when turned on and off. These parameters are usually in the order of magnitude of 0.1pF to 2pF, which are close to the values ​​of the detected capacitance and stray capacitance. In order to solve this problem, the prior art introduces low-frequency switches SW3 and SW4. By setting the frequency of the timing pulse F1, the signals of the stray capacitance and the detected capacitance appear alternately at the input of the amplifier circuit, thereby forming a circuit structure that can reduce the influence of the Con and Coff of the SW3 and SW4 switches. However, for the two switches SW1 and SW2, since it is impossible to form a similar reduction circuit, in actual applications, different batches of electronic switches will cause large differences in the signals finally generated by the circuit.

[0005] Secondly, the effect of temperature on the Con and Coff of the electronic switch is also a contradiction that is difficult to reconcile in the prior art. The Con and Coff parameters of the electronic switch will change with changes in temperature, and this change poses a severe challenge to the performance stability of the circuit. Specifically, when the temperature rises, if the Con change of SW1 is greater than that of SW2, the final output signal of the circuit will become larger; conversely, if the Con change of SW1 is less than that of SW2, the output signal will become smaller. Since the direction and amplitude of the Con change of SW1 and SW2 with temperature are uncertain, this effect cannot be eliminated by simple temperature compensation. This leads to the application scenarios of this circuit having very high requirements for ambient temperature changes, which limits its application in environments with large temperature changes.

[0006] In summary, in the process of realizing charge-discharge type capacitive sensors, the prior art faces difficulties such as differences in electronic switch characteristics and temperature effects, and these problems need to be solved urgently to improve the performance and stability of the capacitive sensors. Summary of the invention

[0007] In order to overcome the deficiencies of the prior art, the present application provides a charge-discharge type capacitance sensor measurement circuit, which aims to improve the problems of the influence of temperature on the product and the large fluctuation of product characteristics in the prior art.

[0008] The technical means adopted by the present invention to solve the technical problem is: a charge-discharge type capacitance sensor measurement circuit, the improvement of which is that it includes: a detected capacitance Cs, a stray capacitance C0, a resistor R0, an isolation capacitor C1, a first transistor Q1, a second transistor Q2, a conduction control valve, a signal acquisition resistor Rs, a signal configuration switch SW1, a signal amplifier AMP, a first linear power supply, a second linear power supply, and an AC / DC converter, wherein:

[0009] One end of the detected capacitor Cs is connected to the object to be measured, and the other end is connected to the collectors of the first transistor Q1 and the second transistor Q2, and is grounded through the stray capacitor C0 and the resistor R0;

[0010] The emitter of the first transistor Q1 is connected to the output end of the first linear power supply, and the emitter of the second transistor is connected to one end of the isolation capacitor C1 and the signal acquisition resistor Rs respectively; the bases of the first transistor Q1 and the second transistor Q2 are connected to the conduction control valve; the other end of the isolation capacitor C1 is connected to the signal configuration switch SW1, and the other end of the signal acquisition resistor Rs is connected to the output end of the first linear power supply;

[0011] The other end of the signal configuration switch SW1 is respectively connected to the positive and negative input terminals of the signal amplifier AMP, the positive power supply pin of the signal amplifier AMP is connected to the output terminal of the second linear power supply, and the negative power supply pin of the signal amplifier AMP is grounded;

[0012] The input end of the second linear power supply is connected to the output end of the first linear power supply, the input end of the first linear power supply is connected to the output end of the AC / DC converter, and the input end of the AC / DC converter is grounded.

[0013] The signal acquisition resistor Rs in the above technical solution can be replaced by an inductor.

[0014] The signal amplifier AMP in the above technical solution has high input impedance and low output impedance.

[0015] The circuit in the above technical solution also includes a protection circuit, which is connected in series between the output end of the AC / DC converter and the input end of the first linear power supply, and is used to automatically cut off the power supply when the power supply voltage is abnormal or the circuit is overloaded.

[0016] The frequency of the timing pulse F1 of the conduction control valve in the above technical solution is 1M-2MHz.

[0017] In the above technical solution, the first linear power supply and the second linear power supply are both low-noise, high-precision adjustable power supplies.

[0018] In the above technical solution, the types of the first transistor and the second transistor include MOS transistors and bipolar transistors.

[0019] The signal configuration switch SW1 in the above technical solution is a single-pole double-throw switch, the normally closed contact NC of the signal configuration switch SW1 is connected to the positive input terminal of the signal amplifier AMP, and the normally open contact NO of the signal configuration switch SW1 is connected to the negative input terminal of the signal amplifier AMP.

[0020] The circuit in the above technical solution also includes an XOR logic gate, capacitors C2 and C3, wherein:

[0021] The XOR logic gate is connected to the signal configuration switch SW1, and generates a combined pulse timing pulse F3 according to the timing pulse F1 and the timing pulse F2 to control the conduction and closing of the signal configuration switch SW1; the frequency of the timing pulse F1 is 1M-2MHz, and the frequency of the timing pulse F2 is 1K-2K;

[0022] One end of the capacitor C2 is connected to one end of the signal configuration switch and the negative input end of the signal amplifier AMP, and the other end is grounded;

[0023] One end of the capacitor C3 is connected to one end of the signal configuration switch SW1 and the positive input end of the signal amplifier AMP, and the other end of the capacitor C3 is grounded.

[0024] The XOR logic gate in the above technical solution also receives an external reset signal, which is used to reset the generation of the timing pulse F3 under certain conditions so that the circuit can restart the measurement process.

[0025] The beneficial effects of the present invention are:

[0026] 1. Improved the influence of temperature on products in the existing technology, ensuring that capacitive sensors can be used in most industrial applications;

[0027] 2. Improved the problem of large fluctuations in product characteristics, eliminated adjustment steps, reduced processing time for a single product, and indirectly reduced product costs;

[0028] 3. After adopting the alternating amplification technology, the product's anti-interference ability is enhanced and the application scenarios are expanded. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A circuit structure diagram of a capacitance sensor in the prior art;

[0030] Figure 2 A structural diagram of a charge-discharge type capacitance sensor measurement circuit shown as an exemplary embodiment of the present invention;

[0031] Figure 3 A pulse timing diagram is shown as an exemplary embodiment of the present invention;

[0032] Figure 4 Another structure diagram of an alternate charge-discharge type capacitance sensor measurement circuit according to an exemplary embodiment of the present invention;

[0033] Figure 5 Another pulse timing diagram with alternating and variable alternating timing is shown in an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0034] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0035] The following will clearly and completely describe the concept, specific structure and technical effects of the present invention in combination with the embodiments and drawings, so as to fully understand the purpose, characteristics and effects of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, other embodiments obtained by technicians in this field without creative work are all within the scope of protection of the present invention. In addition, all the connection / connection relationships involved in the patent do not refer to the direct connection of components, but refer to the formation of a better connection structure by adding or reducing connection accessories according to the specific implementation situation. The various technical features in the invention can be combined interchangeably without conflicting with each other.

[0036] In one possible implementation, Figure 2 As shown, the present invention provides a charge-discharge type capacitance sensor measurement circuit, including a detected capacitance Cs, a stray capacitance C0, a resistor R0, an isolation capacitor C1, a first transistor Q1, a second transistor Q2, a conduction control valve, a signal acquisition resistor Rs, a signal configuration switch SW1, a signal amplifier AMP, a first linear power supply LinearReg1, a second linear power supply LinearReg2, and an AC / DC converter, wherein:

[0037] One end of the detected capacitor Cs is connected to the object to be measured, and the other end is connected to the collectors of the first transistor Q1 and the second transistor Q2, and is grounded through the stray capacitor C0 and the resistor R0;

[0038] The emitter of the first transistor Q1 is connected to the output end of the first linear power supply, and the emitter of the second transistor is respectively connected to one end of the isolation capacitor C1 and the signal acquisition resistor Rs; the bases of the first transistor Q1 and the second transistor Q2 are connected to the conduction control valve.

[0039] In a possible implementation, the signal acquisition resistor Rs may also be replaced by an inductor.

[0040] In a possible implementation, the frequency of the timing pulse F1 of the conduction control valve is 1M-2MHz, and the control timing is as follows: Figure 3 shown.

[0041] The other end of the isolation capacitor C1 is connected to the signal configuration switch SW1, and the other end of the signal collection resistor Rs is connected to the output end of the first linear power supply;

[0042] In a possible implementation, types of the first transistor Q1 and the second transistor Q2 include MOS transistors and bipolar transistors.

[0043] In a possible implementation, the first linear power supply L i near Reg1 and the second linear power supply L inear Reg2 are both low-noise, high-precision adjustable power supplies, and their output voltages can be adjusted through external control signals according to actual measurement requirements to adapt to the measurement range of different detected capacitances Cs, thereby improving the versatility and flexibility of the circuit.

[0044] In a possible implementation, the signal amplifier AMP has high input impedance and low output impedance, and can effectively amplify weak capacitance change signals while maintaining signal linearity and stability.

[0045] The other end of the signal configuration switch SW1 is respectively connected to the positive and negative input terminals of the signal amplifier AMP, the positive power supply pin of the signal amplifier AMP is connected to the output terminal of the second linear power supply, and the negative power supply pin of the signal amplifier AMP is grounded.

[0046] In a possible implementation, the signal configuration switch SW1 is a single-pole double-throw switch, the normally closed contact NC of the signal configuration switch SW1 is connected to the positive input terminal of the signal amplifier AMP, and the normally open contact NO of the signal configuration switch SW1 is connected to the negative input terminal of the signal amplifier AMP.

[0047] The input end of the second linear power supply is connected to the output end of the first linear power supply, the input end of the first linear power supply is connected to the output end of the AC / DC converter, and the input end of the AC / DC converter is grounded.

[0048] In one possible implementation, the circuit also includes a protection circuit, which is connected in series between the output end of the AC / DC converter and the input end of the first linear power supply, and is used to automatically cut off the power supply when the power supply voltage is abnormal or the circuit is overloaded, thereby protecting the circuit components from damage.

[0049] The working principle of the above circuit is:

[0050] Charging process: When the control pulse timing pulse F1 of the conduction control valve is at a high level, the first transistor Q1 of the upper bridge is turned on. At this time, the first linear power supply Linear Reg 1 charges the detected capacitor Cs and the stray capacitor C0 through the first transistor.

[0051] The charging path for the detected capacitor Cs is: first linear power supply Linear Reg.1→first transistor Q1→detected capacitor Cs→PE→earth→AC / DC converter→first linear power supply Linear Reg1, and the charging path does not pass through the signal collection resistor Rs.

[0052] The charging path for the stray capacitance C0 is: LinearReg1→first transistor Q1→stray capacitance C0→resistor R0→VSS2→signal collection resistor Rs→VSS1→first linear power supply LinearReg1. The charging path passes through the signal collection resistor Rs and generates a signal related to the stray capacitance C0.

[0053] Since the timing pulse F1 that turns on the control valve during the charging process is at a high level, the COM terminal of the signal configuration switch SW1 is connected to the normally open contact NO. In this way, the voltage drop generated when the charging current of the stray capacitance C0 flows through the signal acquisition resistor Rs is connected to the normally open contact NO by the signal configuration switch SW1, and the signal is sent to the negative input terminal of the signal amplifier AMP.

[0054] Discharge process: When the control pulse timing pulse F1 of the conduction control valve is at a low level, the second transistor Q2 of the lower bridge is turned on, and the stray capacitance C0 and the detected capacitance Cs discharge the loop through the second transistor Q2.

[0055] Among them, the discharge path of the detected capacitor Cs is: detected capacitor Cs→second transistor Q2→VSS2→signal acquisition resistor Rs→VSS1→first linear power supply Linear Reg1→AC / DC converter→PE→detected capacitor Cs, and the discharge path passes through the signal acquisition resistor Rs to generate an electrical signal related to the detected capacitor Cs.

[0056] The discharge path of the stray capacitance C0 is: stray capacitance C0→second transistor Q2→VSS2→resistor R0→stray capacitance C0, and the discharge path does not pass through the signal acquisition resistor Rs.

[0057] Since the timing pulse F1 is at a low level during the discharge process, the COM terminal of the signal configuration switch SW1 is connected to the normally closed contact NC terminal, and the signal acquisition resistor Rs collects the voltage drop caused by the discharge current of the detected capacitor Cs, and is connected to the normally closed contact NC by the signal configuration switch SW1, sending the signal to the positive input terminal of the signal amplifier AMP.

[0058] Therefore, in a complete charge and discharge cycle, the signal collected on the signal collection resistor Rs is connected to the positive and negative input terminals of the signal amplifier AMP by the signal configuration switch SW1. After amplification by the signal amplifier AMP, a signal is output at the output terminal VS. Since the signal of the detected capacitor Cs is introduced into the positive input terminal of the signal amplifier AMP, the output signal of the output terminal VS increases with the increase of the detected capacitor Cs.

[0059] The mathematical model is expressed as VS = K*(V Cs -V C0 );

[0060] Where V Cs and V C0 It is the integral voltage during the charge and discharge time period, under the condition of 1us control pulse period:

[0061]

[0062] Through the above embodiments, the present invention adopts a signal configuration switch SW1 to pick up V C0 and V CsThe charging and discharging of the stray capacitance C0 and the detected capacitance Cs are changed to the upper and lower bridge control mode. Compared with the prior art, the entire system passes through the same signal configuration switch SW1 and the upper and lower bridge switches in the charging and discharging of the two capacitors. Since the paths passed are the same, the signal changes caused by the differences in the parameters of the electronic components cancel each other out, thereby improving the problem of uncertain signal changes after being affected by temperature in the prior art.

[0063] Since DC signals are naturally susceptible to AC electromagnetic interference, and DC signals in circuits are easily affected by the DC bias of the amplifier circuit and the offset voltage of the operational amplifier, the measurement accuracy is also inaccurate.

[0064] Therefore, in another possible implementation, Figure 4 As shown, the present application also provides another charge-discharge type capacitance sensor measurement circuit, which adds an XOR logic gate, capacitors C2 and C3 on the basis of the above embodiment, wherein:

[0065] The XOR logic gate is connected to the signal configuration switch SW1, and generates a combined pulse timing pulse F3 according to the timing pulse F1 and the timing pulse F2 to control the conduction and closing of the signal configuration switch SW1; the frequency of the timing pulse F1 is 1M-2MHz, and the frequency of the timing pulse F2 is 1K-2K. By increasing the timing of the timing pulse F2, the signal alternation logic is used; at the same time, the XOR logic is added to form a pulse timing pulse F3 composed of the timing pulse F1 and the timing pulse F2, such as Figure 5 shown.

[0066] One end of the capacitor C2 is connected to one end of the signal configuration switch and the negative input end of the signal amplifier AMP, and the other end is grounded;

[0067] One end of the capacitor C3 is connected to one end of the signal configuration switch SW1 and the positive input end of the signal amplifier AMP, and the other end of the capacitor C3 is grounded.

[0068] During the two half cycles of the pulse timing pulse F3, the power-on direction control of the signal configuration switch SW1 is reversed, that is, when the timing pulse F2 is at a high level, the pulse timing pulse F3 is in phase with the pulse timing pulse F1; during the low level period of the second timing pulse F2, the pulse timing pulse F3 is in phase with the pulse timing pulse F1; capacitors C2 and C3 are signal accumulation capacitors, and during the half cycle of the timing pulse F2, the signals collected by the signal acquisition resistor Rs are accumulated on the capacitors respectively.

[0069] In a possible implementation, the XOR logic gate further receives an external reset signal for resetting the generation of the timing pulse F3 under certain conditions so that the circuit can restart the measurement process, thereby improving the flexibility and reliability of the system.

[0070] The working principle of the above circuit is as follows (only the differences from the basic solution are described):

[0071] State 1, when the timing pulse F2 is low:

[0072] When charging, the timing pulse F1 is at a high level, the timing pulse F3 is at a high level, the signal acquisition resistor Rs obtains the relevant signal of the stray capacitance C0, and the signal configuration switch SW1 contact connects the signal to the negative input terminal of the signal amplifier AMP;

[0073] During discharge, the timing pulse F1 is at a low level, the timing pulse F3 is at a low level, and the signal acquisition resistor Rs obtains the relevant signal of the detected capacitor Cs. At the same time, the signal configuration switch SW1 contact connects the signal to the positive input terminal of the signal amplifier AMP.

[0074] State 2, when the timing pulse F2 is high:

[0075] When charging, the timing pulse F1 is high level, and the timing pulse F3 is low level, which is opposite to the timing pulse F1, that is, the phase difference is 180°. When in the charging state, the signal acquisition resistor Rs obtains the relevant signal of the stray capacitance C0, and the signal configuration switch SW1 contact connects the signal to the positive input terminal of the signal amplifier AMP;

[0076] During discharge, the timing pulse F1 is at a low level, the timing pulse F3 is at a high level, and is inversely proportional to the timing pulse F1. The signal acquisition resistor Rs obtains a signal related to the detected capacitor Cs, and the signal configuration switch SW1 contact connects the signal to the negative input terminal of the signal amplifier AMP.

[0077] Through the above embodiments, the signal of the signal acquisition resistor RS is alternately transmitted to the positive and negative input terminals of the signal amplifier AMP in the period of the timing pulse F2, so that the signal VS becomes an alternating state. The advantage of this is not only to improve the quantization deviation of the two signals caused by the difference in loop amplification parameters in the non-alternating state, but also to form an AC signal with the same frequency as the timing pulse F2, which brings advantages to anti-interference. Because when there is an external interference signal with the same frequency as the timing pulse F2, if it only works at the frequency of the timing pulse F2, then when the signal of the detected capacitor Cs is very small, the interference signal replaces the effective signal generated by the detected capacitor Cs, and the subsequent judgment mechanism mistakenly thinks that the interference signal is the CS signal, resulting in a wrong judgment. Therefore, once the AC signal is formed, the upper control can generate a variable frequency timing pulse F2 signal, which can resist the interference of the external natural frequency.

[0078] The above is a specific description of the preferred implementation of the present invention, but the invention is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A charge-discharge type capacitance sensor measurement circuit, characterized in that: It includes a detected capacitor Cs, a stray capacitor C0, a resistor R0, an isolation capacitor C1, a first transistor Q1, a second transistor Q2, a conduction control valve, a signal acquisition resistor Rs, a signal configuration switch SW1, a signal amplifier AMP, a first linear power supply, a second linear power supply, and an AC / DC converter, wherein: One end of the detected capacitor Cs is connected to the object to be measured, and the other end is connected to the collectors of the first transistor Q1 and the second transistor Q2, and is grounded through the stray capacitor C0 and the resistor R0; The emitter of the first transistor Q1 is connected to the output end of the first linear power supply, and the emitter of the second transistor is connected to one end of the isolation capacitor C1 and the signal acquisition resistor Rs respectively; the bases of the first transistor Q1 and the second transistor Q2 are connected to the conduction control valve; the other end of the isolation capacitor C1 is connected to the signal j configuration switch SW1, and the other end of the signal acquisition resistor Rs is connected to the output end of the first linear power supply; The other end of the signal configuration switch SW1 is connected to the positive and negative input terminals of the signal amplifier AMP respectively, the positive power supply pin of the signal amplifier AMP is connected to the output terminal of the second linear power supply, and the negative power supply pin of the signal amplifier AMP is grounded; The input end of the second linear power supply is connected to the output end of the first linear power supply, the input end of the first linear power supply is connected to the output end of the AC / DC converter, and the input end of the AC / DC converter is grounded.

2. The charge-discharge type capacitance sensor measurement circuit according to claim 1, characterized in that: The signal collection resistor Rs can be replaced by an inductor.

3. The charge-discharge type capacitance sensor measurement circuit according to claim 1, characterized in that: The frequency of the timing pulse F1 of the conduction control valve is 1M-2MHz.

4. The charge-discharge type capacitance sensor measurement circuit according to claim 1, characterized in that: The first linear power supply and the second linear power supply are both low-noise, high-precision adjustable power supplies.

5. The charge-discharge type capacitance sensor measurement circuit according to claim 1, characterized in that: Types of the first transistor and the second transistor include MOS transistors and bipolar transistors.

6. The charge-discharge type capacitance sensor measurement circuit according to claim 1, characterized in that: The signal amplifier AMP has high input impedance and low output impedance.

7. The charge-discharge type capacitance sensor measurement circuit according to claim 1, characterized in that: The circuit also includes a protection circuit, which is connected in series between the output end of the AC / DC converter and the input end of the first linear power supply and is used to automatically cut off the power supply when the power supply voltage is abnormal or the circuit is overloaded.

8. The charge-discharge type capacitance sensor measurement circuit according to claim 1, characterized in that: The signal configuration switch SW1 is a single-pole double-throw switch. The normally closed contact NC of the signal configuration switch SW1 is connected to the positive input terminal of the signal amplifier AMP, and the normally open contact NO of the signal configuration switch SW1 is connected to the negative input terminal of the signal amplifier AMP.

9. The charge-discharge type capacitance sensor measurement circuit according to claim 1, characterized in that: The circuit also includes an XOR logic gate, capacitors C2 and C3, wherein: The XOR logic gate is connected to the signal configuration switch SW1, and generates a combined pulse timing pulse F3 according to the timing pulse F1 and the timing pulse F2 to control the conduction and closing of the signal configuration switch SW1; the frequency of the timing pulse F1 is 1M-2MHz, and the frequency of the timing pulse F2 is 1K-2K; One end of the capacitor C2 is connected to one end of the signal configuration switch and the negative input end of the signal amplifier AMP, and the other end is grounded; One end of the capacitor C3 is connected to one end of the signal configuration switch SW1 and the positive input end of the signal amplifier AMP, and the other end of the capacitor C3 is grounded.

10. The charge-discharge type capacitance sensor measurement circuit according to claim 9, characterized in that: The XOR logic gate also receives an external reset signal for resetting the generation of the timing pulse F3 under certain conditions so that the circuit can restart the measurement process.

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