Chip circuit automatic generator and method based on FPGA architecture file

Abstract

The invention relates to the technical field of chip circuit layout, in particular to an automatic chip circuit generator and method based on an FPGA architecture file, and the automatic chip circuit generator comprises an input module, a layout wiring module, a verification module and an output module; the input module is used for analyzing an FPGA (Field Programmable Gate Array) architecture file input by a user by utilizing the architecture file analyzer; the layout wiring module is used for arranging and connecting each column unit circuit model in the required column unit circuit model set and arranging and connecting each row unit circuit in the row unit circuit set; the verification module is used for carrying out verification operation based on a preset error type set on the row unit circuit set and carrying out verification operation based on the error type set on the top circuit diagram; and the output module is used for formatting and outputting the top circuit diagram. According to the invention, the efficiency and accuracy of chip circuit connection can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip circuit layout, and in particular to a chip circuit automatic generator and method based on FPGA architecture files. Background Art

[0002] The circuit design process of FPGA chips is a complex and sophisticated process. It follows the top-down design principle and is divided into three key levels: top-level circuits, row unit circuits, and column unit circuits. Column unit circuits, as the basic building blocks in this hierarchical structure, are particularly important due to their high reusability. When building larger and more complex chip circuits, designers usually need to combine multiple column unit circuits into row unit circuits, and then integrate multiple row unit circuits into the top-level circuit to form a complete and powerful FPGA chip.

[0003] However, the challenges faced in this assembly process are also huge. Due to the extremely large number of signals and interfaces involved, often reaching tens of thousands or even hundreds of thousands, the traditional manual splicing method is not only time-consuming and labor-intensive, but also very easy to cause connection errors due to human negligence or mistakes, thus affecting the performance and stability of the entire chip. Summary of the invention

[0004] The present invention provides a chip circuit automatic generator and method based on FPGA architecture file, the main purpose of which is to improve the efficiency and accuracy of chip circuit connection.

[0005] To achieve the above-mentioned object, the present invention provides a chip circuit automatic generator based on an FPGA architecture file, characterized in that the chip circuit automatic generator includes an input module, a layout and routing module, a verification module and an output module; The input module includes an architecture file parser and a basic column unit circuit library; The input module is used to parse the FPGA architecture file input by the user using the architecture file parser to obtain circuit design information, and query the basic column unit circuit library according to the circuit design information to obtain a required column unit circuit model set; The layout and routing module is used to arrange and connect each column unit circuit model in the required column unit circuit model set according to the circuit design information to obtain a row unit circuit set; The layout and routing module is further used to arrange and connect each row unit circuit in the row unit circuit set according to the row unit circuit verification result sent by the verification module and the circuit design information to obtain a top-level circuit diagram; The verification module is used to perform a verification operation on the row unit circuit set based on a preset error type set to obtain a row unit circuit verification result; The verification module is further used to perform a verification operation on the top-level circuit diagram based on the error type set to obtain a top-level circuit verification result; The output module is used to format and output the top-level circuit diagram according to the top-level circuit verification result to obtain a target-form FPGA circuit.

[0006] In addition, the chip circuit automatic generator also includes an FPGA top-level circuit automatic generation program; The FPGA top-level circuit automatic generation program is developed based on Python and Cadence skill, and the FPGA top-level circuit automatic generation program includes a read architecture service and a parsing architecture service; The FPGA top-level circuit automatic generation program is used to configure the data format of the input module and the layout and routing module; The architecture reading service is used to use the openpyxl library in Python to read the FPGA architecture file and obtain the circuit design information; The parsing architecture service is used to configure the data type of the circuit design information using a pre-built .map text format to obtain the circuit design information in a .map text format.

[0007] In addition, the .map text format consists of keywords for structure, index, direction, associated neighbor relationship and instance information.

[0008] In addition, the basic column unit circuit library includes a preset number of column unit circuit models: The column unit circuit model is obtained by standardizing and storing the pre-built column unit circuit; The column unit circuit model is used to provide retrieval information for the input module so that each column unit circuit can be independently called by the input module; The column unit circuit is obtained by arranging the pre-built logic unit circuit in a column direction.

[0009] In addition, the configuration process of the standardized storage includes maintaining the height of each column unit circuit consistent according to the preset y coordinate setting by using dbCreateRect of dbAccess in the Cadenceskill; The sort in the Cadence skill is used to arrange the IO ports in each column unit circuit in the order of ASCII codes.

[0010] In addition, the preset error type set in the verification module at least includes open circuit, short circuit and floating.

[0011] In addition, the chip circuit automatic generator includes: The FPGA architecture file supports xlsx and XML formats; The target form FPGA circuit supports text format and physical diagram format.

[0012] In addition, the row unit circuit verification results and the top-level circuit verification results are divided into qualified and unqualified; When the row unit circuit verification result or the top-level circuit verification result is unqualified, an unqualified log file is generated and visualized using a warning in the Cadence skill.

[0013] To achieve the above object, the present invention further provides a method for automatically generating a chip circuit based on an FPGA architecture file, characterized in that the method comprises: Get pre-built input modules, layout and routing modules, verification modules, and output modules; Wherein, the input module includes an architecture file parser and a basic column unit circuit library; Using the input module, calling the architecture file parser, parsing the FPGA architecture file input by the user to obtain circuit design information, and querying the basic column unit circuit library according to the circuit design information to obtain a required column unit circuit model set; Using the layout and routing module, according to the circuit design information, arrange and connect each column unit circuit model in the required column unit circuit model set to obtain a row unit circuit set; Using the verification module, performing a verification operation based on a preset error type set on the row unit circuit set to obtain a row unit circuit verification result; Using the layout and routing module, according to the row unit circuit verification result sent by the verification module and the circuit design information, each row unit circuit in the row unit circuit set is arranged and connected to obtain a top-level circuit diagram; Using the verification module, performing a verification operation based on the error type set on the top-level circuit diagram to obtain a top-level circuit verification result; The output module is used to format and output the top-level circuit diagram according to the top-level circuit verification result to obtain a target-form FPGA circuit.

[0014] In addition, the method further comprises: Get pre-built FPGA top-level circuit automatic generation program; The FPGA top-level circuit automatic generation program is developed based on Python and Cadence skill, and the FPGA top-level circuit automatic generation program includes a read architecture service and a parsing architecture service; The FPGA top-level circuit automatic generation program is used to configure the data format of the input module and the layout and routing module, wherein the process of data format configuration is as follows: Using the read architecture service, calling the openpyxl library in Python, reading the FPGA architecture file, and obtaining the circuit design information; The parsing architecture service is used to configure the data type of the circuit design information using the pre-built .map text format to obtain the circuit design information in the .map text format.

[0015] The present invention solves the problem described in the background technology. The present invention constructs a chip circuit automatic generator, uses the input module and layout and routing module in the chip circuit automatic generator, converts the FPGA architecture file input by the user into a target form FPGA circuit, and monitors the layout and routing process through a pre-built verification module, so as to preliminarily realize the automatic connection of the chip circuit; because the layout and routing module uses Cadence skill to execute the layout and routing process, and the Cadence skill does not support the format of the FPGA architecture file, the present invention reads it through Python, and uses a pre-configured .map text format to convert the FPGA architecture file into circuit design information that can be read by Cadence skill, so as to realize the automatic connection of the chip circuit. Therefore, the present invention can improve the efficiency and accuracy of chip circuit connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flowchart of a chip circuit automatic generator based on an FPGA architecture file provided by an embodiment of the present invention; Figure 2 A schematic diagram of an FPGA architecture in a chip circuit automatic generator based on an FPGA architecture file provided in an embodiment of the present invention; Figure 3 A schematic diagram of an FPGA architecture file input into an automatic generator of chip circuits based on an FPGA architecture file provided in an embodiment of the present invention; Figure 4 A schematic diagram of circuit design information in a .map text format in a chip circuit automatic generator based on an FPGA architecture file provided by an embodiment of the present invention; Figure 5A schematic flow chart of a method for automatically generating a chip circuit based on an FPGA architecture file according to an embodiment of the present invention.

[0017] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present application more obvious, the exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the exemplary embodiments described here.

[0019] An embodiment of the present application relates to a chip circuit automatic generator based on an FPGA architecture file, such as Figure 1 As shown, it mainly includes an input module, a layout and routing module, a verification module and an output module; The input module includes an architecture file parser and a basic column unit circuit library; The input module is used to parse the FPGA architecture file input by the user using the architecture file parser to obtain circuit design information, and query the basic column unit circuit library according to the circuit design information to obtain a required column unit circuit model set; The layout and routing module is used to arrange and connect each column unit circuit model in the required column unit circuit model set according to the circuit design information to obtain a row unit circuit set; The layout and routing module is further used to arrange and connect each row unit circuit in the row unit circuit set according to the row unit circuit verification result sent by the verification module and the circuit design information to obtain a top-level circuit diagram; The verification module is used to perform a verification operation on the row unit circuit set based on a preset error type set to obtain a row unit circuit verification result; The verification module is further used to perform a verification operation on the top-level circuit diagram based on the error type set to obtain a top-level circuit verification result; The output module is used to format and output the top-level circuit diagram according to the top-level circuit verification result to obtain a target-form FPGA circuit.

[0020] The FPGA refers to a field programmable gate array.

[0021] The FPGA architecture file is a configuration file used to describe the FPGA hardware logic structure, resource distribution and connection relationship.

[0022] The architecture file parser is a service for parsing the content in the FPGA architecture file.

[0023] The basic column unit circuit library is a database for storing column unit circuits.

[0024] The row unit circuit set and the top-level circuit diagram are structures of different levels in the chip, such as Figure 2 shown.

[0025] The operation of parsing the FPGA architecture file input by the user refers to: Figure 3 The format of the FPGA architecture file shown is used to extract the values ​​of each keyword in the FPGA architecture file to obtain a key-value pair set.

[0026] The row unit circuit verification results and the top-level circuit verification results include qualified and unqualified.

[0027] The preset error type set refers to a data set collected by R&D personnel based on common error types in target scenarios.

[0028] The formatted output refers to the process of selecting a suitable output interface according to the specific situation to output the top-level circuit diagram, such as text or image.

[0029] Specifically, in the embodiment of the present invention, due to the characteristic of the FPGA chip itself that rows and columns are clearly defined, taking the row unit circuit as an example, the row unit circuit is composed of a number of column unit circuits. The data after parsing the architecture file records in detail the column unit circuit type (covering multiple types such as CLELL, DSP, ERAM, etc.) of each column in the row unit circuit, as well as their precise location information inside the chip. Figure 3 As shown, the 24th column in the row unit named TOP1 has a unit circuit of CLELM, and the 25th column has a unit circuit of CLELL.

[0030] Specifically, in an embodiment of the present invention, the circuit design information is obtained by parsing the FPGA architecture file, wherein the circuit design information includes information such as the number of row units in the chip, the number of each row unit, and necessary IO interface information.

[0031] In the embodiment of the present invention, the basic column unit circuit library is called to extract the column unit circuit model corresponding to the circuit design information to obtain a required column unit circuit model set, for example, the required column unit circuit model set [column unit circuit 001, column unit circuit 003, column unit circuit 008, ...].

[0032] The steps of arranging and connecting the column unit circuit models are as follows: Specifically, in the embodiment of the present invention, the arrangement and connection of the layout and routing module is based on the data (circuit design information) parsed by the input module, and the layout and routing module is responsible for automatically completing the layout and routing of the circuit.

[0033] First, according to the rules preset by the technicians, the row unit circuit diagram is automatically generated, and the column unit devices are intelligently placed to complete the automatic connection between them. Furthermore, according to the higher-level rules, the top-level circuit diagram is automatically created, the row unit devices are intelligently placed, and the complex connections between them are completed.

[0034] Furthermore, in order to ensure the correctness of the circuit design, the verification module is responsible for comprehensive verification of the generated circuit, focusing on checking whether there are common error phenomena such as open circuit, short circuit, floating, etc. in the circuit to ensure the stability and reliability of the circuit.

[0035] Specifically, in the embodiment of the present invention, the layout and routing module and the verification module are executed alternately, and the process is as follows: After all components are initialized, the program begins to build the circuit step by step in a bottom-up manner.

[0036] 1) First, the program starts to generate the internal circuits of each row unit. At this stage, the program follows the principle of layout first and then routing.

[0037] 2) In the layout phase, the program will place the column unit circuits inside the row unit circuits column by column based on the layout information read from the circuit design information, and build a detailed information record for each column unit device.

[0038] 3) Subsequently, the wiring module solidifies the information of these column unit devices and accurately completes the connection wiring between column units.

[0039] 4) When the circuit layout and routing work is completed, the program will intelligently generate the pins required for the circuit in the four directions of the column unit: up, down, left, and right.

[0040] 5) In this step, the verification module will perform a preliminary check on the pins of the column units and the interconnections between different column units to check whether there is any floating phenomenon. If there is a pin floating, a warning will be issued, recorded in the log file, and displayed on the schematic through Cadence's built-in warning. The user will determine whether to keep the floating pin.

[0041] 6) Finally, the program will encapsulate these column cells with interface information into a row cell rectangular black box to provide subsequent top-level circuit calls.

[0042] Furthermore, the operations of the layout and routing module and the verification module on the top-level circuit layout are as follows: 1) After generating all the row unit circuits read from the architecture file, the program will start the layout of the top-level circuit. During this process, the program will intelligently place the row units based on the layout information of the architecture file and construct the connection information between the row units.

[0043] 2) The program then automatically completes the wiring in the top-level circuit based on this connection information, ensuring that each row of cells can communicate correctly and efficiently.

[0044] 3) Finally, the program will generate a complete top-level circuit, which includes all necessary row unit circuits and connection information. Error verification such as pin dangling is performed through the built-in functional interface of the EDA tool, such as schCheck in the Cadence skill, and recorded in the log file. The user determines whether the dangling phenomenon is retained. Some ports are actually dangling here, and some special connections are reserved for users to connect manually, usually leaving only a single digit of dangling phenomenon.

[0045] Furthermore, in the embodiment of the present invention, the output module performs the following process: After the verification module checks whether the circuit is short-circuited or open-circuited, if the result is correct, the user can decide to save the final file as cellview that supports EDA tool interaction, that is, openAccess data format, to obtain the target FPGA circuit. The openAccess data format can facilitate interaction with other EDA tools and other engineers; or the netlist format of SPICE syntax is convenient for direct simulation.

[0046] In detail, in the embodiment of the present invention, the chip circuit automatic generator also includes an FPGA top-level circuit automatic generation program; The FPGA top-level circuit automatic generation program is developed based on Python and Cadence skill, and the FPGA top-level circuit automatic generation program includes a read architecture service and a parsing architecture service; The FPGA top-level circuit automatic generation program is used to configure the data format of the input module and the layout and routing module; The architecture reading service is used to use the openpyxl library in Python to read the FPGA architecture file and obtain the circuit design information; The parsing architecture service is used to configure the data type of the circuit design information using a pre-built .map text format to obtain the circuit design information in a .map text format.

[0047] Among them, the Python and Cadence skills are two programming languages / tools in different fields, serving the fields of general software development and electronic design automation (EDA) respectively.

[0048] Among them, the FPGA top-level circuit automatic generation program is not only used to configure the data format of the input module and the layout and routing module, but also used to control the subsequent verification module and output module.

[0049] The openpyxl library is a third-party library in Python specifically used for reading and writing Excel 2010+ format files, and is suitable for the format of the FPGA architecture file in the embodiment of the present invention.

[0050] Wherein, the .map text format is a text format configured by the present invention, refer to Figure 4 As shown, each data segment in the .map text format starts with BEGIN COL and ends with END COL, which is a structured data. Then each data segment contains an index (INDEX), such as X24, X25, X26, etc. In addition, it also contains direction (DIRECTION) information, such as R (right), etc.

[0051] Among them, part of the circuit design information in the .map text format is Figure 4 In content.

[0052] In detail, in the embodiment of the present invention, the .map text format is composed of keywords of structure, index, direction, associated proximity and instance information.

[0053] Specifically, refer to Figure 3 As shown in the figure, each data segment also contains information about the associated (RELATED_VBRK) and adjacent (PRE_COL and NEXT_COL) relationships, such as R1, X23, X25, etc., which may be used to describe the associated adjacent relationship. Each data segment also has an instance (INSTANCE) part, which contains the instance name (INST_NAME) and the master identifier (MASTER). Among them, the contents in brackets such as RELATED_VBRK, PRE_COL and NEXT_COL above represent keywords.

[0054] In detail, in the embodiment of the present invention, the basic column unit circuit library includes a preset number of column unit circuit models: The column unit circuit model is obtained by standardizing and storing the pre-built column unit circuit; The column unit circuit model is used to provide retrieval information for the input module so that each column unit circuit can be independently called by the input module; The column unit circuit is obtained by arranging the pre-built logic unit circuit in a column direction.

[0055] In detail, in the embodiment of the present invention, the configuration process of the standardized storage includes maintaining the height of each column unit circuit consistent by using dbCreateRect of dbAccess in the Cadence skill according to a preset y coordinate setting; The sort in the Cadence skill is used to arrange the IO ports in each column unit circuit in the order of ASCII codes.

[0056] The y coordinate is used to determine the layout position of each circuit unit in the vertical direction in the integrated circuit layout design.

[0057] The dbAccess is a set of interfaces in the Cadence skill programming language for accessing and operating a design database.

[0058] The dbCreateRect is a function used to create a rectangle (Rectangle) in the layout database.

[0059] Here, the sort is a function that can rearrange the elements in a list according to a specified rule (such as numerical value or string order).

[0060] The IO port is an interface in an integrated circuit for signal input (input) and output (output) with an external circuit or device.

[0061] The ASCII code is a character encoding standard based on Latin letters, which uses 7-bit binary numbers to represent 128 characters.

[0062] Specifically, in the embodiment of the present invention, when using Cadence or other EDA tools to build a basic unit circuit library, we strictly follow the following principles to ensure the consistency and compatibility of column units: First, the height of all column units can be kept consistent through dbCreateRect of dbAccess in Cadence skill, and the y coordinate can be set to the same height. This helps to avoid vertical misalignment during the layout process; secondly, the IO ports of the column unit are arranged in ASCII code order through the sort method of cadenceskill. Such standardized sorting not only improves the layout efficiency, but also effectively prevents connection errors or layout confusion caused by inconsistent port order. By following these principles, we ensure the stability and accuracy of the column unit after layout.

[0063] In detail, in the embodiment of the present invention, the preset error type set in the verification module at least includes open circuit, short circuit and floating.

[0064] The open circuit refers to the situation where the current path is disconnected somewhere in the circuit due to a broken wire, a fallen solder joint, a switch not closed, etc., and the current cannot flow normally.

[0065] Among them, the short circuit refers to the situation where two nodes in a circuit that should not be directly connected (such as the positive and negative poles of a power supply, a signal line and ground) are connected by a low-resistance path due to wire contact, component damage, etc.

[0066] The floating refers to a node in the circuit that is not connected to a certain reference point (such as power supply, ground or load), is in a high impedance state, and the potential is unstable due to environmental noise or parasitic capacitance.

[0067] In the embodiment of the present invention, the open circuit, short circuit and floating are the most common error types.

[0068] In detail, in an embodiment of the present invention, the chip circuit automatic generator includes: The FPGA architecture file supports xlsx and XML formats; The target form FPGA circuit supports text format and physical diagram format.

[0069] Specifically, the architecture file in the embodiment of the present invention supports xlsx or XML format, depending on the editing tool used by the user.

[0070] The target form FPGA circuit supports text format and physical diagram format, depending on the user's intention. If you decide to save the target form FPGA circuit as a physical diagram format that supports EDA tool interaction, this data format can facilitate interaction with other EDA tools and other engineers, while choosing a text format, such as a netlist format in SPICE syntax, is convenient for direct simulation.

[0071] In detail, in the embodiment of the present invention, the row unit circuit verification results and the top-level circuit verification results are divided into qualified and unqualified; When the row unit circuit verification result or the top-level circuit verification result is unqualified, an unqualified log file is generated and visualized using a warning in the Cadence skill.

[0072] The log file refers to a record file automatically generated by a computer system, software or device during operation, which is used to store key data such as operation events, status changes, error messages, user behaviors, etc. in detail.

[0073] The warning is a prompt message generated during script execution or design operation, indicating that there are potential problems in the code or operation, but will not immediately lead to program termination or design errors.

[0074] Specifically, in the verification module, a preliminary check will be performed on the pins of the column unit circuit model and the interconnections between different column unit circuits to check whether there is any hanging phenomenon. If any pin is hanging, a warning will be issued, recorded in the log file, and displayed on the schematic through Cadence's built-in warning. The user will determine whether to keep the hanging pin.

[0075] The present invention solves the problem described in the background technology. The present invention constructs a chip circuit automatic generator, uses the input module and layout and routing module in the chip circuit automatic generator, converts the FPGA architecture file input by the user into a target form FPGA circuit, and monitors the layout and routing process through a pre-built verification module, so as to preliminarily realize the automatic connection of the chip circuit; because the layout and routing module uses Cadence skill to execute the layout and routing process, and the Cadence skill does not support the format of the FPGA architecture file, the present invention reads it through Python, and uses a pre-configured .map text format to convert the FPGA architecture file into circuit design information that can be read by Cadence skill, so as to realize the automatic connection of the chip circuit. Therefore, the present invention can improve the efficiency and accuracy of chip circuit connection.

[0076] Further, see Figure 5 As shown, the embodiment of the present invention also provides a method for utilizing Figure 1 The control method performed by the chip circuit automatic generator based on the FPGA architecture file shown includes: S1. Obtain a pre-built input module, a layout and routing module, a verification module, and an output module, wherein the input module includes an architecture file parser and a basic column unit circuit library.

[0077] S2, using the input module to call the architecture file parser, parse the FPGA architecture file input by the user to obtain circuit design information, and query the basic column unit circuit library according to the circuit design information to obtain a required column unit circuit model set; S3, using the layout and routing module to arrange and connect each column unit circuit model in the required column unit circuit model set according to the circuit design information to obtain a row unit circuit set; S4, using the verification module to perform a verification operation based on a preset error type set on the row unit circuit set to obtain a row unit circuit verification result; S5, using the layout and routing module, according to the row unit circuit verification result sent by the verification module and the circuit design information, arranging and connecting each row unit circuit in the row unit circuit set to obtain a top-level circuit diagram; S6. Using the verification module, perform a verification operation based on the error type set on the top-level circuit diagram to obtain a top-level circuit verification result; S7. Utilizing the output module, according to the top-level circuit verification result, the top-level circuit diagram is formatted and output to obtain a target-format FPGA circuit.

[0078] The FPGA refers to a field programmable gate array.

[0079] The FPGA architecture file is a configuration file used to describe the FPGA hardware logic structure, resource distribution and connection relationship.

[0080] The architecture file parser is a service for parsing the content in the FPGA architecture file.

[0081] The basic column unit circuit library is a database for storing column unit circuits.

[0082] The row unit circuit set and the top-level circuit diagram are structures of different levels in the chip, such as Figure 2 shown.

[0083] The operation of parsing the FPGA architecture file input by the user refers to: Figure 3 The format of the FPGA architecture file shown is used to extract the values ​​of each keyword in the FPGA architecture file to obtain a key-value pair set.

[0084] The row unit circuit verification results and the top-level circuit verification results include qualified and unqualified.

[0085] The preset error type set refers to a data set collected by R&D personnel based on common error types in target scenarios.

[0086] The formatted output refers to the process of selecting a suitable output interface according to the specific situation to output the top-level circuit diagram, such as text or image.

[0087] Specifically, in the embodiment of the present invention, due to the characteristic of the FPGA chip itself that rows and columns are clearly defined, taking the row unit circuit as an example, the row unit circuit is composed of a number of column unit circuits. The data after parsing the architecture file records in detail the column unit circuit type (covering multiple types such as CLELL, DSP, ERAM, etc.) of each column in the row unit circuit, as well as their precise location information inside the chip. Figure 3 As shown, the 24th column in the row unit named TOP1 has a unit circuit of CLELM, and the 25th column has a unit circuit of CLELL.

[0088] Specifically, in an embodiment of the present invention, the circuit design information is obtained by parsing the FPGA architecture file, wherein the circuit design information includes information such as the number of row units in the chip, the number of each row unit, and necessary IO interface information.

[0089] In the embodiment of the present invention, the basic column unit circuit library is called to extract the column unit circuit model corresponding to the circuit design information to obtain a required column unit circuit model set, for example, the required column unit circuit model set [column unit circuit 001, column unit circuit 003, column unit circuit 008, ...].

[0090] The steps of arranging and connecting the column unit circuit models are as follows: Specifically, in the embodiment of the present invention, the arrangement and connection of the layout and routing module is based on the data (circuit design information) parsed by the input module, and the layout and routing module is responsible for automatically completing the layout and routing of the circuit.

[0091] First, according to the rules preset by the technicians, the row unit circuit diagram is automatically generated, and the column unit devices are intelligently placed to complete the automatic connection between them. Furthermore, according to the higher-level rules, the top-level circuit diagram is automatically created, the row unit devices are intelligently placed, and the complex connections between them are completed.

[0092] Furthermore, in order to ensure the correctness of the circuit design, the verification module is responsible for comprehensive verification of the generated circuit, focusing on checking whether there are common error phenomena such as open circuit, short circuit, floating, etc. in the circuit to ensure the stability and reliability of the circuit.

[0093] Specifically, in the embodiment of the present invention, the layout and routing module and the verification module are executed alternately, and the process is as follows: After all components are initialized, the program begins to build the circuit step by step in a bottom-up manner.

[0094] 1) First, the program starts to generate the internal circuits of each row unit. At this stage, the program follows the principle of layout first and then routing.

[0095] 2) In the layout phase, the program will place the column unit circuits inside the row unit circuits column by column based on the layout information read from the circuit design information, and build a detailed information record for each column unit device.

[0096] 3) Subsequently, the wiring module solidifies the information of these column unit devices and accurately completes the connection wiring between column units.

[0097] 4) When the circuit layout and routing work is completed, the program will intelligently generate the pins required for the circuit in the four directions of the column unit: up, down, left, and right.

[0098] 5) In this step, the verification module will perform a preliminary check on the pins of the column units and the interconnections between different column units to check whether there is any floating phenomenon. If there is a pin floating, a warning will be issued, recorded in the log file, and displayed on the schematic through Cadence's built-in warning. The user will determine whether to keep the floating pin.

[0099] 6) Finally, the program will encapsulate these column cells with interface information into a row cell rectangular black box to provide subsequent top-level circuit calls.

[0100] Furthermore, the operations of the layout and routing module and the verification module on the top-level circuit layout are as follows: 1) After generating all the row unit circuits read from the architecture file, the program will start the layout of the top-level circuit. During this process, the program will intelligently place the row units based on the layout information of the architecture file and construct the connection information between the row units.

[0101] 2) The program then automatically completes the wiring in the top-level circuit based on this connection information, ensuring that each row of cells can communicate correctly and efficiently.

[0102] 3) Finally, the program will generate a complete top-level circuit, which includes all necessary row unit circuits and connection information. Error verification such as pin dangling is performed through the built-in functional interface of the EDA tool, such as schCheck in the Cadence skill, and recorded in the log file. The user determines whether the dangling phenomenon is retained. Some ports are actually dangling here, and some special connections are reserved for users to connect manually, usually leaving only a single digit of dangling phenomenon.

[0103] Furthermore, in the embodiment of the present invention, the output module performs the following process: After the verification module checks whether the circuit is short-circuited or open-circuited, if the result is correct, the user can decide to save the final file as cellview that supports EDA tool interaction, that is, openAccess data format, to obtain the target FPGA circuit. The openAccess data format can facilitate interaction with other EDA tools and other engineers; or the netlist format of SPICE syntax is convenient for direct simulation.

[0104] In detail, in an embodiment of the present invention, the method further includes: Get pre-built FPGA top-level circuit automatic generation program; The FPGA top-level circuit automatic generation program is developed based on Python and Cadence skill, and the FPGA top-level circuit automatic generation program includes a read architecture service and a parsing architecture service; The FPGA top-level circuit automatic generation program is used to configure the data format of the input module and the layout and routing module, wherein the process of data format configuration is as follows: Using the read architecture service, calling the openpyxl library in Python, reading the FPGA architecture file, and obtaining the circuit design information; The parsing architecture service is used to configure the data type of the circuit design information using the pre-built .map text format to obtain the circuit design information in the .map text format.

[0105] Among them, the Python and Cadence skills are two programming languages / tools in different fields, serving the fields of general software development and electronic design automation (EDA) respectively.

[0106] Among them, the FPGA top-level circuit automatic generation program is not only used to configure the data format of the input module and the layout and routing module, but also used to control the subsequent verification module and output module.

[0107] The openpyxl library is a third-party library in Python specifically used for reading and writing Excel 2010+ format files, and is suitable for the format of the FPGA architecture file in the embodiment of the present invention.

[0108] Wherein, the .map text format is a text format configured by the present invention, refer to Figure 4As shown, each data segment in the .map text format starts with BEGIN COL and ends with END COL, which is a structured data. Then each data segment contains an index (INDEX), such as X24, X25, X26, etc. In addition, it also contains direction (DIRECTION) information, such as R (right), etc.

[0109] Among them, part of the circuit design information in the .map text format is Figure 4 In content.

[0110] In detail, in the embodiment of the present invention, the .map text format is composed of keywords of structure, index, direction, associated proximity and instance information.

[0111] Specifically, refer to Figure 3 As shown in the figure, each data segment also contains information about the associated (RELATED_VBRK) and adjacent (PRE_COL and NEXT_COL) relationships, such as R1, X23, X25, etc., which may be used to describe the associated adjacent relationship. Each data segment also has an instance (INSTANCE) part, which contains the instance name (INST_NAME) and the master identifier (MASTER). Among them, the contents in brackets such as RELATED_VBRK, PRE_COL and NEXT_COL above represent keywords.

[0112] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A chip circuit automatic generator based on FPGA architecture file, characterized in that: The chip circuit automatic generator includes an input module, a layout and routing module, a verification module and an output module; The input module includes an architecture file parser and a basic column unit circuit library; The input module is used to parse the FPGA architecture file input by the user using the architecture file parser to obtain circuit design information, and query the basic column unit circuit library according to the circuit design information to obtain a required column unit circuit model set; The layout and routing module is used to arrange and connect each column unit circuit model in the required column unit circuit model set according to the circuit design information to obtain a row unit circuit set; The layout and routing module is further used to arrange and connect each row unit circuit in the row unit circuit set according to the row unit circuit verification result sent by the verification module and the circuit design information to obtain a top-level circuit diagram; The verification module is used to perform a verification operation on the row unit circuit set based on a preset error type set to obtain a row unit circuit verification result; The verification module is further used to perform a verification operation on the top-level circuit diagram based on the error type set to obtain a top-level circuit verification result; The output module is used to format and output the top-level circuit diagram according to the top-level circuit verification result to obtain a target-form FPGA circuit.

2. The chip circuit automatic generator based on the FPGA architecture file as claimed in claim 1, characterized in that: The chip circuit automatic generator also includes an FPGA top-level circuit automatic generation program; The FPGA top-level circuit automatic generation program is developed based on Python and Cadence skill, and the FPGA top-level circuit automatic generation program includes a read architecture service and a parsing architecture service; The FPGA top-level circuit automatic generation program is used to configure the data format of the input module and the layout and routing module; The architecture reading service is used to use the openpyxl library in Python to read the FPGA architecture file and obtain the circuit design information; The parsing architecture service is used to configure the data type of the circuit design information using a pre-built .map text format to obtain the circuit design information in a .map text format.

3. The chip circuit automatic generator based on FPGA architecture file as claimed in claim 2, characterized in that: The .map text format consists of keywords for structure, index, direction, associated neighbor relationship and instance information.

4. The chip circuit automatic generator based on FPGA architecture file as claimed in claim 3, characterized in that: The basic column unit circuit library includes a preset number of column unit circuit models: The column unit circuit model is obtained by standardizing and storing the pre-built column unit circuit; The column unit circuit model is used to provide retrieval information for the input module so that each column unit circuit can be independently called by the input module; The column unit circuit is obtained by arranging the pre-built logic unit circuit in a column direction.

5. The chip circuit automatic generator based on FPGA architecture file as claimed in claim 4, characterized in that: The configuration process of the standardized storage includes maintaining the height of each column unit circuit consistent according to a preset y coordinate setting by using dbCreateRect of dbAccess in the Cadence skill; The sort in the Cadence skill is used to arrange the IO ports in each column unit circuit in the order of ASCII codes.

6. The chip circuit automatic generator based on FPGA architecture file as claimed in claim 5, characterized in that: The preset error type set in the verification module at least includes open circuit, short circuit and floating.

7. The chip circuit automatic generator based on FPGA architecture file as claimed in claim 6, characterized in that: The chip circuit automatic generator includes: The FPGA architecture file supports xlsx and XML formats; The target form FPGA circuit supports text format and physical diagram format.

8. The chip circuit automatic generator based on FPGA architecture file as claimed in claim 7, characterized in that: The row unit circuit verification results and the top-level circuit verification results are divided into qualified and unqualified; When the row unit circuit verification result or the top-level circuit verification result is unqualified, an unqualified log file is generated and visualized using a warning in the Cadence skill.

9. A method for automatically generating chip circuits based on FPGA architecture files, characterized in that: The method comprises: Get pre-built input modules, layout and routing modules, verification modules, and output modules; Wherein, the input module includes an architecture file parser and a basic column unit circuit library; Using the input module, calling the architecture file parser, parsing the FPGA architecture file input by the user to obtain circuit design information, and querying the basic column unit circuit library according to the circuit design information to obtain a required column unit circuit model set; Using the layout and routing module, according to the circuit design information, arrange and connect each column unit circuit model in the required column unit circuit model set to obtain a row unit circuit set; Using the verification module, performing a verification operation based on a preset error type set on the row unit circuit set to obtain a row unit circuit verification result; Using the layout and routing module, according to the row unit circuit verification result sent by the verification module and the circuit design information, each row unit circuit in the row unit circuit set is arranged and connected to obtain a top-level circuit diagram; Using the verification module, performing a verification operation based on the error type set on the top-level circuit diagram to obtain a top-level circuit verification result; The output module is used to format and output the top-level circuit diagram according to the top-level circuit verification result to obtain a target-form FPGA circuit.

10. The method for automatically generating chip circuits based on FPGA architecture files according to claim 9, characterized in that: The method further comprises: Get pre-built FPGA top-level circuit automatic generation program; The FPGA top-level circuit automatic generation program is developed based on Python and Cadence skill, and the FPGA top-level circuit automatic generation program includes a read architecture service and a parsing architecture service; The FPGA top-level circuit automatic generation program is used to configure the data format of the input module and the layout and routing module, wherein the process of data format configuration is as follows: Using the read architecture service, calling the openpyxl library in Python, reading the FPGA architecture file, and obtaining the circuit design information; The analysis architecture service is used to configure the data type of the circuit design information using the pre-built .map text format to obtain the circuit design information in the .map text format.

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