Chip platemaking method based on superposition process

Abstract

According to the chip platemaking method based on the superposition process provided by the invention, the ASIC top aluminum layer located at the lower part in the integrated chip is merged into the MEMS bottom aluminum layer located at the upper part, so that the ASIC top passivation perforated layer used for connecting the ASIC topmost layer and the MEMS bottommost layer can be synchronously deleted; the size-adjusted top layer through hole connects the combined MEMS bottom layer aluminum layer with the ASIC secondary aluminum layer, and the original function of the integrated chip can also be realized; based on the method, two platemaking layers can be reduced from the original layout layers, the process steps are optimized, the process flow period is shortened, and the manufacturing cost of the chip is also reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip plate making, and in particular to a chip plate making method based on a superposition process. Background Art

[0002] In the field of thermal inkjet technology, the traditional technology is to use a control chip to match the inkjet device for inkjet. With the emergence of through silicon vias (TSV), integrated chips have been developed in the field of thermal inkjet technology. TSV technology can connect chips located in upper and lower positions to printed circuit boards through hundreds of holes. That is, based on TSV technology, vertical through holes are made between chips and between wafers, and then filled with conductive materials such as copper, tungsten, and polysilicon to achieve vertical electrical interconnection of through silicon vias. The latest integrated thermal inkjet chip integrates the inkjet structure and the control chip. The overall structure is as follows: Figure 1 As shown in the figure, MEMS (Micro-Electro-Mechanical System) is on the top, and ASIC (Application Specific Integrated Circuit) for inkjet control is on the bottom. The two are integrated together through a stacking process to form an integrated thermal bubble inkjet chip. Resistors and cavities are set under the MEMS, and ink is poured into the cavity. The ink is heated based on the resistor to make the ink boil, and then it is ejected from the nozzle on the top of the chip to achieve inkjet printing. For example, Epson's PrecisionCore MicroTFP printing chip in the prior art is a print head chip based on this type of technology. The chip uses MEMS technology to manufacture an ultra-thin piezoelectric film (only 1 micron thick) on a silicon wafer, allowing the nozzle to eject 50,000 ink droplets per second.

[0003] In the prior art, when making a plate for such an integrated chip, the chip needs to be made into a layered plate. Figure 2 The figure shows an example of a layered layout of an integrated thermal inkjet chip. During the chip platemaking process, the design is carried out from the bottom up. Then, in the ASIC stage of chip manufacturing, the general platemaking layers include BN (N-type buried layer), TB (N well), TO (active area), GT (polycrystalline), HV (high voltage thick gate oxide), SN (N-type injection), SP (P-type injection), HF (P-type field injection), CT (tungsten via layer), M1 (first aluminum layer), VIA1 (through hole layer), M2 (second aluminum layer), CP (passivation opening), a total of 13 layers of platemaking data, which are arranged in order from bottom to top, respectively. Figure 2 ASIC-1~ASIC-13 layers in the system.

[0004] When the ASIC stage process manufacturing is completed, the chip needs to be transferred to the MEMS process for manufacturing. In the MEMS manufacturing stage, the general plate making layers include the following from bottom to top: INL (thin film resistor aluminum layer), INS (thin film resistor etching), IN3 (thin film resistor protection), PAS (oxide layer pre-etching), TR (channel deep etching), W4 (cavity film), W5 (covering protective film), a total of 7 layers of plate making data, which correspond to the reference Figure 2 The MEMS1~MEMS7 layers.

[0005] When manufacturing a specific integrated thermal inkjet chip, different processes will have different layout layer settings according to the actual design of the ASIC stage and the MEMS stage. Figure 2 For the integrated chip in the example, based on the plate-making process of the existing technology, at least 20 plates are required in total for the ASIC manufacturing stage and the MEMS manufacturing stage. The plate-making fee for each layer of plates is very expensive. The more plates there are, the longer the manufacturing cycle is, resulting in very high chip production costs. Summary of the invention

[0006] In order to solve the problem of high manufacturing cost of integrated chips formed by integrating ASIC and MEMS in the prior art, the present invention provides a chip plate making method based on the stacking process, which can reduce the cost of the plate making stage while ensuring the chip function.

[0007] The technical solution of the present invention is as follows: a chip plate making method based on a superposition process, characterized in that it comprises the following steps: S1: Obtain the last two layout layers designed in the ASIC stage in a bottom-up order, record the last designed layout as: ASIC top passivation opening layer, record the second to last designed layout as: ASIC top aluminum layer; record the aluminum layer closest to the ASIC top aluminum layer as: ASIC secondary aluminum layer; S2: Get the earliest designed layout layer in the MEMS stage in a bottom-up order, recorded as: MEMS bottom aluminum layer; S3: merging the layout design of the ASIC top aluminum layer into the layout design of the MEMS bottom aluminum layer to obtain: a merged MEMS bottom aluminum layer; S4: Deleting the top passivation opening layer of the ASIC.

[0008] It is further characterized by: It also includes the following steps: a1: Find the through-hole layer closest to the top aluminum layer of the ASIC except the top passivation opening layer of the ASIC in the ASIC stage, and record it as: the adjusted top through-hole passivation opening layer; a2: adjusting the size of the through hole in the adjusted top through hole passivation opening layer; In step a2, the method for adjusting the through holes in the adjusted top through hole passivation opening layer comprises the following steps: b1: Increase the size of the through hole used for the bonding port to a size that meets the bonding standard; b2: adjusting the through hole used for interconnection between the original top aluminum layer and the second top aluminum layer to a size that meets the connection requirement between the merged MEMS bottom aluminum layer and the ASIC second aluminum layer; The top aluminum layer of the ASIC is made of copper-doped aluminum; The MEMS bottom aluminum layer is composed of a high-resistance TAN layer and an aluminum layer stacked together; In step S3, when merging, on the MEMS bottom aluminum layer, after etching away the surface Al at the location where a high resistance device is required to be formed, the bottom TAN is exposed to form a resistance device.

[0009] The present application provides a chip plate making method based on the stacking process, which merges the ASIC top aluminum layer located at the bottom of the integrated chip into the MEMS bottom aluminum layer located at the top, so that the ASIC top passivation opening layer used to connect the topmost layer of the ASIC and the bottommost layer of the MEMS can be deleted simultaneously, and the top through hole with adjusted size connects the merged MEMS bottom aluminum layer and the ASIC secondary aluminum layer, which can also realize the original function of the integrated chip; based on this method, the number of plate making layers can be reduced by 2 layers in the original number of layout layers, the process steps are optimized, the process cycle is shortened, and the manufacturing cost of the chip is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the overall structure of an integrated thermal bubble inkjet chip; Figure 2 An example of a layered layout for an integrated thermal inkjet chip; Figure 3 An example of the top aluminum layer of the ASIC and the bottom aluminum layer of the MEMS before merging; Figure 4 It is a front cross-sectional view from the plate-making layer M2 to INL before merging; Figure 5 An example of the bottom aluminum layer of the MEMS after merging; Figure 6 This is the cross-sectional view of the bonding port after merging the M2 of the ASIC stage onto the INL of the MEMS stage; Figure 7 This is the cross-sectional view of the common connection after merging the M2 of the ASIC stage onto the INL of the MEMS stage; Figure 8 An example of the merging method on INL; Fig. 9 Modified example for VIA1 on the bond port; Fig.10 Modified example of VIA1 for interconnection between aluminum layers. DETAILED DESCRIPTION

[0011] According to the manufacturing process of the stacking process, in the MEMS and ASIC stacked in the vertical direction, in order to achieve electrical interconnection, the bottom layer of the MEMS and the top layer of the ASIC must be an aluminum layer. The top layer of aluminum of the ASIC is used for pin bonding gold wires and interconnection between the internal devices of the chip, and is also used for signal connection with the bottom layer of aluminum wires of the MEMS. The aluminum wires at the bottom layer of the MEMS are used to connect the MEMS resistors with the top layer of aluminum of the ASIC to realize the integrated chip interconnection function. Therefore, the technical solution of the present application is applicable to all thermal bubble inkjet chip stacking processes. In the present application, two adjacent aluminum layers are merged to save the number of layout plate making layers. Specifically, the present application includes a chip plate making method based on the stacking process, which includes the following steps.

[0012] S1: Get the last two layout layers of the ASIC stage in a bottom-up order, record the last designed layout as: ASIC top passivation opening layer, record the second to last designed layout as: ASIC top aluminum layer; record the aluminum layer closest to the ASIC top aluminum layer as: ASIC secondary aluminum layer.

[0013] S2: Obtain the earliest designed layout layer in the MEMS stage in a bottom-up order, recorded as: MEMS bottom aluminum layer.

[0014] S3: Merge the layout design of the top aluminum layer of the ASIC into the layout design of the bottom aluminum layer of the MEMS to obtain: the merged bottom aluminum layer of the MEMS.

[0015] S4: Delete the top passivation opening layer of ASIC.

[0016] After removing the top passivation aperture layer of the ASIC, the following steps need to be performed: a1: Find the through-hole layer closest to the top aluminum layer of ASIC except the top passivation opening layer of ASIC in the ASIC stage, that is, the top through-hole layer, recorded as: the adjusted top through-hole passivation opening layer.

[0017] a2: Adjust the size of the through hole in the adjusted top through hole passivation opening layer.

[0018] The specific method for adjusting the through-holes in the adjusted top through-hole passivation opening layer comprises the following steps: b1: Increase the through hole for the bonding port to a size that meets the bonding standard; b2: Adjusting the through holes used for interconnection between the original top aluminum layer and the second top aluminum layer to a size that meets the connection requirements between the merged MEMS bottom aluminum layer and the ASIC second aluminum layer.

[0019] by Figure 2 The layered layout of the integrated thermal bubble inkjet chip shown in the figure is used as an example to illustrate the specific steps of this method. The project process of this embodiment is based on CSMC (China Resources Shanghua) 1um 40V 0.5um backend HV Process, and the process platform is: 1um SPDM 40V HV Process (0.5um backend) Figure 2 The ASIC-1~ASIC-13 layers correspond to the ASIC stage in chip manufacturing. The plate-making levels include BN (N-type buried layer), TB (N-well), TO (active area), GT (polycrystalline), HV (high-voltage thick gate oxide), SN (N-type injection), SP (P-type injection), HF (P-type field injection), CT (tungsten via layer), M1 (first aluminum layer), VIA1 (through hole layer), M2 (second aluminum layer), and CP (passivation opening), which are arranged in order from bottom to top.

[0020] Figure 2 The MEMS1~MEMS7 layers correspond to the MEMS manufacturing stage. The plate-making layers are arranged from bottom to top: INL (thin-film resistor aluminum layer), INS (thin-film resistor etching), IN3 (thin-film resistor protection), PAS (oxide layer pre-etching), TR (channel deep etching), W4 (cavity membrane), and W5 (covering protective film).

[0021] In Figure 2 In the embodiment, the ASIC top aluminum layer is: M2 (second aluminum layer), the ASIC secondary aluminum layer is: M1 (first aluminum layer), the ASIC top passivation opening layer is: CP (passivation opening), the MEMS bottom aluminum layer is: INL (thin-film resistor aluminum layer), and the adjusted top through-hole passivation opening layer is VIA1 (through-hole layer).

[0022] Usually, the INL (thin-film resistor aluminum layer) in the MEMS stage is used to manufacture thin-film resistors and interconnect with the M2 in the ASIC stage. It is not used as an aluminum wire for interconnection in other parts of the chip. Therefore, the top-layer aluminum M2 in the ASIC stage using this overlay process can be merged into the INL in the MEMS stage. After the top-layer aluminum M2 in the ASIC stage is merged into the INL, the CP layer used to open the top passivation layer is no longer needed. This method of merging platemaking layers can reduce the number of platemaking plates by two.

[0023] Specifically, there is a certain difference between the top aluminum M2 of ASIC and the bottom aluminum INL of MEMS. INL is composed of a high-resistance TAN and an aluminum layer stacked together. INL can not only ensure the low resistance of the connection, but also form a high-resistance device by selecting the area that needs to be etched. The M2 at the ASIC stage is just copper-doped aluminum, which only has the low resistance of the connection and does not have the characteristics of forming a high-resistance device. Since the bottom aluminum INL at the MEMS stage also has the low resistance characteristics of the connection, the top aluminum of ASIC can be merged into the bottom aluminum INL at the MEMS stage without affecting the original function of the chip.

[0024] like Figure 8 As shown, after etching away the surface AL on the INL where a high-resistance device is required, the bottom layer TAN is leaked out to form a resistor device, while the M2 at the ASIC stage does not have this feature. The RES part in the figure is a resistor device. Before the M2 at the ASIC stage is merged into the INL at the MEMS stage, it is necessary to adjust the M2 routing where the original M2 and INL overlap or have a small spacing, so that M2 and INL have a certain spacing in other places except where they need to be connected. The specific value of this spacing is preferably not less than 3 microns. After the adjustment of the top aluminum M2 of the ASIC is completed, the M2 of the ASIC can be merged into the INL of the MEMS, thus ensuring that the INL connection at the MEMS stage after the merger will not have a short circuit or a small spacing that causes a decrease in yield.

[0025] Therefore, this method chooses to merge the M2 of the ASIC stage into the INL of the MEMS stage. By merging the M2 of the ASIC stage into the INL of the MEMS stage, two plate-making layers, M2 and CP, can be saved.

[0026] The top aluminum M2 of the ASIC stage is merged into the INL of the MEMS stage. After the original CP (passivation opening) layer is deleted, the VIA1 (via layer) of the ASIC stage will serve as the top passivation opening. The size of the VIA1 designed originally needs to be modified. The size of the VIA1 via used on the bonding port needs to be increased to a size that meets the bonding standard, generally larger than 80um*80um. Other VIA1 vias used for interconnection between aluminum layers only need to be increased to 4um*4um. Figure 3 An example of the top aluminum layer of the ASIC and the bottom aluminum layer of the MEMS before merging; Fig. 9 This shows the modified VIA1 on the bond port. Fig.10 The modified VIA1 of the interconnect between aluminum layers is shown. Fig. 9 and Fig.10 V1A1 is labeled as V1.

[0027] Specifically, Figure 4This is a simplified cross-sectional view of the ASIC aluminum layer and the MEMS aluminum layer of the patterning layer before merging. Figure 4 The thickness of the insulating medium between M2 and M1 is about 1um, so the size of VIA1 connecting M2 and M1 is designed to be 0.55um*0.55um according to the process requirements.

[0028] Figure 5 An example of the bottom aluminum layer of the MEMS after merging; Figure 6 This is a cross-sectional view of the bonding port after the M2 of the ASIC stage is merged into the INL of the MEMS stage. Since the VIA1 hole replaces the function of the original CP passivation opening after the M2 is merged into the INL, the original CP layer is no longer needed. The thickness of the final passivation layer (SIO2+SI3N4) of the ASIC stage is much thicker than 1um, and the port that needs gold wire bonding requires good contact, so the VIA1 design requirement at the port that needs gold wire bonding is 80um*80um.

[0029] Figure 7 This is a cross-sectional view of the common connection after the M2 of the ASIC stage is merged onto the INL of the MEMS stage. After the M2 is merged onto the INL, at the common connection, since the thickness of the final passivation layer (SIO2+SI3N4) of the ASIC stage is much thicker than 1um, and there is no high requirement for bonding at the common connection, appropriately increasing the size of VIA1 can effectively ensure the connection contact requirements between the INL and the lower layer M1. The design requirement in this embodiment is 4um*4um.

[0030] After using the technical solution of the present application, the project's plate-making levels are reduced by two layers, saving two layers of plate-making costs, optimizing the process steps, shortening the process cycle, and reducing the chip manufacturing cost to a certain extent.

Claims

1. A chip plate making method based on superposition process, characterized in that: It includes the following steps: S1: Get the last two layout layers of the ASIC stage in a bottom-up order, record the last designed layout as: ASIC top passivation opening layer, and record the second to last designed layout as: ASIC top aluminum layer; The aluminum layer closest to the ASIC top aluminum layer is recorded as: ASIC secondary aluminum layer; S2: Get the earliest designed layout layer in the MEMS stage in a bottom-up order, recorded as: MEMS bottom aluminum layer; S3: merging the layout design of the ASIC top aluminum layer into the layout design of the MEMS bottom aluminum layer to obtain: a merged MEMS bottom aluminum layer; S4: Delete the top passivation opening layer of the ASIC.

2. A chip plate making method based on the superposition process according to claim 1, characterized in that: It also includes the following steps: a1: Find the through-hole layer closest to the top aluminum layer of the ASIC except the top passivation opening layer of the ASIC in the ASIC stage, and record it as: the adjusted top through-hole passivation opening layer; a2: adjusting the size of the through hole in the adjusted top through hole passivation opening layer.

3. A chip plate making method based on the superposition process according to claim 2, characterized in that: In step a2, the method for adjusting the through holes in the adjusted top through hole passivation opening layer comprises the following steps: b1: Increase the size of the through hole used for the bonding port to a size that meets the bonding standard; b2: Adjusting the through holes used for interconnection between the original top aluminum layer and the second top aluminum layer to a size that meets the connection requirements between the merged MEMS bottom aluminum layer and the ASIC second aluminum layer.

4. A chip plate making method based on the superposition process according to claim 1, characterized in that: The top aluminum layer of the ASIC is made of copper-doped aluminum.

5. The chip plate making method based on the superposition process according to claim 1, characterized in that: The MEMS bottom aluminum layer is composed of a stacked high-resistance TAN layer and an aluminum layer.

6. The chip plate making method based on the superposition process according to claim 1, characterized in that: In step S3, when merging, on the MEMS bottom aluminum layer, after etching away the surface Al at the location where a high resistance device is required to be formed, the bottom TAN is exposed to form a resistance device.

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