Detection method and device, storage medium and electronic equipment
By establishing an RTree index structure in a three-dimensional chip, the intersection of stacked through holes and wires is quickly detected, and the problem of low detection efficiency in the prior art is solved, and efficient intersection detection is achieved.
Patent Information
- Application Number
- CN202411802126.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-03-28
AI Technical Summary
In the prior art, when detecting whether the stacked through holes and wires intersect in a three-dimensional chip, a large amount of coordinate information is required to traverse, resulting in slow search speed and low efficiency.
By obtaining the coordinate pair set of stacked through holes and wires to be detected, an RTree index structure is established, and RTree is used to quickly detect the intersection of stacked through holes and wires.
It improves detection efficiency and can quickly handle the intersection of large-scale through-holes and wires, which improves detection speed.
Smart Images
Figure CN119720936A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip technology, and in particular to a detection method, device, storage medium and electronic device. Background Art
[0002] In digital simulation software, it is often necessary to establish a three-dimensional coordinate system for the chip of the digital circuit. In the three-dimensional chip after the coordinate system is established, the via is in the vertical direction of the circuit, and the wire is in the horizontal direction of the circuit. Among them, the vias (Via) with the same coordinate information in different layers of the chip are stacked vias (stacked Via).
[0003] Currently, the detection of whether stacked vias and wires intersect is mainly carried out by converting the position information of the stacked vias and wires into the coordinate information of their respective blocks, and then traversing the coordinate information of the blocks corresponding to the vias and wires to detect whether the stacked vias and wires intersect.
[0004] However, since there are a large number of stacked vias and wires in the three-dimensional chip, using this detection method requires traversing and searching the coordinate information of the blocks corresponding to each stacked via and wire, resulting in slow search speed and low search efficiency. Summary of the invention
[0005] In view of this, the present application provides a detection method, device, storage medium and electronic device, the main purpose of which is to improve the current existing technology. Due to the presence of a large number of stacked through holes and wires in the three-dimensional chip, when using this detection method, it is necessary to traverse and search for the coordinate information of the blocks corresponding to each stacked through hole and wire, resulting in slow search speed and low search efficiency. Technical problems.
[0006] In a first aspect, the present application provides a detection method, comprising:
[0007] Acquire a target coordinate pair set representing the positions of the stacked vias to be detected and a set of coordinate pairs to be detected representing the positions of the wires included in the metal layer to be detected;
[0008] Establishing an RTree index structure according to the set of coordinate pairs to be detected;
[0009] Detecting the intersection of the to-be-detected stacked via and the to-be-detected metal layer in the RTree index structure based on the target coordinate pair set;
[0010] The intersection of the to-be-detected stacked via and the to-be-detected metal layer is determined based on the detection result.
[0011] Optionally, the metal layer to be detected includes a first metal layer to be detected and a second metal layer to be detected;
[0012] The step of obtaining a set of target coordinate pairs representing positions of stacked through holes to be detected includes:
[0013] Parsing model information of the stacked via to be detected from a first predetermined file describing chip layout information, and parsing rule information of the stacked via to be detected from a second predetermined file describing information of a standard cell library, and determining rectangular area information of the via to be detected based on the rule information of the stacked via to be detected;
[0014] Based on the model information and the rectangular area information, a first coordinate set corresponding to the connection of the through hole to be detected to the first metal layer to be detected and a second coordinate set corresponding to the connection of the through hole to be detected to the second metal layer to be detected are determined, and the target coordinate pair set includes the first coordinate set and the second coordinate set.
[0015] Optionally, obtaining a set of coordinate pairs to be detected representing the positions of the wires contained in the metal layer to be detected includes:
[0016] Parsing the first rectangular area information to be detected corresponding to the first metal layer to be detected and the second rectangular area information to be detected corresponding to the second metal layer to be detected from the first predetermined file;
[0017] Based on the first rectangular area information to be detected, the diagonal coordinates of the rectangle corresponding to each wire contained in the first metal layer to be detected are determined, and the determined diagonal coordinates are combined into a first coordinate pair set to be detected; and, based on the second rectangular area information to be detected, the diagonal coordinates of the rectangle corresponding to each wire contained in the second metal layer to be detected are determined, and the determined diagonal coordinates are combined into a second coordinate pair set to be detected, and the coordinate pair set to be detected includes the first coordinate pair set to be detected and the second coordinate pair set to be detected.
[0018] Optionally, establishing an RTree index structure according to the set of coordinate pairs to be detected includes:
[0019] Establishing a first RTree index structure according to the first set of coordinate pairs to be detected, and establishing a second RTree index structure according to the second set of coordinate pairs to be detected;
[0020] The detecting the intersection of the to-be-detected stacked via and the to-be-detected metal layer in the RTree index structure based on the target coordinate pair set includes:
[0021] Based on the first coordinate set, the intersection of the stacked via to be detected and the first metal layer to be detected is detected in the first RTree index structure, and based on the second coordinate set, the intersection of the stacked via to be detected and the second metal layer to be detected is detected in the second RTree index structure.
[0022] Optionally, the detecting the intersection of the to-be-detected stacked via and the to-be-detected metal layer in the RTree index structure based on the target coordinate pair set further includes:
[0023] In the RTree index structure, the to-be-detected coordinate set is determined as a detection range, and the target coordinate set is detected within the detection range to obtain candidate intersection points of the target coordinate set and the to-be-detected coordinate pair set.
[0024] Optionally, determining the intersection of the to-be-detected stacked via and the to-be-detected metal layer based on the detection result includes:
[0025] Determine the node type corresponding to the candidate intersection in the RTree index structure;
[0026] If it is determined that the candidate intersection point is a leaf node in the RTree index structure, an intersection point that meets a predetermined intersection condition is selected from the candidate intersection points, and the selected intersection point is used as the target intersection point as the target intersection point of the stacked via to be detected and the metal layer to be detected;
[0027] If it is determined that the candidate intersection point is an internal node in the RTree index structure, the intersection of the to-be-detected stacked via and the to-be-detected metal layer is detected based on the candidate node according to the predetermined intersection judgment condition.
[0028] In a second aspect, the present application provides a detection device, comprising:
[0029] An acquisition module is configured to acquire a target coordinate pair set representing the positions of the stacked vias to be detected and a set of coordinate pairs to be detected representing the positions of the wires included in the metal layer to be detected;
[0030] An establishing module, configured to establish an RTree index structure according to the set of coordinate pairs to be detected;
[0031] A detection module, configured to detect the intersection of the to-be-detected stacked via and the to-be-detected metal layer in the RTree index structure based on the target coordinate pair set;
[0032] The determination module is configured to determine the intersection of the to-be-detected stacked via and the to-be-detected metal layer based on the detection result.
[0033] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the detection method described in the first aspect.
[0034] In a fourth aspect, the present application provides an electronic device, comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor implements the detection method described in the first aspect when executing the computer program.
[0035] In a fifth aspect, the present application provides a computer program product, which includes a computer program, and is characterized in that when the computer program is executed by a processor, it implements the detection method described in the first aspect.
[0036] By means of the above technical scheme, the present application provides a detection method, device, storage medium and electronic device. Compared with the current existing technology, the present application obtains a target coordinate pair set representing the position of the stacked through hole to be detected and a set of coordinate pairs to be detected representing the position of the wire contained in the metal layer to be detected; establishes an RTree index structure according to the set of coordinate pairs to be detected; detects the intersection of the stacked through hole to be detected and the metal layer to be detected in the RTree index structure based on the target coordinate pair set; determines the intersection of the stacked through hole to be detected and the metal layer to be detected based on the detection result, so as to establish a coordinate system for the stacked through holes and wires in the three-dimensional chip and establish an RTree for each layer of wires, and converts the intersection problem of the through holes and the wires into the RTree intersection problem of the through holes and the wires. Since the RTree solution method is fast and efficient, it can quickly detect the intersection of large-scale through holes and wires, thereby improving the detection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0038] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0039] Figure 1 A schematic diagram of a detection method provided in an embodiment of the present application is shown;
[0040] Figure 2 A schematic diagram of a detection method provided in an embodiment of the present application is shown;
[0041] Figure 3 A schematic diagram showing an example provided by an embodiment of the present application;
[0042] Figure 4 A schematic diagram showing an example provided by an embodiment of the present application;
[0043] Figure 5 A schematic diagram of the structure of a detection device provided in an embodiment of the present application is shown;
[0044] Figure 6 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0045] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.
[0046] In order to improve the existing technology, due to the presence of a large number of stacked vias and wires in a three-dimensional chip, the use of this detection method requires traversing and searching the coordinate information of the blocks corresponding to each stacked via and wire, resulting in slow search speed and low search efficiency. This embodiment provides a detection method, such as Figure 1 As shown, the method includes:
[0047] Step 101 : Obtain a target coordinate pair set representing the positions of stacked vias to be detected and a coordinate pair set to be detected representing the positions of wires included in a metal layer to be detected.
[0048] In an embodiment of the present application, a target coordinate pair set representing the position of a stacked through hole to be detected may be a target coordinate pair comprising multiple stacked through holes to be detected, wherein the target coordinate pair of each stacked through hole may be the diagonal coordinates of a rectangular area corresponding to each stacked through hole. For example, if through hole 1 connects metal layer 1 and metal layer 2, then there will be a corresponding rectangular area 1 for through hole 1. If the diagonal coordinates of rectangular area 1 are (1, 1) and (-1, -1) respectively, then the target coordinate pair corresponding to through hole 1 is (1, 1) and (-1, -1), and the target coordinate pairs corresponding to each through hole together constitute a target coordinate pair set.
[0049] It should be noted that the stacked through holes to be detected may be multiple stacked through holes that need to be detected, wherein the top metal layer and the bottom metal layer connected to the stacked through holes to be detected are the same, for example, there are stacked through holes 1, stacked through holes 2 and stacked through holes 3 between metal layer m1 and metal layer m2, and there are stacked through holes 4 and stacked through holes 5 between metal layer m2 and metal layer m3, then stacked through holes 1, stacked through holes 2 and stacked through holes 3 can collectively become stacked through holes to be detected, and stacked through holes 4 and stacked through holes 5 can collectively become stacked through holes to be detected.
[0050] In some examples, stacked vias are a common structure in integrated circuit design used to establish electrical connections between different metal layers. Stacked vias usually consist of multiple vias that are aligned in a vertical direction to form a continuous conductive path from one metal layer to another.
[0051] Specifically, stacked vias can span multiple metal layers to achieve electrical connection from the top layer to the bottom layer or any intermediate layer; for example, metal layer 1 (M1) is connected to metal layer 3 (M3) through stacked vias, and may pass through metal layer 2 (M2) in the middle; on each metal layer, stacked vias will form a rectangular area, which includes the via itself and the metal filling area around it. The size of the rectangular area depends on the size of the via and the requirements of the metal filling to ensure good electrical connection and mechanical strength; the via rules (VIARULE) define parameters such as the size, shape and spacing of the vias. These rules are usually defined in the LEF file and referenced in the DEF file. The design of stacked vias needs to take into account reliability and manufacturing process limitations to ensure that problems such as open circuits or short circuits do not occur during long-term use.
[0052] For this embodiment, the metal layer to be detected may be the metal layer of the stacked via connection to be detected, and accordingly, the metal layer is one of the main layers used for wiring. These metal layers contain wires, which are used to connect various components in the circuit, such as transistors, resistors, capacitors, etc. The wires in the metal layer are the key part of realizing the electrical connection inside the chip.
[0053] In some examples, the metal layer to be detected may include multiple wires, each wire has a corresponding rectangular area, and each rectangular area has a pair of diagonal coordinates. For example, if the rectangular area of wire 1 is rectangular area A, and the diagonal coordinates of rectangular area A are (2, 2) and (-2, -2), then the set of coordinate pairs to be detected corresponding to wire 1 can be (2, 2) and (-2, -2), and so on. Examples are not given one by one here.
[0054] Step 102: Establish an RTree index structure based on the set of coordinate pairs to be detected.
[0055] In the embodiment of the present application, R-Tree is a data structure for multidimensional spatial indexing, which is particularly suitable for efficiently processing range queries and nearest neighbor queries. The index structure design of R-Tree enables it to effectively manage and query multidimensional data, such as points, line segments and polygons in geographic information systems (GIS). The basic structure of R-Tree R-Tree is a hierarchical index, similar to B-Tree, but it is designed for multidimensional data. R-Tree consists of multiple nodes, each of which contains pointers to its child nodes and the minimum bounding rectangle (MinimumBoundingRectangle, MBR) corresponding to each child node.
[0056] Step 103 : detecting the intersection of the to-be-detected stacked via and the to-be-detected metal layer in the RTree index structure based on the target coordinate pair set.
[0057] In some examples, in integrated circuit design, an R-Tree index structure can be used to efficiently detect intersections between stacked vias and metal layers.
[0058] Step 104 : determining the intersection of the to-be-detected stacked via and the to-be-detected metal layer based on the detection result.
[0059] In some examples, it is necessary to further determine the type of the detected intersection based on the detection result, and further determine whether the stacked via to be detected and the metal layer to be detected intersect according to different types.
[0060] Compared with the current existing technology, this embodiment obtains a target coordinate pair set representing the position of the stacked through hole to be detected and a coordinate pair set to be detected representing the position of the wire contained in the metal layer to be detected; establishes an RTree index structure based on the coordinate pair set to be detected; detects the intersection of the stacked through hole to be detected and the metal layer to be detected in the RTree index structure based on the target coordinate pair set; determines the intersection of the stacked through hole to be detected and the metal layer to be detected based on the detection result, and can establish an RTree for each layer of wire in the three-dimensional chip, converting the intersection problem of the through hole and the wire into the RTree intersection problem of the through hole and the wire. Since the RTree solution method is fast and efficient, it can quickly detect the intersection of large-scale through holes and wires, thereby improving the detection efficiency.
[0061] As a refinement and extension of the above embodiment, the metal layer to be detected includes a first metal layer to be detected and a second metal layer to be detected. When acquiring a target coordinate pair set representing the position of the stacked through hole to be detected, the following method may be used but is not limited to: Figure 2 As shown, the method includes:
[0062] Step 201, parse the model information of the stacked via to be detected from the first predetermined file describing the chip layout information, and parse the rule information of the stacked via to be detected from the second predetermined file describing the information of the standard cell library, and determine the rectangular area information of the via to be detected based on the rule information of the stacked via to be detected.
[0063] In an embodiment of the present application, the first predetermined file describing the chip layout information may be a Design Exchange Format (DEF) file. Specifically, the DEF file is used to describe the specific physical layout of the chip, including the location of the macro unit, pin connections, wiring paths, etc. DEF files can exchange design data between different EDA tools to ensure the consistency and compatibility of the design. Through the DEF file, layout verification can be performed to check whether the design complies with the rules and constraints.
[0064] In some examples, the model information of the stacked via to be detected may be information of a via model (ViaModel) in a DEF file. Specifically, in integrated circuit design, a VIA model refers to a description that defines the geometry and electrical characteristics of a via (Via).
[0065] Optionally, the second predetermined file describing the information of the standard cell library may be a Library Exchange Format (LEF) file, which is a file format used to describe the standard cell library and other physical design data. The LEF file contains information such as the geometry, pin location, and timing characteristics of various components (such as logic gates, buffers, etc.) used in the design. It also defines the routing layer, via rules, and other constraints and rules related to physical design.
[0066] As an optional method, the rule information of the stacked via to be detected can be the via rule (VIARULE) in the LEF file for defining the via rule. VIARULE specifies how to create vias between different metal layers, including the size, shape and process constraints of the via. These rules ensure the correctness and reliability of the via in the physical design.
[0067] Correspondingly, the rectangular area information of the through hole to be detected can be the rectangle (RECT) information in the LEF file. Specifically, RECT is a keyword used to define a rectangular area. It describes the geometric shape and position of the rectangle by specifying the coordinates of the lower left corner and the upper right corner of the rectangle.
[0068] For example, the corresponding VIARULE can be obtained according to the through-hole model defined in DEF, and the block position information of VIA can be obtained according to the RECT definition of VIARULE defined in LEF. Figure 3 As shown below is a schematic diagram of stacked vias and wires in a three-dimensional chip. A general VIA consists of two metal layers plus a cut layer.
[0069] For example, if the via to be detected is via3_2, and via3_2 is composed of metal layer metal3 (top metal layer) and metal layer metal4 (bottom metal layer), the corresponding RECT describes the diagonal coordinates of the block, such as Figure 4 As shown, the coordinate information of a block is represented by the coordinates of the lower left corner (x1, y1) and the coordinates of the upper right corner (x2, y2). Correspondingly, the corresponding coordinates of Metal3 can be (model.x0, model.y0, model.x1, model.y1).
[0070] Step 202: Determine, based on the model information and the rectangular region information, a first coordinate set corresponding to the through hole to be detected connecting to the first metal layer to be detected and a second coordinate set corresponding to the through hole to be detected connecting to the second metal layer to be detected.
[0071] The target coordinate pair set includes a first coordinate set and the second coordinate set.
[0072] In some examples, the first coordinate set and the second coordinate set may be accumulated coordinates of the through-hole coordinates and the offset.
[0073] Exemplarily, based on step 201, for the through hole to be detected is via3_2, after determining the coordinates corresponding to Metal3, it is necessary to process the through holes with the same position coordinates, merge the through holes with the same position coordinates, and after merging, calculate the actual block position information of VIA according to the VIA model in the LEF file and the physical logical position and orientation information in the DEF. It should be noted that according to the DEF file specification, the directions of VIA are divided into North (North, N), South (South, S), East (East, E), West (W) and Flipped North (FN), Flipped South (FS), Flipped East (FE), Flipped West (FW). For the directions of E, W, FE, and FW, we call them vertical VIA, and the other directions are horizontal VIA. For horizontal VIA, the coordinates of VIA are the sum of the actual coordinates (x, y) defined in DEF and the offsets of the corresponding VIAmodel (model.x0, model.y0, model.x1, model.y1).
[0074] For example, it can be:
[0075] x0_final=x+model.x0
[0076] y0_final=y+model.y0
[0077] x1_final=x+model.x1
[0078] y1_final=y+model.y1
[0079] Correspondingly, for a vertical VIA, it can be specifically:
[0080] x0_final=x+model.y0
[0081] y0_final=y+model.x0
[0082] x1_final=x+model.y1
[0083] y1_final=y+model.x1
[0084] According to the above example and the position information of the corresponding top metal layer and bottom metal layer, the final block position information of the corresponding VIA can be obtained respectively.
[0085] Further, when executing the acquisition of the set of coordinate pairs to be detected representing the positions of the wires contained in the metal layer to be detected, the following method may be used but is not limited thereto. The method includes:
[0086] Step 11: parse the first rectangular area information to be detected corresponding to the first metal layer to be detected and the second rectangular area information to be detected corresponding to the second metal layer to be detected from the first predetermined file.
[0087] In an embodiment of the present application, the position information of the wire is obtained according to the definition of the DEF file. Specifically, in integrated circuit design, the position information of the wire is usually defined in a DEF (Design Exchange Format) file. The DEF file describes the specific layout information of the chip, including the location of the macro unit, pin connection, wiring path, etc. The position information of the wire is defined by the ROUTE statement. The definition of the wire position information is in the DEF file, and the position information of the wire is usually defined by the NET and ROUTE statements. The NET statement defines a network, and the ROUTE statement specifies the specific wiring path in the network.
[0088] Step 12: Based on the first rectangular area information to be detected, determine the diagonal coordinates of the rectangle corresponding to each wire contained in the first metal layer to be detected, and form the determined diagonal coordinates into a first coordinate pair set to be detected; and, based on the second rectangular area information to be detected, determine the diagonal coordinates of the rectangle corresponding to each wire contained in the second metal layer to be detected, and form the determined diagonal coordinates into a second coordinate pair set to be detected.
[0089] The set of coordinate pairs to be detected includes a first set of coordinate pairs to be detected and a second set of coordinate pairs to be detected.
[0090] In integrated circuit design, the location information of wires is usually defined through DEF files. Each wire consists of a series of coordinate points that define the path of the wire. For the convenience of processing and querying, the wire can be converted into one or more rectangular areas. These rectangular areas can be used for multidimensional spatial indexes (such as RTree) to improve query efficiency.
[0091] Optionally, when establishing an RTree index structure according to the set of coordinate pairs to be detected, the following method may be used but is not limited to the following method, including:
[0092] Step 21: Establish a first RTree index structure according to the first set of coordinate pairs to be detected, and establish a second RTree index structure according to the second set of coordinate pairs to be detected.
[0093] Exemplarily, for the top metal interconnect layer of the through hole, the coordinate information of all wires belonging to the top metal layer is established into RTree. The coordinate information of the wire includes the coordinate information (wx0, wy0) and (wx1, wy1) of a square, and, for the bottom metal interconnect layer of the through hole, the coordinate information of all wires belonging to the top metal layer is established into RTree.
[0094] Accordingly, based on step 21, when performing detection of the intersection of the stacked via to be detected and the metal layer to be detected in the RTree index structure based on the target coordinate pair set, the following method may be used but is not limited to, and the method includes:
[0095] Step 22: Detect the intersection of the stacked via to be detected and the first metal layer to be detected in the first RTree index structure based on the first coordinate set, and detect the intersection of the stacked via to be detected and the second metal layer to be detected in the second RTree index structure based on the second coordinate set.
[0096] It should be noted that the first metal layer in the embodiment of the present application can be the top metal layer connected to the through hole to be detected, and correspondingly, the second metal layer can be the bottom metal layer connected to the through hole to be detected. For the intersection of the top metal layer and the through hole to be detected, and the intersection of the bottom metal layer and the through hole to be detected, it is necessary to establish an RTree index structure for detection respectively.
[0097] For example, for the top interconnect layer, since we have obtained the actual coordinate block information (x0_final, y0_final) and (x1_final, y1_final) of VIA and the RTree of the block information of the wire. Each node of the RTree consists of the minimum bounding rectangle (wx0, wy0) and (wx1, wy1). The VIA coordinates of the top metal layer and the bottom metal layer and the RTree of the wire of the corresponding layer can be queried to determine whether they intersect. It should be noted that the bottom interconnect layer can be detected in the same way as the top interconnect layer, and no examples are given here.
[0098] Optionally, when performing detection of the intersection of the to-be-detected stacked via and the to-be-detected metal layer in the RTree index structure based on the target coordinate pair set, the following method may be used but is not limited to, and the method includes:
[0099] Step 31: In the RTree index structure, the coordinate set to be detected is determined as the detection range, and the target coordinate set is detected within the detection range to obtain candidate intersection points of the target coordinate set and the coordinate pair set to be detected.
[0100] Further, based on step 31, when determining the intersection of the stacked via to be detected and the metal layer to be detected based on the detection result, the following method may be used but is not limited to the following method, which includes:
[0101] Step 32: Determine the node type corresponding to the candidate intersection point in the RTree index structure.
[0102] Step 33: If the candidate intersection is determined to be a leaf node in the RTree index structure, an intersection meeting a predetermined intersection condition is selected from the candidate intersections, and the selected intersection is used as a target intersection of the stacked via to be detected and the metal layer to be detected.
[0103] Step 34: If it is determined that the candidate intersection point is an internal node in the RTree index structure, the intersection between the stacked via to be detected and the metal layer to be detected is detected based on the candidate node according to a predetermined intersection judgment condition.
[0104] In an embodiment of the present application, R-Tree is a data structure for multidimensional spatial indexing, particularly suitable for efficiently processing range queries and nearest neighbor queries. R-Tree consists of multiple nodes, which are divided into leaf nodes and internal nodes. Among them, leaf nodes store actual spatial objects, such as the minimum bounding rectangle (MBR) of a wire, and contain specific information pointing to these objects. Each leaf node contains one or more MBRs, and each MBR corresponds to an actual spatial object (such as a wire). Internal nodes do not directly store actual spatial objects, but store pointers to their child nodes and the MBRs corresponding to each child node. Each internal node contains one or more pointers, each pointer is associated with an MBR, indicating the minimum bounding rectangle of all objects or child nodes contained in the child node.
[0105] In some examples, the predetermined intersection condition may include: for each rectangle, we need to know its lower left corner coordinates (x1, y1) and upper right corner coordinates (x2, y2), or the lower left corner coordinates and the width and height of the rectangle. Assuming we have two rectangles, denoted as rect1 and rect2, we can compare the horizontal and vertical boundaries of the two rectangles respectively, including: Horizontal boundary comparison: If the right boundary (x2) of rect1 is smaller than the left boundary (x1) of rect2, or the right boundary of rect2 is smaller than the left boundary of rect1, they do not overlap in the horizontal direction and therefore do not intersect. Vertical boundary comparison: If the upper boundary (y2) of rect1 is smaller than the lower boundary (y1) of rect2, or the upper boundary of rect2 is smaller than the lower boundary of rect1, they do not overlap in the vertical direction and therefore do not intersect. If neither of the above two conditions is met (that is, they overlap at least partially in both the horizontal and vertical directions), the two rectangles intersect.
[0106] It should be noted that, for RTree, the spatial object in the node is represented by a minimum bounding rectangle (MBR), that is, the lower left corner coordinates (x1, y1) and the upper right corner coordinates (x2, y2).
[0107] Exemplarily, the query starts from the root node of RTree. The minimum bounding rectangle of the target block (query block) to be searched for the intersecting block is used as the query range. For the current node (starting from the root node), check whether the minimum bounding rectangle corresponding to each child node intersects with the minimum bounding rectangle of the query block. The method for judging the intersection is to use the judgment condition based on the coordinate axis range mentioned above. If the minimum bounding rectangle of the child node intersects with the query block, there are two cases. If the child node is a leaf node, then the block contained in the child node (the leaf node stores the actual spatial object, i.e., the block) is the candidate block that may intersect with the query block. Further check whether these candidate blocks actually intersect with the query block, and verify them one by one using the block intersection judgment condition mentioned above. If the child node is not a leaf node (i.e., an internal node), the child node is used as the new current node, and the above-mentioned intersection judgment and traversal operation are recursively performed. After the above-mentioned traversal process, all blocks that actually intersect with the query block are collected and returned as query results. For RTree, the complexity is o(log n+k), where n is the height of the number, which is logarithmic, and k is the number of child nodes.
[0108] Compared with the current existing technology, this embodiment obtains a target coordinate pair set representing the position of the stacked through hole to be detected and a coordinate pair set to be detected representing the position of the wire contained in the metal layer to be detected; establishes an RTree index structure based on the coordinate pair set to be detected; detects the intersection of the stacked through hole to be detected and the metal layer to be detected in the RTree index structure based on the target coordinate pair set; determines the intersection of the stacked through hole to be detected and the metal layer to be detected based on the detection result, so as to establish a coordinate system for the stacked through holes and wires in the three-dimensional chip and establish an RTree for each layer of wires, and convert the intersection problem of the through holes and the wires into the RTree intersection problem of the through holes and the wires. Since the RTree solution method is fast and efficient, it can quickly detect the intersection of large-scale through holes and wires, thereby improving the detection efficiency.
[0109] Further, as Figure 1 and Figure 2 The specific implementation of the method shown in this embodiment provides a detection device, such as Figure 5 As shown, the device includes: an acquisition module 31, an establishment module 32, a detection module 33, and a determination module 34.
[0110] An acquisition module 31 is configured to acquire a target coordinate pair set representing the position of the stacked via to be detected and a coordinate pair set to be detected representing the position of the wire included in the metal layer to be detected;
[0111] An establishing module 32 is configured to establish an RTree index structure according to the set of coordinate pairs to be detected;
[0112] A detection module 33 is configured to detect the intersection of the to-be-detected stacked via and the to-be-detected metal layer in the RTree index structure based on the target coordinate pair set;
[0113] The determination module 34 is configured to determine the intersection of the to-be-detected stacked via and the to-be-detected metal layer based on the detection result.
[0114] In some examples of the present embodiment, the metal layer to be detected includes a first metal layer to be detected and a second metal layer to be detected; accordingly, the acquisition module 31 is specifically configured to parse the model information of the stacked through hole to be detected from a first predetermined file describing the chip layout information, and to parse the rule information of the stacked through hole to be detected from a second predetermined file describing the information of the standard cell library, and determine the rectangular area information of the through hole to be detected based on the rule information of the stacked through hole to be detected; based on the model information and the rectangular area information, determine a first coordinate set corresponding to the through hole to be detected connecting the first metal layer to be detected and a second coordinate set corresponding to the through hole to be detected connecting the second metal layer to be detected, and the target coordinate pair set includes the first coordinate set and the second coordinate set.
[0115] In some examples of the present embodiment, the acquisition module 31 is specifically configured to parse out the first rectangular area information to be detected corresponding to the first metal layer to be detected and the second rectangular area information to be detected corresponding to the second metal layer to be detected from the first predetermined file; determine the diagonal coordinates of the rectangle corresponding to each wire contained in the first metal layer to be detected based on the first rectangular area information to be detected, and form the determined diagonal coordinates into a first set of coordinate pairs to be detected; and determine the diagonal coordinates of the rectangle corresponding to each wire contained in the second metal layer to be detected based on the second rectangular area information to be detected, and form the determined diagonal coordinates into a second set of coordinate pairs to be detected, wherein the set of coordinate pairs to be detected includes the first set of coordinate pairs to be detected and the second set of coordinate pairs to be detected.
[0116] In some examples of the present embodiment, the establishment module 32 is specifically configured to establish a first RTree index structure based on the first set of coordinate pairs to be detected, and to establish a second RTree index structure based on the second set of coordinate pairs to be detected; correspondingly, the detection module 33 is specifically configured to detect the intersection of the stacked through hole to be detected and the first metal layer to be detected in the first RTree index structure based on the first coordinate set, and to detect the intersection of the stacked through hole to be detected and the second metal layer to be detected in the second RTree index structure based on the second coordinate set.
[0117] In some examples of this embodiment, the detection module 33 is further configured to determine the set of coordinates to be detected as a detection range in the RTree index structure, and detect the target coordinate set within the detection range to obtain candidate intersection points between the target coordinate set and the set of coordinate pairs to be detected.
[0118] In some examples of the present embodiment, the determination module 34 is specifically configured to determine the node type corresponding to the candidate intersection in the RTree index structure; if the candidate intersection is determined to be a leaf node in the RTree index structure, an intersection that meets a predetermined intersection condition is selected from the candidate intersections, and the selected intersection is used as the target intersection as the target intersection of the stacked through hole to be detected and the metal layer to be detected; if the candidate intersection is determined to be an internal node in the RTree index structure, the intersection of the stacked through hole to be detected and the metal layer to be detected is detected based on the candidate node according to the predetermined intersection judgment condition.
[0119] It should be noted that for other corresponding descriptions of the functional units involved in the detection device provided in this embodiment, reference can be made to Figure 1 and Figure 2 The corresponding description in will not be repeated here.
[0120] Based on the above Figure 1 and Figure 2 The method shown in the embodiment also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned Figure 1 and Figure 2 The method shown.
[0121] Based on this understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, USB flash drive, mobile hard disk, etc.), including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods of various implementation scenarios of the present application.
[0122] like Figure 6 The figure shows a hardware structure diagram of an electronic device of the present invention, including:
[0123] at least one processor 401; and,
[0124] A memory 402 is communicatively connected to at least one of the processors 401; wherein,
[0125] The memory 402 stores instructions that can be executed by at least one of the processors. The instructions are executed by at least one of the processors so that the at least one of the processors can perform the detection method described above.
[0126] Figure 6 A processor 401 is taken as an example.
[0127] The electronic device may further include: an input device 403 and a display device 404 .
[0128] The processor 401, the memory 402, the input device 403 and the display device 404 may be connected via a bus or other means. Figure 6 The example of connecting through bus is taken in the following.
[0129] The memory 402 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions / modules corresponding to the detection method in the embodiment of the present application, for example, Figure 1 and Figure 2 The processor 401 executes various functional applications and data processing by running the non-volatile software programs, instructions and modules stored in the memory 402, that is, implementing the detection method in the above embodiment.
[0130] The memory 402 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required by at least one function; the data storage area may store data created according to the use of the detection method, etc. In addition, the memory 402 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 402 may optionally include a memory remotely arranged relative to the processor 401, and these remote memories may be connected to the device for executing the detection method via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
[0131] The input device 403 can receive user clicks and generate signal inputs related to user settings of the detection method and function control. The display device 404 can include display devices such as a display screen.
[0132] The one or more modules are stored in the memory 402 and, when executed by the one or more processors 401 , execute the detection method in any of the above method embodiments.
[0133] Optionally, the above-mentioned physical device may also include a user interface, a network interface, a camera, a radio frequency (RF) circuit, a sensor, an audio circuit, a WI-FI module, etc. The user interface may include a display, an input unit such as a keyboard, etc., and the optional user interface may also include a USB interface, a card reader interface, etc. The network interface may optionally include a standard wired interface, a wireless interface (such as a WI-FI interface), etc.
[0134] Those skilled in the art will appreciate that the above-mentioned physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or a combination of certain components, or different arrangements of components.
[0135] The storage medium may also include an operating system and a network communication module. The operating system is a program that manages the hardware and software resources of the above-mentioned physical device, and supports the operation of the information processing program and other software and / or programs. The network communication module is used to realize the communication between the components inside the storage medium, and the communication with other hardware and software in the information processing physical device.
[0136] Through the description of the above implementation methods, the technicians in this field can clearly understand that the present application can be implemented by means of software plus the necessary general hardware platform, or by hardware. By applying the scheme of this embodiment, compared with the current prior art, this embodiment obtains a target coordinate pair set representing the position of the stacked through hole to be detected and a set of coordinate pairs to be detected representing the position of the wire contained in the metal layer to be detected; establishes an RTree index structure based on the set of coordinate pairs to be detected; detects the intersection of the stacked through hole to be detected and the metal layer to be detected in the RTree index structure based on the target coordinate pair set; determines the intersection of the stacked through hole to be detected and the metal layer to be detected based on the detection results, and can establish a coordinate system for the stacked through holes and wires in the three-dimensional chip and establish an RTree for each layer of wires, and convert the intersection problem of the through hole and the wire into the RTree intersection problem of the through hole and the wire. Since the RTree solution method is fast and efficient, it can quickly detect the intersection of large-scale through holes and wires, thereby improving the detection efficiency.
[0137] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0138] The above is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features applied for herein.
Claims
1. A detection method, characterized in that: include: Acquire a target coordinate pair set representing the position of the stacked via to be detected and a coordinate pair set to be detected representing the position of the wire included in the metal layer to be detected; Establishing an R-tree RTree index structure according to the set of coordinate pairs to be detected; Detecting the intersection of the to-be-detected stacked via and the to-be-detected metal layer in the RTree index structure based on the target coordinate pair set; The intersection of the to-be-detected stacked via and the to-be-detected metal layer is determined based on the detection result.
2. The method according to claim 1, characterized in that: The metal layer to be detected includes a first metal layer to be detected and a second metal layer to be detected; The step of obtaining a target coordinate pair set representing the positions of the stacked through holes to be detected includes: Parsing model information of the stacked via to be detected from a first predetermined file describing chip layout information, and parsing rule information of the stacked via to be detected from a second predetermined file describing information of a standard cell library, and determining rectangular area information of the via to be detected based on the rule information of the stacked via to be detected; Based on the model information and the rectangular area information, a first coordinate set corresponding to the connection of the through hole to be detected to the first metal layer to be detected and a second coordinate set corresponding to the connection of the through hole to be detected to the second metal layer to be detected are determined, and the target coordinate pair set includes the first coordinate set and the second coordinate set.
3. The method according to claim 2, characterized in that Obtain a set of coordinate pairs to be detected, which represent the positions of the wires contained in the metal layer to be detected, including: Parsing the first rectangular area information to be detected corresponding to the first metal layer to be detected and the second rectangular area information to be detected corresponding to the second metal layer to be detected from the first predetermined file; Based on the first rectangular area information to be detected, the diagonal coordinates of the rectangle corresponding to each wire contained in the first metal layer to be detected are determined, and the determined diagonal coordinates are combined into a first coordinate pair set to be detected; and, based on the second rectangular area information to be detected, the diagonal coordinates of the rectangle corresponding to each wire contained in the second metal layer to be detected are determined, and the determined diagonal coordinates are combined into a second coordinate pair set to be detected, and the coordinate pair set to be detected includes the first coordinate pair set to be detected and the second coordinate pair set to be detected.
4. The method according to claim 3, characterized in that: The step of establishing an RTree index structure according to the set of coordinate pairs to be detected includes: Establishing a first RTree index structure according to the first set of coordinate pairs to be detected, and establishing a second RTree index structure according to the second set of coordinate pairs to be detected; The detecting the intersection of the to-be-detected stacked via and the to-be-detected metal layer in the RTree index structure based on the target coordinate pair set includes: Based on the first coordinate set, the intersection of the stacked via to be detected and the first metal layer to be detected is detected in the first RTree index structure, and based on the second coordinate set, the intersection of the stacked via to be detected and the second metal layer to be detected is detected in the second RTree index structure.
5. The method according to any one of claims 1 to 4, characterized in that The detecting the intersection of the to-be-detected stacked via and the to-be-detected metal layer in the RTree index structure based on the target coordinate pair set further includes: In the RTree index structure, the to-be-detected coordinate set is determined as a detection range, and the target coordinate set is detected within the detection range to obtain candidate intersection points of the target coordinate set and the to-be-detected coordinate pair set.
6. The method according to claim 5, characterized in that The determining, based on the detection result, the intersection of the to-be-detected stacked via and the to-be-detected metal layer comprises: Determine the node type corresponding to the candidate intersection in the RTree index structure; If it is determined that the candidate intersection point is a leaf node in the RTree index structure, an intersection point that meets a predetermined intersection condition is selected from the candidate intersection points, and the selected intersection point is used as the target intersection point as the target intersection point of the stacked via to be detected and the metal layer to be detected; If it is determined that the candidate intersection point is an internal node in the RTree index structure, the intersection of the to-be-detected stacked via and the to-be-detected metal layer is detected based on the candidate node according to the predetermined intersection judgment condition.
7. A detection device, characterized in that: include: An acquisition module is configured to acquire a target coordinate pair set representing the position of the stacked via to be detected and a to-be-detected coordinate pair set representing the position of the wire included in the to-be-detected metal layer; An establishing module, configured to establish an RTree index structure according to the set of coordinate pairs to be detected; A detection module, configured to detect the intersection of the to-be-detected stacked via and the to-be-detected metal layer in the RTree index structure based on the target coordinate pair set; The determination module is configured to determine the intersection of the to-be-detected stacked via and the to-be-detected metal layer based on the detection result.
8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.
9. An electronic device comprising a storage medium, a processor, and a computer program stored in the storage medium and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 6 is implemented.
10. A computer program product, comprising a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.