Calibration apparatus of memory device and calibration method thereof
By using a calibration device with strong arm comparator and logic circuit structure adjustment in the memory device, the problem of signal integrity reduction caused by impedance mismatch in high-speed data transmission is solved, and higher signal integrity and lower calibration error rate are achieved.
Patent Information
- Application Number
- CN202311344295.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-27
- Filing Date
- 2023-10-17
- Publication Date
- 2025-03-28
AI Technical Summary
During high-speed data transmission, due to impedance mismatch, signal integrity is reduced and signal transmission quality is affected.
The calibration device of a memory device is adopted, including impedance, strong arm comparator, logic circuit and calibration controller. By changing the circuit structure (such as using strong arm comparator to replace the original comparison circuit and the structure adjustment of the logic circuit) to reduce the comparison delay time between the comparison signal and the reference signal, ensuring that the impedance calibration circuit has sufficient timing budget and calculation margin.
Reduces the error rate of impedance calibration and improves the integrity of the signal in the memory device.
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Figure CN119724271A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to an impedance calibration technology of a memory device, and in particular to a calibration device and a calibration method of the memory device. Background Art
[0002] High-capacity and high-performance integrated circuit memories, including three-dimensional NAND flash, are continuing to develop, hoping to use three-dimensional stacking technology and multi-level cells (MLC) to reduce the size of storage cells and increase data storage density, and improve data access and transmission speed.
[0003] On the other hand, as the operating speed of the electronic device increases, the swing width of the signal transmitted between the memory devices in the electronic device will be correspondingly reduced, thereby reducing the delay time spent on transmitting the signal. However, as the swing width of the signal is reduced, the transmission of the signal will be greatly affected by external noise, and the signal reflection at the data transmission end will increase due to the impedance mismatch between the transmission paths, making it difficult to transmit data at high speed, reducing signal integrity and affecting the transmission quality of the signal. Impedance mismatch can be caused by changes in the semiconductor manufacturing process, supply voltage, and operating temperature (PVT). Therefore, calibrating the impedance in the data transmission path (such as ZQ calibration) is used to solve the problem of reduced signal integrity due to impedance mismatch during high-speed data transmission. Summary of the invention
[0004] The invention provides an impedance calibration technology for a memory device, which can reduce the error rate of impedance calibration and improve the signal integrity in the memory device.
[0005] The calibration equipment of the memory device described in the embodiment of the present invention includes impedance, a strong arm comparator, a logic circuit and a calibration controller. Impedance is used to generate a comparison voltage. The strong arm comparator includes a non-inverting input terminal and an inverting input terminal. The non-inverting input terminal receives a reference voltage. The inverting input terminal receives the comparison voltage. The strong arm comparator compares the reference voltage with the comparison voltage to generate a comparison result, and latches the comparison result and correspondingly generates a latch signal and an inverted latch signal. The logic circuit is coupled to the strong arm comparator. The logic circuit generates a comparison result signal based on the latch signal and the inverted latch signal. And, the calibration controller implements impedance calibration in the memory device based on the comparison result signal.
[0006] Based on the above, the calibration device and calibration method of the memory device described in the embodiment of the present invention utilizes a change in the circuit structure (for example, replacing the original comparison circuit with a strong-arm comparator, adjusting the structure of the logic circuit) to reduce the delay time in comparing the comparison signal with the reference signal, so that the subsequent impedance calibration circuit (such as a controller implementing ZQ calibration) has sufficient timing budget and calculation margin, thereby reducing the error rate of impedance calibration and improving the signal integrity in the memory device. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 It is a schematic diagram of the structure of a memory block in a three-dimensional memory chip according to an embodiment of the present invention.
[0008] Figure 2 is a circuit block diagram of a calibration apparatus for a memory device according to a first embodiment of the present invention.
[0009] Figure 3 yes Figure 2 Timing diagram of the calibration device signals.
[0010] Figure 4 is a circuit block diagram of a calibration apparatus for a memory device according to a second embodiment of the present invention.
[0011] Figure 5 yes Figure 4 Detailed circuit diagram of the strong arm comparator.
[0012] Figure 6 yes Figure 4 Timing diagram of the calibration device signals.
[0013] Figure 7 is a circuit block diagram of a calibration apparatus for a memory device according to a third embodiment of the present invention.
[0014] Fig. 8A and Figure 8B Schematic diagrams showing the states corresponding to the calibration signals when the calibration controller uses linear search or binary search are shown respectively.
[0015] Fig. 9 is a flow chart of a calibration method for a memory device according to an embodiment of the present invention.
[0016] [Description of Reference Numerals]
[0017] 150: Memory block
[0018] 152: Page
[0019] 154: Storage cell string
[0020] 156.SSL: Serial Select Line
[0021] 157: Storage unit
[0022] 158. GSL: Ground selection line
[0023] 159. CSL: Common Source Line
[0024] BLn, BLn+1: bit lines
[0025] WL0~WL95:Word line
[0026] 200, 400, 700: Calibration equipment
[0027] 210, 410: Impedance
[0028] 220: Comparator
[0029] 231: Delay element
[0030] 234, 434: Data Flip Flop (DFF)
[0031] 240, 440: Calibration controller
[0032] 250, 450: Adjust the drive
[0033] 310, 320, 610: Arrow
[0034] 420: Strong Arm Comparator
[0035] 430: Logic Circuits
[0036] 432: NAND Gate
[0037] 510: Differential input pair
[0038] 520: Latch
[0039] 530-1, 530-2: Reset circuit
[0040] 660: Preamplifier
[0041] S910-S950: Steps of the calibration method of the memory device
[0042] VREF: reference voltage
[0043] Vdr: comparison voltage
[0044] Vin+: non-inverting input terminal
[0045] Vin-: Inverting input terminal
[0046] OSC: Clock signal
[0047] OSCB: Inverted clock signal
[0048] Cout: comparator output
[0049] OSCBD: delayed clock signal
[0050] LAT_OUT1: comparison result
[0051] LAT_OUT: latch signal
[0052] LAT_OUTB: Inverted latch signal
[0053] Result, Sres: comparison result signal
[0054] ZQS[n:0]:calibration signal
[0055] D: Data input terminal
[0056] CK: Clock receiving end
[0057] Q: Data output terminal
[0058] code1~code3:coding
[0059] CDT1~CDT2: Comparison delay
[0060] CADT1~CADT2: Calculation delay
[0061] VRT1~VRT2: reference voltage adjustment time
[0062] O1, O2, O3, R1, R2, R3: Data
[0063] OUT1: The first output terminal of the strong arm comparator
[0064] OUT2: The second output terminal of the strong arm comparator
[0065] PO1: The first output terminal of the differential input pair
[0066] PO2: The second output terminal of the differential input pair
[0067] DFF_CK: trigger clock signal
[0068] M1~M10、MCL:Transistor
[0069] VDD: system voltage terminal
[0070] INV1, INV2: Inverter DETAILED DESCRIPTION
[0071] Figure 11 is a schematic diagram of the structure of a memory block 150 in a three-dimensional memory chip according to an embodiment of the present invention. The memory block 150 may be a part of a three-dimensional NAND flash memory with high capacity and high performance. A plurality of memory cells in the memory block 150 are arranged in three dimensions, for example, an XYZ coordinate system. Taking the memory cell 157 as an example, the memory cell 157 is coupled to the corresponding word line WL0 and the bit line BL. The word lines (e.g., word lines WL0-WL95) formed by the conductive layer or the word line layer and the plurality of memory cells coupled thereto form a plurality of pages 152. In other words, the memory cells in the memory block 150 are divided into a plurality of pages 152. Each page 152 may be, for example, a layer of memory cells in the XY plane, and the memory cells on the same layer (same page) are coupled to the same word line (e.g., word line WL0 or WL95) and obtain corresponding word line voltages. The memory cells on different layers (different pages) are coupled to different word lines. Each page may be connected to a corresponding contact in the driving circuit, for example, to an X decoder (or a scan driver). Each line has a corresponding voltage driver, and these voltage drivers can be controlled by a memory controller (not shown) or corresponding hardware. The multiple memory cells in the memory cell string 154 belong to different pages.
[0072] The memory cell string 154 includes a plurality of memory cells connected in series vertically along the Z direction. The memory cell is configured as a string selection transistor SST coupled to a string selection line SSL 156, and the memory cell may also be configured as a ground selection transistor GST coupled to a ground selection line GSL 158. The memory cell string 154 is connected to one or more drivers, such as a data driver. The memory cell string 154 including the memory cell 157 is connected to a common source line CSL 159 via a ground selection transistor GST. The SSL 156 may be a conductive line or a conductive layer formed on the top of each page 152 (or a word line layer). The memory block 150 may include a plurality of SSLs 156 provided on the top of the page 152. The GSL 158 may be a conductive line or a conductive layer formed on the bottom of each page 152 (or a word line layer). The CSL 159 may be a conductive layer or a plurality of conductive lines formed on a substrate of a three-dimensional storage wafer. A number of dummy lines or corresponding layers (not shown) may be further disposed between the serial selection line SSL 1.56 and the uppermost page 152 , or between the ground selection line GSL 158 and the lowermost page 152 .
[0073] On the other hand, in order to improve signal integrity and enhance the strength of the output signal, whether Figure 1Whether it is a NAND flash memory device or a double data rate synchronous dynamic random access memory (DDR SDRAM), the memory device may be provided with a terminal resistor and a corresponding adjustment driver to calibrate the impedance on the data transmission path (e.g., ZQ calibration), thereby reducing the impedance mismatch caused by changes in the semiconductor manufacturing process, supply voltage, and operating temperature (PVT), thereby maintaining signal integrity.
[0074] Figure 2 FIG. 1 is a circuit block diagram of a calibration apparatus 200 for a memory device according to a first embodiment of the present invention. Figure 2 The calibration device 200 includes an impedance 210, a comparator 220, a delay element 231, a data flip-flop (DFF) 234, a calibration controller 240, and an adjustment driver 250. The impedance 210 can be called a reference impedance, which generates a comparison voltage Vdr by adjusting the current provided by the driver. The comparator 220 has a non-inverting input terminal Vin+, an inverting input terminal Vin-, and an output terminal Cout. The non-inverting input terminal Vin+ receives a reference voltage VREF, and the inverting input terminal Vin- receives the comparison voltage Vdr. The comparator 220 uses an inverted clock signal OSCB, which is inverse to the clock signal OSC, as its clock signal to enable the comparator 220 to perform its function. The comparator 220 is used to compare the reference voltage VREF with the comparison voltage Vdr to generate a comparison result LAT_OUT1 at its output terminal Cout. Figure 2 The calibration device 200 further includes a reference voltage generator, which is controlled by the calibration signal ZQS[n:0] to correspondingly adjust the voltage value of the reference voltage VREF.
[0075] Since the comparator 220 needs a period of processing time to compare the reference voltage VREF with the comparison voltage Vdr, it is not possible to immediately generate the comparison result LAT_OUT1 to the DFF 234. Therefore, the delay element 231 delays the inverted clock signal OSCB for a predetermined time to generate a delayed clock signal OSCBD, and the DFF 234 uses the delayed clock signal OSCBD as the clock signal of the DFF 234 to enable the DFF 234 to perform its function.
[0076] The calibration controller 240 implements impedance calibration (e.g., ZQ calibration) in the memory device in accordance with the comparison result signal Result generated by the DFF 234. Specifically, the calibration controller 240 generates a calibration signal ZQS[n:0] in accordance with the comparison result signal Result to implement impedance calibration. The calibration signal ZQS[n:0] may represent the strength of the ZQ calibration and may be used as a signal provided to the adjustment driver 250. The adjustment driver 250 coupled to the impedance 210 generates an adjusted current in accordance with the calibration signal ZQS[n:0]. The impedance 210 generates a comparison voltage Vdr through the adjusted current generated by the adjustment driver 250. The comparator 220, the delay element 231, the DFF 234, the calibration controller 240, and the adjustment driver 250 in the calibration device 200 are disposed in a chip, and the impedance 210 is a resistor or an impedance transistor disposed outside the chip and coupled to a specific pin (e.g., the ZQ pin) of the chip. The aforementioned resistor may be a passive resistor.
[0077] The processing time (herein referred to as comparison delay) taken by the comparator 220 when comparing the reference voltage VREF with the comparison voltage Vdr will correspondingly squeeze the processing time of the calibration controller 240 in performing impedance calibration. In other words, the calibration controller 240 will not have sufficient timing budget, thereby affecting the accuracy of impedance calibration.
[0078] Figure 3 yes Figure 2 Timing diagram of each signal of the calibration device 200. Each state 1 to state 3 represents a ZQ calibration is performed once. Figure 3 The middle symbol "Vdr / VREF" is used to represent the comparison voltage Vdr ( Figure 3 The corresponding solid line waveform of "Vdr / VREF") and the reference voltage VREF ( Figure 3 The corresponding dotted straight line of "Vdr / VREF"). Figure 3 As shown by arrow 310, the time from the rising edge of the clock signal (inverse clock signal OSCB) corresponding to the comparator 220 to the time when the comparator 220 generates the first data O1 in the comparison result LAT_OUT1 is the aforementioned comparison delay CDT1. Figure 2 The operation timing of DFF 234 is correct, as shown by arrow 320, when the timer in delay element 231 delays a predetermined time according to the inverted clock signal OSCB to generate the delayed clock signal OSCBD. This can prevent DFF 234 from latching an erroneous result due to the slow output of comparator 220. In this way, Figure 2The calibration controller 240 can only calculate the code code2 in the corresponding calibration signal ZQS[n:0] within the calculation delay CADT1 period, and in the next state (for example, state 2), the calibration controller 240 provides the calibration signal ZQS[n:0] with the code code2 to the adjustment driver 250, so that the calibration controller 240 adjusts the voltage value of the reference voltage VREF in the reference voltage adjustment time VRT1, and continues the next ZQ calibration in state 2. The data O1, O2, O3 in the comparison result LAT_OUT1 correspond to the data calculated in different states. The data R1, R2, R3 in the comparison result signal Result correspond to the data calculated in different states.
[0079] from Figure 3 It can be seen that the time point at which the comparator 220 generates the first data O1 in the comparison result LAT_OUT1 is delayed due to the comparison delay CDT1, resulting in the calibration controller 240 shortening the calculation delay CADT1 in performing the ZQ calibration, which correspondingly shortens the refresh time of the calibration signal ZQS[n;0] and shortens the reference voltage adjustment time VRT1. If the calibration signal ZQS[n:0] is refreshed too late, it will affect the reference voltage VREF in the next state and affect the comparator in the next state.
[0080] The second embodiment of the present invention uses a strong arm comparator including a differential input pair and a latch to replace Figure 2 The comparator 220 replaces the delay element 231 composed of multiple inverters with a NAND gate in the logic circuit, so that the calibration device can have more timing budget for the reference voltage VREF in establishing the next state, and extends the timing budget for the calibration controller 240 to perform and calculate ZQ calibration.
[0081] Figure 4 FIG. 4 is a circuit block diagram of a calibration apparatus 400 for a memory device according to a second embodiment of the present invention. Figure 2 and Figure 4 The main difference between the two is that the calibration device 400 is based on Figure 4 Strong arm comparator 420 is used to replace Figure 2 The comparator 220 is used in the calibration device 400, and the NAND gate 432 in the logic circuit 430 is used to replace the delay element composed of multiple inverters. In detail, the calibration device 400 is composed of an impedance 410, a strong arm comparator 420, a logic circuit 430, a calibration controller 440 and an adjustment driver 450. The functions of the impedance 410, the calibration controller 440 and the adjustment driver 450 are similar to Figure 2 The corresponding components are the same.
[0082] The non-inverting input terminal Vin+ of the strong arm comparator 420 receives the reference voltage VREF, and the inverting input terminal Vin- of the strong arm comparator 420 receives the comparison voltage Vdr. The strong arm comparator 420 generates a latch signal LAT_OUT and an inverted latch signal LAT_OUTB at its first output terminal OUT1 and second output terminal OUT2 respectively by comparing the reference voltage VREF with the comparison voltage Vdr. For the detailed circuit structure of the strong arm comparator 420, please see Figure 5 and corresponding description.
[0083] The logic circuit 430 is coupled to the strong arm comparator 420. The logic circuit 430 generates a comparison result signal Sres according to the latch signal LAT_OUT and the inverted latch signal LAT_OUTB. In detail, the logic circuit 430 mainly includes a NAND gate 432 and a DFF 434. The first input terminal of the NAND gate 432 receives the latch signal LAT_OUT, and the second input terminal of the NAND gate 432 receives the inverted latch signal LAT_OUTB. The output terminal of the NAND gate 432 generates a trigger clock signal DFF_CK. Therefore, when the polarity of the latch signal LAT_OUT or the inverted latch signal LAT_OUTB is reversed, the trigger clock signal DFF_CK will trigger the DFF 434.
[0084] The DFF 434 includes a data input terminal D, a clock receiving terminal CK, and a data output terminal Q. The data input terminal D receives a latch signal LAT_OUT, and the clock receiving terminal CK receives a trigger clock signal DFF_CK. The DFF 434 generates a comparison result signal Sres at the data output terminal Q according to the latch signal LAT_OUT and the trigger clock signal DFF_CK. The calibration controller 440 generates a calibration signal ZQS[n:0] according to the comparison result signal Sres, and the calibration signal ZQS[n:0] is provided to the adjustment driver 450 and is used to set the reference voltage VREF through the reference voltage generator.
[0085] Figure 5 yes Figure 4 Detailed circuit diagram of the strong arm comparator 420. Figure 5 The strong arm comparator 420 mainly includes a differential input pair 510 and a latch 520. The differential input pair 510 includes a first input terminal and a second input terminal, the first input terminal is used as a non-inverting input terminal Vin+ of the strong arm comparator 420 to receive a reference voltage VREF, and the second input terminal is used as an inverting input terminal Vin- of the strong arm comparator 420 to receive a comparison voltage Vdr. The differential input pair 510 compares the reference voltage VREF with the comparison voltage Vdr to generate a comparison result.
[0086] In detail, the differential input pair 510 includes a first transistor M1 and a second transistor M2. The control end of the transistor M1 is coupled to the non-inverting input terminal Vin+ of the strong arm comparator 420, and the first end of the transistor M1 serves as the first output terminal PO1 of the differential input pair 510. The control end of the transistor M2 is coupled to the inverting input terminal Vin- of the strong arm comparator 420. The first end of the transistor M2 serves as the second output terminal PO2 of the differential input pair 510. The second end of the transistor M1 is coupled to the second end of the transistor M2. The differential input pair 510 also includes a control transistor MCL and a current source 540. The first end of the control transistor MCL is coupled to the second end of the transistor M1 and the second end of the transistor M2. The control end of the control transistor MCL receives the clock signal CKB. The current source 540 is coupled to the second end of the control transistor MCL. The transistors M1, M2 and MCL of this embodiment are all N-type transistors.
[0087] Figure 5 The latch 520 latches the comparison result provided by the differential input pair 510 from its first output terminal PO1 and second output terminal PO2 and generates a latch signal LAT_OUT and an inverted latch signal LAT_OUTB at its first output terminal OUT1 and second output terminal OUT2 accordingly. Figure 5 The latch 520 includes a first inverter INV1 and a second inverter INV2. The input end of the inverter INV1 is coupled to the first output end OUT1 of the strong arm comparator 420. The output end of the inverter INV1 is coupled to the second output end OUT2 of the strong arm comparator 420. The ground end of the inverter INV1 is coupled to the second output end PO2 of the differential input pair 510. The first output end OUT1 and the second output end OUT2 are used to generate a latch signal LAT_OUT and an inverted latch signal LAT_OUTB, respectively. The input end of the inverter INV2 is coupled to the second output end OUT2 of the strong arm comparator 420, the output end of the inverter INV2 is coupled to the first output end OUT1 of the strong arm comparator 420, and the ground end of the inverter INV2 is coupled to the first output end PO1 of the differential input pair 510.
[0088] The inverter INV1 includes transistors M3 and M4. The control end of the transistor M3 is coupled to the first output end OUT1 of the strong arm comparator 420. The first end of the transistor M3 is coupled to the second output end OUT2 of the strong arm comparator 420. The second end of the transistor M3 is coupled to the second output end PO2 of the differential input pair 510. The control end of the transistor M4 is coupled to the first output end OUT1 of the strong arm comparator 420. The first end of the transistor M4 is coupled to the system voltage end VDD. The second end of the transistor M4 is coupled to the second output end OUT2 of the strong arm comparator 420.
[0089] The inverter INV2 includes transistors M5 and M6. The control end of the transistor M5 is coupled to the second output end OUT2 of the strong arm comparator 420. The first end of the transistor M5 is coupled to the first output end OUT1 of the strong arm comparator 420. The second end of the transistor M5 is coupled to the first output end PO1 of the differential input pair 510. The control end of the transistor M6 is coupled to the second output end OUT2 of the strong arm comparator 420, the first end of the transistor M6 is coupled to the system voltage end VDD, and the second end of the transistor M6 is coupled to the first output end OUT1 of the strong arm comparator 420. The transistors M3 and M5 are both N-type transistors, and the transistors M4 and M6 are both P-type transistors.
[0090] The strong arm controller 420 further includes reset circuits 530-1 and 530-2. The reset circuits 530-1 and 530-2 are coupled to the input differential pair 510 and the latch 520. The reset circuits 530-1 and 530-2 are reset according to the clock signal CKB (ie, Figure 4 The inverted clock signal OSCB) resets the first output terminal PO1 and the second output terminal PO2 of the differential input pair 510 and resets the latch 520.
[0091] In detail, the reset circuit 530-1 includes transistors M7 and M8. The control end of the transistor M7 receives the clock signal CKB, the first end of the transistor M7 is coupled to the system voltage end VDD, and the second end of the transistor M7 is coupled to the first output end OUT1 of the strong arm comparator 420. The control end of the transistor M8 receives the clock signal CKB, the first end of the transistor M8 is coupled to the system voltage end VDD, and the second end of the transistor M8 is coupled to the first output end PO1 of the differential input pair 510. The reset circuit 530-2 includes transistors M9 and M10. The control end of the transistor M9 receives the clock signal, the first end of the transistor M9 is coupled to the system voltage end, and the second end of the transistor M9 is coupled to the second output end OUT2 of the strong arm comparator 420. The control end of the transistor M10 receives the clock signal CKB, the first end of the transistor M10 is coupled to the system voltage end VDD, and the second end of the transistor M10 is coupled to the second output end PO2 of the differential input pair 510. Transistors M7 to M10 are all P-type transistors.
[0092] When the clock signal CKB is enabled, Figure 5 Both ends of transistors M7 to M10 in the reset circuits 530-1 and 530-2 are turned on, so that the potentials at the first output terminal OUT1, the second output terminal OUT2 of the strong-arm comparator 420, the first output terminal PO1, and the second output terminal PO2 of the differential input pair 510 are all increased to the same potential as the system voltage terminal VDD, thereby achieving the reset of the differential input pair 510 and the latch 520.
[0093] Figure 6 yes Figure 4Timing diagram of various signals of calibration device 400. Figure 6 The middle symbol "Vdr / VREF" is used to represent the comparison voltage Vdr ( Figure 6 The corresponding solid line waveform of "Vdr / VREF") and the reference voltage VREF ( Figure 6 The corresponding dotted straight line of "Vdr / VREF"). Each state (state 1 to state 3) indicates a ZQ calibration. Figure 6 As shown by arrow 610 , the time point from the rising edge of the clock signal (inverse clock signal OSCB) corresponding to the strong-arm comparator 420 to the time point when the strong-arm comparator 420 generates the data O1 in the comparison result LAT_OUT1 is the comparison delay CDT2 .
[0094] On the other hand, when the polarities of the latch signal LAT_OUT and the inverted latch signal LAT_OUTB are different, Figure 4 The NAND gate 432 changes the trigger clock signal DFF_CK from disable to enable, and the DFF 434 provides the comparison result signal Sres to the Figure 4 Calibrate controller 440 so that Figure 4 The calibration controller 440 can calculate the code code2 in the corresponding calibration signal ZQS[n:0] within the calculation delay CADT2 period, and in the next state (e.g., state 2), the calibration controller 440 provides the calibration signal ZQS[n:0] having the code code2 to the adjustment driver 450. The calibration controller 440 adjusts the voltage value of the reference voltage VREF during the reference voltage adjustment time VRT2, and continues the next ZQ calibration in state 2.
[0095] Compare Figure 3 and Figure 6 , Figure 6 The length of the CDT2 delay is significantly shorter than Figure 3 Compare delay CDT1. And, Figure 6 The calculation delay CADT2 of the calibration controller 440 in performing ZQ calibration is significantly longer than Figure 3 Calculate the delay CADT1, and Figure 6 The reference voltage adjustment time VRT2 is significantly longer than Figure 2 The reference voltage adjustment time VRT1. Figure 6 The calibration controller 440 may have more time to calculate the ZQ calibration and adjust the reference voltage VREF, thereby avoiding calibration errors.
[0096] Figure 7 FIG. 1 is a circuit block diagram of a calibration device 700 for a memory device according to a third embodiment of the present invention. Figure 6 Compared with the second embodiment, under the conditions of circuit design, Figure 7The calibration device 700 further includes a preamplifier 660. The preamplifier 660 is coupled between the strong arm comparator 420 and the impedance 410. The non-inverting input terminal Vin+ of the strong arm comparator 420 receives the reference voltage VREF through the preamplifier 660. The inverting input terminal Vin- of the strong arm comparator 420 receives the comparison voltage Vdr through the preamplifier 660. In detail, the two input terminals of the preamplifier 660 receive the reference voltage VREF and the comparison voltage Vdr respectively, and the two output terminals of the preamplifier 660 are respectively coupled to the non-inverting input terminal Vin+ and the inverting input terminal Vin- of the strong arm comparator 420 to amplify the difference between the reference voltage VREF and the comparison voltage Vdr.
[0097] Figure 2 and Figure 4 The calibration controller 240 may implement the ZQ calibration in a variety of ways. Fig. 8A and Figure 8B The schematic diagrams of the states corresponding to the calibration signal ZQS[n:0] when the calibration controller uses linear search or binary search are presented respectively, where n and M are positive integers, and M is less than or equal to n. Fig. 8A ) or binary search (corresponding to Figure 8B ) is used as an example to illustrate that ZQ calibration can have multiple implementation aspects.
[0098] Fig. 9 is a flow chart of a calibration method for a memory device according to an embodiment of the present invention. Fig. 9 The calibration method can be applied to Figure 4 Calibration Device 400. Please also refer to Figure 4 and Fig. 9 In step S910, a comparison voltage Vdr is generated according to the impedance 410. Specifically, the impedance 410 generates the comparison voltage Vdr by using the adjustment driver 450 to generate an adjusted current according to the calibration signal ZQS[n:0].
[0099] In step S920, the strong arm comparator 420 is used to compare the comparison voltage Vdr and the reference voltage VREF to generate a comparison result. In step S930, the strong arm comparator 420 is used to latch the above-mentioned comparison result, and a latch signal LAT_OUT and an inverted latch signal LAT_OUTB are generated accordingly. In detail, the strong arm comparator 420 generates a latch signal LAT_OUT at its first output terminal OUT1 and generates an inverted latch signal LAT_OUTB at its second output terminal OUT2.
[0100] In step S940, the logic circuit 430 is used to generate the comparison result signal Sres according to the latch signal LAT_OUT and the inverted latch signal LAT_OUTB. Specifically, the NAND gate 432 is used to generate the trigger clock signal DFF_CK according to the latch signal LAT_OUT and the inverted latch signal LAT_OUTB. Furthermore, the data trigger 434 is used to generate the comparison result signal Sres according to the latch signal LAT_OUT, the inverted latch signal LAT_OUTB and the trigger clock signal DFF_CK. When the polarity of the latch signal LAT_OUT or the inverted latch signal LAT_OUTB is reversed, the trigger clock signal DFF_CK will be enabled to trigger the data trigger 434.
[0101] In step S950, the calibration controller 440 generates a calibration signal ZQS[n:0] according to the comparison result signal Sres to implement impedance calibration in the memory device. As described in the above embodiments, the impedance calibration can be a ZQ calibration, and the ZQ calibration is implemented using a linear search or a binary search.
[0102] In other embodiments consistent with the present invention, it is also possible to use Figure 7 The preamplifier 660 is used to amplify the voltage difference between the reference voltage VREF and the comparison voltage Vdr, so that the strong arm comparator 420 is more sensitive to the comparison between the reference voltage VREF and the comparison voltage Vdr. The detailed process and circuit structure details of the above steps can refer to the above embodiments.
[0103] In summary, the calibration device and calibration method of the memory device described in the embodiments of the present invention utilize changes in the circuit structure (for example, replacing the original comparison circuit with a strong-arm comparator, adjusting the structure of the logic circuit) to reduce the delay time in comparing the comparison signal with the reference signal, so that the subsequent impedance calibration circuit (such as a controller implementing ZQ calibration) has sufficient timing budget and calculation margin, thereby reducing the error rate of impedance calibration and improving the signal integrity in the memory device.
Claims
1. A calibration device for a memory device, characterized in that: include: Impedance, used to generate comparison voltage; A strong-arm (Strong-Am) comparator, comprising a non-inverting input terminal and an inverting input terminal, wherein the non-inverting input terminal receives a reference voltage, and the inverting input terminal receives the comparison voltage. The strong-arm comparator compares the reference voltage with the comparison voltage to generate a comparison result, and latches the comparison result and correspondingly generates a latch signal and an inverted latch signal; A logic circuit, coupled to the strong-arm comparator, generates a comparison result signal according to the latch signal and the inverted latch signal; as well as The calibration controller performs impedance calibration in the memory device according to the comparison result signal.
2. The calibration device according to claim 1, wherein the logic circuit comprises: A NAND gate, wherein a first input terminal of the NAND gate receives the latch signal, a second input terminal of the NAND gate receives the inverted latch signal, and an output terminal of the NAND gate generates a trigger clock signal; as well as A data trigger comprises a data input terminal, a clock receiving terminal and a data output terminal, wherein the data input terminal receives the latch signal, the clock receiving terminal receives the trigger clock signal, and the data trigger generates the comparison result signal at the data output terminal according to the latch signal and the trigger clock signal. 3 . The calibration device according to claim 2 , wherein when the polarity of the latch signal or the inverted latch signal is reversed, the trigger clock signal will be enabled to trigger the data trigger.
4. The calibration device according to claim 1, wherein the strong-arm comparator comprises: A differential input pair, comprising a first input terminal and a second input terminal, wherein the first input terminal serves as the non-inverting input terminal of the strong arm comparator to receive the reference voltage, and the second input terminal serves as the inverting input terminal of the strong arm comparator to receive the comparison voltage, and the differential input pair compares the reference voltage with the comparison voltage to generate the comparison result; as well as The latch is coupled to the differential input pair, latches the comparison result and correspondingly generates the latch signal and the inverted latch signal.
5. The calibration device according to claim 4, wherein the differential input pair comprises: a first transistor, a control terminal of which is coupled to the non-inverting input terminal of the strong-arm comparator, and a first terminal of the first transistor serving as a first output terminal of the differential input pair; as well as A second transistor has a control terminal coupled to the inverting input terminal of the strong-arm comparator, a first terminal of the second transistor serving as a second output terminal of the differential input pair, and a second terminal of the first transistor coupled to a second terminal of the second transistor.
6. The calibration apparatus of claim 5, wherein the differential input pair further comprises: a control transistor, a first terminal of which is coupled to the second terminal of the first transistor and the second terminal of the second transistor, and a control terminal of the control transistor receives a clock signal; as well as The current source is coupled to the second terminal of the control transistor.
7. The calibration apparatus of claim 4, wherein the latch comprises: A first inverter, an input end of which is coupled to the first output end of the strong-arm comparator, an output end of the first inverter is coupled to the second output end of the strong-arm comparator, and a ground end of the first inverter is coupled to the second output end of the differential input pair; as well as a second inverter, an input end of which is coupled to the second output end of the strong-arm comparator, an output end of the second inverter is coupled to the first output end of the strong-arm comparator, and a ground end of the second inverter is coupled to the first output end of the differential input pair, The first output terminal and the second output terminal of the strong-arm comparator are used to generate the latch signal and the inverted latch signal respectively.
8. The calibration device according to claim 7, wherein the first inverter comprises: a third transistor, a control end of which is coupled to the first output end of the strong-arm comparator, a first end of the third transistor is coupled to the second output end of the strong-arm comparator, and a second end of the third transistor is coupled to the second output end of the differential input pair; as well as A fourth transistor, a control end of which is coupled to the first output end of the strong-arm comparator, a first end of which is coupled to the system voltage end, and a second end of which is coupled to the second output end of the strong-arm comparator.
9. The calibration device according to claim 8, wherein the second inverter comprises: a fifth transistor, a control end of which is coupled to the second output end of the strong-arm comparator, a first end of the fifth transistor is coupled to the first output end of the strong-arm comparator, and a second end of the fifth transistor is coupled to the first output end of the differential input pair; as well as A sixth transistor has a control end coupled to the second output end of the strong-arm comparator, a first end of the sixth transistor coupled to the system voltage end, and a second end of the sixth transistor coupled to the first output end of the strong-arm comparator.
10. The calibration device according to claim 4, wherein the strong arm controller further comprises: The reset circuit is coupled to the input differential pair and the latch, and resets the first output terminal and the second output terminal of the differential input pair and the latch according to a clock signal.
11. The calibration device according to claim 10, wherein the reset circuit comprises: a seventh transistor, a control terminal of which receives the clock signal, a first terminal of the seventh transistor coupled to the system voltage terminal, and a second terminal of the seventh transistor coupled to the first output terminal of the strong-arm comparator; an eighth transistor, a control terminal of which receives the clock signal, a first terminal of the eighth transistor coupled to the system voltage terminal, and a second terminal of the eighth transistor coupled to the first output terminal of the differential input pair; a ninth transistor, a control terminal of which receives the clock signal, a first terminal of the ninth transistor coupled to the system voltage terminal, and a second terminal of the ninth transistor coupled to the second output terminal of the strong-arm comparator; as well as A tenth transistor has a control terminal receiving the clock signal, a first terminal of the tenth transistor coupled to the system voltage terminal, and a second terminal of the tenth transistor coupled to the second output terminal of the differential input pair.
12. The calibration device according to claim 1, further comprising: Adjust the driver to couple the impedance, The impedance generates the comparison voltage through the regulated current generated by the regulation driver. 13 . The calibration device according to claim 12 , wherein the calibration controller generates a calibration signal according to the comparison result signal to implement the impedance calibration, and the adjustment driver is controlled by the calibration signal to generate the adjusted current.
14. The calibration device according to claim 1, further comprising: a preamplifier, coupled between the strong-arm comparator and the impedance, wherein the non-inverting input terminal of the strong-arm comparator receives the reference voltage through the preamplifier, and the inverting input terminal of the strong-arm comparator receives the comparison voltage through the preamplifier, The preamplifier is used to amplify the voltage difference between the reference voltage and the comparison voltage. 15 . The calibration apparatus of claim 1 , wherein the impedance calibration is a ZQ calibration, and the calibration controller implements the ZQ calibration using a linear search or a binary search.
16. A method for calibrating a memory device, characterized in that: include: Producing a comparison voltage based on impedance; comparing the comparison voltage with a reference voltage to generate a comparison result; Latching the comparison result and correspondingly generating a latch signal and an inverted latch signal; Generating a comparison result signal according to the latch signal and the inverted latch signal; as well as A calibration signal is generated according to the comparison result signal to implement impedance calibration in the memory device.
17. The calibration method according to claim 16, wherein the step of generating the comparison result signal according to the latch signal and the inverted latch signal comprises: Using a NAND gate to generate a trigger clock signal according to the latch signal and the inverted latch signal; as well as A data trigger is used to generate the comparison result signal according to the latch signal, the inverted latch signal and the trigger clock signal, wherein when the polarity of the latch signal or the inverted latch signal is reversed, the trigger clock signal will be enabled to trigger the data trigger.
18. The calibration method according to claim 16, wherein the step of generating the comparison voltage according to the impedance comprises: The impedance generates the comparison voltage by adjusting the driver to generate an adjusted current according to the calibration signal.
19. The calibration method according to claim 16, further comprising: A preamplifier is used to amplify the voltage difference between the reference voltage and the comparison voltage.
20. The calibration method of claim 16, wherein the impedance calibration is a ZQ calibration, and the ZQ calibration is implemented using a linear search or a binary search.