A SRAM setup and hold time test circuit structure and system

Abstract

The present invention provides a SRAM setup and hold time test circuit structure and system, the structure includes a synchronization circuit, a first delay circuit, a second delay circuit, a third delay circuit and a test control circuit; the synchronization circuit includes a clock signal input terminal, a test signal switching input terminal, a clock signal output terminal, an address signal output terminal and a data signal output terminal; the first delay circuit includes a first control terminal, a clock signal delay input terminal and a clock signal delay output terminal; the second delay circuit includes an address signal delay input terminal, a first selection input terminal and an address signal delay output terminal; the third delay circuit includes a data signal delay input terminal, a second selection input terminal and a data signal delay output terminal. The synchronization clock signal, the synchronization address signal and the synchronization data signal are of the same source, which can significantly reduce the problem of errors in the SRAM setup and hold time obtained due to delayed synchronization processing.

Description

Technical Field

[0001] The present invention relates to the technical field of SRAM (Static Random Access Memory), and in particular to a circuit structure and system for testing the establishment and retention time of an SRAM. Background Art

[0002] SRAM is a very important semiconductor memory, which is widely embedded in high-performance microprocessors. The SRAM setup / hold time (setup / hold time) includes setup time and hold time; setup time is the minimum time that data needs to remain stable before the rising edge of the clock signal, so that the data can be correctly sampled; hold time is the minimum time that data needs to remain stable after the rising edge of the clock signal, so that the data can be accurately transmitted. When the setup / hold time is insufficient, the SRAM cannot be read and written normally, and when the setup / hold time is too long, the SRAM operating frequency will be reduced.

[0003] After SRAM is produced, it is necessary to use a test circuit structure to test the SRAM setup and hold time. The data signal and clock signal used in the currently commonly used test circuit structure are two relatively independent signals. These two signals need to be delayed and matched using a data signal delay circuit and a clock signal delay circuit, i.e., delayed and synchronized. Due to the limitations of process conditions and process deviations, the data signal delay circuit and the clock signal delay circuit in the same test circuit structure cannot accurately delay and synchronize all data signals and clock signals, which results in errors in the acquired SRAM setup and hold time. Summary of the invention

[0004] The invention provides a SRAM setup and hold time test circuit structure and system to solve the technical problem that delayed synchronization processing may lead to errors in the acquired SRAM setup and hold time.

[0005] In order to solve the above technical problems, the present invention provides an SRAM setup hold time test circuit structure, including a synchronization circuit, a first delay circuit, a second delay circuit, a third delay circuit and a test control circuit;

[0006] The synchronization circuit comprises a clock signal input terminal, a test signal switching input terminal, a clock signal output terminal, an address signal output terminal and a data signal output terminal; the clock signal input terminal is used to input an initial clock signal; the test signal switching input terminal is used to switch the direction of the tested signal; the synchronization circuit is used to convert the initial clock signal into a synchronous clock signal, a synchronous address signal and a synchronous data signal;

[0007] The first delay circuit includes a first control terminal, a clock signal delay input terminal and a clock signal delay output terminal; the first control terminal is used to input a first control signal, and the first control signal is used to control the delay time of the first delay circuit; the clock signal delay input terminal is connected to the clock signal output terminal; the clock signal delay output terminal is used to connect to the clock input terminal of the SRAM; the first delay circuit is used to delay the synchronous clock signal;

[0008] The second delay circuit includes an address signal delay input terminal, a first selection input terminal and an address signal delay output terminal; the address signal delay input terminal is connected to the address signal output terminal; the address signal delay output terminal is used to connect to the address input terminal of the SRAM; the second delay circuit is used to delay the synchronous address signal;

[0009] The third delay circuit comprises a data signal delay input terminal, a second selection input terminal and a data signal delay output terminal; the data signal delay input terminal is connected to the data signal output terminal; the data signal delay output terminal is used to connect to the data input terminal of the SRAM; the third delay circuit is used to delay the synchronous data signal;

[0010] The test control circuit includes a test port switching input terminal, a second control terminal, a first output terminal and a second output terminal; the test port switching input terminal is used to switch the port of the SRAM under test; the second control terminal is used to input a second control signal, and the second control signal is used to control the delay time of the second delay circuit and the third delay circuit; the first output terminal is connected to the first selection input terminal; the second output terminal is connected to the second selection input terminal; the test control circuit is used to switch the port of the SRAM under test and the delay time of the second delay circuit and the third delay circuit.

[0011] Preferably, the synchronization circuit includes a first multiplexer, a second multiplexer, a third multiplexer, a first inverter and a second inverter;

[0012] The first multiplexer includes two input interfaces, a test signal switching input interface and an output interface; the two input interfaces of the first multiplexer are respectively used to input the initial clock signal; the test signal switching input interface of the first multiplexer is used to select an input interface to form a path with the output interface;

[0013] The second multiplexer includes two input interfaces, a test signal switching input interface and an output interface; one input interface of the second multiplexer is used to input the initial clock signal, and the other input interface inputs the initial clock signal through the first inverter; the test signal switching input interface of the second multiplexer is used to select an input interface to form a path with the output interface;

[0014] The third multiplexer includes two input interfaces, a test signal switching input interface and an output interface; one input interface of the third multiplexer is used to input the initial clock signal, and the other input interface inputs the initial clock signal through the second inverter; the test signal switching input interface of the third multiplexer is used to select an input interface to form a path with the output interface.

[0015] Preferably, the synchronization circuit also includes a buffer, the input end of the buffer is used to input the initial clock signal, and the node after the input interface of the first multiplexer, the input end of the first inverter and the input end of the second inverter are connected in parallel is connected to the output end of the buffer.

[0016] Preferably, the first delay circuit, the second delay circuit and the third delay circuit have the same circuit structure.

[0017] The present invention also provides an SRAM setup and hold time test system, comprising a first delay calculation circuit and an SRAM setup and hold time test circuit structure as described in any one of the above items; the first delay calculation circuit is used to calculate the delay time of the first inverter of the synchronization circuit in the SRAM setup and hold time test circuit structure;

[0018] The first delay calculation circuit includes a first NAND gate, a first inverter unit and a first frequency divider; one input end of the first NAND gate is used to input a first start signal, and the other input end is used to connect to the output end of the first inverter unit;

[0019] The first inverter unit includes the first inverter, an input end of the first inverter unit is connected to an output end of the first NAND gate, and an output end of the first inverter unit is also connected to an input end of the first frequency divider.

[0020] Preferably, the first inverter unit further includes a plurality of third inverters of the same model as the first inverter, and the plurality of third inverters are connected in series with the first inverter.

[0021] Preferably, the number of the plurality of third inverters is 50-60.

[0022] The present invention also provides another SRAM setup and hold time test system, comprising a second delay calculation circuit and an SRAM setup and hold time test circuit structure as described in any one of the above items; the second delay calculation circuit is used to calculate the delay time of the second inverter of the synchronization circuit in the SRAM setup and hold time test circuit structure;

[0023] The second delay calculation circuit includes a second NAND gate, a second inverter unit and a second frequency divider; one input end of the second NAND gate is used to input a second start signal, and the other input end is used to connect to the output end of the second inverter unit;

[0024] The second inverter unit includes the second inverter, an input end of the second inverter unit is connected to an output end of the second NAND gate, and an output end of the second inverter unit is also connected to an input end of the second frequency divider.

[0025] Preferably, the second inverter unit further includes a plurality of fourth inverters of the same model as the second inverter, and the plurality of fourth inverters and the second inverter are connected in series.

[0026] The present invention also provides another SRAM setup and hold time test system, comprising a third delay calculation circuit and an SRAM setup and hold time test circuit structure as described in any one of the above items; the third delay calculation circuit is used to calculate the delay time of the first delay circuit, the second delay circuit, and the third delay circuit in the SRAM setup and hold time test circuit structure;

[0027] The third delay calculation circuit includes a third NAND gate and a third frequency divider; one input end of the third NAND gate is used to input a third start signal, and the other input end is used to connect the input end of the third frequency divider and the output end of the delay circuit under test, and the delay circuit under test is the first delay circuit, the second delay circuit or the third delay circuit; the output end of the third NAND gate is used to connect the input end of the delay circuit under test.

[0028] The present invention provides a SRAM setup and hold time test circuit structure and system, comprising a synchronization circuit, a first delay circuit, a second delay circuit, a third delay circuit and a test control circuit. The synchronization circuit can convert an initial clock signal into three signals: a synchronization clock signal, a synchronization address signal and a synchronization data signal. Since the synchronization clock signal, the synchronization address signal and the synchronization data signal have the same source, the technical problem that the error in the acquired SRAM setup and hold time due to delayed synchronization processing can be significantly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1The present invention is a schematic structural diagram of an SRAM setup hold time test circuit structure connected to an SRAM according to an embodiment of the present invention.

[0030] Figure 2 It is a structural schematic diagram of a synchronization circuit provided by an embodiment of the present invention.

[0031] Figure 3 It is a structural schematic diagram of a first delay calculation circuit provided by an embodiment of the present invention.

[0032] Figure 4 It is a structural schematic diagram of a second delay calculation circuit provided by an embodiment of the present invention.

[0033] Figure 5 It is a schematic diagram of the structure of a third delay calculation circuit provided by an embodiment of the present invention when in use.

[0034] Figure 6 The present invention is a simulation diagram of a synchronous clock signal, a delayed synchronous clock signal, a delayed synchronous address signal and a delayed synchronous data signal provided by an embodiment of the present invention.

[0035] The reference numerals are as follows:

[0036] Synchronous circuit-1, first delay circuit-2, second delay circuit-3, third delay circuit-4, test control circuit-5;

[0037] Clock signal input terminal-11, test signal switching input terminal-12, clock signal output terminal-13, address signal output terminal-14, data signal output terminal-15;

[0038] A first control terminal-21, a clock signal delay input terminal-22, and a clock signal delay output terminal-23;

[0039] Address signal delay input terminal-31, first selection input terminal-32, address signal delay output terminal-33;

[0040] Data signal delay input terminal-41, second selection input terminal-42, data signal delay output terminal-43;

[0041] Test port switching input terminal-51, second control terminal-52, first output terminal-53, second output terminal-54;

[0042] Clock input terminal-CK, address input terminal-A, data input terminal-D;

[0043] A first multiplexer-MUX1, a second multiplexer-MUX2, a third multiplexer-MUX3, a first inverter-101, a second inverter-102, and a buffer-103;

[0044] A first NAND gate-61, a first inverter unit-1011, and a first frequency divider-71;

[0045] A second NAND gate-62, a second inverter unit-1021, and a second frequency divider-72;

[0046] A third NAND gate-63, a delay circuit under test-234, and a third frequency divider-73;

[0047] Initial clock signal-CLK, high-low level switching signal-HL_SEL, synchronous clock signal-CK0, synchronous address signal-A0, synchronous data signal-D0, first control signal-CTRL1, second control signal-CTRL2, test port switching signal-AD_SEL, delayed synchronous clock signal-CK1, delayed synchronous address signal-A1, delayed synchronous data signal-D1, output terminal-Q of SRAM;

[0048] The first start signal-RO_EN1, the second start signal-RO_EN2, the third start signal-RO_EN3, the output signal of the first frequency divider-RO_OUT1, the output signal of the second frequency divider-RO_OUT2, the output signal of the third frequency divider-RO_OUT3, and the control signal-CTRL. DETAILED DESCRIPTION

[0049] In order to make the purpose, advantages and features of the present invention clearer, the following is a further detailed description of a SRAM setup hold time test circuit structure and system proposed by the present invention in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0050] In the description of the present invention, the terms "first", "second", etc. are added for the convenience of description and reference, and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined by the terms "first", "second", etc. may explicitly or implicitly include one or more of the features.

[0051] like Figure 1As shown, this embodiment provides an SRAM setup hold time test circuit structure, including a synchronization circuit 1, a first delay circuit 2, a second delay circuit 3, a third delay circuit 4 and a test control circuit 5; the synchronization circuit 1 includes a clock signal input terminal 11, a test signal switching input terminal 12, a clock signal output terminal 13, an address signal output terminal 14 and a data signal output terminal 15; the clock signal input terminal 11 is used to input an initial clock signal CLK; the test signal switching input terminal 12 (used to input a high-low level switching signal HL_SEL) is used to switch the direction of the tested signal; the synchronization circuit 1 is used to convert the initial clock signal CLK into a synchronization clock signal CK0 , synchronous address signal A0 and synchronous data signal D0; the first delay circuit 2 includes a first control terminal 21, a clock signal delay input terminal 22 and a clock signal delay output terminal 23; the first control terminal 21 is used to input a first control signal CTRL1, and the first control signal CTRL1 is used to control the delay time of the first delay circuit 2; the clock signal delay input terminal 22 is connected to the clock signal output terminal 13; the clock signal delay output terminal 23 is used to connect the clock input terminal CK of the SRAM; the first delay circuit 2 is used to delay the synchronous clock signal CK0; the second delay circuit 3 includes an address signal delay input terminal 31, a first selection input terminal 32 and address signal delay output terminal 33; the address signal delay input terminal 31 is connected to the address signal output terminal 14; the address signal delay output terminal 33 is used to connect the address input terminal A of the SRAM; the second delay circuit 3 is used to delay the synchronous address signal A0; the third delay circuit 4 includes a data signal delay input terminal 41, a second selection input terminal 42 and a data signal delay output terminal 43; the data signal delay input terminal 41 is connected to the data signal output terminal 15; the data signal delay output terminal 43 is used to connect the data input terminal D of the SRAM; the third delay circuit 4 is used to delay the synchronous data signal D0; the test control circuit Circuit 5 includes a test port switching input terminal 51, a second control terminal 52, a first output terminal 53 and a second output terminal 54; the test port switching input terminal 51 is used to switch the port of the SRAM under test; the second control terminal 52 is used to input the second control signal CTRL2, and the second control signal CTRL2 is used to control the delay time of the second delay circuit 3 and the third delay circuit 4; the first output terminal 53 is connected to the first selection input terminal 32; the second output terminal 54 is connected to the second selection input terminal 42; the test control circuit 5 is used to switch the port of the SRAM under test and the delay time of the second delay circuit 3 and the third delay circuit 4.

[0052] like Figure 1As shown, the synchronous clock signal CK0 is delayed by the first delay circuit 2 to obtain the delayed synchronous clock signal CK1; the synchronous address signal A0 is delayed by the second delay circuit 3 to obtain the delayed synchronous address signal A1; the synchronous data signal D0 is delayed by the third delay circuit 4 to obtain the delayed synchronous data signal D1; the address input terminal A of the SRAM refers to the address (address, address) input port (pin, port) of the SRAM, and the data input terminal D of the SRAM refers to the data (data, data) input port (pin, port) of the SRAM. The function of each signal can be defined by oneself, for example, when the high-low level switching signal HL_SEL is 0, that is, low level, the test is the setup and hold time of 0; when the high-low level switching signal HL_SEL is 1, that is, high level, the test is the setup and hold time of 1; the code (code) of the first control signal CTRL1 is transmitted to the first delay circuit 2 through the first control terminal 21, thereby adjusting the delay time of the first delay circuit 2; when the test port switching signal AD_SEL is 0, the address input terminal A of the SRAM is tested, and the code of the second control signal CTRL2 is transmitted to the second delay circuit 3 through the first output terminal 53, thereby adjusting the delay time of the second delay circuit 3, at this time the delay time of the third delay circuit 4 is set to a fixed value of a longer delay time; when the test port switching signal AD_SEL is 1, the data input terminal D of the SRAM is tested, and the code of the second control signal CTRL2 is transmitted to the third delay circuit 4 through the second output terminal 54, thereby adjusting the delay time of the third delay circuit 4, at this time the delay time of the second delay circuit 3 is set to a fixed value of a longer delay time.

[0053] The present embodiment provides a SRAM setup and hold time test circuit structure, comprising a synchronization circuit 1, a first delay circuit 2, a second delay circuit 3, a third delay circuit 4 and a test control circuit 5. The synchronization circuit 1 can convert an initial clock signal CLK into three signals: a synchronization clock signal CK0, a synchronization address signal A0 and a synchronization data signal D0. Since the synchronization clock signal CK0, the synchronization address signal A0 and the synchronization data signal D0 have the same source, the technical problem of errors in the acquired SRAM setup and hold time due to delayed synchronization processing can be significantly reduced.

[0054] Preferably, Figure 1 and Figure 2As shown, the synchronization circuit 1 includes a first multiplexer MUX1, a second multiplexer MUX2, a third multiplexer MUX3, a first inverter 101 and a second inverter 102; the first multiplexer MUX1 includes two input interfaces A[0] and A[1], a test signal switching input interface (for inputting a high-low level switching signal HL_SEL) and an output interface (for outputting a synchronization clock signal CK0); the two input interfaces A[0] and A[1] of the first multiplexer MUX1 are respectively used to input the initial clock signal CLK; the test signal switching input interface of the first multiplexer MUX1 is used to select an input interface A[0] or A[1] to form a path with the output interface; the second multiplexer MUX2 includes two input interfaces A[0] and A[1], a test signal switching input interface (for inputting a high-low level switching signal HL_SEL) and an output interface (for outputting a synchronization address signal A0); the second multiplexer MUX1 includes two input interfaces A[0] and A[1], a test signal switching input interface (for inputting a high-low level switching signal HL_SEL) and an output interface (for outputting a synchronization address signal A0); One input interface of the multiplexer MUX2, such as A[1], is used to input the initial clock signal CLK, and the other input interface, such as A[0], inputs the initial clock signal CLK through the first inverter 101; the test signal switching input interface of the second multiplexer MUX2 is used to select a signal input interface A[0] or A[1] to form a path with the output interface; the third multiplexer MUX3 includes two input interfaces A[0] and A[1], a test signal switching input interface (for inputting a high-low level switching signal HL_SEL) and an output interface (for outputting a synchronous data signal D0); one input interface of the third multiplexer MUX3, such as A[1], is used to input the initial clock signal CLK, and the other input interface, such as A[0], inputs the initial clock signal CLK through the second inverter 102; the test signal switching input interface of the third multiplexer MUX3 is used to select an input interface A[0] or A[1] to form a path with the output interface.

[0055] In the synchronization circuit 1 provided in this embodiment, one of the two input interfaces of the second multiplexer MUX2 is connected to the first inverter 101, and the other is not connected to the first inverter 101. Its output interface selects one of the signals input from the two input interfaces as the output, so that two inverted signals can be output; similarly, the output interface of the third multiplexer MUX3 can also output two inverted signals, so that the address input terminal A and the data input terminal D of the SRAM can both input high-level or low-level signals, thereby meeting the needs of the SRAM setup and hold time test. When the second multiplexer MUX2 and the third multiplexer MUX3 select the A[0] path, there is one more inverter than the first multiplexer MUX1, and the resulting delay can be measured by Figure 3 and Figure 4The delay calculation circuit shown calculates and subtracts or adds, so it can be considered that the synchronous clock signal CK0, the synchronous address signal A0, and the synchronous data signal D0 are completely synchronized.

[0056] In other embodiments, the first inverter 101 and the second inverter 102 can be replaced by devices such as NAND gates; when one input terminal of the NAND gate is grounded and the other input terminal is connected to a signal that needs to be inverted, it can also function as an inverter.

[0057] Preferably, Figure 2 As shown, the synchronization circuit 1 further includes a buffer 103, the input end of the buffer 103 is used to input the initial clock signal CLK, and the node obtained by connecting the input interface of the first multiplexer MUX1, the input end of the first inverter 101 and the input end of the second inverter 102 in parallel is connected to the output end of the buffer 103. The buffer 103 can enhance the stability of the signal and improve the transmission quality of the signal.

[0058] Preferably, Figure 1 As shown, the circuit structures of the first delay circuit 2, the second delay circuit 3 and the third delay circuit 4 are the same, which can reduce the delay error caused by the first delay circuit 2, the second delay circuit 3 and the third delay circuit 4.

[0059] like Figure 1~Figure 3 As shown, based on the same technical concept as the above-mentioned SRAM setup and hold time test system, this embodiment also provides an SRAM setup and hold time test system, including a first delay calculation circuit and an SRAM setup and hold time test circuit structure described in any one of the above items; the first delay calculation circuit is used to calculate the delay time of the first inverter 101 of the synchronization circuit 1 in the SRAM setup and hold time test circuit structure; the first delay calculation circuit includes a first NAND gate 61, a first inverter unit 1011 and a first frequency divider 71; one input end of the first NAND gate 61 is used to input a first start signal RO_EN1 (high level is valid), and the other input end is used to connect the output end of the first inverter unit 1011; the first inverter unit 1011 includes the first inverter 101, the input end of the first inverter unit 1011 is connected to the output end of the first NAND gate 61, and the output end of the first inverter unit 1011 is also connected to the input end of the first frequency divider 71. Figure 3 RO_OUT1 in represents the output signal of the first frequency divider 71 .

[0060] In the solution provided in this embodiment, assuming that the frequency division multiple of the first frequency divider 71 is a1 and the frequency of RO_OUT1 is f1, the delay time d1 of the first inverter unit 1011 is 1 / (2a1f1), and the delay time calculated in this way is very accurate. If the first inverter unit 1011 includes only one first inverter 101, the delay time of the first inverter 101 is 1 / (2a1f1). If the first inverter unit 1011 also includes (N-1) third inverters of the same model as the first inverter 101, and the plurality of third inverters are connected in series with the first inverter 101, and N is a positive integer greater than 1, the delay time of the first inverter 101 is 1 / (2a1f1N).

[0061] Preferably, Figure 2 and Figure 3 As shown, the first inverter unit 1011 further includes a plurality of third inverters of the same model as the first inverter 101, and the plurality of third inverters are connected in series with the first inverter 101. By setting the plurality of third inverters in series with the first inverter 101 and then testing the delay time, the accuracy of the test can be improved, and the test result can be prevented from being affected by the process deviation of a single first inverter 101.

[0062] Preferably, reference Figure 3 As shown, the number of the plurality of third inverters is 50 to 60. Providing an appropriate number of third inverters can improve the accuracy of the test result and reduce the test cost.

[0063] like Figure 1 , Figure 2 and Figure 4 As shown, based on the same technical concept as the above-mentioned SRAM setup and hold time test system, this embodiment also provides another SRAM setup and hold time test system, including a second delay calculation circuit and an SRAM setup and hold time test circuit structure described in any one of the above items; the second delay calculation circuit is used to calculate the delay time of the second inverter 102 of the synchronization circuit 1 in the SRAM setup and hold time test circuit structure; the second delay calculation circuit includes a second NAND gate 62, a second inverter unit 1021 and a second frequency divider 72; one input end of the second NAND gate 62 is used to input a second start signal RO_EN2 (high level is valid), and the other input end is used to connect the output end of the second inverter unit 1021; the second inverter unit 1021 includes the second inverter 102, the input end of the second inverter unit 1021 is connected to the output end of the second NAND gate 62, and the output end of the second inverter unit 1021 is also connected to the input end of the second frequency divider 72. Figure 4 RO_OUT2 in represents the output signal of the second frequency divider 72 .

[0064] In the solution provided in this embodiment, assuming that the frequency division multiple of the second frequency divider 72 is a2, and the frequency of RO_OUT2 is f2, the delay time d2 of the second inverter unit 1021 is 1 / (2a2f2), and the delay time calculated in this way is very accurate. If the second inverter unit 1021 includes only one second inverter 102, the delay time of the second inverter 102 is 1 / (2a2f2). If the second inverter unit 1021 also includes (N-1) fourth inverters of the same model as the second inverter 102, and the plurality of fourth inverters are connected in series with the second inverter 102, and N is a positive integer greater than 1, the delay time of the second inverter 102 is 1 / (2a2f2N). Figure 3 and Figure 4 The principle is the same as that of the first inverter 101 and the second inverter 102. If the first inverter 101 and the second inverter 102 are of the same type, they can be directly used. Figure 3 The calculated delay time of the first inverter 101 is used as the delay time of the second inverter 102 .

[0065] Preferably, Figure 4 As shown, the second inverter unit 1021 further includes a plurality of fourth inverters of the same model as the second inverter 102, and the plurality of fourth inverters are connected in series with the second inverter 102. By setting a plurality of fourth inverters in series with the second inverter 102 and then testing the delay time, the accuracy of the test can be improved, and the test result can be prevented from being affected by the process deviation of a single second inverter 102.

[0066] like Figure 1 and Figure 5 As shown, based on the same technical concept as the above-mentioned SRAM setup and hold time test system, this embodiment also provides another SRAM setup and hold time test system, including a third delay calculation circuit and an SRAM setup and hold time test circuit structure described in any one of the above items; the third delay calculation circuit is used to calculate the delay time of the first delay circuit 2, the second delay circuit 3, and the third delay circuit 4 in the SRAM setup and hold time test circuit structure; the third delay calculation circuit includes a third NAND gate 63 and a third frequency divider 73; one input end of the third NAND gate 63 is used to input a third start signal RO_EN3 (high level is valid), and the other input end is used to connect the input end of the third frequency divider 73 and the output end of the delay circuit 234 under test, and the delay circuit 234 under test is the first delay circuit 2, the second delay circuit 3 or the third delay circuit 4; the output end of the third NAND gate 63 is used to connect the input end of the delay circuit 234 under test. Figure 5The control signal CTRL in the figure represents the first control signal CTRL1 or the second control signal CTRL2; when the delay circuit 234 under test is the first delay circuit 2, the control signal CTRL is the first control signal CTRL1; when the delay circuit 234 under test is the second delay circuit 3 or the third delay circuit 4, the control signal CTRL is the second control signal CTRL2; RO_OUT3 represents the output signal of the third frequency divider 73.

[0067] In the solution provided by this embodiment, assuming that the frequency division multiple of the third frequency divider 73 is a3, and the frequency of RO_OUT3 is f3, then the delay time of the control signal CTRL in the measured delay circuit 234 is d3=1 / (2a3f3), and the delay time calculated in this way is very accurate. When the present invention is actually used, the circuit structures of the first delay circuit 2, the second delay circuit 3 and the third delay circuit 4 are preferably the same structure, and the first control signal CTRL1 and the second control signal CTRL2 are preferably the same signal. At this time, as long as one of the first delay circuit 2, the second delay circuit 3 and the third delay circuit 4 is connected to the third delay calculation circuit, the control signal CTRL selects the first control signal CTRL1 or the second control signal CTRL2, and the delay time calculated in this way can be used as the delay time of the first control signal CTRL1 in the first delay circuit 2, and the delay time of the second control signal CTRL2 in the second delay circuit 3 and the third delay circuit 4.

[0068] refer to Figure 1 to Figure 6 As shown, it is assumed that the delay time of the first delay circuit 2 is t1, the delay time of the second delay circuit 3 is t2, the delay time of the third delay circuit 4 is t3, and the delay time of the first inverter 101 and the second inverter 102 are both t4. When performing the setup and hold time test of the SRAM address input terminal A, the test address input terminal A can be selected by the test port switching signal AD_SEL. At this time, the delay of the data input terminal D is very large, so its setup and hold time must be satisfied. When the setup and hold time of the address input terminal A is not sufficient, it will cause the SRAM output result, that is, the data output by the output terminal Q of the SRAM, to be wrong. Therefore, the critical value that just meets the SRAM output result is selected as the minimum setup and hold time.

[0069] The establishment time of the address input terminal A for the high level, i.e. 1, is equal to Figure 5 The circuit shown calculates the delay time t1 of the first delay circuit 2 minus the delay time t2 of the second delay circuit 3 when the address input terminal A is established at a high level, that is, the establishment time t as1 =t1-t2.

[0070] The establishment time of the address input terminal A to the low level, i.e. 0, is equal to Figure 5 The circuit shown calculates the delay time t1 of the first delay circuit 2 minus the delay time t2 of the second delay circuit 3 minus the delay time t2 of the first delay circuit 2 minus the delay time t1 of the second delay circuit 3 minus the delay time t2 of the first delay circuit 2 minus the delay time t2 of the second delay circuit 3 minus the delay time t1 of the first delay circuit 2 minus the delay time t2 of the second delay circuit 3 minus the delay Figure 3 The delay time t4 of the single first inverter 101 calculated by the circuit shown, that is, the establishment time t as0 =t1-t2-t4.

[0071] The holding time of the address input terminal A for the high level, i.e. 1, is equal to Figure 5 The circuit shown calculates the delay time t2 of the second delay circuit 3 minus the delay time t1 of the first delay circuit 2 plus the delay time t2 of the second delay circuit 3 minus the delay time t1 of the first delay circuit 2 ... Figure 3 The delay time t4 of the single first inverter 101 calculated by the circuit shown, that is, the holding time t of the address input terminal A to the high level ah1 =t2-t1+t4.

[0072] The holding time of the address input terminal A for the low level, i.e. 0, is equal to Figure 5 The circuit shown calculates the delay time t2 of the second delay circuit 3 minus the delay time t1 of the first delay circuit 2 when the address input terminal A is kept at a low level, that is, the holding time t ah0 =t2-t1.

[0073] The calculation method of the setup and hold time of the data input terminal D and the address input terminal A is the same. The setup time t ds1 =t1-t3, the establishment time for low level t ds0 =t1-t3-t4, holding time for high level t dh1 =t3-t1+t4, holding time for low level t dh0 =t3-t1.

[0074] In summary, the present invention provides a SRAM setup and hold time test circuit structure and system, including a synchronization circuit 1, a first delay circuit 2, a second delay circuit 3, a third delay circuit 4 and a test control circuit 5. The synchronization circuit 1 can convert an initial clock signal CLK into three signals: a synchronization clock signal CK0, a synchronization address signal A0 and a synchronization data signal D0. Since the synchronization clock signal CK0, the synchronization address signal A0 and the synchronization data signal D0 are of the same source, the technical problem of errors in the acquired SRAM setup and hold time due to delayed synchronization processing can be significantly reduced.

[0075] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A SRAM setup hold time test circuit structure, characterized in that: It includes a synchronization circuit, a first delay circuit, a second delay circuit, a third delay circuit and a test control circuit; The synchronization circuit comprises a clock signal input terminal, a test signal switching input terminal, a clock signal output terminal, an address signal output terminal and a data signal output terminal; the clock signal input terminal is used to input an initial clock signal; the test signal switching input terminal is used to switch the direction of the tested signal; the synchronization circuit is used to convert the initial clock signal into a synchronous clock signal, a synchronous address signal and a synchronous data signal; The first delay circuit includes a first control terminal, a clock signal delay input terminal and a clock signal delay output terminal; the first control terminal is used to input a first control signal, and the first control signal is used to control the delay time of the first delay circuit; the clock signal delay input terminal is connected to the clock signal output terminal; the clock signal delay output terminal is used to connect to the clock input terminal of the SRAM; the first delay circuit is used to delay the synchronous clock signal; The second delay circuit includes an address signal delay input terminal, a first selection input terminal and an address signal delay output terminal; the address signal delay input terminal is connected to the address signal output terminal; the address signal delay output terminal is used to connect to the address input terminal of the SRAM; the second delay circuit is used to delay the synchronous address signal; The third delay circuit comprises a data signal delay input terminal, a second selection input terminal and a data signal delay output terminal; the data signal delay input terminal is connected to the data signal output terminal; the data signal delay output terminal is used to connect to the data input terminal of the SRAM; the third delay circuit is used to delay the synchronous data signal; The test control circuit includes a test port switching input terminal, a second control terminal, a first output terminal and a second output terminal; the test port switching input terminal is used to switch the port of the SRAM under test; the second control terminal is used to input a second control signal, and the second control signal is used to control the delay time of the second delay circuit and the third delay circuit; the first output terminal is connected to the first selection input terminal; the second output terminal is connected to the second selection input terminal; the test control circuit is used to switch the port of the SRAM under test and the delay time of the second delay circuit and the third delay circuit.

2. A SRAM setup hold time test circuit structure as claimed in claim 1, characterized in that: The synchronization circuit includes a first multiplexer, a second multiplexer, a third multiplexer, a first inverter, and a second inverter; The first multiplexer includes two input interfaces, a test signal switching input interface and an output interface; the two input interfaces of the first multiplexer are respectively used to input the initial clock signal; The test signal switching input interface of the first multiplexer is used to select an input interface and an output interface to form a path; The second multiplexer includes two input interfaces, a test signal switching input interface and an output interface; one input interface of the second multiplexer is used to input the initial clock signal, and the other input interface inputs the initial clock signal through the first inverter; The test signal switching input interface of the second multiplexer is used to select an input interface and an output interface to form a path; The third multiplexer includes two input interfaces, a test signal switching input interface and an output interface; one input interface of the third multiplexer is used to input the initial clock signal, and the other input interface inputs the initial clock signal through the second inverter; The test signal switching input interface of the third multiplexer is used to select an input interface to form a path with the output interface.

3. A SRAM setup hold time test circuit structure as claimed in claim 2, characterized in that: The synchronization circuit also includes a buffer, the input end of the buffer is used to input the initial clock signal, and the node obtained by connecting the input interface of the first multiplexer, the input end of the first inverter and the input end of the second inverter in parallel is connected to the output end of the buffer.

4. A SRAM setup hold time test circuit structure as claimed in claim 1, characterized in that: The first delay circuit, the second delay circuit and the third delay circuit have the same circuit structure.

5. A SRAM setup and hold time test system, characterized in that: The invention comprises a first delay calculation circuit and an SRAM setup and hold time test circuit structure as claimed in any one of claims 1 to 4; the first delay calculation circuit is used to calculate the delay time of the first inverter of the synchronization circuit in the SRAM setup and hold time test circuit structure; The first delay calculation circuit includes a first NAND gate, a first inverter unit and a first frequency divider; one input end of the first NAND gate is used to input a first start signal, and the other input end is used to connect to the output end of the first inverter unit; The first inverter unit includes the first inverter, an input end of the first inverter unit is connected to an output end of the first NAND gate, and an output end of the first inverter unit is also connected to an input end of the first frequency divider.

6. A SRAM setup and hold time test system as claimed in claim 5, characterized in that: The first inverter unit further includes a plurality of third inverters of the same model as the first inverter, and the plurality of third inverters are connected in series with the first inverter.

7. A SRAM setup and hold time test system as claimed in claim 6, characterized in that: The number of the plurality of third inverters is 50-60.

8. A SRAM setup and hold time test system, characterized in that: The invention comprises a second delay calculation circuit and an SRAM setup and hold time test circuit structure as claimed in any one of claims 1 to 4; the second delay calculation circuit is used to calculate the delay time of the second inverter of the synchronization circuit in the SRAM setup and hold time test circuit structure; The second delay calculation circuit includes a second NAND gate, a second inverter unit and a second frequency divider; one input end of the second NAND gate is used to input a second start signal, and the other input end is used to connect to the output end of the second inverter unit; The second inverter unit includes the second inverter, an input end of the second inverter unit is connected to an output end of the second NAND gate, and an output end of the second inverter unit is also connected to an input end of the second frequency divider.

9. A SRAM setup and hold time test system as claimed in claim 8, characterized in that: The second inverter unit further includes a plurality of fourth inverters of the same model as the second inverter, and the plurality of fourth inverters are connected in series with the second inverter.

10. A SRAM setup and hold time test system, characterized in that: A method for testing a SRAM setup and hold time comprising a third delay calculation circuit and a SRAM setup and hold time test circuit structure according to any one of claims 1 to 4; wherein the third delay calculation circuit is used to calculate the delay time of the first delay circuit, the second delay circuit, and the third delay circuit in the SRAM setup and hold time test circuit structure; The third delay calculation circuit includes a third NAND gate and a third frequency divider; one input end of the third NAND gate is used to input a third start signal, and the other input end is used to connect the input end of the third frequency divider and the output end of the delay circuit under test, and the delay circuit under test is the first delay circuit, the second delay circuit or the third delay circuit; the output end of the third NAND gate is used to connect the input end of the delay circuit under test.

Images