Packaging structure and forming method thereof

Abstract

The invention discloses a packaging structure and a forming method thereof, and the method comprises the steps: providing a first wafer which comprises a first conductive bump and a first solder ball disposed on the first conductive bump, and the first conductive bump is electrically connected with the first solder ball; forming a heat conduction layer covering the first wafer, wherein the heat conduction layer covers the first conductive bumps and the first solder balls; forming an opening for exposing the first solder ball in the heat conduction layer; providing a second wafer, wherein the second wafer comprises a second conductive bump; and placing the first wafer on the second wafer for welding so as to bond the first solder balls with the second conductive bumps to form a stacked wafer. By forming the heat conduction layer covering the first wafer and forming the opening for exposing the first solder ball in the heat conduction layer, the reliability and the heat dissipation performance of the packaging structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor packaging, and in particular to a packaging structure and a method for forming the same. Background Art

[0002] As the demand for smaller size, more functions, high reliability and low cost increases, the innovation of semiconductor advanced packaging technology becomes particularly important. Chip stacking technology can stack multiple chips vertically together to improve the performance and function of the chip, realize the modularization of functions, improve the overall performance of the system, and save space and power consumption.

[0003] Through Silicon Via (TSV) technology is an advanced packaging technology that achieves vertical electrical interconnection of silicon vias by making vertical conductions between chips and wafers. TSV technology achieves vertical electrical interconnection of silicon vias by filling conductive materials such as copper, tungsten, and polysilicon. It is the fourth generation packaging technology after wire bonding, TAB, and flip chip (FC). The significant advantage of TSV technology is that it can reduce the interconnection length, signal delay, and capacitance / inductance through vertical interconnection, achieve low power consumption between chips, high-speed communication, increase bandwidth, and realize miniaturization of device integration. In 2.5D and 3D IC packaging, TSV technology is a key enabling technology that enables semiconductor dies and wafers to be stacked together with higher density interconnections.

[0004] The stacked chips need to be bonded and reinforced with non-conductive film (NCF). Since it does not contain conductive fillers, it will not cause short circuits at the welding points. At the same time, it provides good physical protection and stress buffering, enhancing the reliability of the device. However, during the welding process of the stacked chips, some adhesive film will inevitably remain, resulting in solder voids and solder extrusion, affecting the reliability of the stacked chips. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a packaging structure and a method for forming the same, thereby improving the reliability and heat dissipation performance of the packaging structure.

[0006] To solve the above problems, an embodiment of the present invention provides a method for forming a packaging structure, comprising: providing a first chip, the first chip comprising a first conductive bump and a first solder ball arranged on the first conductive bump, the first conductive bump being electrically connected to the first solder ball; forming a thermal conductive layer covering the first chip, the thermal conductive layer encapsulating the first conductive bump and the first solder ball; forming an opening in the thermal conductive layer to expose the first solder ball; providing a second chip, the second chip comprising a second conductive bump; placing the first chip on the second chip for welding, so as to join the first solder ball with the second conductive bump to form a stacked chip.

[0007] Optionally, the process of forming the opening also includes: forming a groove in the thermal conductive layer on the side of the first solder ball, the groove including a comb handle groove extending along a first direction and comb tooth grooves arranged in parallel and spaced apart along a second direction, the comb handle groove is connected to the comb tooth grooves, and the comb tooth grooves expose the side wall of the first solder ball, and the first direction is perpendicular to the second direction.

[0008] Optionally, the groove is formed on one side of the first solder ball; or, the groove is formed on both sides of the first solder ball.

[0009] Optionally, when the grooves are formed on both sides of the first solder ball, the grooves between adjacent first solder balls share a comb handle groove.

[0010] Optionally, the width of the comb tooth groove in the first direction is 0.5 microns to 1.5 microns; the width of the comb handle groove in the second direction is 1 micron to 3 microns.

[0011] Optionally, the process of forming the opening includes a laser process.

[0012] Optionally, in the step of forming the heat-conducting layer, the material of the heat-conducting layer includes one or more of epoxy resin, a mixture of phenolic resin and silicon dioxide, a mixture of phenolic resin and aluminum oxide, and a mixture of phenolic resin and boron nitride.

[0013] Optionally, in the step of providing a first chip, the first chip also includes a first chip, a first dielectric layer formed on the first chip, and a first redistribution layer of one or more layers stacked in the first dielectric layer, and the topmost layer of the first redistribution layer is electrically connected to the first conductive bump.

[0014] Optionally, a first interconnection through-hole structure penetrating the first chip is also formed in the first chip of the first wafer, and the first interconnection through-hole structure is electrically connected to the first redistribution layer of the bottom layer; when multiple layers of the first redistribution layers are arranged in the first dielectric layer, a second interconnection through-hole structure is formed in the first dielectric layer between adjacent first redistribution layers, and the second interconnection through-hole structure is electrically connected to adjacent first redistribution layers.

[0015] Optionally, the process of placing the first wafer on the second wafer for welding to join the first solder ball with the second conductive bump includes a high temperature and high pressure welding process or a high temperature reflow process.

[0016] Optionally, in the step of providing a second chip, the second chip also includes a second chip, a second dielectric layer formed on the top surface of the second chip, a second rewiring layer of one or more layers stacked in the second dielectric layer, a third dielectric layer formed on the bottom surface of the second chip, a third rewiring layer of one or more layers stacked in the third dielectric layer, a third conductive bump protruding from the surface of the third dielectric layer and electrically connected to the third rewiring layer, and a second solder ball formed on the third conductive bump, wherein the second conductive bump is electrically connected to the topmost layer of the second rewiring layer.

[0017] Optionally, after forming the stacked wafer, the method for forming the packaging structure further includes: mounting the stacked wafer on a substrate.

[0018] Optionally, the process of mounting the stacked wafers on the substrate includes a hot pressing process or a high-temperature reflow process.

[0019] Correspondingly, an embodiment of the present invention also provides a packaging structure, including: a substrate; a stacked chip mounted on the substrate, the stacked chip including a second chip and a first chip located above the second chip and welded to the second chip, the first chip including a first conductive bump and a first solder ball arranged on the first conductive bump, the first conductive bump is electrically connected to the first solder ball, the second chip including a second conductive bump, the second conductive bump is electrically connected to the first solder ball, and the first solder ball is bonded to the second conductive bump; a thermal conductive layer located between the first chip and the second chip, and covering the side walls of the first conductive bump, the second conductive bump and the first solder ball.

[0020] Optionally, the packaging structure also includes: a groove located in the heat conductive layer on the side of the first solder ball, the groove including a comb handle groove extending along a first direction and comb tooth grooves arranged in parallel and spaced apart along a second direction, the comb handle groove being connected to the comb tooth grooves, and the comb tooth grooves exposing the side walls of the first solder ball, and the first direction is perpendicular to the second direction.

[0021] Optionally, the groove is arranged on one side of the first solder ball; or, the groove is arranged on both sides of the first solder ball.

[0022] Optionally, when the grooves are located on both sides of the first solder ball, the grooves between adjacent first solder balls share a comb handle groove.

[0023] Optionally, the width of the comb tooth groove in the first direction is 0.5 microns to 1.5 microns; the width of the comb handle groove in the second direction is 1 micron to 3 microns.

[0024] Optionally, the material of the heat-conducting layer includes one or more of epoxy resin, a mixture of phenolic resin and silicon dioxide, a mixture of phenolic resin and aluminum oxide, and a mixture of phenolic resin and boron nitride.

[0025] Optionally, the first chip also includes: a first chip; a first dielectric layer, located on the first chip; a first rewiring layer of one or more stacked layers, located in the first dielectric layer, and the topmost first rewiring layer is electrically connected to the first conductive bump; a first interconnection through-hole structure, located in the first chip and passing through the first chip, and the first interconnection through-hole structure is electrically connected to the bottommost first rewiring layer; when the number of layers of the first rewiring layer is multiple layers, the first chip also includes: a second interconnection through-hole structure, located in the first dielectric layer between adjacent first rewiring layers, and the second interconnection through-hole structure is electrically connected to adjacent first rewiring layers.

[0026] Optionally, the second wafer also includes: a second chip; a second dielectric layer located on the top surface of the second chip; one or more stacked second rewiring layers located in the second dielectric layer, and the topmost second rewiring layer is electrically connected to the second conductive bump; a third dielectric layer located on the bottom surface of the second chip; one or more stacked third rewiring layers located in the third dielectric layer; a third conductive bump protruding from the surface of the third dielectric layer and electrically connected to the third rewiring layer; a second solder ball located on the third conductive bump; a third interconnection via located in the second chip and passing through the second chip, and the third interconnection via is electrically connected to the second rewiring layer and the third rewiring layer.

[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0028] In the method for forming a packaging structure provided by an embodiment of the present invention, a heat-conducting layer covering the first chip is formed, the heat-conducting layer covers the first conductive bump and the first solder ball, and an opening exposing the first solder ball is formed in the heat-conducting layer. By forming the opening, the solder area of ​​each first solder ball can be exposed, thereby reducing the probability of residual adhesive film on the surface of the first solder ball. In the subsequent process of placing the first chip on the second chip for welding to join the first solder ball with the second conductive bump to form a stacked chip, the risk of voids or solder extrusion during welding between the first solder ball and the second conductive bump can be reduced. At the same time, by forming the heat-conducting layer covering the first chip, the heat-conducting layer has a high heat dissipation characteristic, which can significantly improve the heat dissipation performance of the packaging structure. In summary, by forming the heat-conducting layer covering the first chip and forming the opening exposing the first solder ball in the heat-conducting layer, the reliability and heat dissipation performance of the packaging structure can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 7 is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a packaging structure of the present invention;

[0030] Figures 8 to 10 is a schematic structural diagram corresponding to each step in the second embodiment of the method for forming a packaging structure of the present invention;

[0031] Fig.11 is a structural schematic diagram corresponding to the first embodiment of the packaging structure of the present invention;

[0032] Fig.12 It is a structural schematic diagram corresponding to the second embodiment of the packaging structure of the present invention. DETAILED DESCRIPTION

[0033] As can be seen from the background technology, at present, multiple stacked chips need to be bonded and reinforced by non-conductive film (NCF). Because it does not contain conductive fillers, it will not cause short circuits at the welding points. At the same time, it provides good physical protection and stress buffering, and enhances the reliability of the device. However, in the process of welding stacked chips, due to the low glass transition temperature (Tg) of NCF and the high viscosity of NCF, some adhesive film will inevitably remain, and the bubbles generated by the pyrolysis of organic matter in the flux cannot overflow in time, resulting in solder voids and solder extrusion, which affects the reliability of the stacked chips.

[0034] In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a packaging structure, including: providing a first chip, the first chip including a first conductive bump and a first solder ball arranged on the first conductive bump, the first conductive bump being electrically connected to the first solder ball; forming a thermal conductive layer covering the first chip, the thermal conductive layer encapsulating the first conductive bump and the first solder ball; forming an opening in the thermal conductive layer to expose the first solder ball; providing a second chip, the second chip including a second conductive bump; placing the first chip on the second chip for welding to join the first solder ball with the second conductive bump to form a stacked chip.

[0035] In the method for forming a packaging structure provided by an embodiment of the present invention, a heat-conducting layer covering the first chip is formed, the heat-conducting layer covers the first conductive bump and the first solder ball, and an opening exposing the first solder ball is formed in the heat-conducting layer. By forming the opening, the solder area of ​​each first solder ball can be exposed, thereby reducing the probability of residual adhesive film on the surface of the first solder ball. In the subsequent process of placing the first chip on the second chip for welding to join the first solder ball with the second conductive bump to form a stacked chip, the risk of voids or solder extrusion during welding between the first solder ball and the second conductive bump can be reduced. At the same time, by forming the heat-conducting layer covering the first chip, the heat-conducting layer has a high heat dissipation characteristic, which can significantly improve the heat dissipation performance of the packaging structure. In summary, by forming the heat-conducting layer covering the first chip and forming the opening exposing the first solder ball in the heat-conducting layer, the reliability and heat dissipation performance of the packaging structure can be improved.

[0036] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figures 1 to 7 It is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a packaging structure of the present invention.

[0038] refer to Figure 1 , providing a first chip 100, wherein the first chip 100 includes a first conductive bump 101 and a first solder ball 103 disposed on the first conductive bump 101, and the first conductive bump 101 is electrically connected to the first solder ball 103.

[0039] Specifically, the first wafer 100 is used to be welded with a second wafer provided subsequently to form a stacked wafer.

[0040] It should be noted that the first conductive bumps 101 can electrically connect the first chip 100 to an external circuit structure (for example, a second chip provided subsequently), and the first conductive bumps 101 are distributed on the surface of the first chip 100, thereby improving the connection density of the first chip 100. At the same time, the first conductive bumps 101 also provide a bearing surface for setting the first solder ball 103, which helps the first solder ball 103 to form a stable electrical connection with the first conductive bumps 101.

[0041] As an example, the material of the first conductive bump 101 includes one or more of copper, nickel, tin and silver.

[0042] Specifically, the first solder ball 103 is used to be welded with the second conductive bump on the second chip provided subsequently, so that the first chip 100 can realize electrical signal transmission with the second chip. At the same time, the welding of the first solder ball 103 with the second conductive bump also improves the bonding force between the first chip 100 and the second chip, making it less likely for the first chip 100 to fall off from the second chip, thereby improving the structural reliability of the packaging structure.

[0043] As an example, the material of the first solder ball 103 includes one or more of a tin-silver alloy, a gold-tin alloy, and a tin-lead alloy.

[0044] In this embodiment, the first chip 100 also includes a first chip 105, a first dielectric layer 108 formed on the first chip 105, and a first redistribution layer 110 (RDL) of one or more stacked layers arranged in the first dielectric layer 108, and the topmost first redistribution layer 110 is electrically connected to the first conductive bump 101.

[0045] Specifically, the first chip 105 is a chip with a specific function. Specifically, the type of the first chip 105 is determined according to actual functional requirements or application scenarios. For example, the first chip 105 includes one or more of a radio frequency chip, a memory chip, an ASIC (Application-Specific Integrated Circuit) chip, a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip, and an FPGA (Field-Programmable Gate Array) chip.

[0046] In other embodiments, according to actual process requirements, the first chip 105 may also be other chips.

[0047] Specifically, the first dielectric layer 108 is used to electrically isolate the first redistribution layers 110 , thereby reducing the risk of electrical leakage between adjacent first redistribution layers 110 .

[0048] As an example, the material of the first dielectric layer 108 includes one or more of polyimide resin, epoxy resin, phenolic resin, and bismaleimide triazine resin.

[0049] It should be noted that the first redistribution layer 110 can reallocate the input ports and output ports on the first chip 105, thereby improving the flexibility of electrical signal connection, and can reduce the path length of electrical signal transmission and reduce electrical signal transmission delay.

[0050] It should also be noted that the topmost first rewiring layer 110 is electrically connected to the first conductive bump 101 , so that one or more rewiring layers can be electrically connected to an external circuit structure through the first conductive bump 101 .

[0051] As an example, Figure 1 As shown, a first redistribution layer 110 of a 2-layer stack is shown.

[0052] In this embodiment, the material of the first redistribution layer 110 includes one or more of copper, aluminum and silver.

[0053] In this embodiment, a first interconnection through-via structure 106 (TSV) penetrating the first chip 105 is further formed in the first chip 105 of the first wafer 100 . The first interconnection through-via structure 106 is electrically connected to the first redistribution layer 110 at the bottom layer.

[0054] Specifically, by forming the first interconnection through-hole structure 106 penetrating the first chip 105 , after the first wafer 100 is welded with the subsequent second wafer to form a stacked wafer, the density of the packaging structure can be improved and the transmission of electrical signals can be accelerated.

[0055] In this embodiment, the material of the first interconnection via structure 106 includes one or more of copper, tungsten and polysilicon.

[0056] In this embodiment, when multiple layers of the first redistribution layers 110 are arranged in the first dielectric layer 108 , a second interconnection via structure 111 is formed in the first dielectric layer 108 between adjacent first redistribution layers 110 , and the second interconnection via structure 111 is electrically connected to the adjacent first redistribution layers 110 .

[0057] It should be noted that multiple layers of the first redistribution layers 110 are provided in the first dielectric layer 108 to meet the requirements of high-density integration.

[0058] In this embodiment, the material of the second interconnection via structure 111 includes copper.

[0059] refer to Figure 2 , forming a heat conducting layer 120 covering the first wafer 100 , wherein the heat conducting layer 120 encapsulates the first conductive bumps 101 and the first solder balls 103 .

[0060] Specifically, the thermal conductive layer 120 provides a process basis for the subsequent formation of an opening to expose the first solder ball 103. The subsequent formation of the opening can expose the solder area of ​​the first solder ball 103, thereby reducing the probability of residual adhesive film on the surface of the first solder ball 103. In the subsequent process of placing the first chip 100 on the second chip for welding to join the first solder ball 103 with the second conductive bump to form a stacked chip, the risk of voids or solder extrusion during welding of the first solder ball 103 and the second conductive bump can be reduced. At the same time, by forming the thermal conductive layer 120 covering the first chip 100, the thermal conductive layer 120 has a high heat dissipation characteristic, which can significantly improve the heat dissipation performance of the packaging structure. In summary, by forming the thermal conductive layer 120 covering the first chip 100 and forming an opening in the thermal conductive layer 120 to expose the first solder ball 103, the reliability and heat dissipation performance of the packaging structure can be improved.

[0061] In this embodiment, the process of forming the heat conducting layer 120 covering the first wafer 100 includes a chemical vapor deposition process or a coating process.

[0062] As an example, in the step of forming the heat-conducting layer 120 , the material of the heat-conducting layer 120 includes one or more of epoxy resin, a mixture of phenolic resin and silicon dioxide, a mixture of phenolic resin and aluminum oxide, and a mixture of phenolic resin and boron nitride.

[0063] Specifically, epoxy resin, a mixture of phenolic resin and silicon dioxide, a mixture of phenolic resin and aluminum oxide, and a mixture of phenolic resin and boron nitride have good heat dissipation effects. After the first chip 100 is stacked with the subsequently provided second chip to form a stacked chip, when the stacked chip is in a working state, the thermal conductive layer 120 can quickly dissipate the heat generated by the working operation, so that the heat dissipation performance of the packaging structure is improved. At the same time, it also has a good insulation effect. After the first chip 100 and the second chip form a stacked chip, the thermal conductive layer 120 can electrically isolate the adjacent joined first solder balls 103 and the second solder balls on the second chip, thereby reducing the risk of leakage between each other.

[0064] refer to Figure 3 An opening 121 exposing the first solder ball 103 is formed in the heat conducting layer 120 .

[0065] It should be noted that the opening 121 exposes the solder area of ​​the first solder ball 103, providing a process window for the subsequent welding process with the second conductive bump of the second chip. At the same time, the formation of the opening 121 also reduces the probability of residual adhesive film on the surface of the first solder ball 103. In the subsequent process of joining the first solder ball 103 and the second conductive bump to form a stacked chip, the risk of voids or solder extrusion during welding between the first solder ball 103 and the second conductive bump can be reduced.

[0066] In this embodiment, the process of forming the opening 121 includes a laser process.

[0067] Specifically, the laser process has high cutting accuracy, which can make the opening 121 accurately expose the first solder ball 103 and will not cause accidental damage to the thermal conductive layer 120 in other areas. At the same time, the laser process is used to form the opening 121, which can cleanly remove the adhesive film on the surface of the first solder ball 103. In the subsequent process of forming a stacked chip, the risk of voids or solder extrusion during welding between the first solder ball 103 and the second conductive bump can be reduced.

[0068] In addition, the laser process has high cutting efficiency, which can improve the production efficiency of the production line and thus increase economic benefits.

[0069] refer to Figure 4 , providing a second chip 130 , wherein the second chip 130 includes second conductive bumps 133 .

[0070] Specifically, the second chip 130 is used to be welded with the first chip 100 to form a stacked chip, and then the stacked chip is mounted on a substrate.

[0071] It should be noted that the second conductive bumps 133 can electrically connect the second chip 130 to an external circuit structure (eg, the first chip 100 ), and the second conductive bumps 133 are distributed on the surface of the second chip 130 , thereby improving the connection density of the second chip 130 .

[0072] As an example, the material of the second conductive bump 133 includes one or more of copper, nickel and gold.

[0073] Specifically, the second conductive bump 133 is used to be welded to the first solder ball 103 on the first chip 100, so that the second chip 130 can transmit electrical signals with the first chip 100. At the same time, the welding of the second conductive bump 133 and the first solder ball 103 also improves the bonding force between the second chip 130 and the first chip 100, making it less likely for the second chip 130 to fall off the first chip 100, thereby improving the structural reliability of the packaging structure.

[0074] In this embodiment, the second chip 130 also includes a second chip 131, a second dielectric layer 132 formed on the top surface of the second chip 131, a second redistribution layer 135 which is a stack of one or more layers arranged in the second dielectric layer 132, a third dielectric layer 136 formed on the bottom surface of the second chip 131, a third redistribution layer 137 which is a stack of one or more layers arranged in the third dielectric layer 136, a third conductive bump 138 protruding from the surface of the third dielectric layer 136 and electrically connected to the third redistribution layer 137, and a second solder ball 139 formed on the third conductive bump 138, and the second conductive bump 133 is electrically connected to the second redistribution layer 135 at the top layer.

[0075] Specifically, the second chip 131 is a chip with a specific function. Specifically, the type of the second chip 131 is determined according to actual functional requirements or application scenarios. For example, the second chip 131 includes one or more of a radio frequency chip, a memory chip, an ASIC (Application-Specific Integrated Circuit) chip, a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip, and an FPGA (Field-Programmable Gate Array) chip.

[0076] In other embodiments, according to actual process requirements, the second chip 131 may also be other chips.

[0077] Specifically, the second dielectric layer 132 is used to electrically isolate the second redistribution layer 135, thereby reducing the risk of leakage between adjacent second redistribution layers 135. At the same time, in the subsequent process of forming stacked chips, the second dielectric layer 132 is also bonded to the thermal conductive layer 120, thereby providing bonding reinforcement between the first chip 100 and the second chip 130.

[0078] As an example, the material of the second dielectric layer 132 includes one or more of polyimide resin, epoxy resin, phenolic resin, and bismaleimide triazine resin.

[0079] It should be noted that the second redistribution layer 135 can reallocate the input ports and output ports on the second chip 131, thereby improving the flexibility of electrical signal connection, and can reduce the path length of electrical signal transmission and reduce electrical signal transmission delay.

[0080] It should also be noted that the topmost second rewiring layer 135 is electrically connected to the second conductive bump 133, so that one or more layers of the second rewiring layer 135 can be electrically connected to the external circuit structure through the second conductive bump 133, and then the second chip 131 can be electrically connected to the external circuit structure.

[0081] Specifically, the third dielectric layer 136 is used to electrically isolate the third redistribution layers 137 , thereby reducing the risk of electrical leakage between adjacent third redistribution layers 137 .

[0082] As an example, the material of the third dielectric layer 136 includes one or more of polyimide resin, epoxy resin, phenolic resin, and bismaleimide triazine resin.

[0083] It should be noted that the third redistribution layer 137 can reallocate the input ports and output ports on the second chip 131, thereby improving the flexibility of electrical signal connection, and can reduce the path length of electrical signal transmission and reduce electrical signal transmission delay.

[0084] It should also be noted that the third conductive bump 138 is used to electrically connect the second chip 130 to a subsequently provided substrate, and the third conductive bump 138 is distributed on the surface of the second chip 130, thereby improving the connection density of the second chip 130. At the same time, the third conductive bump 138 also provides a bearing surface for setting the second solder ball 139, which helps the second solder ball 139 and the third conductive bump 138 to form a stable electrical connection.

[0085] As an example, the material of the third conductive bump 138 includes copper.

[0086] Specifically, the second solder balls 139 are used to be soldered to a substrate provided subsequently, so that the stacked wafer can be electrically connected to the circuit structure in the substrate through the second solder balls 139 .

[0087] As an example, the material of the second solder ball 139 includes one or more of a tin-silver alloy, a gold-tin alloy, and a tin-lead alloy.

[0088] refer to Figure 5 to Figure 6 , the first wafer 100 is placed on the second wafer 130 and soldered to bond the first solder balls 103 to the second conductive bumps 133 to form a stacked wafer 150 .

[0089] Specifically, placing the first chip 100 on the second chip 130 and welding them together to form a stacked chip 150 can improve packaging density and packaging integration, and is beneficial to reducing the signal transmission distance between the first chip 105 and the second chip 131, thereby reducing power consumption and further improving heat dissipation performance.

[0090] Meanwhile, forming the stacked wafer 150 is also convenient for subsequent mounting on a substrate.

[0091] In this embodiment, the process of placing the first wafer 100 on the second wafer 130 for welding to bond the first solder balls 103 to the second conductive bumps 133 includes a high temperature reflow process or a high temperature and high pressure welding process.

[0092] Specifically, taking the high temperature reflow process as an example, the high temperature reflow process can only locally heat the first solder ball 103 and the second conductive bump 133 to complete the welding, reducing the probability of thermal shock to other components of the first chip 100 and the second chip 130. At the same time, the high temperature reflow process can allow the excess flux in the first solder ball 103 and the second conductive bump 133 to fully volatilize, reducing the residue after welding, thereby improving the welding quality.

[0093] refer to Figure 7 After forming the stacked chip 150 , the method for forming the packaging structure further includes: mounting the stacked chip 150 on a substrate 160 .

[0094] Specifically, the stacked wafer 150 is mounted on the substrate 160 . The stacked wafer 150 may include chips with different functions. By mounting the chips with different functions on the substrate 160 , a packaging structure with multiple functions can be realized.

[0095] It should be noted that the substrate 160 serves as a packaging carrier to provide support for the stacked chip 150 and provide an electrical connection path between the stacked chip 150 and an external circuit, thereby achieving packaging integration and electrical integration of the stacked chip 150 .

[0096] In this embodiment, the substrate 160 may include a package substrate 160 (Package Substrate), an interposer (Interposer) or a printed circuit board (PCB). As an example, the substrate 160 is a package substrate 160 .

[0097] In this embodiment, the process of mounting the stacked wafer 150 on the substrate 160 includes a high temperature reflow process.

[0098] Specifically, the second solder ball 139 of the second chip 130 and the solder on the substrate 160 are locally heated through a high-temperature reflow process to complete the welding, which can reduce the probability of thermal shock to other components of the stacked chip 150. At the same time, the high-temperature reflow process can allow the excess flux in the solder on the second solder ball 139 and the substrate 160 to fully volatilize, reducing the residue after welding, thereby improving the welding quality.

[0099] Figures 8 to 10 It is a schematic structural diagram corresponding to each step in the second embodiment of the method for forming a packaging structure of the present invention.

[0100] The similarities between the method for forming the package structure of the present invention and the first embodiment are not described in detail here. The differences between the method for forming the package structure of the present invention and the first embodiment are as follows:

[0101] refer to Figures 8 to 10 ,in, Figure 8 It is a top view. Fig. 9 yes Figure 8 In the cross-sectional view along the AA direction, in the process of forming the opening 221, the process further includes: forming a groove 272 in the heat-conducting layer 220 at the side of the first solder ball 203, the groove 272 including a groove along the first direction (such as Figure 8 The comb handle groove 270 extending in the second direction (as shown in the Y direction) and the comb handle groove 270 extending in the second direction (as shown in the Y direction) Figure 8 The comb tooth grooves 271 are arranged in parallel with each other (as shown in the X direction), the comb handle groove 270 is connected with the comb tooth grooves 271, and the comb tooth grooves 271 expose the side walls of the first solder ball 203, and the first direction is perpendicular to the second direction.

[0102] Specifically, in the subsequent process of welding the first solder ball 203 and the second conductive bump to form a stacked chip, a large amount of hot air will be generated. By forming a groove 272 in the thermal conductive layer 220 on the side of the first solder ball 203, the hot air can be discharged through the groove 272, thereby reducing the risk of forming a void at the joint of the first solder ball 203 and the second conductive bump in the process of welding to form a stacked chip, thereby further improving the reliability of the packaging structure.

[0103] It should be noted that the hot air is discharged through the comb tooth grooves 271 and then gathered into the comb handle grooves 270 to be discharged from the packaging structure.

[0104] Specifically, the trench 272 is formed during the process of forming the opening 221 , that is, the trench 272 and the opening 221 are formed in the same step, thereby reducing the number of process steps and the process cost.

[0105] In other embodiments, the opening 221 and the groove 272 may also be formed in different steps.

[0106] As an example, the grooves 272 are formed on both sides of the first solder ball 203 .

[0107] Specifically, the grooves 272 are formed on both sides of the first solder ball 203 , so that hot air can be quickly discharged through the grooves 272 on both sides of the first solder ball 203 , thereby reducing the risk of voids and improving the reliability of the packaging structure.

[0108] In other embodiments, Fig.10 As shown, the groove 272 may also be formed on one side of the first solder ball 203 .

[0109] In this embodiment, when the grooves 272 are formed on both sides of the first solder balls 203 , the grooves 272 between adjacent first solder balls 203 share a comb handle groove 270 .

[0110] It should be noted that the grooves 272 between adjacent first solder balls 203 share a comb handle groove 270. By eliminating a comb handle groove 270, the thermal conductive layer 220 between adjacent first solder balls 203 can be retained to the maximum extent, so that the heat dissipation effect of the thermal conductive layer 220 will not be affected, thereby ensuring the heat dissipation performance of the packaging structure. At the same time, the grooves 272 between adjacent first solder balls 203 share a comb handle groove 270, which is also conducive to further integration of the packaging structure, thereby reducing the area occupied by the packaging structure.

[0111] Specifically, the width of the comb-tooth groove 271 in the first direction should not be too large or too small. If the width of the comb-tooth groove 271 in the first direction is too large, it is easy to cause too much heat-conducting layer 220 to be removed, thereby affecting the heat dissipation effect of the heat-conducting layer 220, and further affecting the heat dissipation performance of the packaging structure; if the width of the comb-tooth groove 271 in the first direction is too small, it is easy to cause a large amount of hot air to be difficult to be discharged quickly, increasing the risk of forming a cavity at the junction of the first solder ball 203 and the second conductive bump, thereby affecting the reliability of the packaging structure. For this reason, in this embodiment, the width of the comb-tooth groove 271 in the first direction is 0.5 microns to 1.5 microns.

[0112] It should be noted that the width of the comb handle groove 270 in the second direction should not be too large or too small. If the width of the comb handle groove 270 in the second direction is too large, it is easy to cause too much heat-conducting layer 220 to be removed, thereby affecting the heat dissipation effect of the heat-conducting layer 220, and further affecting the heat dissipation performance of the packaging structure; if the width of the comb tooth groove 271 in the second direction is too small, after the hot air in the multiple comb tooth grooves 271 is gathered in the comb handle groove 270, it is easy to cause the comb handle groove 270 to fail to quickly discharge the hot air, so that a large amount of hot air is accumulated in the comb handle groove 270, thereby increasing the temperature of the packaging structure and affecting the performance of the packaging structure. For this reason, in this embodiment, the width of the comb handle groove 270 in the second direction is 1 micron to 3 microns.

[0113] Accordingly, an embodiment of the present invention further provides a packaging structure. Fig.11 A structural schematic diagram corresponding to the first embodiment of the packaging structure of the present invention is shown.

[0114] The packaging structure includes: a substrate 360; a stacked chip 350 mounted on the substrate 360, the stacked chip 350 includes a second chip 330 and a first chip 300 located above the second chip 330 and welded to the second chip 330, the first chip 300 includes a first conductive bump 301 and a first solder ball 303 arranged on the first conductive bump 301, the first conductive bump 301 is electrically connected to the first solder ball 303, the second chip 330 includes a second conductive bump 333, the second conductive bump 333 is electrically connected to the first solder ball 303, and the first solder ball 303 is bonded to the second conductive bump 333; a thermal conductive layer 320 is located between the first chip 300 and the second chip 330, and covers the side walls of the first conductive bump 301, the second conductive bump 333 and the first solder ball 303.

[0115] Specifically, in the process of forming the packaging structure, an opening exposing the first solder ball 303 is formed in the thermal conductive layer 320. By forming the opening, the solder area of ​​each first solder ball 303 can be exposed, thereby reducing the probability of residual adhesive film on the surface of the first solder ball 303. In the process of placing the first chip 300 on the second chip 330 for welding, so as to join the first solder ball 303 with the second conductive bump 333 to form a stacked chip 350, the risk of voids or solder extrusion during welding of the first solder ball 303 and the second conductive bump 333 can be reduced. At the same time, by setting the thermal conductive layer 320 covering the first chip 300, the thermal conductive layer 320 has a high heat dissipation characteristic, which can significantly improve the heat dissipation performance of the packaging structure. In summary, by setting the thermal conductive layer 320 covering the first chip 300 and forming an opening exposing the first solder ball 303 in the thermal conductive layer 320, the reliability and heat dissipation performance of the packaging structure can be improved.

[0116] It should be noted that the substrate 360 ​​serves as a packaging carrier to provide support for the stacked chip 350 and provide an electrical connection path between the stacked chip 350 and an external circuit, thereby achieving packaging integration and electrical integration of the stacked chip 350 .

[0117] In this embodiment, the substrate 360 ​​may include a package substrate 360 ​​(Package Substrate), an interposer (Interposer) or a printed circuit board (Printed Circuit Board, PCB). As an example, the substrate 360 ​​is a package substrate 360.

[0118] Specifically, the stacked wafer 350 is mounted on the substrate 360 ​​. The stacked wafer 350 may include chips with different functions. By mounting the chips with different functions on the substrate 360 ​​, a packaging structure with multiple functions can be realized.

[0119] Specifically, the first wafer 300 is used to be welded with the second wafer 330 to form a stacked wafer 350 .

[0120] It should be noted that the first conductive bump 301 can electrically connect the first chip 300 to an external circuit structure (such as the second chip 330), and the first conductive bump 301 is distributed on the surface of the first chip 300, thereby improving the connection density of the first chip 300. At the same time, the first conductive bump 301 also provides a bearing surface for setting the first solder ball 303, which helps the first solder ball 303 to form a stable electrical connection with the first conductive bump 301.

[0121] As an example, the material of the first conductive bump 301 includes copper.

[0122] Specifically, the first solder ball 303 is used to be welded with the second conductive bump 333 on the second chip 330, so that the first chip 300 can realize electrical signal transmission with the second chip 330. At the same time, the welding of the first solder ball 303 and the second conductive bump 333 also improves the bonding force between the first chip 300 and the second chip 330, making it less likely for the first chip 300 and the second chip 330 to fall off, thereby improving the structural reliability of the packaging structure.

[0123] As an example, the material of the first solder ball 303 includes one or more of a tin-silver alloy, a gold-tin alloy, and a tin-lead alloy.

[0124] In this embodiment, the first chip 300 also includes: a first chip 305; a first dielectric layer 308, located on the first chip 305; a first redistribution layer 310 of one or more layers stacked, located in the first dielectric layer 308, and the topmost first redistribution layer 310 is electrically connected to the first conductive bump 301; a first interconnection through-hole structure 306, located in the first chip 305 and passing through the first chip 305, and the first interconnection through-hole structure 306 is electrically connected to the bottommost first redistribution layer 310.

[0125] Specifically, the first chip 305 is a chip with a specific function. Specifically, the type of the first chip 305 is determined according to actual functional requirements or application scenarios. For example, the first chip 305 includes one or more of a radio frequency chip, a memory chip, an ASIC (Application-Specific Integrated Circuit) chip, a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip, and an FPGA (Field-Programmable Gate Array) chip.

[0126] In other embodiments, according to actual process requirements, the first chip 305 may also be other chips.

[0127] Specifically, the first dielectric layer 308 is used to electrically isolate the first redistribution layers 310 , thereby reducing the risk of electrical leakage between adjacent first redistribution layers 310 .

[0128] As an example, the material of the first dielectric layer 308 includes one or more of polyimide resin, epoxy resin, phenolic resin, and bismaleimide triazine resin.

[0129] It should be noted that the first redistribution layer 310 can reallocate the input ports and output ports on the first chip 305, thereby improving the flexibility of electrical signal connection, and can reduce the path length of electrical signal transmission and reduce electrical signal transmission delay.

[0130] It should also be noted that the topmost first rewiring layer 310 is electrically connected to the first conductive bump 301 , so that one or more rewiring layers can be electrically connected to an external circuit structure through the first conductive bump 301 .

[0131] As an example, Fig.11 As shown, a first redistribution layer 310 of a 2-layer stack is shown.

[0132] In this embodiment, the material of the first redistribution layer 310 includes one or more of copper, aluminum and silver.

[0133] In this embodiment, a first interconnection through-via structure 306 (TSV) penetrating the first chip 305 is further provided in the first chip 305 of the first wafer 300 . The first interconnection through-via structure 306 is electrically connected to the first redistribution layer 310 at the bottom layer.

[0134] Specifically, by forming the first interconnection via structure 306 penetrating the first chip 305 , after the first wafer 300 and the second wafer 330 are welded to form the stacked wafer 350 , the density of the packaging structure can be increased and the transmission of electrical signals can be accelerated.

[0135] In this embodiment, the material of the first interconnection via structure 306 includes one or more of copper, tungsten and polysilicon.

[0136] In this embodiment, when the number of layers of the first re-wiring layer 310 is multiple layers, the first chip 300 also includes: a second interconnection through-hole structure 311, which is located in the first dielectric layer 308 between adjacent first re-wiring layers 310, and the second interconnection through-hole structure 311 is electrically connected to the adjacent first re-wiring layer 310.

[0137] It should be noted that multiple layers of the first redistribution layer 310 are provided in the first dielectric layer 308 to meet the requirements of high-density integration.

[0138] In this embodiment, the material of the second interconnection via structure 311 includes copper.

[0139] Specifically, the second chip 330 is used to be welded with the first chip 300 to form a stacked chip 350 , and then the stacked chip 350 is mounted on the substrate 360 ​​.

[0140] It should be noted that the second conductive bumps 333 can electrically connect the second chip 330 to an external circuit structure (eg, the first chip 300 ), and the second conductive bumps 333 are distributed on the surface of the second chip 330 , thereby improving the connection density of the second chip 330 .

[0141] As an example, the material of the second conductive bump 333 includes one or more of copper, nickel and gold.

[0142] Specifically, the second conductive bump 333 is used to be welded to the first solder ball 303 on the first chip 300, so that the second chip 330 can transmit electrical signals with the first chip 300. At the same time, the welding of the second conductive bump 333 and the first solder ball 303 also improves the bonding force between the second chip 330 and the first chip 300, making it less likely for the second chip 330 to fall off the first chip 300, thereby improving the structural reliability of the packaging structure.

[0143] In this embodiment, the second chip 330 also includes: a second chip 331; a second dielectric layer 332, located on the top surface of the second chip 331; a second redistribution layer 335 stacked in one or more layers, located in the second dielectric layer 332, and the topmost second redistribution layer 335 is electrically connected to the second conductive bump 333; a third dielectric layer 336, located on the bottom surface of the second chip 331; a third redistribution layer 337 stacked in one or more layers, located in the third dielectric layer 336; a third conductive bump 338, protruding from the surface of the third dielectric layer 336 and electrically connected to the third redistribution layer 337; a second solder ball 339, located on the third conductive bump 338; a third interconnection through-hole structure 399, located in the second chip 331 and penetrating the second chip 331, and the third interconnection through-hole structure 399 is electrically connected to the second redistribution layer 335 and the third redistribution layer 337.

[0144] Specifically, the second chip 331 is a chip with a specific function. Specifically, the type of the second chip 331 is determined according to actual functional requirements or application scenarios. For example, the second chip 331 includes one or more of a radio frequency chip, a memory chip, an ASIC (Application-Specific Integrated Circuit) chip, a CPU (Central Processing Unit) chip, a GPU (Graphics Processing Unit) chip, and an FPGA (Field-Programmable Gate Array) chip.

[0145] In other embodiments, according to actual process requirements, the second chip 331 may also be other chips.

[0146] Specifically, the second dielectric layer 332 is used to electrically isolate the second redistribution layer 335, thereby reducing the risk of leakage between adjacent second redistribution layers 335. At the same time, in the process of setting up the stacked chip 350, the second dielectric layer 332 is also bonded to the thermal conductive layer 320, thereby providing bonding reinforcement between the first chip 300 and the second chip 330.

[0147] As an example, the material of the second dielectric layer 332 includes one or more of polyimide resin, epoxy resin, phenolic resin, and bismaleimide triazine resin.

[0148] It should be noted that the second redistribution layer 335 can reallocate the input ports and output ports on the second chip 331, thereby improving the flexibility of electrical signal connection, and can reduce the path length of electrical signal transmission and reduce electrical signal transmission delay.

[0149] It should also be noted that the topmost second rewiring layer 335 is electrically connected to the second conductive bump 333, so that one or more layers of the second rewiring layer 335 can be electrically connected to the external circuit structure through the second conductive bump 333, and then the second chip 331 can be electrically connected to the external circuit structure.

[0150] Specifically, the third dielectric layer 336 is used to electrically isolate the third redistribution layers 337 , thereby reducing the risk of electrical leakage between adjacent third redistribution layers 337 .

[0151] As an example, the material of the third dielectric layer 336 includes one or more of polyimide resin, epoxy resin, phenolic resin, and bismaleimide triazine resin.

[0152] It should be noted that the third redistribution layer 337 can reallocate the input ports and output ports on the second chip 331, thereby improving the flexibility of electrical signal connection, and can reduce the path length of electrical signal transmission and reduce electrical signal transmission delay.

[0153] It should also be noted that the third conductive bump 338 is used to electrically connect the second chip 330 to the substrate 360, and the third conductive bump 338 is distributed on the surface of the second chip 330, thereby improving the connection density of the second chip 330. At the same time, the third conductive bump 338 also provides a bearing surface for setting the second solder ball 339, which helps the second solder ball 339 and the third conductive bump 338 to form a stable electrical connection.

[0154] As an example, the material of the third conductive bump 338 includes copper.

[0155] Specifically, the second solder balls 339 are used to be soldered to the substrate 360 ​​, so that the stacked wafer 350 can be electrically connected to the circuit structure in the substrate 360 ​​through the second solder balls 339 .

[0156] As an example, the material of the second solder ball 339 includes one or more of a tin-silver alloy, a gold-tin alloy, and a tin-lead alloy.

[0157] Specifically, by providing the third interconnection through-hole penetrating the second chip 331 , after providing the stacked wafer 350 , the density of the packaging structure can be improved, and the transmission of electrical signals can be accelerated.

[0158] As an example, the material of the third interconnect via structure 399 includes one or more of copper, tungsten and polysilicon.

[0159] It should be noted that, by arranging the heat-conducting layer 320 between the first chip 300 and the second chip 330 , the heat-conducting layer 320 has a high heat-dissipating property, which can significantly improve the heat-dissipating performance of the packaging structure.

[0160] As an example, in the step of forming the heat-conducting layer 320 , the material of the heat-conducting layer 320 includes one or more of epoxy resin, a mixture of phenolic resin and silicon dioxide, a mixture of phenolic resin and aluminum oxide, and a mixture of phenolic resin and boron nitride.

[0161] Specifically, epoxy resin, a mixture of phenolic resin and silicon dioxide, a mixture of phenolic resin and aluminum oxide, and a mixture of phenolic resin and boron nitride have good heat dissipation effects. After the stacked chip 350 is set, when the stacked chip 350 is in working state, the thermal conductive layer 320 can quickly dissipate the heat generated by the operation, so that the heat dissipation performance of the packaging structure is improved. At the same time, it also has a good insulation effect. After the stacked chip 350 is set, the thermal conductive layer 320 can electrically isolate the adjacent connected first solder balls 303, first conductive bumps 301 and second conductive bumps 333, thereby reducing the risk of leakage between each other.

[0162] Accordingly, Fig.12 A structural schematic diagram corresponding to the second embodiment of the packaging structure of the present invention is shown.

[0163] The similarities between the packaging structure of the present invention and the first embodiment are not described in detail here. The differences between the packaging structure of the present invention and the first embodiment are as follows:

[0164] refer to Fig.12 The packaging structure further includes: a groove 472 located in the heat conducting layer 420 at the side of the first solder ball 403, the groove 472 including a first direction (such as Fig.12 The comb handle groove 470 extending in the second direction (as shown in the Y direction) and the comb handle groove 470 extending in the second direction (as shown in the Y direction) Fig.12 The comb tooth grooves 471 are arranged in parallel at intervals (as shown in the X direction), the comb handle groove 470 is connected with the comb tooth grooves 471, and the comb tooth grooves 471 expose the side walls of the first solder ball 403, and the first direction is perpendicular to the second direction.

[0165] Specifically, a large amount of hot air will be generated in the process of welding the first solder ball 403 and the second conductive bump to form a stacked chip. By forming a groove 472 in the thermal conductive layer 420 on the side of the first solder ball 403, the hot air can be discharged through the groove 472, thereby reducing the risk of forming a void at the joint of the first solder ball 403 and the second conductive bump in the process of welding to form a stacked chip, thereby further improving the reliability of the packaging structure.

[0166] It should be noted that the hot air is discharged through the comb tooth grooves 471 and then gathered into the comb handle grooves 470 to be discharged from the packaging structure.

[0167] In this embodiment, the grooves 472 are disposed on two sides of the first solder ball 403 .

[0168] Specifically, the grooves 472 are formed on both sides of the first solder ball 403 , so that hot air can be quickly discharged through the grooves 472 on both sides of the first solder ball 403 , thereby reducing the risk of voids and improving the reliability of the packaging structure.

[0169] In other embodiments, the groove may also be disposed on one side of the first solder ball.

[0170] In this embodiment, when the grooves 472 are located on both sides of the first solder balls 403 , the grooves 472 between adjacent first solder balls 403 share a comb handle groove 470 .

[0171] It should be noted that the grooves 472 between adjacent first solder balls 403 share a comb handle groove 470. By eliminating a comb handle groove 470, the thermal conductive layer 420 between adjacent first solder balls 403 can be retained to the maximum extent, so that the heat dissipation effect of the thermal conductive layer 420 will not be affected, thereby ensuring the heat dissipation performance of the packaging structure. At the same time, the grooves 472 between adjacent first solder balls 403 share a comb handle groove 470, which is also conducive to further integration of the packaging structure, thereby reducing the area occupied by the packaging structure.

[0172] Specifically, the width of the comb-tooth groove 471 in the first direction should not be too large or too small. If the width of the comb-tooth groove 471 in the first direction is too large, it is easy to cause too much heat-conducting layer 420 to be removed, thereby affecting the heat dissipation effect of the heat-conducting layer 420, and further affecting the heat dissipation performance of the packaging structure; if the width of the comb-tooth groove 471 in the first direction is too small, it is easy to cause a large amount of hot air to be difficult to be discharged quickly, increasing the risk of forming a cavity at the junction of the first solder ball 403 and the second conductive bump, thereby affecting the reliability of the packaging structure. For this reason, in this embodiment, the width of the comb-tooth groove 471 in the first direction is 0.5 microns to 1.5 microns.

[0173] It should be noted that the width of the comb handle groove 470 in the second direction should not be too large or too small. If the width of the comb handle groove 470 in the second direction is too large, it is easy to cause too much heat-conducting layer 420 to be removed, thereby affecting the heat dissipation effect of the heat-conducting layer 420, and further affecting the heat dissipation performance of the packaging structure; if the width of the comb tooth groove 471 in the second direction is too small, after the hot air in the multiple comb tooth grooves 471 is gathered in the comb handle groove 470, it is easy to cause the comb handle groove 470 to fail to quickly discharge the hot air, so that a large amount of hot air is accumulated in the comb handle groove 470, thereby increasing the temperature of the packaging structure and affecting the performance of the packaging structure. For this reason, in this embodiment, the size of the comb handle groove 470 in the second direction is 1 micron to 3 microns.

[0174] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a packaging structure, characterized in that: include: Providing a first wafer, the first wafer comprising a first conductive bump and a first solder ball disposed on the first conductive bump, the first conductive bump being electrically connected to the first solder ball; forming a heat-conducting layer covering the first wafer, wherein the heat-conducting layer encapsulates the first conductive bump and the first solder ball; forming an opening in the heat conductive layer to expose the first solder ball; providing a second wafer, the second wafer comprising a second conductive bump; The first wafer is placed on the second wafer for welding, so as to connect the first solder balls with the second conductive bumps to form a stacked wafer.

2. The method for forming a packaging structure according to claim 1, wherein: The process of forming the opening also includes: forming a groove in the heat-conducting layer on the side of the first solder ball, the groove including a comb handle groove extending along a first direction and comb tooth grooves arranged in parallel and spaced apart along a second direction, the comb handle groove is connected to the comb tooth grooves, and the comb tooth grooves expose the side walls of the first solder ball, and the first direction is perpendicular to the second direction.

3. The method for forming a packaging structure according to claim 2, wherein: The groove is formed on one side of the first solder ball; or, The grooves are formed on both sides of the first solder ball.

4. The method for forming a packaging structure according to claim 2 or 3, characterized in that: When the grooves are formed on both sides of the first solder ball, the grooves between adjacent first solder balls share a comb handle groove.

5. The method for forming a package structure according to claim 2, wherein: The width of the comb groove in the first direction is 0.5 micrometers to 1.5 micrometers; The width of the comb handle groove in the second direction is 1 micrometer to 3 micrometers.

6. The method for forming a packaging structure according to claim 1, wherein: The process of forming the opening includes a laser process.

7. The method for forming a package structure according to claim 1, wherein: In the step of forming the heat-conducting layer, the material of the heat-conducting layer includes one or more of epoxy resin, a mixture of phenolic resin and silicon dioxide, a mixture of phenolic resin and aluminum oxide, and a mixture of phenolic resin and boron nitride.

8. The method for forming a package structure according to claim 1, wherein: In the step of providing a first chip, the first chip also includes a first chip, a first dielectric layer formed on the first chip, and a first redistribution layer of one or more layers stacked in the first dielectric layer, and the topmost first redistribution layer is electrically connected to the first conductive bump.

9. The method for forming a package structure according to claim 8, wherein: A first interconnection through-hole structure penetrating the first chip is also formed in the first chip of the first wafer, and the first interconnection through-hole structure is electrically connected to the first redistribution layer at the bottom layer; When multiple layers of the first rewiring layers are arranged in the first dielectric layer, a second interconnection via structure is formed in the first dielectric layer between adjacent first rewiring layers, and the second interconnection via structure is electrically connected to the adjacent first rewiring layers.

10. The method for forming a package structure according to claim 1, wherein: The process of placing the first wafer on the second wafer for welding to join the first solder ball with the second conductive bump includes a high temperature reflow process or a high temperature and high pressure welding process.

11. The method for forming a package structure according to claim 1, wherein: In the step of providing a second chip, the second chip also includes a second chip, a second dielectric layer formed on the top surface of the second chip, a second redistribution layer of one or more layers stacked in the second dielectric layer, a third dielectric layer formed on the bottom surface of the second chip, a third redistribution layer of one or more layers stacked in the third dielectric layer, a third conductive bump protruding from the surface of the third dielectric layer and electrically connected to the third redistribution layer, and a second solder ball formed on the third conductive bump, wherein the second conductive bump is electrically connected to the second redistribution layer at the topmost layer.

12. The method for forming a package structure according to claim 1, wherein: After forming the stacked wafers, the method for forming the packaging structure further includes: mounting the stacked wafers on a substrate.

13. The method for forming a package structure according to claim 12, wherein: The process of mounting the stacked wafers on a substrate includes a high temperature reflow process.

14. A packaging structure, characterized in that: include: substrate; A stacked wafer mounted on the substrate, the stacked wafer comprising a second wafer and a first wafer located above the second wafer and soldered to the second wafer, the first wafer comprising a first conductive bump and a first solder ball disposed on the first conductive bump, the first conductive bump being electrically connected to the first solder ball, the second wafer comprising a second conductive bump, the second conductive bump being electrically connected to the first solder ball, and the first solder ball being bonded to the second conductive bump; The heat conducting layer is located between the first chip and the second chip and covers the first conductive bump, the second conductive bump and the side wall of the first solder ball.

15. The packaging structure according to claim 14, characterized in that: The packaging structure also includes: a groove located in the heat conductive layer on the side of the first solder ball, the groove including a comb handle groove extending along a first direction and comb tooth grooves arranged in parallel and spaced apart along a second direction, the comb handle groove is connected to the comb tooth grooves, and the comb tooth grooves expose the side walls of the first solder ball, and the first direction is perpendicular to the second direction.

16. The packaging structure according to claim 15, characterized in that: The groove is arranged on one side of the first solder ball; or, The grooves are arranged on both sides of the first solder ball.

17. The packaging structure according to claim 15 or 16, characterized in that: When the grooves are located on both sides of the first solder ball, the grooves between adjacent first solder balls share a comb handle groove.

18. The packaging structure according to claim 15, characterized in that: The width of the comb groove in the first direction is 0.5 micrometers to 1.5 micrometers; The width of the comb handle groove in the second direction is 1 micrometer to 3 micrometers.

19. The packaging structure according to claim 14, characterized in that: The material of the heat-conducting layer includes one or more of epoxy resin, a mixture of phenolic resin and silicon dioxide, a mixture of phenolic resin and aluminum oxide, and a mixture of phenolic resin and boron nitride.

20. The packaging structure according to claim 14, characterized in that: The first wafer further includes: a first chip; a first dielectric layer located on the first chip; one or more stacked first rewiring layers located in the first dielectric layer, and the topmost first rewiring layer is electrically connected to the first conductive bump; a first interconnection via structure located in the first chip and penetrating the first chip, and the first interconnection via structure is electrically connected to the bottommost first rewiring layer; When the first rewiring layer has multiple layers, the first chip further includes: a second interconnection via structure located in the first dielectric layer between adjacent first rewiring layers, and the second interconnection via structure is electrically connected to the adjacent first rewiring layer.

21. The packaging structure according to claim 14, characterized in that: The second wafer also includes: a second chip; a second dielectric layer, located on the top surface of the second chip; one or more stacked second rewiring layers, located in the second dielectric layer, and the topmost second rewiring layer is electrically connected to the second conductive bump; a third dielectric layer, located on the bottom surface of the second chip; one or more stacked third rewiring layers, located in the third dielectric layer; a third conductive bump, protruding from the surface of the third dielectric layer and electrically connected to the third rewiring layer; a second solder ball, located on the third conductive bump; a third interconnection via, located in the second chip and penetrating the second chip, and the third interconnection via is electrically connected to the second and third rewiring layers.

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