Method for packaging a chip and chip package
By arranging the die and lead frame side by side in the chip package, and forming a covered dielectric layer and metal layer in the thickness direction, the problems of excessive size and poor heat dissipation performance of traditional chip packages are solved, and a smaller package size and better heat dissipation effect are achieved.
Patent Information
- Application Number
- CN202411833052.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-12
- Publication Date
- 2025-03-28
AI Technical Summary
Traditional chip packaging solutions have problems such as excessive size and poor heat dissipation performance, especially square flat pinless packages and chip packages on leadframes have insufficient size and heat dissipation performance.
By arranging the die and lead frame side by side on the carrier plate and forming a covered dielectric layer in the thickness direction, a metal layer is formed on the bottom side of the die and lead frame after removing the carrier plate, and vias and interconnection layers are formed in the dielectric layer to achieve electrical connection between the chip and the circuit board and heat dissipation.
It achieves a smaller chip package size and better heat dissipation performance, avoids the dimensional interference problem caused by glue bonding in traditional technology, and significantly improves the heat dissipation ability of the chip.
Smart Images
Figure CN119725117A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure generally relate to semiconductor manufacturing, and more particularly to methods for packaging chips and chip packaging Background Art
[0002] Traditional chip packaging mainly adopts Quad Flat No-leads Package (QFN) and Chip On Lead (COL). However, these chip packaging solutions are not satisfactory.
[0003] For square flat leadless packages, in order to mount the chip on a printed circuit board, the size of the chip lead is strictly limited. For example, the outer lead length of the chip package should be longer than a certain length, such as 0.3-0.5mm; limited by the lead frame processing accuracy, the space from the inside of the lead to the edge of the die (DiePaddle) needs to be longer than a certain distance, such as 0.15-0.2mm. In addition, in order to ensure the heat dissipation performance of the chip, silver glue is usually used to mount the die. In order to prevent the glue from overflowing the edge of the die, a safe area for glue overflow needs to be retained, which is usually 0.15-0.2mm. All these restrictions lead to the chip package being too large.
[0004] For chip on lead packaging, the chip substrate and the leads extending inward from each pin are in contact. In order to avoid short circuits between the pins, the bare die cannot be bonded with conductive adhesive, which results in poor heat dissipation performance of the chip. In addition, when non-conductive adhesive is used to bond the bare die, higher requirements are placed on the structural design of the chip package.
[0005] There are further improved requirements for traditional chip packaging. Summary of the invention
[0006] Embodiments of the present disclosure provide a method for packaging a chip and a chip package, aiming to solve one or more of the above problems and other potential problems.
[0007] According to the first aspect of the present disclosure, a method for packaging a chip is provided. The method comprises: providing a carrier board; arranging the first side of a bare die and a lead frame in a thickness direction on the surface of the carrier board and the bare die is separated from the lead frame by a distance in a horizontal plane, the horizontal plane being perpendicular to the thickness direction; forming a first dielectric layer covering the bare die and the lead frame on a second side in the thickness direction of the bare die and the lead frame, the second side being opposite to the first side; removing the carrier board; forming a first metal layer on a first surface of the bare die located on the first side, the first metal layer being in direct contact with the first surface of the bare die; forming a second dielectric layer covering the first metal layer on the first side of the bare die and the lead frame; forming a first via hole in the second dielectric layer connected to the first metal layer; and forming a first bare die interconnection layer interconnected with the first metal layer in the first via hole and on the outer surface of the second dielectric layer.
[0008] In some embodiments, the first metal layer extends laterally from the first surface of the die at least partially in the horizontal plane to form a pad connection area below the lead frame.
[0009] In some embodiments, the method further includes using the first die interconnect layer as a first pad for electrically connecting the chip to a corresponding pin on a circuit board.
[0010] In some embodiments, the method also includes: forming a second metal layer on the surface of the lead frame located on the first side, the second metal layer being in direct contact with the surface of the lead frame located on the first side; forming a second via hole in the second dielectric layer that is connected to the second metal layer; and forming a lead frame interconnection layer interconnected with the second metal layer in the second via hole and on the outer surface of the second dielectric layer.
[0011] In some embodiments, the lead frame interconnect layer is used as a second pad for electrically connecting the chip to corresponding pins on a circuit board.
[0012] In some embodiments, the method further includes: forming a third via in the second dielectric layer in an area corresponding to below the first surface of the die, and forming a second die interconnection layer interconnected with the first metal layer in the third via and on the outer surface of the second dielectric layer, the second die interconnection layer being connected to the first metal layer located below the first surface of the die through the third via.
[0013] In some embodiments, the method further includes using the second die interconnect layer as a third pad for electrically connecting the chip to a predetermined potential on a circuit board.
[0014] In some embodiments, the method also includes: before forming a first dielectric layer covering the die and the lead frame on the second side in the thickness direction of the die and the lead frame, it also includes: forming a rewiring layer on the second side of the die; before removing the carrier board, it also includes: forming a fourth via in the first dielectric layer, the fourth via being formed in an area corresponding to the surface above the die and the lead frame located on the second side; simultaneously with, before or after forming the first metal layer on the first surface of the die located on the first side: forming a metal interconnection layer in the fourth via and on the outer surface of the first dielectric layer and interconnecting the rewiring layer and the lead frame of the die to each other using the metal interconnection layer; and forming a third dielectric layer covering the formed metal interconnection layer and the first dielectric layer above the formed metal interconnection layer.
[0015] According to a second aspect of the present disclosure, a chip package is provided. The chip package includes: a die, including a top side and a bottom side in a thickness direction; a lead frame, spaced apart from the die by a gap in a horizontal direction, the horizontal direction being perpendicular to the thickness direction; a first dielectric layer, configured to cover the die and the lead frame and fill the gap between the die and the lead frame; a first metal layer, located on the bottom side of the die and at least partially in direct contact with the bottom side surface of the die; a second dielectric layer, located on the bottom side of the first metal layer and including a first via; and a first die interconnect layer, located on the bottom side surface of the second dielectric layer and interconnected with the first metal layer via the first via.
[0016] In some embodiments, the first metal layer at least partially extends laterally from the bottom side surface of the die and forms a pad connection area below the lead frame.
[0017] In some embodiments, the first die interconnect layer is configured as a first pad for electrically connecting the chip to a corresponding pin on a circuit board.
[0018] In some embodiments, the chip package also includes: a second metal layer, which is located on the bottom surface of the lead frame and is at least partially in direct contact with the bottom surface of the lead frame; a second via, which is located in the second dielectric layer and is connected to the second metal layer; and a lead frame interconnection layer, which is located on the bottom surface of the second dielectric layer and is interconnected with the second metal layer via the second via.
[0019] In some embodiments, the lead frame interconnect layer is configured as a second pad for electrically connecting the chip to a corresponding pin on a circuit board.
[0020] In some embodiments, the chip package also includes: a third via located in an area of the second dielectric layer corresponding to below the bottom surface of the die, and a second die interconnection layer located on the bottom surface of the second dielectric layer and interconnected with the first metal layer via the third via.
[0021] In some embodiments, the second die interconnect layer is configured as a third pad for electrically connecting the chip to a predetermined potential on a circuit board.
[0022] In some embodiments, the chip package further includes: a rewiring layer located on the top side of the die; a fourth via in the first dielectric layer and located in an area corresponding to above the top side surfaces of the die and the lead frame; a metal interconnection layer interconnecting the rewiring layer and the lead frame of the die to each other via the fourth via; and a third dielectric layer located above the metal interconnection layer and covering the metal interconnection layer and the first dielectric layer.
[0023] According to the present disclosure, when the die is in operation, the heat emitted by the die can be conducted through the first metal layer directly in contact with the bottom surface of the die, and then conducted to the first via and the first die interconnection layer, and finally released through the first die interconnection layer. As a result, the heat dissipation capability of the chip package is significantly enhanced compared to the conventional technology. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The above and other objects, features and advantages of the embodiments of the present disclosure will become readily understood by referring to the accompanying drawings and reading the following detailed description. In the accompanying drawings, several embodiments of the present disclosure are shown by way of example and not limitation.
[0025] Figure 1 A cross-sectional view of a chip package according to a first embodiment of the present disclosure is shown.
[0026] Figure 2a-2i Schematic diagrams of different manufacturing stages for manufacturing a chip package according to the first embodiment of the present disclosure are respectively shown.
[0027] Figure 3 A cross-sectional view of a chip package according to a second embodiment of the present disclosure is shown.
[0028] Figure 4a-4d Schematic diagrams of different manufacturing stages for manufacturing a chip package according to a second embodiment of the present disclosure are respectively shown.
[0029] In the various drawings, the same or corresponding reference numerals represent the same or corresponding parts. DETAILED DESCRIPTION
[0030] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.
[0031] In the following description, various specific details are shown to provide a deeper understanding of various examples of embodiments according to the description. Embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure aspects of the embodiments.
[0032] References to "one embodiment" or "some implementations" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment," "in some embodiments," etc., which may appear in various aspects of this specification, do not necessarily refer to exactly the same embodiment. Furthermore, particular configurations, structures, or characteristics may be combined in any appropriate manner in one or more embodiments.
[0033] In the present disclosure, directional terms such as "upper", "lower", "top side", "bottom side", "front", "back", "inside" and "outside" are defined relative to the orientation or position of the components schematically placed in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, rather than indicating or implying that the referred device or component must have a specific orientation, or be constructed and operated in a specific orientation. They may change accordingly according to the change of the orientation of the components placed in the drawings, and therefore cannot be understood as a limitation of the present application.
[0034] Figure 1 A cross-sectional view of a chip package 1 according to a first embodiment of the present disclosure is shown. Figure 1 The view shown corresponds to the position corresponding to the pins and shows the structural details inside the chip package 1. Figure 1 As shown, the chip package 1 includes a die 10 and one or more lead frames 20 arranged side by side with the die. The die 10 includes a top side and a bottom side in the thickness direction. The lead frame 20 is located at the lateral side of the die 10 and is separated from the die 10 by a gap. The first dielectric layer 40 is configured to cover the die 10 and the lead frame 20 and fill the gap between the die 10 and the wire, thereby electrically insulating the die 10 and the lead frame 20 from each other.
[0035] The first metal layer 30a is located on the bottom side of the die 10 and is at least partially in direct contact with the bottom side surface of the die 10. In some embodiments, Figure 1 As shown, the first metal layer 30a can extend across the entire bottom surface of the die. The second dielectric layer 50 is located on the bottom side of the first metal layer 30a, and the die 10 and the lead frame 20 can be electrically insulated from other components in the thickness direction through the second dielectric layer 50. The second dielectric layer 50 can be provided with one or more first vias 52a. The first die interconnection layer 60a is located below the second dielectric layer 50 and is interconnected with the first metal layer 30a via the first vias 52a.
[0036] According to the present disclosure, unlike the traditional QNF and COL packages, the die 10 and the lead frame 20 are arranged side by side, which reduces the requirements for the size of the chip package. In particular, the die 10 and the lead frame 20 are maintained by the first dielectric layer 40 and the second dielectric layer 50 located at different thicknesses, which avoids the use of glue to bond the die 10 and the lead frame 20. As a result, the problem of multiple sizes interfering with each other on the same mounting plane is avoided, and the size of the chip package can be effectively reduced. According to the structure of the chip package of the present disclosure, in the case of the same die size, the chip package size is smaller; in the case of the same chip package size, the die size can be larger, reducing the difficulty of chip design.
[0037] In addition, the side-by-side arrangement of the die 10 and the lead frame 20 also significantly enhances the heat dissipation capability of the die 10, which is particularly provided by the first metal layer 30a, the first via 52a and the first die interconnection layer 60a. When the die 10 is in operation, the heat dissipated by the die 10 can be conducted through the first metal layer 30a directly in contact with the bottom surface of the die 10, and then conducted to the first via 52a and the first die interconnection layer 60a, and finally released through the first die interconnection layer 60a. As a result, the heat dissipation capability of the chip package is significantly enhanced compared to the conventional technology.
[0038] In some embodiments, the first metal layer 30a at least partially extends laterally from the bottom surface of the die 10, and the first metal layer 30a can extend to the area where the lead frame 20 is located, and form a pad connection area located below the lead frame 20. In some embodiments, the first metal layer 30a can extend across the entire area below the lead frame 20. One or more first vias 52a can be formed in the second dielectric layer 50, and the first die interconnection layer 60a is interconnected with the first metal layer 30a via the first vias 52a. In the illustrated embodiment, four vias 52a are shown, which can significantly enhance the electrical / thermal conductivity between the first die interconnection layer 60a and the first metal layer 30a.
[0039] In some embodiments, the first die interconnect layer 60a is configured as a first pad for electrically connecting the chip to a corresponding pin on a circuit board. Figure 1 As shown, the first die interconnect layer 60a used as the first pad is formed at different thicknesses relative to the lead frame 20 and the die 10, which can avoid interference between multiple dimensions during chip packaging and further reduce the size requirements of the chip packaging.
[0040] In some embodiments, Figure 1 As shown, the chip package 1 may further include a second metal layer 30b. The second metal layer 30b is located on the bottom surface of the lead frame 20 and is at least partially in direct contact with the bottom surface of the lead frame 20. A second via 52b connected to the second metal layer 30b may be formed in the second dielectric layer 50. A lead frame interconnection layer 60b may be located on the bottom surface of the second dielectric layer 50 and is interconnected with the second metal layer 30b via the second via 52b. In some embodiments, the lead frame interconnection layer 60b is configured as a second pad for electrically connecting the chip to a corresponding pin on a circuit board.
[0041] In some embodiments, Figure 1 As shown, the chip package 1 may further include a rewiring layer 12 located on the top side of the die 10, and may be interconnected with other components (e.g., a lead frame) on the top side through the rewiring layer. One or more fourth vias 42 may be provided in the first dielectric layer 40. The fourth vias 42 may be located in an area corresponding to directly above the top side surfaces of the die 10 and the lead frame 20. The chip package 1 may further include a metal interconnection layer 70. The metal interconnection layer 70 interconnects the rewiring layer 12 of the die 10 and the lead frame 20 to each other via the fourth vias 42. Thus, the interconnection of the die 10 and the lead frame 20 may be achieved on the top side of the die 10 and the lead frame 20.
[0042] In some embodiments, the chip package 1 may further include a third dielectric layer 80 , which may be located above the metal interconnection layer 70 and cover the metal interconnection layer 70 and the first dielectric layer 40 . In some embodiments, the chip package 1 may further include a protective layer 90 .
[0043] Figure 2a-2i Schematic diagrams of different manufacturing stages for manufacturing a chip package according to the first embodiment of the present disclosure are respectively shown.
[0044] like Figure 2a As shown, the die 10 may include a top side 15 and a bottom side 13 in the thickness direction. A rewiring layer 12 may be formed on the wafer and the wafer may be cut into Figure 2a The bare die 10 is shown. Figure 2bAs shown, a carrier board 25 is provided, and the bare chip 10 and the lead frame 20 are arranged side by side on the surface of the carrier board 25. In a horizontal plane perpendicular to the thickness direction, the bare chip 10 and the lead frame 20 are separated from each other by a distance. In some embodiments, for example, in batch chip packaging, the lead frame can be an integral component, and a predetermined position is formed as shown in FIG. Figure 2b The bare die 10 and the lead frame 20 are arranged in the pattern shown. The bare die 10 is arranged in the space formed by the lead frame. In some embodiments, the bare die 10 and the lead frame 20 can be detachably mounted to the carrier board 25 via the detachable film 17. Considering that the bare die 10 and the lead frame 20 are arranged side by side on the surface of the carrier board 25 and do not require too high dimensional accuracy, these operations do not have to be performed in the chip packaging workshop. As an example, these operations can be performed in a circuit board processing workshop.
[0045] like Figure 2c As shown, a first dielectric layer 40 may be formed on the second side 15 in the thickness direction of the die 10 and the lead frame 20. The first dielectric layer 40 may electrically insulate the die 10 and the lead frame 20 from each other and may also support the die 10 and the lead frame 20. Figure 2d As shown, a fourth via hole 42 is formed in the first dielectric layer 40, and the fourth via hole 42 is formed in a region corresponding to the surface of the die 10 and the lead frame 20 located above the second side 15. For example, it can be formed by laser drilling. Figure 2e As shown, the carrier plate 25 is removed.
[0046] like Figure 2f As shown, a first metal layer 30a may be formed on the first surface of the die 10 located on the first side 13, and the first metal layer 30a is in direct contact with the first surface of the die 10. In some embodiments, as Figure 2f As shown, a second metal layer 30b may also be formed on the surface of the lead frame 20 located on the first side 13, and the second metal layer 30b is in direct contact with the surface of the lead frame 20 located on the first side 13. Figure 2f As shown, a metal interconnection layer 70 may also be formed on the surface of the bare die 10 and the lead frame 20 located on the second side 15, and the metal interconnection layer 70 interconnects the bare die 10 and the lead frame 20. In some embodiments, a seed layer may be first deposited by scattered plating, and then the first metal layer 30a, the second metal layer 30b and / or the metal interconnection layer 70 are formed by electroplating or metal lamination. It should be understood that the formation of the first metal layer 30a, the second metal layer 30b and / or the metal interconnection layer 70 may be performed independently of each other or simultaneously, which may be implemented, for example, by single-sided or double-sided operations.
[0047] like Figure 2gAs shown, a second dielectric layer 50 covering the first metal layer 30a is formed on the first side 13 of the die 10 and the lead frame 20. A third dielectric layer 80 covering the metal interconnect layer 70 is formed on the second side 15 of the die 10 and the lead frame 20. Figure 2h As shown, a first via hole 52a connected to the first metal layer 30a is formed in the second dielectric layer 50. The first via hole 52a can be formed below the first metal layer 30a to facilitate interconnection with the first metal layer 30a via the first via hole 52a. In some embodiments, as Figure 2h As shown, in the same process or in a different process as the formation of the first via 52a, a second via 52b connected to the second metal layer 30b is formed in the second dielectric layer 50. The second via 52b can be formed below the second metal layer 30b to facilitate interconnection with the second metal layer 30b through the second via 52b.
[0048] like Figure 2i As shown, a first die interconnection layer 60a interconnected with the first metal layer 30a is formed in the first via 52a and on the outer surface (i.e., the bottom surface in the figure) of the second dielectric layer 50. When the chip is mounted on the circuit board, the first die interconnection layer 60a can be used as a first pad to electrically connect the chip to the corresponding pin on the circuit board. In some embodiments, a protective layer 92, such as Sn, can also be provided on the first die interconnection layer 60a.
[0049] In some embodiments, Figure 2i As shown, a lead frame interconnection layer 60b interconnected with the second metal layer 30b is formed in the second via hole 52b and on the outer surface of the second dielectric layer 50. When the chip is mounted on the circuit board, the lead frame interconnection layer 60b can be used as a second pad for electrically connecting the chip to the corresponding pins on the circuit board. In some embodiments, a protective layer 92, such as Sn, can also be provided on the lead frame interconnection layer 60b.
[0050] Figure 3 A cross-sectional view of a chip package 1 according to a second embodiment of the present disclosure is shown. Figure 3 The embodiment shown is similar to the embodiment shown in FIG2 . The difference from the embodiment shown in FIG2 is that: Figure 3 The chip package 1 of the illustrated embodiment further includes a ground pad for providing a ground potential for the die, which is particularly useful in applications where an independent ground potential is required for the die. Figure 3 The cross-sectional view shown corresponds to the position corresponding to the ground pad of the die and shows the structural details inside the chip package 1. Figure 3 Examples and Figure 1 The similarities of the embodiments shown are described herein, and the differences are mainly described, while the description of the identical parts is omitted.
[0051] like Figure 3 As shown, the chip package 1 also includes a third via 52c located in the second dielectric layer 50. The third via 52c can be located in an area corresponding to the bottom surface of the die 10, so as to be electrically connected to the bottom surface of the die 10 through the third via 52c. The second die interconnection layer 60c can be located on the bottom surface of the second dielectric layer 50 and interconnected with the third metal layer 30c via the third via 52c. Thus, the ground connection of the chip can be conveniently provided through the third via 52c and the second die interconnection layer 60c. The second die interconnection layer 60b can be a third pad that electrically connects the chip to a predetermined potential on the circuit board. The heat dissipation capacity of the chip package 1 can also be further enhanced by this arrangement.
[0052] Figure 4a-4d Schematic diagrams of different manufacturing stages for manufacturing a chip package according to a second embodiment of the present disclosure are respectively shown. Figure 4a-4d The embodiment shown is Figure 2a-2i The embodiments shown are similar and the description will focus on the differences.
[0053] like Figure 4a As shown, in addition to the first metal layer 30a and the second metal layer 30b, a third metal layer 30c may be formed on the bottom surface of the die 10, and the third metal layer 30c is in direct contact with the first surface of the die 10. It should be understood that the third metal layer 30c may be formed by the same or different process as the first metal layer 30a, the second metal layer 30b and / or the metal interconnection layer 70. Figure 4b and Figure 2g Similar, such as Figure 4b As shown, after the third metal layer 30 c is formed, a second dielectric layer 50 is formed on the bottom side surfaces of the die 10 and the lead frame 20 to cover the third metal layer 30 c. Figure 4c and Figure 2h Similar, such as Figure 4c As shown, a third via hole 52c connected to the third metal layer 30c is formed in the second dielectric layer 50. The third via hole 52c can be formed below the third metal layer 30c so as to interconnect with the third metal layer 30c through the third via hole 52c. In some embodiments, the third via hole 52c can be formed in the same process or in different processes as the first via hole 52a and the second via hole 52b. Figure 4d and Figure 2i As shown, Figure 4dAs shown, a second die interconnection layer 60b interconnected with the third metal layer 30c is formed in the third via 52c and on the outer surface (i.e., the bottom surface in the figure) of the second dielectric layer 50. When the chip is mounted on the circuit board, the second die interconnection layer 60b can be used as a third pad, such as a ground pad, to electrically connect the chip to the corresponding pin on the circuit board. In some embodiments, a protective layer 92, such as Sn, can also be provided on the second die interconnection layer 60b.
[0054] In addition, although each operation is described in a specific order, this should be understood as requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination mode.
[0055] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.
[0056] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.
Claims
1. A method for packaging a chip, comprising: Providing a carrying plate (25); Arranging the first side (13) of the bare chip (10) and the lead frame (20) in the thickness direction on the surface of the carrier board (25) and the bare chip (10) and the lead frame (20) are spaced apart from each other by a distance in a horizontal plane, wherein the horizontal plane is perpendicular to the thickness direction; forming a first dielectric layer (40) covering the die (10) and the lead frame (20) on a second side (15) in the thickness direction of the die (10) and the lead frame (20), the second side (15) being opposite to the first side (13); removing the carrying plate (25); forming a first metal layer (30a) on a first surface of the die (10) located on the first side (13), wherein the first metal layer (30a) is in direct contact with the first surface of the die (10); forming a second dielectric layer (50) covering the first metal layer (30a) on the bare chip (10) and the first side (13) of the lead frame (20); forming a first via hole (52a) in the second dielectric layer (50) and communicating with the first metal layer (30a); and A first bare chip interconnection layer (60a) interconnected with the first metal layer (30a) is formed in the first via hole (52a) and on the outer surface of the second dielectric layer (50).
2. The method of claim 1, wherein the first metal layer (30a) extends laterally from the first surface of the die (10) at least partially in the horizontal plane to form a pad connection area below the lead frame (20).
3. The method of claim 2, wherein the method further comprises using the first die interconnect layer (60a) as a first pad for electrically connecting the chip to a corresponding pin on a circuit board.
4. The method according to claim 1, further comprising: forming a second metal layer (30b) on the surface of the lead frame (20) located on the first side (13), wherein the second metal layer (30b) is in direct contact with the surface of the lead frame (20) located on the first side (13); forming a second via hole (52b) in the second dielectric layer (50) and communicating with the second metal layer (30b); and A lead frame interconnection layer (60b) interconnected with the second metal layer (30b) is formed in the second via hole (52b) and on the outer surface of the second dielectric layer (50).
5. The method of claim 4, wherein the lead frame interconnect layer (60b) is used as a second pad for electrically connecting the chip to a corresponding pin on a circuit board.
6. The method according to claim 1, further comprising: forming a third via hole (52c) in the second dielectric layer (50) at a region corresponding to below the first surface of the die (10); and A second die interconnection layer (60c) interconnected with the first metal layer (30a) is formed in the third via hole (52c) and on the outer surface of the second dielectric layer (50); the second die interconnection layer (60c) is connected to the first metal layer (30a) located below the first surface of the die (10) through the third via hole (52c).
7. The method according to claim 6, wherein the method further comprises using the second die interconnect layer (60c) as a third pad for electrically connecting the chip to a predetermined potential on a circuit board.
8. The method according to any one of claims 1 to 7, wherein: Before forming a first dielectric layer (40) covering the die (10) and the lead frame (20) on the second side (15) in the thickness direction of the die (10) and the lead frame (20), the method further includes: forming a rewiring layer (12) on the second side (15) of the die (10); Before removing the carrier plate (25), the method further includes: forming a fourth via hole (42) in the first dielectric layer (40), wherein the fourth via hole (42) is formed in an area corresponding to a surface of the bare chip (10) and the lead frame (20) located on the second side (15); Simultaneously with, before or after forming a first metal layer (30a) on a first surface of the die (10) on the first side (13): forming a metal interconnection layer (70) in the fourth via hole (42) and on an outer surface of the first dielectric layer (40) and interconnecting the rewiring layer (12) of the die (10) and the lead frame (20) with each other using the metal interconnection layer (70); and A third dielectric layer (80) is formed above the metal interconnection forming layer (70) to cover the metal interconnection forming layer (70) and the first dielectric layer (40).
9. A chip package, comprising: A bare die (10), comprising a top side and a bottom side in a thickness direction; A lead frame (20) is spaced apart from the bare chip (10) by a gap in a horizontal direction, wherein the horizontal direction is perpendicular to the thickness direction; A first dielectric layer (40) configured to cover the die (10) and the lead frame (20) and fill a gap between the die (10) and the lead frame; A first metal layer (30a) located on the bottom side of the die (10) and at least partially in direct contact with the bottom side surface of the die (10); A second dielectric layer (50) located on the bottom side of the first metal layer (30a) and comprising a first via hole (52a); as well as A first bare die interconnection layer (60a) is located on the bottom side surface of the second dielectric layer (50) and is interconnected with the first metal layer (30a) via the first via (52a).
10. The chip package according to claim 9, wherein the first metal layer (30a) at least partially extends laterally from the bottom side surface of the die (10) and forms a pad connection area located below the lead frame (20).
11. The chip package according to claim 10, wherein the first die interconnect layer (60a) is configured as a first pad for electrically connecting the chip to a corresponding pin on a circuit board.
12. The chip package according to claim 11, further comprising: a second metal layer (30b), the second metal layer (30b) being located on the bottom surface of the lead frame (20) and at least partially in direct contact with the bottom surface of the lead frame (20); A second via hole (52b) located in the second dielectric layer (50) and connected to the second metal layer (30b); as well as A lead frame interconnection layer (60b) is located on the bottom surface of the second dielectric layer (50) and is interconnected with the second metal layer (30b) via the second via hole (52b).
13. The chip package according to claim 12, wherein the lead frame interconnect layer (60b) is configured as a second pad for electrically connecting the chip to a corresponding pin on a circuit board.
14. The chip package according to claim 9, further comprising: a third via hole (52c) located in the second dielectric layer (50) in a region corresponding to below the bottom surface of the die (10); and A second bare die interconnect layer (60c) is located on the bottom surface of the second dielectric layer (50) and is interconnected with the first metal layer (30a) via the third via (52c).
15. The chip package according to claim 14, wherein the second die interconnect layer (60b) is configured as a third pad for electrically connecting the chip to a predetermined potential on a circuit board.
16. The chip package according to any one of claims 9 to 15, further comprising: a redistribution layer (12) located on the top side of the die (10); a fourth via (42) in the first dielectric layer (40) and located in an area corresponding to above the top side surfaces of the die (10) and the lead frame (20); A metal interconnection layer (70) interconnecting the rewiring layer (12) of the die (10) and the lead frame (20) via the fourth via (42); as well as A third dielectric layer (80) is located above the metal interconnection layer (70) and covers the metal interconnection layer (70) and the first dielectric layer (40).