Main control framework of energy storage converter

Abstract

The invention discloses an energy storage converter master control framework which comprises a DSP chip and a ZYNQ chip which are connected through a bus, the DSP chip is connected with a first AD sampling circuit and a DO control circuit, and the ZYNQ chip is connected with a second AD sampling circuit and an SD card circuit. The second AD sampling circuit comprises two AD chips, the first AD chip is respectively connected with a sampling signal input circuit of IA, IB and IC three-phase inversion current and a sampling signal input circuit of UA, UB and UC three-phase inversion voltage, and the second AD chip is respectively connected with a sampling signal input circuit of UgA, UgB and UgC three-phase AC side power grid voltage and a sampling signal input circuit of Udc1 and Udc2 two-path DC bus voltage. And a sampling signal input circuit of the direct current Idc. According to the invention, the DSP (TMS320F28335) and the ZYNQ (XC7Z020) are adopted as the main control chip, and other auxiliary peripheral circuits are configured for design, so that the system can be suitable for various types of energy storage converters.

Description

Technical Field

[0001] The present invention relates to the electric power industry, and in particular to a main control architecture of an energy storage converter. Background Art

[0002] The main control architecture of the energy storage converter determines the functions it implements. Currently, most energy storage converters in the industry use DSP+FPGA or DSP+ARM main control architecture. In this architecture, DSP is mainly used to implement control algorithms, and FPGA or ARM is responsible for processing some logic or communication functions.

[0003] With the development of market demand, various remote data transmission and real-time monitoring have become an indispensable part of the functions of energy storage inverters. These traditional main control architectures are stretched to the limit in the face of diversified demands. In order to solve such problems, some communication equipment has to be added separately, which undoubtedly increases the design cost and subsequent maintenance cost. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a main control architecture of an energy storage converter which adopts DSP (TMS320F28335) + ZYNQ (XC7Z020) as a main control chip and is configured with other auxiliary peripheral circuits for design and can be applied to various types of energy storage converters.

[0005] The object of the present invention is achieved through the following technical solutions: a main control architecture of an energy storage converter, comprising a DSP chip and a ZYNQ chip connected through a bus, the DSP chip being connected to a first AD sampling circuit and a DO control circuit respectively, and the ZYNQ chip being connected to a second AD sampling circuit and an SD card circuit respectively;

[0006] The ZYNQ chip uses XC7Z020, and the second AD sampling circuit includes two AD chips, both of which use ADS8555; the Y20, Y21, AA21, U19, T21, and U21 pins of the ZYNQ chip are connected to the first AD chip through a connector, and the first AD chip is respectively connected to the sampling signal input circuit of the three-phase inverter current IA, IB, and IC and the sampling signal input circuit of the three-phase inverter voltage UA, UB, and UC; the C19, D18, A22, B21, C20, and E19 pins of the ZYNQ chip are connected to the second AD chip through a connector, and the second AD chip is respectively connected to the sampling signal input circuit of the three-phase AC side grid voltage UgA, UgB, and UgC, the sampling signal input circuit of the two DC bus voltages Udc1 and Udc2, and the sampling signal input circuit of the DC current Idc;

[0007] The DSP chip adopts TMS320F28335, the first AD sampling circuit is a three-phase load current sampling circuit, and the 40, 41, and 42 pins of the DSP chip are respectively connected to the I_loadA, I_loadB, and I_loadC three-phase load current sampling circuits.

[0008] The beneficial effects of the present invention are: the present invention adopts DSP (TMS320F28335) + ZYNQ (XC7Z020) as the main control chip, and configures other auxiliary peripheral circuits for design, which can be applied to various types of energy storage converters. It has the following advantages:

[0009] 1. The price of ZYNQ chip is much lower than that of FPGA+ARM, so it can greatly reduce the cost of hardware design.

[0010] 2. Traditional FPGAs cannot support operating system operation, and ARM cannot implement programmable logic. ZYNQ combines a dual-core ARM Cortex-A9 processor and a Xilinx 7 series FPGA, providing the performance of ASIC and the flexibility of FPGA. This combination enables ZYNQ to perform well in handling complex computing tasks while maintaining a high degree of programmability.

[0011] 3. ZYNQ can perfectly support the Linux operating system. Various apps developed on this operating system can help developers develop and debug applications more efficiently, allowing engineers or users to control device status more easily. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a structural schematic diagram of the main control architecture of the energy storage converter of the present invention;

[0013] Figure 2 The three-phase load current sampling circuit diagram of the present invention;

[0014] Figure 3 This is the circuit diagram of the AD chip;

[0015] Figure 4 The circuit diagram of the sampling signal input circuit of the IA inverter current;

[0016] Figure 5 The circuit diagram of the sampling signal input circuit of the UA inverter voltage;

[0017] Figure 6 A circuit diagram of a signal test circuit;

[0018] Figure 7 The circuit diagram of the 2.5V reference voltage conversion circuit;

[0019] Figure 8This is the DSP chip bus data schematic diagram;

[0020] Fig. 9 This is the schematic diagram of the ZYNQ chip bus data;

[0021] Fig.10 This is the schematic diagram of the DSP chip bus address;

[0022] Fig.11 This is the schematic diagram of the ZYNQ chip bus address;

[0023] Fig.12 This is the schematic diagram of the DSP end of the SPI interface;

[0024] Fig.13 This is the circuit diagram of the level conversion chip;

[0025] Fig.14 This is the SPI interface circuit diagram of the ZYNQ chip;

[0026] Fig.15 is a circuit diagram of a driving circuit;

[0027] Fig.16 This is the circuit diagram of the TXS02612RTWR level conversion chip;

[0028] Fig.17 This is the circuit diagram of the PHY chip;

[0029] Fig.18 This is the circuit diagram of the G24P02S network port transformer;

[0030] Fig.19 This is the circuit diagram of the RJ45 network port terminal. DETAILED DESCRIPTION

[0031] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0032] like Figure 1 As shown, a main control architecture of an energy storage converter of the present invention includes a DSP chip and a ZYNQ chip connected through a bus, the DSP chip is respectively connected to a first AD sampling circuit and a DO control circuit, and the ZYNQ chip is respectively connected to a second AD sampling circuit and an SD card circuit;

[0033] The ZYNQ chip uses XC7Z020, and the second AD sampling circuit includes two AD chips, both of which use ADS8555; the Y20, Y21, AA21, U19, T21, and U21 pins of the ZYNQ chip are connected to the first AD chip through a connector, Y20 corresponds to the 5th pin of an AD chip, Y21 corresponds to the 11th pin of an AD chip, AA21 corresponds to the 28th pin of an AD chip, U19 corresponds to the 7th pin of an AD chip, T21 corresponds to the 5th pin of an AD chip, and U21 corresponds to the 6th pin of an AD chip; the first AD chip is used to collect the three-phase inverter currents of IA, IB, and IC and the three-phase inverter currents of UA, UB, and UC. voltage, respectively connected to the sampling signal input circuit of the three-phase inverter current IA, IB, IC and the sampling signal input circuit of the three-phase inverter voltage UA, UB, UC; the C19, D18, A22, B21, C20, E19 pins of the ZYNQ chip are connected to the second AD chip through a connector, and the second AD chip is used to collect the three-phase AC side grid voltage UgA, UgB, UgC, the two-way DC bus voltage Udc1, Udc2 and the DC current Idc, and are respectively connected to the sampling signal input circuit of the three-phase AC side grid voltage UgA, UgB, UgC, the sampling signal input circuit of the two-way DC bus voltage Udc1, Udc2, and the sampling signal input circuit of the DC current Idc;

[0034] IA, IB, IC, UA, UB, UC are all AC signals collected from the inverter side; UgA, UgB, UgC are AC signals collected from the AC grid side; Udc1, Udc2, Idc are DC signals collected from the DC side. These signals are sent from the analog sampling board (HX30002-20WA) terminals, which are connected to the external analog sampling board.

[0035] The DSP chip uses TMS320F28335, the first AD sampling circuit is a three-phase load current sampling circuit, and the 40, 41, and 42 pins of the DSP chip are connected to the I_loadA, I_loadB, and I_loadC three-phase load current sampling circuits respectively. Figure 2 As shown, the three-phase load current sampling circuit includes a Schottky diode, an inductor and a capacitor. Pin 1 of the Schottky diode is grounded, pin 2 is connected to a 3.3V power supply, pin 3 is connected to the capacitor, and the other end of the capacitor is grounded; one end of the capacitor connected to the Schottky diode is connected to the inductor, and the end connected to the inductor is the sampling signal input end, and the other end of the inductor is the output section.

[0036] The structures of the sampling signal input circuits of the three-phase inverter currents IA, IB, and IC, the sampling signal input circuits of the two-way DC bus voltages Udc1 and Udc2, and the sampling signal input circuit of the DC current Idc are all the same; the circuit of the first AD chip is as follows Figure 3 As shown, the output signals of the sampling signal input circuit of the three-phase inverter current IA, IB, IC are respectively connected to the 33, 36, 39 pins of the first AD chip, that is, the ADCH0, ADCH1 and ADCH2 signals on the way; the output signals of the sampling signal input circuit of the two-way DC bus voltage Udc1 and Udc2 and the sampling signal input circuit of the DC current Idc are respectively connected to the 42, 45, 48 pins of the second AD chip.

[0037] The AD chip also includes some peripheral circuits that are not related to sampling. The 19th and 18th pins of the AD chip are connected to the AD chip select signal AD1_FSen and the AD chip busy indication signal AD1_BSYINT after being connected in series with a resistor. The former is controlled by the ZYNQ chip through a connector, and the latter is sent by the AD chip to the ZYNQ chip through a connector. The 21st, 22nd, and 23rd pins of the AD chip are connected in parallel and connected to the chip conversion start signal AD1_CONVST through a resistor. This signal is controlled by the ZYNQ chip through a connector. The 11th pin of the AD chip is connected to the AD chip data transmission clock signal AD1_CLK through a resistor. This signal is controlled by the ZYNQ chip through a connector. AD1_SODA, AD1_SODB, and AD1_SODC are the conversion data output by the AD chip. These three data signals are sent to the ZYNQ chip through a connector and are connected to the 7th, 6th, and 5th pins of the AD chip, respectively.

[0038] The sampling signal input circuit includes two operational amplifiers, a first Schottky diode, multiple capacitors and resistors. The operational amplifier uses LM2904, and the first Schottky diode uses BAR43S. The specific circuit is as follows Figure 4 As shown (taking the sampling signal input circuit of IA inverter current as an example).

[0039] A first resistor and a second resistor are connected in series, the other end of the first resistor is connected to the input signal, the other end of the second resistor is connected to pin 3 of the first operational amplifier, pin 1 of the first operational amplifier is connected in series with the third resistor and then connected to pin 6 of the second operational amplifier, pin 7 of the second operational amplifier is connected in series with a fourth resistor, the other end of the fourth resistor is a sampling signal output end, and is connected to the first AD chip;

[0040] Pin 1 and pin 2 of the first operational amplifier are connected, and pin 8 and pin 4 are connected to the positive and negative poles of the power supply respectively;

[0041] The common end of the first Schottky diode is connected between the second resistor and the first operational amplifier, and the positive electrode and the negative electrode of the first Schottky diode are connected to the negative electrode and the positive electrode of the power supply respectively;

[0042] One end of the fifth resistor is connected between the first resistor and the signal input port, and the other end is grounded; one end of the sixth resistor is connected between the first resistor and the second resistor, and the other end is grounded; one end of the first capacitor is connected between the second resistor and the first operational amplifier, and the other end is grounded; pin 5 of the second operational amplifier is connected to the seventh resistor, and the other end of the seventh resistor is grounded; the eighth resistor and the second capacitor are connected in parallel, and the parallel circuit is connected between pins 6 and 7 of the second operational amplifier; one end of the third capacitor is connected between the fourth resistor and the sampling signal output terminal, and the other end is grounded.

[0043] The structures of the sampling signal input circuits of the three-phase inverter voltages UA, UB, and UC and the sampling signal input circuits of the three-phase AC side grid voltages UgA, UgB, and UgC are the same. The output signals of the sampling signal input circuits of the three-phase inverter voltages UA, UB, and UC are connected to the 42nd, 45th, and 48th pins of the first AD chip, respectively. Figure 3 ADCH3, ADCH4 and ADCH5 signals in; the output signals of the sampling signal input circuit of the three-phase AC side grid voltage UgA, UgB, UgC are connected to the 33, 36, 39 pins of the second AD chip respectively;

[0044] The sampling signal input circuit includes three operational amplifiers, a second Schottky diode, multiple capacitors and resistors. The operational amplifier uses LM2904, and the second Schottky diode uses BAR43S. The specific circuit is as follows Figure 5 As shown (taking the sampling signal input circuit of UA inverter voltage as an example).

[0045] The ninth resistor and the tenth resistor are connected in series, the other end of the ninth resistor is connected to the signal input end, and the other end of the tenth resistor is connected to the 3rd pin of the third operational amplifier; the 1st pin and the 2nd pin of the third operational amplifier are connected, and the 8th pin and the 4th pin are respectively connected to the positive and negative poles of the power supply; the 1st pin of the third operational amplifier is connected in series with the 11th resistor and then connected to the 6th pin of the fourth operational amplifier, the 7th pin of the fourth operational amplifier is connected to the 12th resistor and then connected to the 5th pin of the fifth operational amplifier, the 7th pin of the fifth operational amplifier is connected in series with the 13th resistor, and the other end of the 13th resistor is the sampling signal output end, which is connected to the first AD chip;

[0046] The common end of the second Schottky diode is connected between the tenth resistor and the third operational amplifier, and the positive electrode and the negative electrode of the second Schottky diode are connected to the negative electrode and the positive electrode of the power supply respectively;

[0047] One end of the fourteenth resistor is connected between the ninth resistor and the signal input port, and the other end is grounded; one end of the fifteenth resistor is connected between the ninth resistor and the tenth resistor, and the other end is grounded; one end of the fourth capacitor is connected between the tenth resistor and the third operational amplifier, and the other end is grounded; one end of the sixteenth resistor is connected to the 5th pin of the fourth operational amplifier, and the other end is grounded; the seventeenth resistor and the fifth capacitor are connected in parallel, and the parallel circuit is connected between the 6th pin and the 7th pin of the fourth operational amplifier, and the connection end of the parallel circuit connected to the 7th pin of the fourth operational amplifier is connected to the eighteenth resistor, and the other end of the eighteenth resistor is the test signal output point;

[0048] Pin 6 and pin 7 of the fifth operational amplifier are connected to each other; one end of the sixth capacitor is connected between the thirteenth resistor and the signal output port, and the other end is grounded.

[0049] The test signal output point is connected to an external signal test circuit, which includes a sixth operational amplifier, six resistors and two capacitors. The sixth operational amplifier uses LM2903. The specific circuit is as follows Figure 6 As shown; one end of the nineteenth resistor is connected to the test signal output by the eighteenth resistor, and the other end is connected to the 6th pin of the sixth operational amplifier; one end of the seventh capacitor is connected between the nineteenth resistor and the sixth operational amplifier, and the other end is grounded; the twentieth resistor, the twenty-first resistor and the twenty-second resistor are connected in series, the other end of the twentieth resistor is grounded, and the other end of the twenty-second resistor is connected to the positive pole of the power supply; the 6th pin of the sixth operational amplifier is connected to the series end of the twentieth resistor and the twenty-first resistor, and the 7th pin is connected to the series end of the twenty-first resistor and the twenty-second resistor; at the same time, the 7th pin of the sixth operational amplifier is also connected to the twenty-third resistor, and the other end of the twenty-third resistor is the test signal output end; the twenty-fourth resistor and the eighth capacitor are connected in parallel, one end of the parallel circuit is connected to the output end of the twenty-third resistor, and the other end is grounded. After passing through this circuit, the voltage signal is converted into this FREQ0 square wave signal, and then the voltage frequency can be obtained by measuring the test point with an oscilloscope. The function of this signal is to monitor the voltage frequency.

[0050] The 31 and 30 pins of the AD chip are connected to the positive and negative electrodes of the 15V power supply respectively, and the 51 pin is connected to the 2.5V reference voltage conversion circuit. The 2.5V reference voltage conversion circuit is used to convert the 5V power supply into a 2.5V reference voltage, and then transmit it to the AD chip. The circuit is as shown in FIG. Figure 7As shown; the 2.5V reference voltage conversion circuit includes a seventh operational amplifier, two inductors, six capacitors and a voltage reference chip, the seventh operational amplifier adopts TP1281L1, and the voltage reference chip is REF3025AIDBZR; the two inductors are connected in parallel, one end of the parallel inductor is connected to the input voltage of 5V, and the other end is connected to the 1 pin of the voltage reference chip; the ninth capacitor, the tenth capacitor, and the eleventh capacitor are connected in parallel, one end of the three parallel capacitors is connected between the 1 pin of the voltage reference chip and the inductor, and the other end is respectively connected to the 3 pin of the voltage reference chip and the twelfth capacitor, and the voltage reference A twelfth capacitor is connected across pins 3 and 2 of the chip, and the connection point between pin 2 of the voltage reference chip and the twelfth capacitor is respectively connected to pin 3 of the seventh operational amplifier, and a test point is led out at the connection point, which is recorded as VF-2.5; pins 5 and 2 of the seventh operational amplifier are respectively connected to the positive and negative poles of the power supply, and pins 1 and 4 are connected. Pin 1 of the seventh operational amplifier is an output pin, which outputs a reference voltage of 2.5V; the thirteenth capacitor and the fourteenth capacitor are connected in parallel, one end of the two parallel capacitors is connected between pin 1 of the seventh operational amplifier and the output port, and the other end is grounded.

[0051] The bus between the DSP chip and the ZYNQ chip is connected by a parallel bus and an SPI bus. The parallel bus mode is: the DSP chip and the ZYNQ chip are connected by a parallel data bus; Figure 8 , Fig. 9 They are respectively the DSP chip bus data schematic diagram and the ZYNQ chip bus data schematic diagram. In the figure, CPU_D represents the parallel data bus between the two. Fig.10 , Fig.11 They are the DSP chip bus address schematic diagram and the ZYNQ chip bus address schematic diagram, respectively. In the figure, CPU_A represents the parallel address line between the two. Through these two types of connections, the two can achieve high-speed parallel data interaction. The 176, 175, 174, 172, 169, 168 and other pins of the DSP chip are connected to the V12, W12, W20, W21 and other pins of the ZYNQ chip to form the parallel communication address line between the two; the 115, 116, 119 and other pins of the DSP chip are connected to the J16, J17, D16 and other pins of the ZYNQ chip to form the parallel communication data line between the two.

[0052] The SPI bus mode is: the 96, 97, 98, and 99 pins of the DSP chip are connected to the G7, B4, C5, and A6 pins of the ZYNQ chip through a level conversion chip model LSF0204RUTR to achieve serial communication. Fig.12 , Fig.13 , Fig.14They are the schematic diagram of the SPI interface DSP end, the circuit diagram of the level conversion chip and the circuit diagram of the SPI interface of the ZYNQ chip. Through this circuit, SPI communication between the two can be achieved.

[0053] The H17 and H18 pins of the ZYNQ chip are connected to the driving circuit through connectors, respectively, and the PWM driving waveform and the wave-sealing signal generated by the ZYNQ chip are sent to the driving circuit; the driving circuit includes a driver of model SN75451, and the 2 and 4 pins of the driver are connected to the H17 and H18 pins of the ZYNQ chip respectively, and the 3 and 5 pins of the driver transmit the PWM driving waveform and the wave-sealing signal to the optical fiber transmitter of model HFBR1521 respectively, and the PWM driving waveform and the wave-sealing signal are sent to the external driving board through the optical fiber transmitter, and the power unit is driven to be turned on and off through the external driving board (the driving board and the power unit are connected together through the DB25 line, and the two are packaged in the same box, and the power unit is used for switching between AC and DC, which is equivalent to a switch), so as to realize the conversion between AC and DC. Two resistors are connected in parallel between the connection ends of the two optical fiber transmitters and the driver.

[0054] An inverter chip 74HCT14 and a resistor are also connected between the H17 pin of the ZYNQ chip and the 2 pin of the driver. The 1 pin of the inverter chip is connected to the H17 pin of the ZYNQ chip, the 2 pin is connected in series with the resistor and then connected to the 2 pin of the driver, the 14 pin of the inverter chip is connected to the power supply as shown in the figure, and a resistor is connected between the 1 pin and the 7 pin; the 2 pin of the inverter chip is connected in series with a resistor and then connected to the power supply. Another inverter chip 74HCT14 and a resistor are also connected between the H18 pin of the ZYNQ chip and the 4 pin of the driver. The 2 pin of the inverter chip is connected to the H18 pin of the ZYNQ chip, the 4 pin is connected in series with the resistor and then connected to the 4 pin of the driver; the 3 pin of the inverter chip is connected in parallel with a resistor, and the other end of the resistor is grounded; the 4 pin of the inverter chip is connected to another resistor in series with the resistor and then connected to the power supply.

[0055] The SD card circuit includes a level conversion chip, an SD card slot and an SD card; the ZYNQ chip is connected to the SD card slot through a level conversion chip model TXS02612RTWR, and the SD card is connected through the SD card slot to complete data storage; the E14, C8, D8, B11, E13, and B9 pins of the ZYNQ chip are respectively connected to the 9, 4, 6, 7, 1, and 3 pins of the TXS02612RTWR level conversion chip. The circuit of the level conversion chip is as shown in FIG. Fig.16 shown.

[0056] The pins D6, E9, A7, E10, A8, F11, A14, E11, B7, F12, A13, and D7 of the ZYNQ chip are connected to the pins 21, 19, 18, 17, 16, 20, 28, 26, 25, 24, 23, and 27 of the network port PHY chip model YT8521SC; the PHY chip is connected to the RJ45 network port terminal through the network port transformer model G24P02S. The circuit of the PHY chip is as follows: Fig.17 As shown; the 2, 3, 4, 5, 6, 7, 8, 10, 11 pins of the PHY chip are connected to the 2, 3, 5, 6, 8, 9, 11, 12 pins of the G24P02S network port transformer respectively. The circuit of the G24P02S network port transformer is as follows Fig.18 As shown; the 23, 22, 20, 19, 17, 16, 14, 13 pins of the G24P02S network port transformer are connected to the 1, 2, 3, 4, 5, 6, 7, 8 pins of the RJ45 network port terminal respectively. Fig.19 As shown, the network port is used to connect to the WEB or cloud. Pins 1, 4, 7, and 10 of the PHY chip are grounded, and pins 15, 18, 21, and 24 are connected in series with an inductor and then grounded.

[0057] The DO control circuit includes a driver and a Darlington transistor. The DSP chip is connected to a driver of model 74HCT245 through a connector. The driver is connected to a Darlington transistor of model ULQ2003ADR. The DO signal is outputted from the 14th pin of the Darlington transistor.

[0058] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the present invention.

Claims

1. A main control architecture of an energy storage converter, characterized in that: It includes a DSP chip and a ZYNQ chip connected via a bus, the DSP chip is respectively connected to a first AD sampling circuit and a DO control circuit, and the ZYNQ chip is respectively connected to a second AD sampling circuit and an SD card circuit; The ZYNQ chip uses XC7Z020, and the second AD sampling circuit includes two AD chips, both of which use ADS8555; the Y20, Y21, AA21, U19, T21, and U21 pins of the ZYNQ chip are connected to the first AD chip through a connector, and the first AD chip is respectively connected to the sampling signal input circuit of the three-phase inverter current IA, IB, and IC and the sampling signal input circuit of the three-phase inverter voltage UA, UB, and UC; the C19, D18, A22, B21, C20, and E19 pins of the ZYNQ chip are connected to the second AD chip through a connector, and the second AD chip is respectively connected to the sampling signal input circuit of the three-phase AC side grid voltage UgA, UgB, and UgC, the sampling signal input circuit of the two DC bus voltages Udc1 and Udc2, and the sampling signal input circuit of the DC current Idc; The DSP chip adopts TMS320F28335, the first AD sampling circuit is a three-phase load current sampling circuit, and the 40, 41, and 42 pins of the DSP chip are respectively connected to the I_loadA, I_loadB, and I_loadC three-phase load current sampling circuits.

2. The energy storage converter main control architecture according to claim 1, characterized in that: The structures of the sampling signal input circuits of the three-phase inverter currents IA, IB, and IC, the sampling signal input circuits of the two-way DC bus voltages Udc1 and Udc2, and the sampling signal input circuit of the DC current Idc are all the same; the output signals of the sampling signal input circuits of the three-phase inverter currents IA, IB, and IC are respectively connected to the 33rd, 36th, and 39th pins of the first AD chip; the output signals of the sampling signal input circuits of the two-way DC bus voltages Udc1 and Udc2 and the sampling signal input circuit of the DC current Idc are respectively connected to the 42nd, 45th, and 48th pins of the second AD chip; The sampling signal input circuit includes two operational amplifiers, a first Schottky diode, multiple capacitors and resistors. The operational amplifier uses LM2904, and the first Schottky diode uses BAR43S. A first resistor and a second resistor are connected in series, the other end of the first resistor is connected to the input signal, the other end of the second resistor is connected to pin 3 of the first operational amplifier, pin 1 of the first operational amplifier is connected in series with the third resistor and then connected to pin 6 of the second operational amplifier, pin 7 of the second operational amplifier is connected in series with a fourth resistor, the other end of the fourth resistor is a sampling signal output end, and is connected to the first AD chip; Pin 1 and pin 2 of the first operational amplifier are connected, and pin 8 and pin 4 are connected to the positive and negative poles of the power supply respectively; The common end of the first Schottky diode is connected between the second resistor and the first operational amplifier, and the positive electrode and the negative electrode of the first Schottky diode are connected to the negative electrode and the positive electrode of the power supply respectively; One end of the fifth resistor is connected between the first resistor and the signal input port, and the other end is grounded; one end of the sixth resistor is connected between the first resistor and the second resistor, and the other end is grounded; one end of the first capacitor is connected between the second resistor and the first operational amplifier, and the other end is grounded; pin 5 of the second operational amplifier is connected to the seventh resistor, and the other end of the seventh resistor is grounded; the eighth resistor and the second capacitor are connected in parallel, and the parallel circuit is connected between pins 6 and 7 of the second operational amplifier; one end of the third capacitor is connected between the fourth resistor and the sampling signal output terminal, and the other end is grounded.

3. The energy storage converter main control architecture according to claim 1, characterized in that: The structures of the sampling signal input circuits of the three-phase inverter voltages UA, UB, and UC and the sampling signal input circuits of the three-phase AC side grid voltages UgA, UgB, and UgC are the same, the output signals of the sampling signal input circuits of the three-phase inverter voltages UA, UB, and UC are respectively connected to the 42, 45, and 48 pins of the first AD chip, and the output signals of the sampling signal input circuits of the three-phase AC side grid voltages UgA, UgB, and UgC are respectively connected to the 33, 36, and 39 pins of the second AD chip; The sampling signal input circuit includes three operational amplifiers, a second Schottky diode, multiple capacitors and resistors. The operational amplifier uses LM2904, and the second Schottky diode uses BAR43S. The ninth resistor and the tenth resistor are connected in series, the other end of the ninth resistor is connected to the signal input end, and the other end of the tenth resistor is connected to the 3rd pin of the third operational amplifier; the 1st pin and the 2nd pin of the third operational amplifier are connected, and the 8th pin and the 4th pin are respectively connected to the positive and negative poles of the power supply; the 1st pin of the third operational amplifier is connected in series with the 11th resistor and then connected to the 6th pin of the fourth operational amplifier, the 7th pin of the fourth operational amplifier is connected to the 12th resistor and then connected to the 5th pin of the fifth operational amplifier, the 7th pin of the fifth operational amplifier is connected in series with the 13th resistor, and the other end of the 13th resistor is the sampling signal output end, which is connected to the first AD chip; The common end of the second Schottky diode is connected between the tenth resistor and the third operational amplifier, and the positive electrode and the negative electrode of the second Schottky diode are connected to the negative electrode and the positive electrode of the power supply respectively; One end of the fourteenth resistor is connected between the ninth resistor and the signal input port, and the other end is grounded; one end of the fifteenth resistor is connected between the ninth resistor and the tenth resistor, and the other end is grounded; one end of the fourth capacitor is connected between the tenth resistor and the third operational amplifier, and the other end is grounded; one end of the sixteenth resistor is connected to the 5th pin of the fourth operational amplifier, and the other end is grounded; the seventeenth resistor and the fifth capacitor are connected in parallel, and the parallel circuit is connected between the 6th pin and the 7th pin of the fourth operational amplifier, and the connection end of the parallel circuit connected to the 7th pin of the fourth operational amplifier is connected to the eighteenth resistor, and the other end of the eighteenth resistor is the test signal output point; Pin 6 and pin 7 of the fifth operational amplifier are connected to each other; one end of the sixth capacitor is connected between the thirteenth resistor and the signal output port, and the other end is grounded.

4. The energy storage converter main control architecture according to claim 3, characterized in that: The test signal output point is externally connected to a signal test circuit, which includes a sixth operational amplifier, six resistors and two capacitors, and the sixth operational amplifier adopts LM2903; one end of the nineteenth resistor is connected to the test signal output by the eighteenth resistor, and the other end is connected to the 6th pin of the sixth operational amplifier; one end of the seventh capacitor is connected between the nineteenth resistor and the sixth operational amplifier, and the other end is grounded; the twentieth resistor, the twenty-first resistor and the twenty-second resistor are connected in series, the other end of the twentieth resistor is grounded, and the other end of the twenty-second resistor is connected to the positive electrode of the power supply; the 6th pin of the sixth operational amplifier is connected to the series end of the twentieth resistor and the twenty-first resistor, and the 7th pin is connected to the series end of the twenty-first resistor and the twenty-second resistor; at the same time, the 7th pin of the sixth operational amplifier is also connected to the twenty-third resistor, and the other end of the twenty-third resistor is the test signal output end; the twenty-fourth resistor and the eighth capacitor are connected in parallel, one end of the parallel circuit is connected to the output end of the twenty-third resistor, and the other end is grounded.

5. The energy storage converter main control architecture according to claim 1, characterized in that: The 31 and 30 pins of the AD chip are connected to the positive and negative electrodes of the 15V power supply respectively, and the 51 pin is connected to the 2.5V reference voltage conversion circuit, which is used to convert the 5V power supply into a 2.5V reference voltage and then transmit it to the AD chip; The 2.5V reference voltage conversion circuit includes a seventh operational amplifier, two inductors, six capacitors and a voltage reference chip, the seventh operational amplifier adopts TP1281L1, and the voltage reference chip is REF3025AIDBZR; the two inductors are connected in parallel, one end of the parallel inductor is connected to the input voltage of 5V, and the other end is connected to the 1 pin of the voltage reference chip; the ninth capacitor, the tenth capacitor, and the eleventh capacitor are connected in parallel, one end of the three parallel capacitors is connected between the 1 pin of the voltage reference chip and the inductor, and the other end is respectively connected to the 3 pin of the voltage reference chip and the twelfth capacitor, the twelfth capacitor is bridged between the 3 pin and the 2 pin of the voltage reference chip, and the connection point of the 2 pin of the voltage reference chip and the twelfth capacitor is respectively connected to the 3 pin of the seventh operational amplifier; the 5 pin and the 2 pin of the seventh operational amplifier are respectively connected to the positive and negative poles of the power supply, the 1 pin and the 4 pin are connected, the 1 pin of the seventh operational amplifier is an output pin, and outputs a 2.5V reference voltage; the thirteenth capacitor and the fourteenth capacitor are connected in parallel, one end of the two parallel capacitors is connected between the 1 pin of the seventh operational amplifier and the output port, and the other end is grounded.

6. The energy storage converter main control architecture according to claim 1, characterized in that: The bus between the DSP chip and the ZYNQ chip is connected via a parallel bus and an SPI bus. The parallel bus mode is that the DSP chip and the ZYNQ chip are connected via a parallel data bus; the SPI bus mode is that the 96, 97, 98, and 99 pins of the DSP chip are connected to the G7, B4, C5, and A6 pins of the ZYNQ chip via a level conversion chip model LSF0204RUTR to achieve serial communication.

7. The energy storage converter main control architecture according to claim 1, characterized in that: The H17 and H18 pins of the ZYNQ chip are respectively connected to the driving circuit through a connector, and the PWM driving waveform and the wave-sealing signal generated by the ZYNQ chip are respectively sent to the driving circuit; the driving circuit includes a driver of model SN75451, and the 2nd and 4th pins of the driver are respectively connected to the H17 and H18 pins of the ZYNQ chip, and the 3rd and 5th pins of the driver transmit the PWM driving waveform and the wave-sealing signal to the optical fiber transmitter of model HFBR1521, and the PWM driving waveform and the wave-sealing signal are sent to the external driving board through the optical fiber transmitter, and the power unit is driven to be turned on and off through the external driving board.

8. The energy storage converter main control architecture according to claim 1, characterized in that: The SD card circuit includes a level conversion chip, an SD card slot and an SD card; the ZYNQ chip is connected to the SD card slot through a level conversion chip model TXS02612RTWR, and is connected to the SD card through the SD card slot; the E14, C8, D8, B11, E13, and B9 pins of the ZYNQ chip are respectively connected to the 9, 4, 6, 7, 1, and 3 pins of the TXS02612RTWR.

9. The energy storage converter main control architecture according to claim 1, characterized in that: The pins D6, E9, A7, E10, A8, F11, A14, E11, B7, F12, A13, and D7 of the ZYNQ chip are connected to the pins 21, 19, 18, 17, 16, 20, 28, 26, 25, 24, 23, and 27 of the network port PHY chip model YT8521SC; the PHY chip is connected to the RJ45 network port terminal through the network port transformer model G24P02S, and the pins 2, 3, 4, 5, 6, and 7 of the PHY chip are connected to the RJ45 network port terminal through the network port transformer model G24P02S. The 1, 2, 3, 4, 5, 6, 7, and 8 pins of the PHY chip are connected to the ground respectively, and the 15, 18, 21, and 24 pins are connected in series with an inductor and then grounded.

10. The energy storage converter main control architecture according to claim 1, characterized in that: The DO control circuit includes a driver and a Darlington transistor. The DSP chip is connected to a driver of model 74HCT245 through a connector. The driver is connected to a Darlington transistor of model ULQ2003ADR. The Darlington transistor outputs a DO signal.

Images