High-efficiency ultra-low static power consumption BOOST converter for high-voltage light-load application

Abstract

The invention relates to a high-efficiency ultra-low static power consumption BOOST converter applied to a high-voltage light load. The BOOST converter comprises a power level circuit, a BURST loop controller based on asynchronous rectification and a logic and driving circuit. The power level circuit is used for performing energy conversion on the input voltage to obtain an output voltage; the BURST loop controller based on asynchronous rectification is used for adjusting the output voltage and controlling the working state of the BOOST converter; and the logic and driving circuit is used for generating a control signal and driving the power stage circuit and the BURST loop controller based on asynchronous rectification by using the control signal. According to the BURST control scheme based on asynchronous rectification and the high-performance low-power-consumption strategy, the on-off state of the high-power-consumption circuit is controlled according to the control signal, the light-load conversion efficiency of the BOOST converter is improved, the system complexity is reduced, and the good characteristic of low static power consumption is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and in particular to a high-efficiency ultra-low static power consumption BOOST converter for high-voltage and light-load applications. Background Art

[0002] The widespread popularity and diversified development of electronic devices are inseparable from reliable power management chips, and the further development of cutting-edge wearable devices has put forward more requirements for power management chips, and the demand for power management chips has continued to grow. According to data from market research institutions, the global power management chip market size is expected to grow from approximately US$33 billion in 2020 to approximately US$56.5 billion in 2026, with an annual compound growth rate of approximately 10.6%. Among them, diversified application scenarios under high-voltage and light-load conditions continue to emerge, such as home biomedical equipment, cutting-edge wearable devices, precision sensors, etc. In the current market, BOOST converter chip technology with high efficiency and ultra-low static power consumption under high-voltage and light-load conditions is mainly monopolized by international giants such as ADI and TI, which highlights the urgency and importance of developing similar chip technologies with independent intellectual property rights.

[0003] At present, domestic academic and industrial circles have made commendable achievements in the research and development of high-efficiency and ultra-low static power consumption BOOST converter chips for high-voltage and light-load applications. They have achieved good performance in terms of input range, conversion efficiency and static power consumption. However, compared with the top international designs, there is still a performance gap that cannot be ignored. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a high-efficiency and ultra-low static power consumption BOOST converter for high-voltage and light-load applications.

[0005] According to a first aspect of an embodiment of the present invention, a high-efficiency ultra-low static power consumption BOOST converter for high-voltage light-load applications is provided, wherein the BOOST converter comprises: a power stage circuit, a BURST loop controller based on asynchronous rectification, and a logic and drive circuit; the second end of the logic and drive circuit comprises: a first sub-end, a second sub-end, and a third sub-end; the SW end of the power stage circuit is connected to the SW end of the BURST loop controller based on asynchronous rectification, and the N end of the power stage circuit is connected to the N end of the BURST loop controller based on asynchronous rectification. CLK The terminals are respectively connected to the N terminals of the BURST loop controller based on asynchronous rectification. CLK terminals and the logic and driver circuits N CLK end, the power stage circuit V FB The terminal is connected to the V of the BURST loop controller based on asynchronous rectification. FBThe VOUT terminal of the power stage circuit is connected to the VOUT terminal of the BURST loop controller based on asynchronous rectification, and the V O1 The terminal is connected to the first sub-terminal of the logic and drive circuit, and the V of the BURST loop controller based on asynchronous rectification is O2 The terminal is connected to the second sub-terminal of the logic and drive circuit, and the V of the BURST loop controller based on asynchronous rectification is O3 The terminal is connected to the third sub-terminal of the logic and drive circuit;

[0006] The power stage circuit is used to perform energy conversion on the input voltage to obtain the output voltage;

[0007] The BURST loop controller based on asynchronous rectification is used to adjust the output voltage and control the working state of the BOOST converter;

[0008] The logic and driving circuit is used to generate a control signal and use the control signal to drive the power stage circuit and the asynchronous rectification-based BURST loop controller.

[0009] Optionally, the BOOST converter further comprises: a high power supply rejection ratio bias circuit, a protection circuit, and an enable and startup circuit; the V REF The terminal is connected to the V of the BURST loop controller based on asynchronous rectification. REF end, the high PSRR bias circuit I BIAS The terminal is connected to the I of the BURST loop controller based on asynchronous rectification. BIAS end, the high PSRR bias circuit I REF The terminal is connected to the I of the BURST loop controller based on asynchronous rectification. REF The protection circuit is connected to the logic and drive circuit, and the enable and start circuit is connected to the logic and drive circuit.

[0010] Optionally, the high power supply rejection ratio bias circuit is used to provide a bias voltage and a bias current to the asynchronous rectification-based BURST loop controller;

[0011] The protection circuit is used to ensure that the BOOST converter operates within a standard voltage and standard temperature range;

[0012] The enabling and starting circuit is used to control the operation and stopping of the BOOST converter.

[0013] Optionally, the power stage circuit includes: an inductor L, a power tube N1, a diode D1, an output capacitor C OUT, switch VOSNS, feedback resistor R FB1 and feedback resistor R FB2 The first end of the inductor L is connected to the power supply terminal VIN, the drain end of the power tube N1 and the anode of the diode D1 are connected to form the SW end connected to the second end of the inductor L; the gate of the power tube N1 is connected to the BURST loop controller N based on asynchronous rectification CLK The source of the power tube N1 is grounded; the output capacitor C OUT The VOUT end formed by connecting the upper plate of the switch VOSNS and the first end of the switch VOSNS is connected to the cathode of the diode D1; the output capacitor C OUT The lower plate of the switch VOSNS is grounded; the second end of the switch VOSNS is connected to the feedback resistor R FB1 The first end of the feedback resistor R FB1 The second end is connected to the feedback resistor R FB2 The first end of the feedback resistor R FB2 The second end is grounded.

[0014] Optionally, the BURST loop controller based on asynchronous rectification includes: V FB comparator, ripple limiting circuit and adaptive peak current limiting circuit, the V FB Comparator V REF end and the ripple limiting circuit V REF The terminals are connected to the V REF end, the V FB The I REF end and the ripple limiting circuit I REF The terminals are connected to the I REF end, the adaptive peak current limiting circuit N CLK The N terminal is connected to the power stage circuit CLK end, the adaptive peak current limiting circuit I BIAS The high power supply rejection ratio bias circuit is connected to the I BIAS end.

[0015] Optionally, the high power supply rejection ratio bias circuit includes: a high PSR reference voltage source; the high PSR reference voltage source includes: an operational amplifier G1, a resistor R1, a resistor R 2_1 , resistor R 2_2 , transistor Q1 and transistor Q2; the output end of the operational amplifier G1 is connected to the first end of the resistor R1, the in-phase input end of the operational amplifier G1 and the resistor R 2_2The node B formed by connecting the first end of the transistor Q2 to the collector, the inverting input terminal of the operational amplifier G1 and the resistor R 2_1 The node A formed by connecting the first end of the resistor R1 and the first end of the resistor R2 is connected to the base and collector of the transistor Q1 respectively; the second end of the resistor R1 and the first end of the resistor R 2_1 The second end and the resistor R 2_2 The node C formed by connecting the second ends of is connected to the base of the transistor Q2.

[0016] Optionally, the high power supply rejection ratio bias circuit also includes: a high input voltage rejection ratio bias circuit; the high input voltage rejection ratio bias circuit includes: a high PSR reference source core circuit and a high PSR reference source holding circuit; the high PSR reference source holding circuit includes: a switch S1, a switch S2, a low power consumption OTA1 and a capacitor C1; the first end of the switch S1 is connected to the high PSR reference source core circuit; the first end of the switch S2 is connected to a node formed by connecting the second end of the switch S1 and the in-phase input end of the low power consumption OTA1; the second end of the switch S2, the output end of the low power consumption OTA1 and the inverting input end of the low power consumption OTA1 form a node V REF1 Connected to the upper plate of the capacitor C1; the lower plate of the capacitor C1 is connected to the ground.

[0017] Optionally, the high input voltage rejection ratio bias circuit also includes: a high PSR reference source current source circuit; the high PSR reference source current source circuit includes: a low power consumption OTA2, a MOS tube M1, a MOS tube M2, a MOS tube M3 and a resistor R1; the output end of the low power consumption OTA2 is connected to the gate of the MOS tube M1, and the first end of the resistor R1 is connected to the node formed by the inverting input end of the low power consumption OTA2 and the source of the MOS tube M1; the node formed by the drain of the MOS tube M1, the gate of the MOS tube M2 and the drain of the MOS tube M2 is connected to the gate of the MOS tube M3; the source of the MOS tube M2 and the source of the MOS tube M3 are both connected to the power supply; the second end of the resistor R1 is grounded.

[0018] The technical solution provided by the present invention may include the following beneficial effects:

[0019] The BURST control scheme based on asynchronous rectification provided by the present invention improves its conversion efficiency under light load and reduces system complexity; the high-performance and low-power strategy provided by the present invention greatly reduces the overall power consumption of the circuit while ensuring the circuit performance through a high power supply rejection ratio bias circuit and on-demand adjustment technology.

[0020] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings:

[0022] Figure 1 It is a schematic structural diagram of a high-efficiency and ultra-low static power consumption BOOST converter for high-voltage and light-load applications according to an exemplary embodiment.

[0023] Figure 2 The diagram is a signal diagram according to an exemplary embodiment.

[0024] Figure 3a is a circuit schematic diagram of a traditional reference voltage source according to an exemplary embodiment.

[0025] Figure 3b is a circuit schematic diagram of a high PSR reference voltage source according to an exemplary embodiment.

[0026] Figure 3c It is a structural diagram of a small signal feedback model according to an exemplary embodiment.

[0027] Figure 4 The diagram is a schematic structural diagram of a high power supply rejection ratio bias circuit according to an exemplary embodiment.

[0028] Figure 5 The figure is a schematic diagram of a low static power consumption on-demand adjustment strategy according to an exemplary embodiment.

[0029] Figure 6 It is a conversion efficiency simulation diagram of a high-efficiency and ultra-low static power consumption BOOST converter for high-voltage and light-load applications according to an exemplary embodiment. DETAILED DESCRIPTION

[0030] Figure 1 FIG. 1 is a schematic diagram of a high-efficiency, ultra-low static power consumption BOOST converter for high-voltage and light-load applications according to an exemplary embodiment. Figure 1 As shown, the BOOST converter includes: a power stage circuit, a BURST loop controller based on asynchronous rectification and a logic and drive circuit; the second end of the logic and drive circuit includes: a first sub-end, a second sub-end and a third sub-end; the SW end of the power stage circuit is connected to the SW end of the BURST loop controller based on asynchronous rectification, and the N CLK The two ends are connected to the N of the BURST loop controller based on asynchronous rectification. CLK N terminals and logic and driver circuits CLKterminal, the power stage circuit V FB The terminal is connected to the V of the BURST loop controller based on asynchronous rectification. FB The VOUT terminal of the power stage circuit is connected to the VOUT terminal of the BURST loop controller based on asynchronous rectification. The V O1 The terminal is connected to the first sub-terminal of the logic and drive circuit, and the V O2 The second terminal is connected to the logic and drive circuit, and the V of the BURST loop controller based on asynchronous rectification O3 The terminal is connected to a third sub-terminal of the logic and drive circuit;

[0031] A power stage circuit is used to convert the input voltage into an output voltage;

[0032] A BURST loop controller based on asynchronous rectification is used to adjust the output voltage and control the working state of the BOOST converter;

[0033] The logic and driving circuit is used to generate control signals and use the control signals to drive the power stage circuit and the BURST loop controller based on asynchronous rectification.

[0034] Optionally, refer to Figure 1 , the BOOST converter also includes: a high power supply rejection ratio bias circuit, a protection circuit, and an enable and startup circuit; the V REF The terminal is connected to the V of the BURST loop controller based on asynchronous rectification. REF end, high power supply rejection ratio bias circuit I BIAS The terminal is connected to the I of the BURST loop controller based on asynchronous rectification. BIAS end, high power supply rejection ratio bias circuit I REF The terminal is connected to the I of the BURST loop controller based on asynchronous rectification. REF The protection circuit is connected to the logic and drive circuit, and the enabling and starting circuit is connected to the logic and drive circuit.

[0035] Optionally, a high power supply rejection ratio bias circuit for providing a bias voltage and a bias current to a BURST loop controller based on asynchronous rectification;

[0036] Protection circuit to ensure that the BOOST converter operates within the standard voltage and standard temperature range;

[0037] The enabling and starting circuit is used to control the operation and stopping of the BOOST converter.

[0038] Optionally, refer to Figure 1The power stage circuit includes: inductor L, power tube N1, diode D1, output capacitor C OUT , switch VOSNS, feedback resistor R FB1 and feedback resistor R FB2 The first end of the inductor L is connected to the power supply terminal VIN, and the drain end of the power tube N1 and the anode of the diode D1 are connected to form the SW end connected to the second end of the inductor L; the gate of the power tube N1 is connected to the BURST loop controller N based on asynchronous rectification. CLK The source of the power tube N1 is grounded; the output capacitor C OUT The VOUT terminal formed by connecting the upper plate of the switch VOSNS to the cathode of the diode D1; the output capacitor C OUT The lower plate of the switch VOSNS is grounded; the second end of the switch VOSNS is connected to the feedback resistor R FB1 The first end of the feedback resistor R FB1 The second end is connected to the feedback resistor R FB2 The first end of the feedback resistor R FB2 The second end is grounded.

[0039] Optionally, refer to Figure 1 , the BURST loop controller based on asynchronous rectification includes: V FB Comparator, ripple limiting circuit and adaptive peak current limiting circuit, V FB Comparator V REF terminal and ripple limiting circuit V REF Both ends are connected to the V REF Terminal, V FB The I REF terminal and ripple limiting circuit I REF Both ends are connected to the I REF The adaptive peak current limiting circuit N CLK The N terminal is connected to the power stage circuit CLK The adaptive peak current limiting circuit I BIAS The terminal is connected to the I BIAS end.

[0040] In one embodiment, Figure 2 is a signal schematic diagram according to an exemplary embodiment. Figure 2 As shown in Figure 1, the BURST loop controller based on asynchronous rectification is mainly divided into active mode and sleep mode. The control circuit is mainly composed of Figure 1 V FB The comparator, ripple limiting circuit and adaptive peak current limiting circuit are composed of V FB The comparator compares the output voltage V FB and reference voltage VREF The value of V OUT The maximum value V CON The ripple limiting circuit detects V OUT Ripple V ripple The adaptive peak current limiting circuit detects the inductor current peak value I PEAK .

[0041] The circuit works in two stages:

[0042] (1)V B -V C Stage (output rising):

[0043] The BOOST converter (boost converter) is in the DCM (Discontinuous Conduction Mode) state with peak current limitation. The output rises and the BOOST converter is in Figure 2 T ON The power tube N1 is turned on during this time period to charge the inductor L. ON The time is determined by the adaptive peak current limit circuit, when the current rises from 0 to I PEAK After that, T ON End. Then turn off the power tube N1, the BOOST converter enters the asynchronous rectification stage, the energy stored in the inductor is transferred to the output, and the output rises. The time of the asynchronous rectification stage is T OFF and T ID Determined by the logic and drive circuits. After this output charging phase, the output rises. In this phase, all circuits work normally, V FB The comparator continuously compares the output voltage V FB With high PSRR bias circuit output V REF (1V). When the output voltage is divided into FB Greater than 1V, output voltage V OUT Greater than V CON , that is, reaching V C Click to enter the next stage.

[0044] (2) V C -V B Phase (output falling):

[0045] The BOOST converter is in BURST mode, and the output drops under the action of the load. At this time, most of the high power supply rejection ratio bias circuit and the adaptive peak current limit circuit in the BURST loop controller are in sleep mode. OSNS The switch also turns off the feedback resistor to minimize the circuit's static power consumption. At this time, only the ripple limiting circuit works, which detects the output voltage V OUTThe ripple is reduced by 30mV (V B ), and enter stage (1).

[0046] It can be understood that the BOOST converter is controlled by a BURST loop controller based on asynchronous rectification to boost the output voltage to the required value in active mode; it works at low power consumption in sleep mode to improve the conversion efficiency of the system. FB The on or off state of most circuits in the comparator, adaptive peak current limiting circuit, and high power supply rejection ratio bias circuit) is used to compress the static current consumption; a stable reference voltage is provided by a high input voltage rejection ratio bias circuit to ensure high performance and low power consumption.

[0047] Optionally, Figure 3a is a circuit schematic diagram of a traditional reference voltage source according to an exemplary embodiment. Figure 3b is a circuit schematic diagram of a high PSR reference voltage source according to an exemplary embodiment. Figure 3c is a structural diagram of a small signal feedback model according to an exemplary embodiment. Figure 3a , Figure 3b and Figure 3c As shown, the high power supply rejection ratio bias circuit includes: a high PSR reference voltage source; the high PSR reference voltage source includes: an operational amplifier G1, a resistor R1, a resistor R 2_1 , resistor R 2_2 , transistor Q1 and transistor Q2; the output end of the operational amplifier G1 is connected to the first end of the resistor R1, the in-phase input end of the operational amplifier G1 and the resistor R 2_2 The first end of the node B is connected to the collector of transistor Q2, the inverting input terminal of operational amplifier G1 and the resistor R 2_1 The node A formed by connecting the first end of the resistor R1 and the first end of the resistor R2 is connected to the base and collector of the transistor Q1 respectively; the second end of the resistor R1 and the resistor R 2_1 The second end and resistor R 2_2 The node C formed by connecting the second ends of is connected to the base of transistor Q2.

[0048] It can be understood that a high PSR reference voltage source can provide a reference voltage with better robustness. The small signal feedback model of the conventional reference voltage source circuit and the high PSR reference voltage source provided by the present invention is as follows: Figure 3c As shown. And Figure 3a and Figure 3b The power consumption of the reference voltage source is consistent. Figure 3c The feedback model can be calculated that the power supply voltage (input voltage) suppression ratio PSR of the reference source is:

[0049]

[0050] Where S1 is the gain from the supply voltage of the operational amplifier OPA to its output voltage, G1 is the gain of the OPA, and F is the voltage source output V REF The gain to the op amp input ports A and B, G1F is much greater than 1, and the simplified formula holds. The F of the high PSR reference voltage source of the conventional structure and the present invention are respectively:

[0051]

[0052] F1 and F2 are the gains corresponding to the traditional reference voltage source and the high PSR reference voltage source provided by the present invention, respectively. For easier comparison, when F1 and F2 are substituted into the designed circuit, R1=46.9kΩ and R2=7.6kΩ, it can be calculated that F1=0.074, F2=2.33. It can be seen that the power supply voltage rejection ratio of the reference voltage source proposed by the present invention is improved by 31 times compared with the traditional structure.

[0053] Optionally, Figure 4 is a schematic structural diagram of a high power supply rejection ratio bias circuit according to an exemplary embodiment. Figure 4 As shown, the high power supply rejection ratio bias circuit also includes: a high input voltage rejection ratio bias circuit; the high input voltage rejection ratio bias circuit includes: a high PSR reference source core circuit and a high PSR reference source holding circuit; the high PSR reference source holding circuit includes: a switch S1, a switch S2, a low power consumption OTA1 and a capacitor C1; the first end of the switch S1 is connected to the high PSR reference source core circuit; the first end of the switch S2 is connected to a node formed by connecting the second end of the switch S1 and the in-phase input end of the low power consumption OTA1; the second end of the switch S2, the output end of the low power consumption OTA1 and the inverting input end of the low power consumption OTA1 are connected to form a node V REF1 Connected to the upper plate of capacitor C1; the lower plate of capacitor C1 is connected to the ground; the high PSR reference source core circuit is obtained based on the high PSR reference voltage source principle circuit topology, and can provide a reference voltage with better robustness; the high PSR reference source holding circuit can provide a stable reference voltage in active mode and sleep mode.

[0054] Optionally, refer to Figure 4The high input voltage rejection ratio bias circuit also includes: a high PSR reference source current source circuit; the high PSR reference source current source circuit includes: a low power consumption OTA2, a MOS tube M1, a MOS tube M2, a MOS tube M3 and a resistor R1; the output end of the low power consumption OTA2 is connected to the gate of the MOS tube M1, the first end of the resistor R1 is connected to a node formed by connecting the inverting input end of the low power consumption OTA2 and the source of the MOS tube M1; the node formed by connecting the drain of the MOS tube M1, the gate of the MOS tube M2 and the drain of the MOS tube M2 is connected to the gate of the MOS tube M3; the source of the MOS tube M2 and the source of the MOS tube M3 are both connected to the power supply; the second end of the resistor R1 is grounded; the high PSR reference source current source circuit provides a reference current with better robustness.

[0055] It is understandable that the high PSR reference source core circuit is based on Figure 3b The high PSR reference source principle circuit is extended from the CLK1 and NCLK1 are anti-phase signals. In the active mode, CLK1 closes the switch S1 and NCLK1 opens the switch S1. Under the feedback of the operational amplifier, the output of the high PSR reference source core circuit is connected to V REF1 In sleep mode, the charge stored in capacitor C1 in active mode will slowly leak out. At the same time, CLK1 opens switch S1, NCLK1 closes switch S2, and the high PSR reference source core circuit is turned off. At this time, the charge on capacitor C1 will not be affected by the leakage current due to the holding effect of the op amp and switch S2, and will automatically remain at V REF1 The high PSR reference current source circuit converts the reference voltage into current through a voltage-to-current conversion circuit. Compared with the traditional current source, the current converted by the reference source is more stable and is not easily affected by changes in factors such as power supply voltage, achieving high-performance bias.

[0056] In one embodiment, Figure 5 is a schematic diagram of a low static power consumption on-demand adjustment strategy according to an exemplary embodiment. Figure 5 As shown, in high-voltage light-load applications, as the load current decreases, static power consumption becomes one of the key factors that reduce conversion efficiency. Therefore, low static power consumption is required to improve system endurance. However, the reduction of circuit static power consumption will lead to performance degradation. Therefore, the present invention proposes a high-performance and low-power strategy. Figure 5 As shown, the on-demand modulation strategy can dynamically switch the on or off state of high-power circuits according to working needs, thereby compressing static current consumption and improving efficiency. Figure 5The names of the specific modules are shown in Table 1. Due to the small load current, the BOOST converter stays in sleep mode for a long time. In sleep mode, only the low-power circuit works to achieve ultra-low static power consumption. In addition, in order to ensure high performance and low power consumption at the same time, the high PSR reference current source circuit is divided into two parts: the high PSR reference core circuit and the high PSR reference holding circuit.

[0057] Table 1

[0058] (1) High PSR reference source core circuit (2) High PSR reference source holding circuit (3) Adaptive peak current monitoring circuit (4) Low power current source (5) Protection circuit <![CDATA[(6)V FB Comparator]]> (7) Ripple limiting circuit (8)VOSNS

[0059] It can improve the conversion efficiency of the BOOST converter under light load and reduce the complexity. Through the high power supply rejection ratio bias circuit and on-demand adjustment technology, the overall power consumption of the circuit is greatly reduced while ensuring the circuit performance. The voltage boost conversion is completed through the power stage circuit. The power stage circuit realizes the stability of the system loop, the stability of the output voltage, the switching of the working state, the peak control of the inductor current, the establishment of the circuit start working state and the determination of the appropriate working state through the detection of the BURST loop controller and the logic and drive circuit. The voltage and current bias of the BURST loop controller is provided by the high power supply rejection ratio bias circuit. In addition, the protection circuit can provide the overvoltage and overtemperature logic to the logic and drive circuit, and the enable and startup circuit can provide the system start working logic to the logic and drive circuit, thereby ensuring the system's stable operation under high voltage and light load applications, and has the good characteristics of high efficiency and low static power consumption.

[0060] In one embodiment, Figure 6 is a conversion efficiency simulation diagram of a high-efficiency ultra-low static power consumption BOOST converter for high-voltage light-load applications according to an exemplary embodiment. The converter can work stably under the conditions of Vin = 3.6V, Vout = 10V, Iout = 10mA, and according to Figure 6 The simulation data provided calculated the conversion efficiency to be 86.8%, achieving a conversion efficiency of more than 85% for the non-synchronous BOOST converter.

[0061] The present invention improves the conversion efficiency of the BOOST converter under light load and reduces the system complexity; the high-performance and low-power consumption strategy provided greatly reduces the overall power consumption of the circuit under the condition of ensuring the circuit performance through a high power supply rejection ratio bias circuit and an on-demand adjustment technology; the voltage boost conversion is completed through a power stage circuit, and the power stage circuit realizes the stability of the system loop, the stability of the output voltage, the switching of the working state, the peak value control of the inductor current, the establishment of the circuit starting working state and the determination of the appropriate working state through the detection of the BURST loop controller and the logic and drive circuit, and the voltage and current bias of the BURST loop controller based on asynchronous rectification is provided by a high power supply rejection ratio bias circuit, in addition, the protection circuit can provide the logic of overvoltage and overtemperature to the logic and drive circuit, and the enable and start circuit can provide the logic of system starting work to the logic and drive circuit, thereby ensuring the stable operation of the system under high-voltage and light-load applications, and having the good characteristics of high efficiency and low static power consumption.

[0062] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0063] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0064] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A high efficiency ultra-low quiescent power BOOST converter for high voltage light load applications, characterized in that: The BOOST converter comprises: a power stage circuit, a BURST loop controller based on asynchronous rectification and a logic and drive circuit; the second end of the logic and drive circuit comprises: a first sub-end, a second sub-end and a third sub-end; the SW end of the power stage circuit is connected to the SW end of the BURST loop controller based on asynchronous rectification, and the N CLK The terminals are respectively connected to the N terminals of the BURST loop controller based on asynchronous rectification. CLK terminals and the logic and driver circuits N CLK end, the power stage circuit V FB The terminal is connected to the V of the BURST loop controller based on asynchronous rectification. FB The VOUT terminal of the power stage circuit is connected to the VOUT terminal of the BURST loop controller based on asynchronous rectification, and the V O1 The terminal is connected to the first sub-terminal of the logic and drive circuit, and the V of the BURST loop controller based on asynchronous rectification is O2 The terminal is connected to the second sub-terminal of the logic and drive circuit, and the V of the BURST loop controller based on asynchronous rectification is O3 The terminal is connected to the third sub-terminal of the logic and drive circuit; The power stage circuit is used to perform energy conversion on the input voltage to obtain the output voltage; The BURST loop controller based on asynchronous rectification is used to adjust the output voltage and control the working state of the BOOST converter; The logic and driving circuit is used to generate a control signal and use the control signal to drive the power stage circuit and the asynchronous rectification-based BURST loop controller.

2. The high-efficiency ultra-low static power consumption BOOST converter for high-voltage light-load applications according to claim 1, characterized in that: The BOOST converter further includes: a high power supply rejection ratio bias circuit, a protection circuit, and an enable and startup circuit; the V REF The terminal is connected to the V of the BURST loop controller based on asynchronous rectification. REF end, the high PSRR bias circuit I BIAS The terminal is connected to the I of the BURST loop controller based on asynchronous rectification. BIAS end, the high PSRR bias circuit I REF The terminal is connected to the I of the BURST loop controller based on asynchronous rectification. REF The protection circuit is connected to the logic and drive circuit, and the enable and start circuit is connected to the logic and drive circuit.

3. The high-efficiency ultra-low static power consumption BOOST converter for high-voltage light-load applications according to claim 2, characterized in that: The high power supply rejection ratio bias circuit is used to provide a bias voltage and a bias current to the asynchronous rectification-based BURST loop controller; The protection circuit is used to ensure that the BOOST converter operates within a standard voltage and standard temperature range; The enabling and starting circuit is used to control the operation and stopping of the BOOST converter.

4. The high efficiency and ultra-low static power consumption BOOST converter for high voltage and light load applications according to claim 2, characterized in that: The power stage circuit includes: an inductor L, a power tube N1, a diode D1, an output capacitor C OUT , switch VOSNS, feedback resistor R FB1 and feedback resistor R FB2 The first end of the inductor L is connected to the power supply terminal VIN, the drain end of the power tube N1 and the anode of the diode D1 are connected to form the SW end connected to the second end of the inductor L; the gate of the power tube N1 is connected to the BURST loop controller N based on asynchronous rectification CLK The source of the power tube N1 is grounded; the output capacitor C OUT The VOUT end formed by connecting the upper plate of the switch VOSNS and the first end of the switch VOSNS is connected to the cathode of the diode D1; the output capacitor C OUT The lower plate of the switch VOSNS is grounded; the second end of the switch VOSNS is connected to the feedback resistor R FB1 The first end of the feedback resistor R FB1 The second end is connected to the feedback resistor R FB2 The first end of the feedback resistor R FB2 The second end is grounded.

5. The high-efficiency ultra-low static power consumption BOOST converter for high-voltage light-load applications according to claim 2, characterized in that: The BURST loop controller based on asynchronous rectification includes: V FB comparator, ripple limiting circuit and adaptive peak current limiting circuit, the V FB Comparator V REF end and the ripple limiting circuit V REF The terminals are connected to the V REF end, the V FB The I REF end and the ripple limiting circuit I REF The terminals are connected to the I REF end, the adaptive peak current limiting circuit N CLK The N terminal is connected to the power stage circuit CLK end, the adaptive peak current limiting circuit I BIAS The high power supply rejection ratio bias circuit is connected to the I BIAS end.

6. The high-efficiency ultra-low static power consumption BOOST converter for high-voltage light-load applications according to claim 3, characterized in that: The high power supply rejection ratio bias circuit includes: a high PSR reference voltage source; the high PSR reference voltage source includes: an operational amplifier G1, a resistor R1, a resistor R 2_1 , resistor R 2_2 , transistor Q1 and transistor Q2; the output end of the operational amplifier G1 is connected to the first end of the resistor R1, the in-phase input end of the operational amplifier G1 and the resistor R 2_2 The node B formed by connecting the first end of the transistor Q2 to the collector, the inverting input terminal of the operational amplifier G1 and the resistor R 2_1 The node A formed by connecting the first end of the resistor R1 and the first end of the resistor R2 is connected to the base and collector of the transistor Q1 respectively; the second end of the resistor R1 and the first end of the resistor R 2_1 The second end and the resistor R 2_2 The node C formed by connecting the second ends of is connected to the base of the transistor Q2.

7. The high efficiency ultra-low static power consumption BOOST converter for high voltage and light load applications according to claim 3, characterized in that: The high power supply rejection ratio bias circuit also includes: a high input voltage rejection ratio bias circuit; the high input voltage rejection ratio bias circuit includes: a high PSR reference source core circuit and a high PSR reference source holding circuit; the high PSR reference source holding circuit includes: a switch S1, a switch S2, a low power consumption OTA1 and a capacitor C1; the first end of the switch S1 is connected to the high PSR reference source core circuit; the first end of the switch S2 is connected to a node formed by connecting the second end of the switch S1 and the in-phase input end of the low power consumption OTA1; the second end of the switch S2, the output end of the low power consumption OTA1 and the inverting input end of the low power consumption OTA1 form a node V REF1 Connected to the upper plate of the capacitor C1; the lower plate of the capacitor C1 is connected to the ground.

8. The high efficiency ultra-low static power consumption BOOST converter for high voltage and light load applications according to claim 7, characterized in that: The high input voltage rejection ratio bias circuit also includes: a high PSR reference source current source circuit; the high PSR reference source current source circuit includes: a low power consumption OTA2, a MOS tube M1, a MOS tube M2, a MOS tube M3 and a resistor R1; the output end of the low power consumption OTA2 is connected to the gate of the MOS tube M1, and the first end of the resistor R1 is connected to the node formed by the inverting input end of the low power consumption OTA2 and the source of the MOS tube M1; the node formed by the drain of the MOS tube M1, the gate of the MOS tube M2 and the drain of the MOS tube M2 is connected to the gate of the MOS tube M3; the source of the MOS tube M2 and the source of the MOS tube M3 are both connected to a power supply; the second end of the resistor R1 is grounded.

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