Boost converter controlled by PFM mode and zero-cross detection circuit

Abstract

The invention provides a boost converter controlled in a PFM mode and a zero cross detection circuit thereof. The zero-cross detection circuit is composed of a biasing circuit and a three-stage comparator. In the three-stage comparator, the first stage adopts a common-gate circuit, receives zero-cross detection two-end input, and adapts to a wide input range; the second stage is a push-pull amplifier, receives the output of the first stage, and accelerates the overturning speed through push-pull input and output; and the third stage is responsible for outputting a zero-cross detection comparison result. The boost converter system comprises a mode switching unit, a switch logic control unit, a driving control unit and a main circuit. The mode switching unit judges whether to enter a PFM mode or not according to the zero-cross detection circuit signal; the switch logic control unit outputs a logic control instruction according to the signal; the driving control unit controls the on and off of the N-type power tube and the P-type power tube in the main circuit according to the instructions. The control mode is combined with high-precision and high-speed zero-cross detection, so that the stability and the response speed of the system are remarkably improved.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a PFM mode controlled boost converter and a zero-crossing detection circuit. Background Art

[0002] The zero-crossing detection circuit is a basic module in the design of DC-DC converter chips. Each analog part in the converter chip contains a zero-crossing detection circuit. In different boost converter chip control loops, the zero-crossing detection circuit works differently. In addition, the performance of the zero-crossing detection circuit in the control loop of the boost converter chip directly affects the performance of the entire chip.

[0003] The boost converter chip in the traditional PFM control mode can be fully shut down to reduce power consumption, but the output voltage ripple is large, and multiple module circuits are still required to work during the operation of the chip, and the control loop is more complicated.

[0004] Therefore, it is necessary to reasonably use the zero-crossing detection circuit to simplify the control loop of the converter chip, reduce the output voltage ripple, and improve the output stability.

[0005] The detection accuracy of the zero-crossing detection circuit is generally determined by its open-loop gain. The speed and accuracy of the traditional zero-crossing detection composed of two-stage comparators are moderate. The N-type MOS tube and the P-type MOS tube of the comparator composed of a push-pull operational amplifier can be turned on in turn, and the RC constant is small and the conversion speed is fast, which can improve the flipping speed of the circuit, but the comparison accuracy is low. The multi-stage cascade comparison method can achieve high-precision comparison, but in the prior art, the multi-stage cascade leads to an increase in circuit nodes and parasitic capacitance, which reduces the working speed of the comparator. The flipping speed difference between the simulation before and after is large, and the flipping speed of the actual tape-out test is large compared with the previous simulation.

[0006] Therefore, a comparator structure is needed that can achieve high gain while ensuring the flipping speed, and achieve the performance requirements of high speed and high precision. Summary of the invention

[0007] The present invention provides a high-speed and high-precision zero-crossing detection circuit, which is applied to a boost converter control loop in a PFM control mode. Technically, the control mode of the loop is changed by reasonably using the zero-crossing detection circuit, and a zero-crossing detection circuit composed of a multi-stage comparator is used to reduce output voltage ripple and improve output stability.

[0008] The technical solution of the present invention is achieved in this way:

[0009] The first aspect of the present application discloses a PFM mode controlled boost converter, comprising: a mode switching unit, a switch logic control unit, a drive control unit, and a main circuit;

[0010] The switch logic control unit is connected to the mode switching unit and the drive control unit respectively, and the mode switching unit is connected to the inductor output current of the main circuit, and is used to receive the inductor output current of the main circuit, output a zero-crossing detection signal, and judge to enter the PFM mode according to the number of zero-crossing detection signals;

[0011] The switch logic control unit is used to output a logic control signal according to the zero-crossing detection signal and the constant on-time control signal;

[0012] The driving control unit is used to output a driving control signal to drive the N-type and P-type power tubes in the main circuit to turn on and off according to the received logic control signal.

[0013] Optionally, in the above-mentioned PFM mode controlled boost converter, the mode switching unit comprises: a zero-crossing detection circuit and a PFM mode enabling circuit; wherein:

[0014] One end of the zero-crossing detection circuit is input as an input end of the mode switching unit to receive the inductor output current of the main circuit; one end of the zero-crossing detection circuit is output as an input end of the PFM mode enabling circuit to output a zero-crossing detection signal;

[0015] The output end of the PFM mode enabling circuit serves as the output end of the mode switching unit to output a PFM mode enabling signal.

[0016] Optionally, in the above-mentioned PFM mode-controlled boost converter, the PFM mode enabling circuit is composed of four D flip-flops, including a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, and a fourth D flip-flop DFF4, the D terminal of the first D flip-flop DFF1 is connected to the zero-crossing detection signal PDB, the CLK terminal of the first D flip-flop DFF2 is connected to the drive signal, the Re terminal of the first D flip-flop DFF2 is connected to the input terminal of the voltage source VIN in the main circuit, and the output Q is connected to the second D flip-flop DFF2 and the third D flip-flop DFF4. F3, the Re terminal of the fourth D flip-flop DFF4, the CLK terminal of the second D flip-flop DFF2 is connected to the drive signal, the D terminal of the second D flip-flop DFF2 is connected to the Q non-terminal, the CLK terminal of the third D flip-flop DFF2 is connected to the D terminal of the second D flip-flop DFF2, the D terminal of the third D flip-flop DFF2 is connected to the Q non-terminal, the D terminal of the fourth D flip-flop DFF2 is connected to the input terminal of the voltage source VIN in the main circuit, the CLK terminal of the fourth D flip-flop DFF2 is connected to the D terminal of the third D flip-flop DFF2, and the Q terminal of the fourth D flip-flop DFF2 is connected to the output PFM_EN signal.

[0017] Optionally, in the above-mentioned PFM mode-controlled boost converter, the mode switching unit is specifically used to: after receiving the zero-crossing detection signal four times, the PFM mode enabling circuit outputs a PFM_EN signal of a high level, which is input to the switching logic control unit to indicate that the system enters the PFM mode.

[0018] Optionally, in the above-mentioned PFM mode-controlled boost converter, the switch logic control unit includes a zero-crossing detection circuit, a constant on-time PFM circuit, a two-input AND gate AND, and an RS trigger; wherein: the zero-crossing detection circuit outputs a circuit zero-crossing detection signal, the input is connected to the main circuit inductor output current, and the output is connected to the PFM constant on-time circuit and the two-input AND gate AND; the output of the PFM constant on-time circuit is connected to the S terminal of the RS trigger; the two-input AND gate AND provides a logic AND signal, the input is connected to the PFM_EN signal and the zero-crossing detection signal, and the output is connected to the R terminal of the RS trigger; the RS trigger provides an RS logic signal to the drive circuit, and the output Q terminal is connected to the drive circuit input.

[0019] Optionally, in the above-mentioned PFM mode-controlled boost converter, the drive control unit includes a drive circuit and a hysteresis comparator; wherein: the input end of the drive circuit is connected to the hysteresis comparator output and the RS trigger output Q end in the switch logic control unit, and the output end of the drive circuit is connected to the N-type power tube gate and the P-type power tube gate in the main circuit to drive the N-type power tube and the P-type power tube to be turned on and off; the positive input end of the hysteresis comparator is connected to the feedback voltage VFB in the main circuit, and the negative input end is connected to VREF, and the output end of the hysteresis comparator is connected to the drive circuit to output a hysteresis comparison signal.

[0020] Optionally, in the above-mentioned boost converter controlled by the PFM mode, the main circuit includes: an input voltage source VIN, an input capacitor, an inductor, an N-type power tube, a P-type power tube, an output capacitor and a first resistor RFB1 and a second resistor RFB2; wherein: one end of the input capacitor is connected to the positive input end of the input voltage source VIN to receive the input voltage, the other end of the input capacitor is connected to the negative input end of the input voltage source VIN, one end of the inductor is connected to the input after being filtered by the input capacitor, as the input end of the main circuit, and the other end is respectively connected to the drain end of the N-type power tube and the source end of the P-type power tube, as the first output end of the main circuit. end, outputting the SW end voltage; the drain end of the P-type power tube is respectively connected to one end of the output capacitor and one end of the first resistor RFB1, and the connection point serves as the second output end of the main circuit to output the output voltage; the other end of the output capacitor is respectively connected to the other end of the second resistor RFB2 in the main circuit and the second end of the N-type power tube in the main circuit, the other end of the first resistor RFB1 in the main circuit is connected to one end of the second resistor RFB2 in the main circuit, and the connection point serves as the third output end of the main circuit to output the feedback voltage VFB; the gate end of the N-type power tube and the gate end of the P-type power tube in the main circuit receive corresponding on-off control signals respectively.

[0021] Optionally, in the above-mentioned PFM mode-controlled boost converter, the driving control circuit in the driving control unit is specifically used to: when the mode switching unit outputs a high-level PFM_EN signal, when the output hysteresis comparison signal is received as a high level, control the N-type power tube and the P-type power tube in the main circuit to be disconnected; when the output hysteresis comparison signal is received as a low level, control the N-type power tube and the P-type power tube in the main circuit to be turned on and off according to the output of the switch logic control unit; when the switch logic control unit is at a high level, the N-type power tube in the main circuit is turned off, and the P-type power tube in the main circuit is turned on; when the switch logic control unit is at a low level, the N-type power tube in the main circuit is turned on, and the P-type power tube in the main circuit is turned off.

[0022] The second aspect of the present application discloses a zero-crossing detection circuit for a PFM mode boost converter, comprising: a bias circuit, a three-stage comparator

[0023] Optionally, in the above-mentioned zero-crossing detection circuit for the PFM mode boost converter, the three-stage comparator includes a first-stage input stage, a second-stage amplifier stage, and a third-stage amplifier stage. The first-stage input is connected to the inputs of both ends of the zero-crossing detection, and the output is connected to the input of the second-stage amplifier stage. The output of the second-stage amplifier stage is connected to the input of the third-stage output stage, and the third-stage amplifier stage outputs the zero-crossing detection comparison result.

[0024] The first input stage is composed of an input pair tube, a clamp tube and an active load, including a first P-type MOS tube MP4, a second P-type MOS tube MP5, a third P-type MOS tube MP6, a fourth P-type MOS tube MP7, a fifth P-type MOS tube MP8, a first N-type MOS tube MN5, a second N-type MOS tube MN6, a third N-type MOS tube MN4, a fourth N-type MOS tube MN7 and a fifth N-type MOS tube MN8; in the first input stage, the source terminal of the first P-type MOS tube MP4 is connected to the output signal VOUT in the main circuit, the second P-type MOS tube MP5 is connected to the SW signal in the main circuit, the drain terminal of the first P-type MOS tube MP4 is connected to the source terminal of the fourth P-type MOS tube MP7, the source terminal of the second P-type MOS tube MP5 is connected to the source terminal of the fifth P-type MOS tube MP8, the gate terminals of the first P-type MOS tube MP4 and the second P-type MOS tube are connected to the enable signal EN, and the source terminal of the third P-type MOS tube MP6 is connected to the output signal VOUT in the main circuit. OUT, the gate terminal of the third P-type MOS transistor MP6 is connected to the gate terminals of the fourth P-type MOS transistor and the fifth P-type MOS transistor, the drain terminal of the third P-type MOS transistor MP6 is connected to the drain terminal of the third N-type MOS transistor MN4, the gate terminal of the first N-type MOS transistor MN5 is connected to the first N-type MOS transistor MN1 in the bias circuit, the source terminal of the first N-type MOS transistor MN5 is connected to the drain terminal of the fourth N-type MOS transistor MN7, the gate terminal of the second N-type MOS transistor MN6 is connected to the first N-type MOS transistor MN1 in the bias circuit, the source terminal of the second N-type MOS transistor MN6 is connected to the drain terminal of the fifth N-type MOS transistor MN8, the gate terminal of the third N-type MOS transistor MN4 is connected to the gate terminal of the third N-type MOS transistor MN3 in the bias circuit, the source terminal of the third N-type MOS transistor MN4 is connected to GND, the gate terminal of the fourth N-type MOS transistor MN7 is connected to the gate terminal of the third N-type MOS transistor MN4, the gate terminal of the fifth N-type MOS transistor MN8 is connected to the gate terminal of the fourth N-type MOS transistor MN7, and the fourth N-type MOS transistor MN7 is connected to the fifth N-type MOS transistor MN8 and GND.

[0025] The second-stage amplifier stage includes a first P-type MOS transistor MP10, a second P-type MOS transistor MP11, a third P-type MOS transistor MP12, a fourth P-type MOS transistor MP9, a fifth P-type MOS transistor MP13, a first N-type MOS transistor MN10, a second N-type MOS transistor MN11, a third N-type MOS transistor MN9, and a fourth N-type MOS transistor MN12; the source end of the first P-type MOS transistor MP10 in the second-stage amplifier stage is connected to VDD, the gate end of the first P-type MOS transistor MP10 is connected to the gate end of the first P-type MOS transistor MP1 in the bias circuit, the drain end of the first P-type MOS transistor MP10 is connected to the source ends of the second P-type MOS transistor MP11 and the third P-type MOS transistor MP12, the second P-type MOS transistor MP11 is connected to the gate end of the fifth P-type MOS transistor MP8 in the first-stage input stage, and the gate end of the first P-type MOS transistor MP10 is connected to the gate end of the first P-type MOS transistor MP1 in the bias circuit. The drain of the second P-type MOS transistor MP11 is connected to the drain of the first N-type MOS transistor MN10, the gate of the third P-type MOS transistor MP12 is connected to the drain of the fourth P-type MOS transistor MP7 in the first input stage, the drain of the third P-type MOS transistor MP12 is connected to the drain of the second N-type MOS transistor MN11, the gate and drain of the first N-type MOS transistor MN10 and the gate of the third N-type MOS transistor MN9 are connected, the source of the first N-type MOS transistor MN10 is connected to GND, the gate and drain of the second N-type MOS transistor MN11 and the gate of the fourth N-type MOS transistor MN12 are connected, the source of the second N-type MOS transistor MN11 is connected to GND, the source of the third N-type MOS transistor MN9 is connected to GND, and the source of the fourth N-type MOS transistor MN12 is connected to GND.

[0026] The third stage amplifier stage includes a first P-type MOS transistor MP14, a first N-type MOS transistor MN13, a first inverter INV1, and a second inverter INV2; the source end of the first P-type MOS transistor MP14 in the second stage amplifier stage is connected to VDD, the gate end of the first P-type MOS transistor MP14 is connected to the first P-type MOS transistor MP1 in the bias circuit, the drain end of the first P-type MOS transistor MP14 is connected to the drain end of the first N-type MOS transistor MN13 and the input end of the first inverter INV1, and the gate end of the first N-type MOS transistor MP14 is connected to the first P-type MOS transistor MP1 in the bias circuit. The gate end of the OS transistor MN13 is connected to the drain ends of the fifth P-type MOS transistor MP13 and the fourth N-type MOS transistor MN12 in the second amplifier stage, the source end of the first N-type MOS transistor MN13 is connected to GND, the input end of the first inverter INV1 is connected to the drains of the first P-type MOS transistor MP14 and the first N-type MOS transistor MN13, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is connected to the output end of the zero-crossing detection circuit.

[0027] Optionally, in the above-mentioned zero-crossing detection circuit for the PFM mode boost converter, the bias circuit includes a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, and a current source IB, the source end of the first P-type MOS transistor MP1 is connected to VDD, the gate end of the first P-type MOS transistor is connected to the gate ends of the second P-type MOS transistor MP2, the third P-type MOS transistor MP3, the first P-type MOS transistor MP10 in the second amplifier stage, and the first P-type MOS transistor MP14 in the third amplifier stage, the drain end of the first P-type MOS transistor is connected to the current source IB, the source end of the second P-type MOS transistor MP2 is connected to VDD, and the drain end of the second P-type MOS transistor MP2 is connected to VDD. The gate terminal of the first N-type MOS transistor MN1 is connected to the drain terminal of the first N-type MOS transistor MN1, the source terminal of the third P-type MOS transistor MP3 is connected to VDD, the drain terminal of the third P-type MOS transistor MP3 is connected to the drain terminal of the second N-type MOS transistor MN2, the gate terminal of the first N-type MOS transistor MN1 is connected to the drain terminal and the gate terminals of the first N-type MOS transistor MN5 and the second N-type MOS transistor MN6 in the first-stage input stage, the source electrode of the first N-type MOS transistor MN1 is connected to GND, the gate terminal of the second N-type MOS transistor MN2 is connected to the drain terminal of the third N-type MOS transistor MN3, the gate terminal of the third N-type MOS transistor MN3 is connected to the gate terminal of the third N-type MOS transistor MN4 in the first-stage input stage, and the source electrode of the third N-type MOS transistor MN3 is connected to GND.

[0028] The zero-crossing detection circuit for a boost converter provided by the present invention comprises: a bias circuit and a three-stage comparator; the three-stage comparator comprises a first-stage input stage, a second-stage amplifier stage and a third-stage amplifier stage; the first-stage input is connected to the input of two ends of the zero-crossing detection, and is an amplifier with a source input current mirror as a load, which can realize the comparison of a wide range of inputs; the output is connected to the input of the second-stage amplifier stage, the second-stage amplifier stage is a push-pull amplifier, the N-type MOS tube and the P-type MOS tube can be turned on in turn, the RC constant is small and the conversion speed is fast, and the flipping speed of the circuit can be improved; the output is connected to the input of the third-stage output stage, and the third-stage amplifier stage is a common source amplifier circuit that outputs the zero-crossing detection comparison result; the zero-crossing detection circuit is used for the PFM control of the boost converter The circuit includes: a mode switching unit, a switch logic control unit, a drive control unit, and a main circuit; wherein: the switch logic control unit is connected to the mode switching unit and the drive control unit respectively, the mode switching unit is connected to the inductor output current of the main circuit, and is used to receive the inductor output current of the main circuit, output a zero-crossing detection signal, and judge to enter the PFM mode according to the number of zero-crossing detection signals; the switch logic control unit is used to output a logic control signal according to the zero-crossing detection signal and a constant on-time control signal; the drive control unit is used to output a drive control signal to drive the N-type and P-type power tubes in the main circuit to turn on and off according to the received logic control signal. This PFM mode-controlled boost converter and its zero-crossing detection circuit can simplify the system control loop, improve the output stability, and realize high-precision and fast detection of circuit zero-crossing detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic structural diagram of a PFM mode controlled boost converter provided by an embodiment of the present invention;

[0030] Figure 2 is a schematic structural diagram of a PFM mode enabling circuit provided by an embodiment of the present invention;

[0031] Figure 3 It is a zero-crossing detection PDB signal and a PFM mode enable signal of the boost converter circuit in the PFM mode provided by an embodiment of the present invention;

[0032] Figure 4 Switch logic signal, switch drive signal, inductor current waveform;

[0033] Figure 5 It is a structural schematic diagram of a zero-crossing detection circuit for a boost converter provided by an embodiment of the present invention.

[0034] Among them, 101 is a mode switching unit; 102 is a switch logic control unit; 103 is a drive control unit; 104 is a main circuit. DETAILED DESCRIPTION

[0035] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the following is a detailed description of a PFM mode controlled boost converter and a zero-crossing detection circuit thereof proposed in accordance with the present invention in combination with the accompanying drawings and specific implementation methods.

[0036] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0037] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the statement "including one..." do not exclude the existence of other identical elements in the article or device including the elements.

[0038] See also Figure 1 The PFM mode controlled boost converter includes: a mode switching unit 101, a switch logic control unit 102, a drive control unit 103, and a main circuit 104.

[0039] The switch logic control unit 102 is connected to the mode switching unit 101 and the drive control unit 103 respectively.

[0040] The mode switching unit 101 includes: a zero-crossing detection circuit and a PFM mode enabling circuit.

[0041] Among them, one end input of the zero-crossing detection circuit serves as the input end of the mode switching unit 101 to receive the inductor output current of the main circuit 104; one end output of the zero-crossing detection circuit serves as the input end of the PFM mode enabling circuit to output a zero-crossing detection signal.

[0042] The output end of the PFM mode enabling circuit serves as the output end of the mode switching unit to output a PFM mode enabling signal.

[0043] The switch logic control unit 102 is used to output a logic control signal according to the zero-crossing detection signal and the constant on-time control signal.

[0044] The driving control unit 103 is used to output a driving control signal to drive the N-type and P-type power tubes in the main circuit 104 to turn on and off according to the received logic control signal.

[0045] Specifically, the switch logic control unit 102 includes a zero-crossing detection circuit, a constant on-time PFM circuit, a two-input AND gate AND, and an RS trigger; the zero-crossing detection circuit outputs a circuit zero-crossing detection signal, the input is connected to the inductor output current of the main circuit 104, and the output is connected to the PFM constant on-time circuit and the two-input AND gate AND; the output of the PFM constant on-time circuit is connected to the S terminal of the RS trigger; the two-input AND gate AND provides a logic AND signal, the input is connected to the PFM_EN signal and the zero-crossing detection signal, and the output is connected to the R terminal of the RS trigger; the RS trigger provides an RS logic signal to the drive circuit, and the output Q terminal is connected to the drive circuit input.

[0046] Among them, the driving control unit 103 includes a driving circuit and a hysteresis comparator; the input end of the driving circuit is connected to the output of the hysteresis comparator and the output end Q of the RS trigger in the switch logic control unit, and the output end of the driving circuit is connected to the gate of the N-type power tube and the gate of the P-type power tube in the main circuit to drive the N-type power tube and the P-type power tube to be turned on and off; the positive input end of the hysteresis comparator is connected to the feedback voltage VFB in the main circuit, and the negative input end is connected to VREF. The output end of the hysteresis comparator is connected to the driving circuit to output a hysteresis comparison signal.

[0047] Among them, the main circuit 104 includes: an input voltage source VIN, an input capacitor, an inductor, an N-type power tube, a P-type power tube, an output capacitor and a first resistor RFB1, and a second resistor RFB2; one end of the input capacitor is connected to the positive input end of the input voltage source VIN to receive the input voltage, the other end of the input capacitor is connected to the negative input end of the input voltage source VIN, one end of the inductor is connected to the input after being filtered by the input capacitor, as the input end of the main circuit, and the other end is respectively connected to the drain end of the N-type power tube and the source end of the P-type power tube, as the first output end of the main circuit, and the output SW end voltage is output. voltage; the drain end of the P-type power tube is respectively connected to one end of the output capacitor and one end of the first resistor RFB1, and the connection point serves as the second output end of the main circuit to output the output voltage; the other end of the output capacitor is respectively connected to the other end of the second resistor RFB2 in the main circuit and the second end of the N-type power tube in the main circuit, the other end of the first resistor RFB1 in the main circuit is connected to one end of the second resistor RFB2 in the main circuit, and the connection point serves as the third output end of the main circuit to output the feedback voltage VFB; the gate end of the N-type power tube and the gate end of the P-type power tube in the main circuit receive corresponding on-off control signals respectively.

[0048] For details, see Figure 2 , Figure 3The PFM mode enabling circuit is composed of four D flip-flops, including a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, and a fourth D flip-flop DFF4. The D terminal of the first D flip-flop DFF1 is connected to the zero-crossing detection signal PDB, the CLK terminal of the first D flip-flop DFF2 is connected to the driving signal, the Re terminal of the first D flip-flop DFF2 is connected to the input terminal of the voltage source VIN in the main circuit, the output Q is connected to the Re terminals of the second D flip-flop DFF2, the third D flip-flop DFF3, and the fourth D flip-flop DFF4, the CLK terminal of the second D flip-flop DFF2 is connected to the driving signal, the D terminal of the second D flip-flop DFF2 is connected to the Q non-terminal, the CLK terminal of the third D flip-flop DFF2 is connected to the D terminal of the second D flip-flop DFF2, the D terminal of the third D flip-flop DFF2 is connected to the Q non-terminal, the D terminal of the fourth D flip-flop DFF2 is connected to the input terminal of the voltage source VIN in the main circuit, the CLK terminal of the fourth D flip-flop DFF2 is connected to the D terminal of the third D flip-flop DFF2, and the Q terminal of the fourth D flip-flop DFF2 is connected to the output PFM_EN signal. According to the zero-crossing detection signal, four judgments are generated to enter the PFM mode, and the PFM mode enable signal is output ( Figure 2 After receiving the zero-crossing detection signal four times, the PFM mode enabling circuit outputs a PFM_EN signal of a high level, which is input to the switch logic control unit to indicate that the system enters the PFM mode.

[0049] For details, see Figure 5 , a zero-crossing detection circuit for a PFM mode boost converter includes a bias circuit and a three-stage comparator.

[0050] Among them, the three-stage comparator includes a first input stage, a second amplifier stage, and a third amplifier stage. The first input is connected to the inputs of both ends of the zero-crossing detection, and the output is connected to the input of the second amplifier stage. The output of the second amplifier stage is connected to the input of the third output stage, and the third amplifier stage outputs the zero-crossing detection comparison result.

[0051] The first input stage is composed of an input pair tube, a clamp tube and an active load, including a first P-type MOS tube MP4, a second P-type MOS tube MP5, a third P-type MOS tube MP6, a fourth P-type MOS tube MP7, a fifth P-type MOS tube MP8, a first N-type MOS tube MN5, a second N-type MOS tube MN6, a third N-type MOS tube MN4, a fourth N-type MOS tube MN7 and a fifth N-type MOS tube MN8; in the first input stage, the source terminal of the first P-type MOS tube MP4 is connected to the output signal VOUT in the main circuit, the second P-type MOS tube MP5 is connected to the SW signal in the main circuit, the drain terminal of the first P-type MOS tube MP4 is connected to the source terminal of the fourth P-type MOS tube MP7, the source terminal of the second P-type MOS tube MP5 is connected to the source terminal of the fifth P-type MOS tube MP8, the gate terminals of the first P-type MOS tube MP4 and the second P-type MOS tube are connected to the enable signal EN, the source terminal of the third P-type MOS tube MP6 is connected to the output signal VOUT in the main circuit, The gate terminal of the third P-type MOS transistor MP6 is connected to the gate terminals of the fourth P-type MOS transistor and the fifth P-type MOS transistor, the drain terminal of the third P-type MOS transistor MP6 is connected to the drain terminal of the third N-type MOS transistor MN4, the gate terminal of the first N-type MOS transistor MN5 is connected to the first N-type MOS transistor MN1 in the bias circuit, the source terminal of the first N-type MOS transistor MN5 is connected to the drain terminal of the fourth N-type MOS transistor MN7, the gate terminal of the second N-type MOS transistor MN6 is connected to the first N-type MOS transistor MN1 in the bias circuit, the source terminal of the second N-type MOS transistor MN6 is connected to the drain terminal of the fifth N-type MOS transistor MN8, the gate terminal of the third N-type MOS transistor MN4 is connected to the gate terminal of the third N-type MOS transistor MN3 in the bias circuit, the source terminal of the third N-type MOS transistor MN4 is connected to GND, the gate terminal of the fourth N-type MOS transistor MN7 is connected to the gate terminal of the third N-type MOS transistor MN4, the gate terminal of the fifth N-type MOS transistor MN8 is connected to the gate terminal of the fourth N-type MOS transistor MN7, and the fourth N-type MOS transistor MN7 is connected to the fifth N-type MOS transistor MN8 and GND.

[0052] The second amplifier stage includes a first P-type MOS transistor MP10, a second P-type MOS transistor MP11, a third P-type MOS transistor MP12, a fourth P-type MOS transistor MP9, a fifth P-type MOS transistor MP13, a first N-type MOS transistor MN10, a second N-type MOS transistor MN11, a third N-type MOS transistor MN9, and a fourth N-type MOS transistor MN12; the source end of the first P-type MOS transistor MP10 in the second amplifier stage is connected to VDD, the gate end of the first P-type MOS transistor MP10 is connected to the gate end of the first P-type MOS transistor MP1 in the bias circuit, the drain end of the first P-type MOS transistor MP10 is connected to the source ends of the second P-type MOS transistor MP11 and the third P-type MOS transistor MP12, the second P-type MOS transistor MP11 is connected to the drain end of the fifth P-type MOS transistor MP8 in the first input stage. The gate terminal of the third P-type MOS transistor MP12 is connected to the drain terminal of the fourth P-type MOS transistor MP7 in the first input stage, the drain terminal of the third P-type MOS transistor MP12 is connected to the drain terminal of the second N-type MOS transistor MN11, the gate terminal and the drain terminal of the first N-type MOS transistor MN10 and the gate terminal of the third N-type MOS transistor MN9 are connected, the source terminal of the first N-type MOS transistor MN10 is connected to GND, the gate terminal and the drain terminal of the second N-type MOS transistor MN11 and the gate terminal of the fourth N-type MOS transistor MN12 are connected, the source terminal of the second N-type MOS transistor MN11 is connected to GND, the source electrode of the third N-type MOS transistor MN9 is connected to GND, and the source terminal of the fourth N-type MOS transistor MN12 is connected to GND.

[0053] The third amplifier stage includes a first P-type MOS transistor MP14, a first N-type MOS transistor MN13, a first inverter INV1, and a second inverter INV2; the gate end of the first P-type MOS transistor MP14 is connected to the first P-type MOS transistor MP1 in the bias circuit, the drain end of the first P-type MOS transistor MP14 is connected to the drain end of the first N-type MOS transistor MN13 and the input end of the first inverter INV1, the gate end of the first N-type MOS transistor MN13 is connected to the drain end of the fifth P-type MOS transistor MP13 and the fourth N-type MOS transistor MN12 in the second amplifier stage, the source end of the first N-type MOS transistor MN13 is connected to GND, the input end of the first inverter INV1 is connected to the drain electrodes of the first P-type MOS transistor MP14 and the first N-type MOS transistor MN13, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is connected to the output end of the zero-crossing detection circuit.

[0054] The bias circuit includes a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, and a current source IB; the source end of the first P-type MOS transistor MP1 is connected to VDD, the gate end of the first P-type MOS transistor is connected to the gate ends of the second P-type MOS transistor MP2, the third P-type MOS transistor MP3, the first P-type MOS transistor MP10 in the second-stage amplifier stage, and the first P-type MOS transistor MP14 in the third-stage amplifier stage, the drain end of the first P-type MOS transistor is connected to the current source IB, the source end of the second P-type MOS transistor MP2 is connected to VDD, the drain end of the second P-type MOS transistor MP2 is connected to the drain end of the first N-type MOS transistor MN1, and the drain end of the second P-type MOS transistor MP2 is connected to the drain end of the first N-type MOS transistor MN1. The first input stage is connected to the input terminal, the source terminal of the third P-type MOS transistor MP3 is connected to VDD, the drain terminal of the third P-type MOS transistor MP3 is connected to the drain terminal of the second N-type MOS transistor MN2, the gate terminal and the drain terminal of the first N-type MOS transistor MN1 and the gate terminals of the first N-type MOS transistor MN5 and the second N-type MOS transistor MN6 in the first input stage are connected, the source electrode of the first N-type MOS transistor MN1 is connected to GND, the gate terminal and the drain terminal of the second N-type MOS transistor MN2 are connected to the gate terminal of the third N-type MOS transistor MN3, the source electrode of the second N-type MOS transistor MN2 is connected to the drain terminal of the third N-type MOS transistor MN3, the gate terminal of the third N-type MOS transistor MN3 is connected to the gate terminal of the third N-type MOS transistor MN4 in the first input stage, and the source electrode of the third N-type MOS transistor MN3 is connected to GND.

[0055] See also Figure 4 When the mode switching unit outputs the PFM_EN signal at a high level, when the output hysteresis comparison signal is received at a high level, the N-type power tube and the P-type power tube in the main circuit are controlled to be disconnected. When the output hysteresis comparison signal is received at a low level, the N-type power tube and the P-type power tube in the main circuit are controlled to be on and off according to the output of the switch logic control unit. When the switch logic control unit is at a high level, the N-type power tube in the main circuit is turned off, and the P-type power tube in the main circuit is turned on. When the switch logic control unit is at a low level, the N-type power tube in the main circuit is turned on, and the P-type power tube in the main circuit is turned off.

Claims

1. A boost converter controlled in PFM mode, characterized in that: include: A mode switching unit (101), a switch logic control unit (102), a drive control unit (103), and a main circuit (104); wherein: the switch logic control unit (102) is connected to the mode switching unit (101) and the drive control unit (103) respectively; the mode switching unit (101) is connected to the inductor output current of the main circuit (104) and is used to receive the inductor output current of the main circuit, output a zero-crossing detection signal, and judge whether to enter a PFM mode according to the number of zero-crossing detection signals; the switch logic control unit (102) is used to output a logic control signal according to the zero-crossing detection signal and a constant on-time control signal; and the drive control unit (103) is used to output a drive control signal according to the received logic control signal to drive the N-type and P-type power tubes in the main circuit (104) to turn on and off.

2. The PFM mode controlled boost converter according to claim 1, characterized in that: The mode switching unit (101) comprises: a zero-crossing detection circuit and a PFM mode enabling circuit; wherein: one end of the zero-crossing detection circuit is input as an input end of the mode switching unit (101) to receive the inductor output current of the main circuit (104); one end of the zero-crossing detection circuit is output as an input end of the PFM mode enabling circuit to output a zero-crossing detection signal; and the output end of the PFM mode enabling circuit is output as an output end of the mode switching unit (101) to output a PFM mode enabling signal.

3. The PFM mode controlled boost converter according to claim 2, characterized in that: The PFM mode enabling circuit is composed of four D flip-flops, including a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, and a fourth D flip-flop DFF4. The D terminal of the first D flip-flop DFF1 is connected to a zero-crossing detection signal PDB, the CLK terminal of the first D flip-flop DFF2 is connected to a driving signal, the Re terminal of the first D flip-flop DFF2 is connected to an input terminal of a voltage source VIN in a main circuit (104), and the output Q is connected to the second D flip-flop DFF2, the third D flip-flop DFF3, and the fourth D flip-flop DF The Re terminal of F4, the CLK terminal of the second D flip-flop DFF2 is connected to the drive signal, the D terminal of the second D flip-flop DFF2 is connected to the Q non-terminal, the CLK terminal of the third D flip-flop DFF2 is connected to the D terminal of the second D flip-flop DFF2, the D terminal of the third D flip-flop DFF2 is connected to the Q non-terminal, the D terminal of the fourth D flip-flop DFF2 is connected to the input terminal of the voltage source VIN in the main circuit (104), the CLK terminal of the fourth D flip-flop DFF2 is connected to the D terminal of the third D flip-flop DFF2, and the Q terminal of the fourth D flip-flop DFF2 is connected to the output PFM_EN signal.

4. A zero-crossing detection circuit for a boost converter controlled in PFM mode as claimed in claims 1 to 3, characterized in that: The zero-crossing detection circuit is divided into two parts, a bias circuit and a three-stage comparator. The three-stage comparator includes a first-stage input stage, a second-stage amplifier stage, and a third-stage amplifier stage. The first-stage input is connected to the inputs of both ends of the zero-crossing detection, and the output is connected to the input of the second-stage amplifier stage. The output of the second-stage amplifier stage is connected to the input of the third-stage output stage, and the third-stage amplifier stage outputs the zero-crossing detection comparison result.

5. The zero-crossing detection circuit according to claim 4, characterized in that: The first input stage is composed of an input pair tube, a clamp tube and an active load, and includes a first P-type MOS tube MP4, a second P-type MOS tube MP5, a third P-type MOS tube MP6, a fourth P-type MOS tube MP7, a fifth P-type MOS tube MP8, a first N-type MOS tube MN5, a second N-type MOS tube MN6, a third N-type MOS tube MN4, a fourth N-type MOS tube MN7 and a fifth N-type MOS tube MN8; in the first input stage, the source terminal of the first P-type MOS tube MP4 is connected to the output signal VOUT in the main circuit (104), the second P-type MOS tube MP5 is connected to the SW signal in the main circuit (104), the drain terminal of the first P-type MOS tube MP4 is connected to the source terminal of the fourth P-type MOS tube MP7, the source terminal of the second P-type MOS tube MP5 is connected to the source terminal of the fifth P-type MOS tube MP8, the gate terminals of the first P-type MOS tube MP4 and the second P-type MOS tube are connected to the enable signal EN, and the source terminal of the third P-type MOS tube MP6 is connected to the output signal VOUT in the main circuit (104). The output signal VOUT is outputted from the output signal VOUT, the gate terminal of the third P-type MOS transistor MP6 is connected to the gate terminals of the fourth P-type MOS transistor and the fifth P-type MOS transistor, the drain terminal of the third P-type MOS transistor MP6 is connected to the drain terminal of the third N-type MOS transistor MN4, the gate terminal of the first N-type MOS transistor MN5 is connected to the first N-type MOS transistor MN1 in the bias circuit, the source terminal of the first N-type MOS transistor MN5 is connected to the drain terminal of the fourth N-type MOS transistor MN7, the gate terminal of the second N-type MOS transistor MN6 is connected to the first N-type MOS transistor MN1 in the bias circuit, the source terminal of the second N-type MOS transistor MN6 is connected to the drain terminal of the fifth N-type MOS transistor MN8, the gate terminal of the third N-type MOS transistor MN4 is connected to the gate terminal of the third N-type MOS transistor MN3 in the bias circuit, the source terminal of the third N-type MOS transistor MN4 is connected to GND, the gate terminal of the fourth N-type MOS transistor MN7 is connected to the gate terminal of the third N-type MOS transistor MN4, the gate terminal of the fifth N-type MOS transistor MN8 is connected to the gate terminal of the fourth N-type MOS transistor MN7, and the fourth N-type MOS transistor MN7 is connected to the fifth N-type MOS transistor MN8 and GND.

6. The zero-crossing detection circuit according to claim 4, characterized in that: The second amplifier stage includes a first P-type MOS transistor MP10, a second P-type MOS transistor MP11, a third P-type MOS transistor MP12, a fourth P-type MOS transistor MP9, a fifth P-type MOS transistor MP13, a first N-type MOS transistor MN10, a second N-type MOS transistor MN11, a third N-type MOS transistor MN9, and a fourth N-type MOS transistor MN12; the source end of the first P-type MOS transistor MP10 in the second amplifier stage is connected to VDD, the gate end of the first P-type MOS transistor MP10 is connected to the gate end of the first P-type MOS transistor MP1 in the bias circuit, the drain end of the first P-type MOS transistor MP10 is connected to the source ends of the second P-type MOS transistor MP11 and the third P-type MOS transistor MP12, the second P-type MOS transistor MP11 is connected to the drain end of the fifth P-type MOS transistor MP8 in the first input stage. The gate terminal of the third P-type MOS transistor MP12 is connected to the drain terminal of the fourth P-type MOS transistor MP7 in the first input stage, the drain terminal of the third P-type MOS transistor MP12 is connected to the drain terminal of the second N-type MOS transistor MN11, the gate terminal and the drain terminal of the first N-type MOS transistor MN10 and the gate terminal of the third N-type MOS transistor MN9 are connected, the source terminal of the first N-type MOS transistor MN10 is connected to GND, the gate terminal and the drain terminal of the second N-type MOS transistor MN11 and the gate terminal of the fourth N-type MOS transistor MN12 are connected, the source terminal of the second N-type MOS transistor MN11 is connected to GND, the source electrode of the third N-type MOS transistor MN9 is connected to GND, and the source terminal of the fourth N-type MOS transistor MN12 is connected to GND.

7. The zero-crossing detection circuit according to claim 4, characterized in that: The third stage amplifier includes a first P-type MOS transistor MP14, a first N-type MOS transistor MN13, a first inverter INV1, and a second inverter INV2; the source end of the first P-type MOS transistor MP14 in the second stage amplifier is connected to VDD, the gate end of the first P-type MOS transistor MP14 is connected to the first P-type MOS transistor MP1 in the bias circuit, the drain end of the first P-type MOS transistor MP14 is connected to the drain end of the first N-type MOS transistor MN13 and the input end of the first inverter INV1, and the gate end of the first P-type MOS transistor MP14 is connected to the gate end of the first N-type MOS transistor MN13 and the input end of the first inverter INV2. The gate terminal of the S transistor MN13 is connected to the drain terminals of the fifth P-type MOS transistor MP13 and the fourth N-type MOS transistor MN12 in the second amplifier stage, the source terminal of the first N-type MOS transistor MN13 is connected to GND, the input terminal of the first inverter INV1 is connected to the drain terminals of the first P-type MOS transistor MP14 and the first N-type MOS transistor MN13, the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2, and the output terminal of the second inverter INV2 is connected to the output terminal of the zero-crossing detection circuit.

8. The zero-crossing detection circuit according to claim 4, characterized in that: The bias circuit includes a first P-type MOS transistor MP1, a second P-type MOS transistor MP2, a third P-type MOS transistor MP3, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, and a current source IB. The source end of the first P-type MOS transistor MP1 is connected to VDD, the gate end of the first P-type MOS transistor is connected to the gate ends of the second P-type MOS transistor MP2, the third P-type MOS transistor MP3, the first P-type MOS transistor MP10 in the second-stage amplifier stage, and the first P-type MOS transistor MP14 in the third-stage amplifier stage, the drain end of the first P-type MOS transistor is connected to the current source IB, the source end of the second P-type MOS transistor MP2 is connected to VDD, and the drain end of the second P-type MOS transistor MP2 is connected to the drain end of the first N-type MOS transistor MN1. The source terminal of the third P-type MOS transistor MP3 is connected to VDD, the drain terminal of the third P-type MOS transistor MP3 is connected to the drain terminal of the second N-type MOS transistor MN2, the gate terminal and the drain terminal of the first N-type MOS transistor MN1 and the gate terminals of the first N-type MOS transistor MN5 and the second N-type MOS transistor MN6 in the first-stage input stage are connected, the source electrode of the first N-type MOS transistor MN1 is connected to GND, the gate terminal and the drain terminal of the second N-type MOS transistor MN2 are connected to the gate terminal of the third N-type MOS transistor MN3, the source electrode of the second N-type MOS transistor MN2 is connected to the drain terminal of the third N-type MOS transistor MN3, the gate terminal of the third N-type MOS transistor MN3 is connected to the gate terminal of the third N-type MOS transistor MN4 in the first-stage input stage, and the source electrode of the third N-type MOS transistor MN3 is connected to GND.

9. The PFM mode controlled boost converter according to any one of claims 2 to 3, characterized in that: The mode switching unit (101) is specifically used for: after receiving the zero-crossing detection signal four times, the PFM mode enabling circuit outputs a PFM_EN signal of a high level, which is input to the switch logic control unit (102) to indicate that the system enters the PFM mode.

10. The PFM mode controlled boost converter according to claim 1, characterized in that: The switch logic control unit (102) comprises a zero-crossing detection circuit, a constant on-time PFM circuit, a two-input AND gate AND, and an RS trigger; wherein: the zero-crossing detection circuit outputs a circuit zero-crossing detection signal, the input is connected to the inductor output current of the main circuit (104), and the output is connected to the PFM constant on-time circuit and the two-input AND gate AND; the output of the PFM constant on-time circuit is connected to the S terminal of the RS trigger; the two-input AND gate AND provides a logic AND signal, the input is connected to the PFM_EN signal and the zero-crossing detection signal, and the output is connected to the R terminal of the RS trigger; the RS trigger provides an RS logic signal to the drive circuit, and the output Q terminal is connected to the drive circuit input.

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