Level conversion circuit and conversion method applied to cross-device joint debugging scene such as FPGA debugging

Abstract

The invention relates to a level conversion circuit and method applied to cross-device joint debugging scenes such as FPGA debugging, and belongs to the technical field of integrated circuits. The level conversion circuit comprises a PMOS, resistors R1, R2, R3 and R4, an error amplifier and a multiplexer, the S pole of the PMOS is connected with a signal input end, the G pole of the PMOS is connected with the error amplifier, the reverse end of the error amplifier is connected with one end of the R1 and one end of the R2, the other end of the R1 is connected with Vref, the other end of the R2 is grounded, the same-direction end of the error amplifier is connected with one end of the R3 and one end of the R4, and the other end of the R3 and the other end of the R4 are grounded. The other end of the R3 is connected with a feedback signal input interface of a multiplexer, the other end of the R4 is grounded, a D pole of the PMOS is respectively connected with the multiplexer and a signal output end, and the resistors R1, R2, R3 and R4, the error amplifier and the multiplexer jointly form a negative feedback system. By adjusting the resistance in the feedback circuit, the output of different level signals can be realized.

Description

Technical Field

[0001] The present invention relates to a level conversion circuit and a conversion method applied to cross-device joint debugging scenarios such as FPGA debugging, and belongs to the technical field of integrated circuits. Background Art

[0002] FPGA (Field Programmable Gate Array), Chinese name, field programmable logic gate array, is a common device in chip research and development. When it is used for debugging, it often needs to be connected to other devices as its master or slave device. In this process, the level matching problem is one of the most common debugging problems. Taking the common FPGA on the market as an example, the common level of the input and output interface of its FMC (FPGA Mezzanine Card) connector is fixed at 1.2V or 1.8V. When the input and output interface voltage of the docked master or slave device is a mixture of 1.2V and 1.8V levels, or other common levels such as 1.5V and 3.3V, there will be a problem of mismatch in the levels of the devices at both ends. This problem may cause the high and low levels to not be recognized normally, affecting the FPGA function debugging, or even causing the device to burn out. For example, when the FPGA is at a 1.2V level and the opposite device is at a 1.8V level, 1.8V exceeds the upper limit of the withstand voltage of the 1.2V MOS, which will burn out the FPGA port and even the main control chip and PMU (power control system), causing debugging failures. Therefore, the level conversion circuit has a wide range of application scenarios in device cross-connection scenarios such as FPGA debugging.

[0003] In the current level conversion method, a levelshifter chip composed of two inverters is often used, but the levelshifter chips on the market usually require two external power supplies. The voltage values ​​of these two external power supplies determine the level conversion values ​​that can be achieved. For example, if the external power supplies are 1.8V and 1.2V, it can only achieve signal conversion from 1.8V level to 1.2V level or from 1.2V level to 1.8V level. The achievable level conversion range is limited by the input voltage, and flexible level conversion cannot be achieved. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention provides a level conversion circuit and conversion method for cross-device joint debugging scenarios such as FPGA debugging. By adjusting the resistance in the feedback circuit, the output of different level signals can be achieved. The output level is V out =V ref ×[R2(R3+R4)] / [R4(R1+R2)], at V ref After determination, different V can be achieved by adjusting R1, R2, R3, and R4. outOutput to meet the needs of different debugging scenarios such as FPGA debugging and device cross-connect debugging.

[0005] Terminology explanation:

[0006] PMOS: refers to a MOS tube with n-type substrate and p-channel, which transports current by the flow of holes.

[0007] The technical solution of the present invention is as follows:

[0008] A level conversion circuit used in cross-device joint debugging scenarios such as FPGA debugging includes a PMOS, resistors R1, R2, R3, R4, an error amplifier and a multiplexer, wherein:

[0009] The S pole of the PMOS is connected to the signal input terminal, the G pole is connected to the error amplifier, the reverse end of the error amplifier is connected to one end of R1 and R2 respectively, the other end of R1 is connected to Vref, the other end of R2 is grounded, the same direction end of the error amplifier is connected to one end of R3 and R4 respectively, the other end of R3 is connected to the feedback signal input interface of the multiplexer, the other end of R4 is grounded, the D pole of the PMOS is connected to the multiplexer and the signal output terminal respectively, and the resistors R1, R2, R3, R4, the error amplifier and the multiplexer together constitute a negative feedback system.

[0010] A multiplexer can select physical pin replacements with similar functionality.

[0011] According to the present invention, it is further preferred that four PMOS are provided, the S poles of the four PMOS are respectively connected to four signal input terminals, which are named as signal 1 input terminal, signal 2 input terminal, signal 3 input terminal and signal 4 input terminal, and the D poles of the four PMOS are respectively connected to four signal output terminals, which are named as signal 1 output terminal, signal 2 output terminal, signal output terminal 3 and signal 4 output terminal, and the other connection structures of the PMOS remain unchanged.

[0012] The above-mentioned conversion method of the level conversion circuit applied to cross-device joint debugging scenarios such as FPGA debugging has the following steps:

[0013] (1) The FPGA is the host, and the FPGA is the signal receiving end. A level conversion circuit is set between the host and the FPGA to obtain the level of the FPGA communication interface and the level of the host communication interface. If the levels of the host and the FPGA do not match, a level conversion circuit is required to convert them. Set the resistance values ​​of R1, R2, R3, and R4 and V ref Voltage; for example, the communication interface level of the FPGA end is 1.2V, and the communication interface level of the host end is 1.8V. Set the variable resistors R1, R2, R3, and R4 to 5kohm, 4kohm, 1kohm, and 2kohm, V refConnect to the host end 1.8V power supply;

[0014] (2) The signal collected by the multiplexer is used to realize the level conversion of one or more signals. For example, when multiple signals are converted from 1.8V to 1.2V, only the feedback level of one signal is collected to the feedback signal input interface, so as to realize the control of the output levels of multiple signals. Taking the scenario where there is only one output signal on the host side as an example, the output signal is connected to the signal 1 input end of the level conversion circuit, and the feedback signal of signal 1 is connected to the feedback signal input interface by adjusting the multiplexer;

[0015] (3) The host and FPGA start signal transmission. The signal goes from the host to the S pole of the PMOS inside the circuit through the signal 1 input interface of the level conversion circuit. At this time, the level of the same-direction end of the error amplifier is 0, and the voltage of the reverse end is 1.2 V. The error amplifier outputs a negative voltage, and the PMOS is in a fully turned-on state. The output voltage of the D pole of the PMOS gradually increases. At the same time, the increased voltage is fed back to the G pole of the PMOS in real time through the negative feedback system, which has a real-time impact on the working state of the PMOS.

[0016] (4) As negative feedback continues, according to the physical properties of the error amplifier, when the entire loop reaches a stable state through the negative feedback system, the error amplifier will be in a virtual short state, that is, the voltage at the same direction end of the error amplifier is equal to the voltage at the reverse direction end. At this time, the voltage at the same direction end is V ref ×R2 / (R1+R2), the reverse terminal voltage is V out ×R4 / (R3+R4), combined with the resistance value set in step (1) and V ref Voltage, calculated to get V out =V ref ×[R2(R3+R4)] / [R4(R1+R2)]=1.2V; realize level conversion of inputting 1.8V level signal at the signal input end and outputting 1.2V level signal at the signal output end.

[0017] Preferably, in step (1), the level conversion circuit is set up in such a way that a level conversion circuit is inserted between the main control chip and the signal interface at the host end, and the signal interface at the host end is connected to the signal interface at the FPGA end via an FPC soft board. When a signal is sent or received, it will first pass through the deployed level conversion circuit to achieve matching of the levels at both ends during communication. This method is suitable for the circuit board of the communication device (host end or FPGA end), and the problem of level mismatch at both ends of the communication device is considered at the beginning of the design, and the method is used to design and deploy the level conversion circuit. The advantage of this method is that the host end or the FPGA end has its own level conversion system, and can communicate directly without other circuit connections, which is easy to use.

[0018] According to the preferred embodiment of the present invention, in step (1), the level conversion circuit is set in such a way that the level conversion circuit is hardened on the circuit board to form a level conversion device, and the two ends of the level conversion device are respectively connected to the signal interface of the host end and the signal interface of the FPGA end through the FPC soft board. When the host end device transmits the signal, it first passes through the level conversion device for level conversion before reaching the FPGA end, so as to achieve the matching of the signal levels of the two end devices. This method is suitable for the communication equipment circuit board (host end or FPGA end) when the level mismatch signal is not level converted at the beginning of the design, and the problem signal is converted by adding an intermediate level conversion circuit board or a level conversion chip in the later stage. The advantage of this method is that the level conversion device is independent of the host end or the FPGA end, and the host end, the FPGA end and the level conversion device are replaced or redesigned without affecting each other, and it is flexible to use.

[0019] The beneficial effects of the present invention are:

[0020] The present invention can realize the output of signals of different levels by adjusting the resistance in the feedback circuit. The output level is V out =V ref ×[R2(R3+R4)] / [R4(R1+R2)], at V ref After determination, different V can be achieved by adjusting R1, R2, R3, and R4. out Output to meet the needs of different debugging scenarios such as FPGA debugging and device cross-connect debugging. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the cross-device connection scenario for debugging an existing FPGA;

[0022] Figure 2 This is a schematic diagram of the scenario where the device level does not match during existing FPGA debugging;

[0023] Figure 3 This is an application mode of the level conversion circuit of embodiment 1 of the present invention;

[0024] Figure 4 This is an application mode of the level conversion circuit of embodiment 2 of the present invention;

[0025] Figure 5 It is a schematic diagram of the internal structure of the level conversion circuit of the present invention. DETAILED DESCRIPTION

[0026] The present invention will be further described below by way of embodiments in conjunction with the accompanying drawings, but is not limited thereto.

[0027] Embodiment 1:

[0028] This embodiment provides a level conversion circuit for use in cross-device joint debugging scenarios such as FPGA debugging, including a PMOS, resistors R1, R2, R3, R4, an error amplifier, and a multiplexer, wherein:

[0029] The S pole of the PMOS is connected to the signal input terminal, the G pole is connected to the error amplifier, the reverse end of the error amplifier is connected to one end of R1 and R2 respectively, the other end of R1 is connected to Vref, the other end of R2 is grounded, the same direction end of the error amplifier is connected to one end of R3 and R4 respectively, the other end of R3 is connected to the feedback signal input interface of the multiplexer, the other end of R4 is grounded, the D pole of the PMOS is connected to the multiplexer and the signal output terminal respectively, and the resistors R1, R2, R3, R4, the error amplifier and the multiplexer together constitute a negative feedback system.

[0030] There are four PMOSs, and the S poles of the four PMOSs are connected to four signal input terminals, respectively named as signal 1 input terminal, signal 2 input terminal, signal 3 input terminal and signal 4 input terminal, and the D poles of the four PMOSs are connected to four signal output terminals, respectively named as signal 1 output terminal, signal 2 output terminal, signal output terminal 3 and signal 4 output terminal, and the other connection structures of the PMOS remain unchanged.

[0031] The connection topology when FPGA performs cross-device joint debugging is as follows Figure 1 As shown in the figure, the FPGA peer device (taking FPGA as the receiving end as an example, the peer end is the host end) connects the two end devices through the connection medium of FPC (Flexible Printed Circuit) to transmit signals. When the signal levels of the two end devices do not match, the following will occur: Figure 2 In the hardware burnout situation shown in the figure, when a high-level signal is transmitted to a low-level device through a transmission medium, the voltage will exceed the withstand voltage upper limit of the communication interface, causing the interface to burn out and unable to communicate normally. The high voltage may even flow back into the main control chip and the power management system (PMU) along the board-level circuit, causing complete damage to the device. At this time, a level conversion circuit is needed to convert the signal levels at both ends.

[0032] The above-mentioned conversion method of the level conversion circuit applied to cross-device joint debugging scenarios such as FPGA debugging has the following steps:

[0033] (1) The FPGA is the host, and the FPGA is the signal receiving end. A level conversion circuit is set between the host and the FPGA to obtain the level of the FPGA communication interface and the level of the host communication interface. If the levels of the host and the FPGA do not match, a level conversion circuit is required to convert them. Set the resistance values ​​of R1, R2, R3, and R4 and V refVoltage; for example, the communication interface level of the FPGA end is 1.2V, and the communication interface level of the host end is 1.8V. Set the variable resistors R1, R2, R3, and R4 to 5kohm, 4kohm, 1kohm, and 2kohm, V ref Connect to the host end 1.8V power supply;

[0034] (2) The signal collected by the multiplexer is used to realize the level conversion of one or more signals. For example, when multiple signals are converted from 1.8V to 1.2V, only the feedback level of one signal is collected to the feedback signal input interface, so as to realize the control of the output levels of multiple signals. Taking the scenario where there is only one output signal on the host side as an example, the output signal is connected to the signal 1 input end of the level conversion circuit, and the feedback signal of signal 1 is connected to the feedback signal input interface by adjusting the multiplexer;

[0035] (3) The host and FPGA start signal transmission. The signal goes from the host to the S pole of the PMOS inside the circuit through the signal 1 input interface of the level conversion circuit. At this time, the level of the same-direction end of the error amplifier is 0, and the voltage of the reverse end is 1.2 V. The error amplifier outputs a negative voltage, and the PMOS is in a fully turned-on state. The output voltage of the D pole of the PMOS gradually increases. At the same time, the increased voltage is fed back to the G pole of the PMOS in real time through the negative feedback system, which has a real-time impact on the working state of the PMOS.

[0036] (4) As negative feedback continues, according to the physical properties of the error amplifier, when the entire loop reaches a stable state through the negative feedback system, the error amplifier will be in a virtual short state, that is, the voltage at the same direction end of the error amplifier is equal to the voltage at the reverse direction end. At this time, the voltage at the same direction end is V ref ×R2 / (R1+R2), the reverse terminal voltage is V out ×R4 / (R3+R4), combined with the resistance value set in step (1) and V ref Voltage, calculated to get V out =V ref ×[R2(R3+R4)] / [R4(R1+R2)]=1.2V; realize level conversion of inputting 1.8V level signal at the signal input end and outputting 1.2V level signal at the signal output end.

[0037] In step (1), the level conversion circuit is set up in such a way that a level conversion circuit is inserted between the main control chip and the signal interface at the host end. The signal interface at the host end is connected to the signal interface at the FPGA end through an FPC soft board. When a signal is sent or received, it will first pass through the deployed level conversion circuit to achieve matching of the levels at both ends during communication. This method is suitable for the communication device circuit board (host end or FPGA end) to consider the level mismatch problem at both ends of the communication device at the beginning of the design, and adopt this method to design and deploy the level conversion circuit. The advantage of this method is that the host end or the FPGA end has its own level conversion system, and can communicate directly without other circuit connections, which is easy to use.

[0038] Embodiment 2:

[0039] A conversion method for a level conversion circuit in a cross-device joint debugging scenario such as FPGA debugging as described in Example 1, the difference is that in step (1), the level conversion circuit is set in such a way that the level conversion circuit is hardened on a circuit board to form a level conversion device, and the two ends of the level conversion device are respectively connected to the signal interface of the host end and the signal interface of the FPGA end through an FPC soft board. When the host end device transmits a signal, it first passes through the level conversion device for level conversion before reaching the FPGA end, so as to achieve matching of the signal levels of the devices at both ends. This method is suitable for the communication equipment circuit board (host end or FPGA end) when the level mismatch signal is not level converted at the beginning of the design, and the problem signal is converted by adding an intermediate level conversion circuit board or a level conversion chip in the later stage. The advantage of this method is that the level conversion device is independent of the host end or the FPGA end, and the host end, the FPGA end and the level conversion device are replaced or redesigned without affecting each other, and it is flexible to use.

[0040] The above embodiments are used to illustrate the present invention rather than to limit the present invention. Any equivalent changes made to the present invention within the protection scope of the claims of the present invention shall fall within the protection scope of the present invention.

Claims

1. A level conversion circuit used in cross-device joint debugging scenarios such as FPGA debugging, characterized in that: It includes PMOS, resistors R1, R2, R3, R4, error amplifier and multiplexer, among which: The S pole of the PMOS is connected to the signal input terminal, the G pole is connected to the error amplifier, the reverse end of the error amplifier is connected to one end of R1 and R2 respectively, the other end of R1 is connected to Vref, the other end of R2 is grounded, the same direction end of the error amplifier is connected to one end of R3 and R4 respectively, the other end of R3 is connected to the feedback signal input interface of the multiplexer, the other end of R4 is grounded, the D pole of the PMOS is connected to the multiplexer and the signal output terminal respectively, and the resistors R1, R2, R3, R4, the error amplifier and the multiplexer together constitute a negative feedback system.

2. The level conversion circuit used in cross-device joint debugging scenarios such as FPGA debugging according to claim 1 is characterized in that: There are four PMOSs, and the S poles of the four PMOSs are connected to four signal input terminals, respectively named as signal 1 input terminal, signal 2 input terminal, signal 3 input terminal and signal 4 input terminal, and the D poles of the four PMOSs are connected to four signal output terminals, respectively named as signal 1 output terminal, signal 2 output terminal, signal output terminal 3 and signal 4 output terminal.

3. A conversion method for a level conversion circuit applied to a cross-device joint debugging scenario such as FPGA debugging as claimed in claim 2, characterized in that: Here are the steps: (1) The FPGA is the host, and the FPGA is the signal receiving end. A level conversion circuit is set between the host and the FPGA to obtain the level of the FPGA communication interface and the level of the host communication interface. If the levels of the host and the FPGA do not match, a level conversion circuit is required to convert them. Set the resistance values ​​of R1, R2, R3, and R4 and V ref Voltage; (2) realizing level conversion of one or more signals through the signals collected by the multiplexer; (3) The host and FPGA start signal transmission. The signal goes from the host to the S pole of the PMOS inside the circuit through the signal 1 input interface of the level conversion circuit. At this time, the level of the same-direction end of the error amplifier is 0, and the voltage of the reverse end is 1.2 V. The error amplifier outputs a negative voltage, and the PMOS is in a fully turned-on state. The output voltage of the D pole of the PMOS gradually increases. At the same time, the increased voltage is fed back to the G pole of the PMOS in real time through the negative feedback system, which has a real-time impact on the working state of the PMOS. (4) As negative feedback continues, according to the physical properties of the error amplifier, when the entire loop reaches a stable state through the negative feedback system, the error amplifier will be in a virtual short state, that is, the voltage at the same direction end of the error amplifier is equal to the voltage at the reverse direction end. At this time, the voltage at the same direction end is V ref ×R2 / (R1+R2), the reverse terminal voltage is V out ×R4 / (R3+R4), combined with the resistance value set in step (1) and V ref Voltage, calculated to get V out =V ref ×[R2(R3+R4)] / [R4(R1+R2)]; Realize level conversion.

4. The conversion method of the level conversion circuit applied to cross-device joint debugging scenarios such as FPGA debugging as claimed in claim 3 is characterized in that: In step (1), the level conversion circuit is set up in such a way that the level conversion circuit is inserted between the main control chip and the signal interface at the host end, and the signal interface at the host end is connected to the signal interface at the FPGA end through an FPC soft board.

5. The conversion method of the level conversion circuit applied to cross-device joint debugging scenarios such as FPGA debugging as claimed in claim 3 is characterized in that: In step (1), the level conversion circuit is set up in such a way that the level conversion circuit is hardened on a circuit board to form a level conversion device, and two ends of the level conversion device are respectively connected to a signal interface at the host end and a signal interface at the FPGA end through an FPC soft board.

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