A time domain residual error amplifier for a pipelined analog-to-digital converter

Abstract

The application discloses a time domain residual error amplifier for a pipeline analog-to-digital converter, comprising a threshold detection circuit, a voltage amplification circuit and a phase detector; wherein the voltage amplification circuit is connected with the threshold detection circuit and the phase detector respectively; the threshold detection circuit is connected with the phase detector; the voltage amplification circuit comprises a first-stage sampling capacitor, a second-stage sampling capacitor and a constant current pull-down charge pump. The constant current pull-down charge pump discharges the first-stage sampling capacitor at a constant speed through a mirror current of a current mirror, and converts the residual error voltage reserved by the first-stage sampling capacitor into a time signal; the phase detector controls the second-stage sampling capacitor to charge and discharge according to the triggering condition of the threshold detection circuit, and converts the time signal back into a voltage signal. The time domain residual error amplifier for the pipeline analog-to-digital converter provided by the application can realize voltage gain in the form of the product of the proportion of a capacitor and the proportion of a current mirror current, and can optimize linearity and PVT robustness while retaining low power consumption characteristics.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a time-domain residual amplifier for pipelined analog-to-digital converters. Background Technology

[0002] Pipeline analog-to-digital converters (ADCs) are in high demand for high-speed and high-resolution applications. Furthermore, pipelined ADCs place high demands on the residual amplifier, whose performance directly determines the overall performance of the pipelined ADC. Therefore, pipelined ADCs require a high-speed, high-linearity, and sufficiently stable residual amplifier. Traditional residual amplifiers often employ closed-loop operational amplifiers (MDACs) or dynamic amplifiers (DAs), but these amplifiers are limited by bandwidth, gain, and energy efficiency, restricting their application in modern high-precision ADCs.

[0003] To address the demands for high speed and low power consumption, this invention provides a time-domain residual voltage amplifier that processes residual voltage using a time signal, thereby achieving higher linearity and PVT robustness while maintaining an open-loop structure. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a time-domain residual amplifier for pipelined analog-to-digital converters. The technical solution adopted by this invention is as follows:

[0005] The aforementioned time-domain residual amplifier for a pipelined analog-to-digital converter includes:

[0006] The circuit includes a threshold detection circuit, a voltage amplification circuit, and a phase detector; among which,

[0007] The voltage amplifier circuit is connected to the threshold detection circuit and the phase detector respectively; the threshold detection circuit is connected to the phase detector.

[0008] The voltage amplifier circuit includes first-stage sampling capacitors DAC_P and DAC_N, second-stage sampling capacitors DAC2_P and DAC2_N, and a constant current pull-down charge pump.

[0009] The voltage amplifier circuit includes:

[0010] A constant current source; a first current mirror structure consisting of 12 NMOS transistors MM1_1 to MM1_12; a second current mirror structure consisting of 6 PMOS transistors MM2_1 to MM2_6; 2 NMOS transistors MD1_1 and MD1_2; first-stage sampling capacitors DAC_P and DAC_N; 8 NMOS transistors MD2_1 to MD2_8; second-stage sampling capacitors DAC2_P and DAC2_N; and 2 NMOS transistors ME1 and ME2.

[0011] In the voltage amplifier circuit, the upper plates of the first-stage sampling capacitors DAC_P and DAC_N are connected to the sources of MD1_1 and MD1_2 respectively and input with the residual voltage Vres, while the lower plates are grounded; the gates of MD1_1 and MD1_2 are connected to the EN enable signal.

[0012] In the voltage amplification circuit, the upper plates of the second-stage sampling capacitors DAC2_P and DAC2_N are connected to the sources of MD2_1 and MD2_5 respectively, and output the result Vout; the lower plates are all grounded; the gates of MD2_1 to MD2_8 receive the UP, UPN, DW, and DWN signals.

[0013] The threshold detection circuit described above uses a continuous-time comparator;

[0014] The continuous-time comparator employs a four-stage cascaded self-biased open-loop operational amplifier, combined with a five-transistor operational amplifier to perform differential-to-single-ended operation, resulting in a single-ended output.

[0015] The phase detector includes two D flip-flops and one AND gate.

[0016] The self-biased open-loop operational amplifier consists of seven transistors M1 to M7, where M1 to M3 are NMOS transistors and M4 to M6 are PMOS transistors. The gates Vin and Vip of M2 and M3 are connected to the reference threshold voltage Vthres and the upper plate voltage of the first-stage sampling capacitor, respectively. The drain voltages Von and Vop of M2 and M3 output Vout.

[0017] The five-transistor op-amp is a classic five-transistor OTA. Von and Vop are connected to the differential input terminals of the five-transistor op-amp, and the single-ended output is obtained after passing through two inverters to obtain the output VOUT.

[0018] All of the D flip-flops are rising-edge triggered and have a reset terminal (Reset).

[0019] In the phase detector, the D terminal of the D flip-flop is always connected to a high level; the output signal of the threshold detection circuit is connected to the first two-input AND gate; the output of the first two-input AND gate is connected to the CLK input terminal of the D flip-flop; the Q output terminal of the D flip-flop generates UP and DW rectangular pulse signals; UP and DW are input to the second two-input AND gate; the output of the second two-input AND gate is connected to the Reset terminal of the D flip-flop; UP and DW are each connected to an inverter; the inverter outputs UPN and DWN.

[0020] Compared with the prior art, the advantages of the present invention are as follows:

[0021] The present invention provides a time-domain residual amplifier for pipelined analog-to-digital converters. The gain is determined by the capacitance ratio and the current ratio, thus the gain fluctuation is small under different PVT conditions. It has high linearity and high robustness, and is suitable for high-speed and high-precision applications.

[0022] The present invention provides a time-domain residual amplifier for pipelined analog-to-digital converters, which reduces the overhead of operational amplifier design and has lower power consumption compared with traditional closed-loop amplifiers. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of a time-domain residual amplifier for a pipelined analog-to-digital converter provided by an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of the working waveform of a time-domain residual amplifier for a pipelined analog-to-digital converter provided by an embodiment of the present invention;

[0026] Figure 3 This is a structural diagram of a voltage amplifier circuit provided in an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of a threshold detection circuit and phase detector provided in an embodiment of the present invention;

[0028] Figure 5 This is a schematic diagram of a threshold detection circuit provided in an embodiment of the present invention; Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0031] Example 1

[0032] like Figure 1As shown, the present invention provides a time-domain residual amplifier for a pipelined analog-to-digital converter, comprising:

[0033] The circuit includes a threshold detection circuit, a voltage amplification circuit, and a phase detector; among which,

[0034] The voltage amplifier circuit includes a first-stage sampling capacitor, a second-stage sampling capacitor, and a constant-current pull-down charge pump.

[0035] The first-stage sampling capacitors DAC_P and DAC_N sample the residual voltage Vres. The current Iref of the constant current pull-down charge pump is amplified N times by a current mirror to charge and discharge the first-stage sampling capacitors. The threshold detection circuit compares the threshold voltage Vthres with the voltage on the first-stage sampling capacitors and inputs the comparison result to the phase detector. The outputs UP and DW of the phase detector are the inputs to the second-stage sampling capacitors to control their charging and discharging. The current Iref of the constant current pull-down charge pump is amplified M times by a current mirror to charge and discharge the second-stage sampling capacitors DAC2_P and DAC2_N. After charging and discharging, the differential voltage Vout on the second-stage sampling capacitors is the amplified final output.

[0036] In this embodiment, to further illustrate the working principle of the residual amplifier of the present invention, the present invention provides the following... Figure 2 The diagram shows the working waveform. Assume the first-stage sampling capacitor has a single-ended capacitance of CS1 and a positive voltage, i.e., VDAC_P > VDAC_N. The constant current pull-down charge pump current is ICP1, and the differential charge pump's pull-up and pull-down currents are both ICP2. When EN is high, the constant current pull-down charge pump starts discharging both DAC_P and DAC_N simultaneously with current ICP1. The voltage values ​​at the two ports are shown in equations (1) and (2), respectively.

[0037]

[0038] In the formula, VDAC_P(t) and VDAC_N(t) are the upper plate voltages of DAC_P and DAC_N at time t, respectively. Since VDAC_P>VDAC_N at the initial time, assuming that VDAC_N(t1) = VREF at time t1, the threshold detection circuit is triggered, the phase detector output signal UP is raised to a high level, and UPN is pulled low. The differential charge pump switch makes a corresponding switch, that is, charging DAC2_P and discharging DAC2_N. Since the second-stage sampling capacitor is CS2 and has the same initial voltage, the voltage values ​​of the two ports of the second-stage sampling capacitor after time t1 can be expressed as Equation (3) and Equation (4), respectively:

[0039]

[0040] The first - stage sampling capacitor continues to discharge with ICP1 until VDAC_P(t2) = VREF at time t2. Another threshold - detection circuit is triggered, the output signal DW of the phase - detector is raised to a high level, and DWN is pulled down. At this time, both the UP and DW signals are at a high level, the output of the AND logic gate becomes high, resetting the output of the phase - detector to a low level. The differential charge - pump switches are all turned off, and the second - stage sampling capacitor enters the holding state, ending the residual - voltage amplification process. At this time, the voltages at both ports of the second - stage sampling capacitor are respectively as shown in Equations (5) and (6):

[0041]

[0042] In addition, the voltage difference between the two ports of the first - stage sampling capacitor can be expressed as Equation (7):

[0043]

[0044] After the amplification process ends, the voltage difference between the two ports of the second - stage sampling capacitor is Equation (8):

[0045]

[0046] The gain GAIN of the inter - stage amplifier circuit can be expressed as Equation (9):

[0047]

[0048] For the initial case of VDAC_P < VDAC_N, the gain is also as shown in Equation (9). Only by maintaining the linearity of the charge - pump current ratio and the capacitance ratio can a high gain linearity be maintained under PVT variations.

[0049] Refer to Figure 3 , Figure 3 which is the structural diagram of a voltage - amplification circuit provided by an embodiment of the present invention. The voltage - amplification circuit includes:

[0050] A constant - current source; a first - group current - mirror structure composed of 12 NMOS transistors MM1_1 to MM1_12; a second - group current - mirror structure composed of 6 PMOS transistors MM2_1 to MM2_6; 2 NMOS transistors MD1_1, MD1_2; a first - stage sampling capacitor DAC_P and DAC_N; 8 NMOS transistors MD2_1 to MD2_8; a second - stage sampling capacitor DAC2_P, DAC2_N; 2 NMOS transistors ME1, ME2;

[0051] The upper plates of the first-stage sampling capacitors DAC_P and DAC_N sample the residual voltage Vres, while the lower plates are grounded. DAC_P and DAC_N discharge through MD1_1 and MD1_2 with a current of N times IREF. The gates of MD1_1 and MD1_2 are connected to the EN enable signal.

[0052] In the voltage amplification circuit, the upper plate voltages of the second-stage sampling capacitors DAC2_P and DAC2_N are connected to the sources of MD2_1 and MD2_5, respectively, and the lower plates are grounded. DAC2_P and DAC2_N are charged and discharged with M times IREF current through differential pairs MD2_1 to MD2_4 and differential pairs MD2_5 to MD2_8, respectively. The gate inputs of UP, UPN, DW, and DWN signals of MD2_1 to MD2_8 control the opening and closing of the differential pairs, thereby controlling the charging and discharging of the second-stage sampling capacitor. Finally, the upper plate voltage of the second-stage sampling capacitor is the amplified output voltage Vout.

[0053] In this embodiment, when the EN enable signal is high, the circuit operates, and the first-stage sampling capacitors DAC_P and DAC_N discharge; when UP is high, DAC2_P charges and DAC2_N discharges; when DW is high, DAC2_N charges and DAC2_P discharges; when both UP and DW signals are high, the circuit is reset; the amplification factor GAIN = (2 × M × CDAC) / (N × CDAC2).

[0054] See Figure 4 , Figure 4 This is a schematic diagram of a threshold detection circuit and a phase detector provided in an embodiment of the present invention. The threshold detection circuit uses a continuous-time comparator, with the upper plate voltage of the first-stage sampling capacitors DAC_P and DAC_N as its input signal. Its output signal is then connected to the phase detector after passing through two input AND gates with the EN enable signal at the other end. The phase detector includes two rising-edge triggered D flip-flops with reset terminals and a logic AND gate.

[0055] The D terminal of the D flip-flop in the phase detector is always connected to a high level. The output signal of the threshold detection circuit is connected to the input CLK terminal of the D flip-flop after passing through two input AND gates connected to the EN enable signal at the other end, and generates high-level UP and DW rectangular pulse signals at the output Q terminal. UP and DW are provided to the reset signal Reset of the D flip-flop through the AND gate. UP and DW are inverted by inverters to obtain UPN and DWN respectively. The UP, DW, UPN and DWN signals are input to the gates of MD2_1 to MD2_8 to control their on / off state, thereby controlling the charging and discharging of DAC2_P and DAC2_N.

[0056] Furthermore, when the EN enable signal is high, the output of the two-input AND gate is VOUT, at which time the threshold detection circuit is in working state; when the EN enable signal is low, the output is 0, at which time the threshold detection circuit is in standby state.

[0057] The D flip-flop outputs 1 at Q terminal when VOUT at the input CLK terminal is high and 0 at Q terminal when VOUT at the input CLK terminal is low. When the Q outputs of both D flip-flops are 0, the flip-flop remains active. When the Q outputs of both D flip-flops are 1, the signal at the Reset terminal of the input D flip-flop is 1, thus resetting the flip-flop.

[0058] In this embodiment, if VDAC_P > VDAC_N, then UP is high, DW is low, DAC2_P is charging, and DAC2_N is discharging; if VDAC_P < VDAC_N, then UP is low, DW is high, DAC2_N is charging, and DAC2_P is discharging.

[0059] like Figure 5 As shown, the continuous-time comparator uses a four-stage cascaded self-biased open-loop operational amplifier, combined with a five-transistor operational amplifier to perform differential-to-single-ended operation, resulting in a single-ended output.

[0060] The self-biased open-loop operational amplifier consists of seven transistors, M1 to M7. M1 to M3 are NMOS transistors, and M4 to M6 are PMOS transistors. The gates Vin and Vip of M2 and M3 are respectively connected to the reference threshold voltage Vthres and the upper plate voltage VDAC of the sampling capacitor DAC and compared. The drain voltages Von and Vop of M2 and M3 are output differentially based on the comparison result.

[0061] The five-transistor op-amp is a classic five-transistor OTA. Von and Vop are the differential inputs of this five-transistor op-amp, and its single-ended output is obtained by passing through two inverters to obtain the output VOUT.

[0062] In this embodiment, if the voltage VDAC on the upper plate of the sampling capacitor DAC is greater than the reference threshold voltage Vthres, the output VOUT is low; if the voltage VDAC on the upper plate of the sampling capacitor DAC is less than the reference threshold voltage Vthres, the output VOUT is high.

[0063] In this embodiment, the amplification function of the residual voltage is achieved by charging and discharging the first-stage sampling capacitor and the second-stage sampling capacitor as described above.

[0064] The present invention provides a time-domain residual amplifier for pipelined analog-to-digital converters, which realizes voltage gain in the form of the product of capacitance ratio and current mirror current ratio, and optimizes linearity and PVT robustness while retaining low power consumption characteristics.

[0065] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0066] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A time-domain residual amplifier for pipelined analog-to-digital converters, characterized in that, include: The circuit includes a threshold detection circuit, a voltage amplification circuit, and a phase detector; among which, The voltage amplifier circuit is connected to the threshold detection circuit and the phase detector respectively; the threshold detection circuit is connected to the phase detector; the voltage amplifier circuit includes first-stage sampling capacitors DAC_P and DAC_N, second-stage sampling capacitors DAC2_P and DAC2_N, and a constant current pull-down charge pump. The voltage amplifier circuit includes: A constant current source; a first current mirror structure consisting of 12 NMOS transistors MM1_1~MM1_12; a second current mirror structure consisting of 6 PMOS transistors MM2_1~MM2_6; 2 NMOS transistors MD1_1 and MD1_2; first-stage sampling capacitors DAC_P and DAC_N; 8 NMOS transistors MD2_1~MD2_8; second-stage sampling capacitors DAC2_P and DAC2_N; 2 NMOS transistors ME1 and ME2; The upper plates of the first-stage sampling capacitors DAC_P and DAC_N are connected to the sources of MD1_1 and MD1_2 respectively and input with the residual voltage Vres. The lower plates are grounded. The gates of MD1_1 and MD1_2 are connected to the EN enable signal. The upper plates of the second-stage sampling capacitors DAC2_P and DAC2_N are connected to the sources of MD2_1 and MD2_5 respectively and output the result Vout. The lower plates are all grounded. The gates of MD2_1 to MD2_8 are input with UP, UPN, DW, and DWN signals. The threshold detection circuit uses a continuous-time comparator; The continuous-time comparator uses a four-stage cascaded self-biased open-loop operational amplifier, combined with a five-transistor operational amplifier to perform differential-to-single-ended operation, resulting in a single-ended output. The phase detector consists of two D flip-flops and one AND gate; The self-biased open-loop op-amp consists of seven transistors M1 to M7. M1 to M3 are NMOS transistors, and M4 to M6 are PMOS transistors. The gates Vin and Vip of M2 and M3 are connected to the reference threshold voltage Vthres and the upper plate voltage of the first-stage sampling capacitor, respectively. The drain voltages Von and Vop of M2 and M3 output Vout. Von and Vop are connected to the differential input of the five-transistor op-amp. The single-ended output VOUT is obtained after passing through two inverters. All D flip-flops are rising-edge triggered and have a reset terminal (Reset). The D terminal of the D flip-flop in the phase detector is always connected to a high level. The output signal of the threshold detection circuit is connected to the first two-input AND gate. The output of the first two-input AND gate is connected to the CLK input of the D flip-flop. The Q output of the D flip-flop generates UP and DW rectangular pulse signals. UP and DW are input to the second two-input AND gate. The output of the second two-input AND gate is connected to the Reset terminal of the D flip-flop. UP and DW are each connected to an inverter. The inverter outputs UPN and DWN.

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