Method for optimizing signal integrity of high-speed PCB

Abstract

According to the method for optimizing the signal integrity of the high-speed PCB, the pattern layout around the target pattern area used for signal transmission on the PCB is improved, so that the glue filling uniformity in the manufacturing process of the target pattern area in the pressing process is improved, the thickness of the dielectric layer on the signal layer of the high-speed PCB is more uniform, and the signal integrity of the high-speed PCB is improved. And the signal integrity of the high-speed PCB is improved. Specifically, a surrounding pattern which keeps a certain distance from a target pattern and is high in residual copper rate is arranged around the target pattern, so that the thickness uniformity of a dielectric layer on a signal layer is improved, the signal integrity of the high-speed PCB is improved, and noise interference is reduced; secondly, the surrounding pattern is filled between the target pattern and the surrounding pattern, so that the residual copper rate of the target pattern and the surrounding area of the target pattern is further improved, the electromagnetic effect in a signal propagation path is improved, the loss is reduced, the overall impedance of the signal layer is balanced, and the thickness uniformity of the dielectric layer on the signal layer is improved; and the signal integrity of the high-speed PCB is improved.

Description

Technical Field

[0001] The present invention relates to the field of printed circuit board manufacturing, and more particularly to a method for optimizing high-speed PCB signal integrity. Background Art

[0002] In printed circuit board (PCB) design, PCB signal integrity (SI) refers to the ability to ensure that electrical signals maintain high quality, are not distorted, and are not affected by noise during transmission. Signal integrity mainly focuses on problems such as distortion, reflection, crosstalk, and attenuation of signals during high-speed transmission, ensuring that the signal can accurately reflect the original signal of the sender when it reaches the destination. Specifically, in the actual production process of PCB, the factors affecting PCB signal integrity mainly involve the following key aspects: 1. Signal reflection: When the signal encounters impedance mismatches such as wire ends or connectors, part of the signal will be reflected back to the source, causing signal distortion; 2. Crosstalk: Adjacent signal lines on the circuit board may interfere with each other, affecting signal quality; 3. Timing issues: The delay in signal propagation and the difference in propagation time of different signal lines may cause the signal to be out of sync and produce bit errors; 4. Signal attenuation: Due to factors such as cables, materials, or long-distance transmission, the signal strength may be weakened, resulting in the inability of the receiving end to accurately read the signal; 5. Power supply noise and ground noise: Fluctuations in the power supply system or unstable ground lines may also affect the quality of the signal. In order to ensure the signal integrity on the PCB, it is usually necessary to solve or alleviate these problems through proper design and layout, such as reasonably selecting the impedance of the signal line, shortening the signal transmission path, increasing the ground plane design, optimizing power management, etc.

[0003] At present, the port rate of mainstream data center switches in China is being upgraded from 10 / 40G to 400 / 800G, which has improved the market application of high-speed PCBs. When designing and manufacturing high-speed PCBs, higher requirements are placed on signal integrity, impedance matching, signal coupling, and signal noise on PCBs. In order to meet these requirements, special materials and special processes are required when making high-speed PCBs. However, due to the existence of the glass fiber effect, the different dielectric constants of the glass fiber and epoxy resin used will inevitably cause differences in signal propagation delays, namely skew, which in turn affects the timing of the signal, especially in high-speed and high-frequency signal transmission, which will lead to timing errors and signal distortion. In order to improve the skew caused by the glass fiber effect, in the design of multi-layer PCBs, it is usually considered to reasonably arrange the inter-layer settings of the PCB and the specific settings of the signal lines, such as taking shorter signal lines, reducing crossings and sharp bends, and avoiding signal lines from passing through uneven dielectric layer areas, reducing reflections and losses caused by interfaces between different materials, such as the interface between resin and glass fiber; in the application of high-speed PCBs, high-quality PCB materials are selected, PCB layout and wiring are optimized, and the process in the PCB manufacturing process is controlled to ensure the uniformity of the thickness of the dielectric layer during the manufacturing process, thereby significantly reducing the delay difference in signal transmission and improving signal integrity.

[0004] In the actual production process, in the signal layer graphic design of high-speed PCB, due to the isolation and impedance design requirements of high-speed signal lines, the signal layer of high-speed PCB often adopts a graphic design with a small residual copper rate around the signal line to improve signal integrity, reduce electromagnetic interference, and improve the transmission and stability of high-speed signals. However, the residual copper rate around the high-speed signal line is small, and there are often blank board areas, which makes the high-speed PCB create a continuous pressing low-voltage area around the signal line during pressing, resulting in a thinner dielectric layer set on the signal layer after pressing and obvious uneven thickness, affecting the reliability of the high-speed PCB. At the same time, the high-speed signal may cause the signal propagation speed to slow down in the area with thicker dielectric layer, while the thin area propagates faster, resulting in the delay difference of high-speed signal transmission; and in the multi-layer design of PCB, the uneven thickness of the dielectric layer will also cause the electromagnetic coupling between different signal layers to change, increase the interference and delay difference of the signal, thereby aggravating the glass fiber effect affecting the signal integrity in high-speed signal transmission. Summary of the invention

[0005] The present invention aims to overcome at least one defect of the above-mentioned prior art and provides a method for optimizing the signal integrity of a high-speed PCB. By optimizing the graphic design and manufacturing process on the high-speed PCB, the thickness uniformity of the dielectric layer on the signal layer on the high-speed PCB is improved, thereby optimizing the signal transmission performance on the high-speed PCB and improving the signal integrity.

[0006] The technical solution adopted by the present invention first provides a method for optimizing high-speed PCB signal integrity, comprising the following steps: S1. Cut the material and perform chemical cleaning; S2. Dry film covering and pattern etching; S3. Browning; S4. Arrange the plates and press them together; In step S2, the etched image includes the optimized target pattern and surrounding patterns outside the target pattern, and the optimization method is based on the following principles: When the residual copper rate of the surrounding pattern is between 50% and 70%, a surrounding pattern is added between the target pattern and the surrounding pattern, wherein the surrounding pattern is composed of a plurality of spaced grooves and blocks continuously distributed, and the grooves connect the target pattern and the surrounding pattern; When the residual copper rate of the surrounding pattern is between 70% and 75%, a surrounding pattern is added between the target pattern and the surrounding pattern, wherein the surrounding pattern is composed of spaced single grooves and blocks continuously distributed, and the grooves connect the target pattern and the surrounding pattern; When the residual copper rate of the surrounding pattern exceeds 75%, a surrounding pattern is added between the target pattern and the surrounding pattern, wherein the surrounding pattern is formed by continuously distributed stoppers, and the surrounding pattern separates the target pattern and the surrounding pattern.

[0007] In the technical scheme, by improving the graphic layout around the target graphic area used for signal transmission on the PCB, the uniformity of the glue filling in the target graphic area during the lamination process is improved, so that the thickness of the dielectric layer on the high-speed PCB signal layer is more uniform, and the signal integrity of the high-speed PCB is improved. Specifically, by setting a surrounding graphic with a certain distance and a high residual copper rate around the target graphic, the signal integrity of the high-speed PCB is improved, the noise interference is reduced, and the performance of the overall circuit is improved while the thickness uniformity of the dielectric layer on the signal layer is improved. Among them, there is a certain distance between the target graphic and the surrounding graphic for high-speed signal transmission, so that the high-speed signal can be effectively isolated to avoid signal crosstalk. At the same time, by selecting a graphic design with a high residual copper rate for the surrounding graphic, the uniformity of the thickness of the dielectric layer on the signal layer during lamination is improved; preferably, by laying a continuous copper surface in the blank area around the target graphic as a surrounding graphic to increase the residual copper rate of the entire board surface of the signal layer, a low-impedance return path is provided for the high-speed signal, the electromagnetic radiation of the signal line is reduced, the signal crosstalk is reduced, the signal integrity is enhanced, and the impedance is effectively controlled.

[0008] Furthermore, by filling the target pattern and the surrounding pattern in the middle, the residual copper rate of the target pattern and the surrounding area is further improved, the electromagnetic effect in the signal propagation path is improved, the loss is reduced, the impedance of the signal layer as a whole is balanced, the thickness uniformity of the dielectric layer on the signal layer is improved, and the signal integrity of the high-speed PCB is improved. Specifically, by adding the surrounding pattern between the target pattern and the surrounding pattern, the area of ​​the glue filling area around the target pattern is reduced, and the resin accumulation caused by the continuous low-pressure area formed near the target pattern during lamination is avoided, thereby improving the thickness uniformity of the dielectric layer formed after the PCB is pressed, avoiding the signal line from contacting the uneven dielectric layer, and improving the signal integrity of the high-speed PCB. Due to different design requirements of high-speed PCBs, the copper plating area of ​​surrounding graphics is different for impedance design and other requirements. Based on the differences in the graphics formed by the surrounding graphics on different high-speed PCBs, the surrounding graphics filled between the signal line target graphics and the surrounding graphics are also different. By forming different surrounding graphics based on the residual copper rate of the surrounding graphics, the overall impedance of the matching signal layer can be accurately designed, and the uniformity of the glue flow in the signal line target graphic area can be improved, thereby improving the overall uniformity of the dielectric layer thickness on the signal layer and reducing the difference in signal propagation delay caused by the glass fiber effect. At the same time, by setting the surrounding graphics corresponding to the surrounding graphics and the target graphics, the board impedance can be balanced, thereby improving the integrity and efficiency of signal propagation on the high-speed signal line. Specifically, when the residual copper rate of the surrounding graphics is between 50% and 70%, the surrounding graphics added between the target graphics and the surrounding graphics are composed of a plurality of grooves and blocks continuously distributed at intervals, and the grooves connect the target graphics and the surrounding graphics; when the residual copper rate of the surrounding graphics is between 70% and 75%, a surrounding graphics is added between the target graphics and the surrounding graphics, and the surrounding graphics are composed of a single groove and blocks continuously distributed at intervals, and the grooves connect the target graphics and the surrounding graphics; in this case, by setting continuous blocks and multiple grooves, it is beneficial for the resin in the semi-cured layer to fully flow between the target graphics and the surrounding graphics during lamination, thereby further improving the uneven thickness of the dielectric layer formed on the signal layer after lamination. When the residual copper rate of the surrounding pattern exceeds 75%, a surrounding pattern is added between the target pattern and the surrounding pattern. The surrounding pattern is composed of continuously distributed blocks, and the surrounding pattern separates the target pattern and the surrounding pattern. In this case, the overall residual copper rate of the signal layer is high, which greatly improves the thickness uniformity of the dielectric layer on the signal layer. However, the resin filled around the target line area during the lamination process has poor fluidity, so it is not suitable for the situation where the resin fluidity in the semi-cured sheet set on the signal layer is poor.

[0009] Furthermore, the step S2 also includes the following principles: When the residual copper rate of the surrounding pattern is lower than 50%, a surrounding pattern is added between the target pattern and the surrounding pattern, wherein the surrounding pattern is formed by continuously distributed stoppers, and the surrounding pattern separates the target pattern and the surrounding pattern.

[0010] In the present technical scheme, when the design residual copper rate of the surrounding graphics of the high-speed PCB is lower than 50% due to the requirements of impedance design, in order to make it convenient to balance the symmetry and uniformity of the graphics setting on the overall signal layer after adding the surrounding graphics that separate the target graphics and the surrounding graphics, and at the same time effectively adjust the matching of the filling uniformity of the target line area with the filling uniformity of the overall board surface of the signal layer, the surrounding graphics are arranged to be composed of continuously distributed blocks, thereby improving the local residual copper rate of the periphery of the target graphics, avoiding the lamination low-pressure area caused by retaining a continuous blank board surface between the target graphics and the surrounding graphics, thereby improving the overall filling uniformity on the signal layer board surface graphics, improving the uniformity of the dielectric layer thickness on the signal layer after lamination, and ensuring the signal integrity of the high-speed PCB.

[0011] Furthermore, in step S2, the target pattern is distributed in a long strip shape as a whole, the surrounding pattern is in a rectangular shape as a whole, and a guide pattern is provided on the outside of at least one short side of the rectangle. In order to reduce the loss and crosstalk of the signal line, and reduce the reflection and signal loss on the transmission path, the target pattern used for high-speed signal transmission is set to be a long strip, and the surrounding pattern is arranged in a rectangular shape around the area where the target pattern is located. Preferably, the two long sides of the rectangle forming the surrounding pattern are arranged between the target pattern and the surrounding pattern to achieve effective isolation between the two. A guide pattern is also provided on the outside of at least one short side, and the resin during lamination is discharged from the board edge of the high-speed PCB through the guide pattern, thereby avoiding the accumulation of resin in the target pattern area during lamination, and improving the thickness uniformity of the overall dielectric layer on the target pattern area and the signal layer, thereby reducing the glass fiber effect and improving the signal integrity on the high-speed PCB.

[0012] Preferably, the configuration shape and density of the guide pattern match the amount of resin to be retained on the surface of the signal layer and the resin flow rate. Specifically, when the residual copper rate of the surrounding pattern is between 50% and 70%, the guide pattern is a circular array distribution structure, and the guide groove of the guide pattern is formed in the gap between the circles. In this case, the backflow gap formed between the guide patterns is larger, thereby improving the resin fluidity around the target line area, promoting the resin to fully fill the gap and the excess resin can be discharged in time around the target line area, providing a thinner dielectric layer thickness on the signal layer while ensuring the uniform thickness of the dielectric layer. When the residual copper rate of the surrounding pattern is between 70% and 75%, the guide pattern is a square array distribution structure, and the guide groove of the guide pattern is formed in the gap between the squares. In this case, the backflow gap formed between the guide patterns is smaller, thereby appropriately reducing the resin fluidity around the target line area and reducing the amount of resin discharged around the target line area, promoting the resin to flow and mix evenly on the signal layer after fully filling the gap to form a dielectric layer, thereby increasing the thickness of the dielectric layer while ensuring the uniform thickness of the dielectric layer.

[0013] Furthermore, in step S2, the target pattern is distributed in a long strip shape as a whole, and the surrounding pattern is a rectangle as a whole. When the residual copper rate of the surrounding pattern exceeds 75% or is less than 50%, the line width of the short side of one side of the rectangle is greater than that of the other side, so that the setting of the surrounding pattern balances the impedance between the surrounding patterns adjacent to the two sides of the short side of the rectangle and the guide pattern adjacent to the board edge and the influence on the thickness of the dielectric layer. Preferably, the line width of the short side of one side of the rectangle is 3-5 times that of the other side.

[0014] Furthermore, the target pattern is set to rotate 1-5° relative to the surrounding patterns. By rotating the target pattern to adjust the propagation direction of the high-speed signal, the impedance mismatch caused by the signal line passing through the glass fiber layers in different directions is reduced, signal reflection and crosstalk are reduced, and thus the signal delay difference (skew) and uneven propagation are reduced, thereby improving the signal quality.

[0015] Furthermore, the chemical cleaning in step S1 omits the micro-etching process compared to the traditional chemical cleaning process, including ultrasonic immersion, degreasing, pickling and drying; by adopting a non-micro-etching mode to clean the high-speed PCB surface, the traditional roughening treatment is avoided, the mechanical damage to the PCB surface is effectively reduced, the roughness of the copper surface itself is retained, and the loss of high-speed PCB signal integrity is reduced.

[0016] Furthermore, in step S3, the browning process adopts low roughness browning, and the micro-etching rate is controlled between 7.5±2.5μinch. Specifically, by using ultra-low roughness browning solution for etching in the browning process, the concentration of the browning solution and the micro-etching rate are precisely controlled to control the corrosion of the copper surface, so as to controllably reduce the roughness, thereby reducing the loss caused by the skin effect and improving the signal integrity, thereby realizing the optimization of the signal integrity loss of the manufactured high-speed PCB during the browning process. Preferably, in one embodiment of the present application, the browning solution is H with a concentration of 28±8ml / L. 2 O 2 .

[0017] Furthermore, in step S2, the laminating pressure of the dry film is between 4.5 kg and 5.5 kg. By adopting appropriate laminating pressure, the dry film is closely fitted to the substrate of the high-speed PCB, thereby avoiding the generation and distribution of bubbles and uneven media, thereby improving the accuracy of the circuit on the high-speed PCB, reducing impedance mismatch, improving heat conduction and electromagnetic interference problems, and effectively ensuring the transmission quality and reliability of the signal.

[0018] Compared with the prior art, the present invention has the following beneficial effects: 1. By setting a surrounding pattern with a certain distance and a high residual copper rate around the target pattern for high-speed signal transmission, the signal integrity of the high-speed PCB is improved, noise interference is reduced, and the performance of the overall circuit is improved while improving the thickness uniformity of the dielectric layer on the signal layer. Among them, a certain distance is designed between the target pattern and the surrounding pattern so that the high-speed signals can be effectively isolated to avoid signal crosstalk. At the same time, by selecting a pattern design with a high residual copper rate for the surrounding pattern, the thickness uniformity of the dielectric layer on the signal layer during lamination is improved; preferably, by laying a continuous copper surface in the blank area around the target pattern as the surrounding pattern to increase the residual copper rate of the entire signal layer board surface, a low-impedance return path is provided for the high-speed signal, the electromagnetic radiation of the signal line is reduced, the signal crosstalk is reduced, the signal integrity is enhanced, and the impedance is effectively controlled.

[0019] 2. By filling the target pattern and the surrounding pattern in the middle, the residual copper rate of the target pattern and the surrounding area is further improved, the electromagnetic effect in the signal propagation path is improved, the loss is reduced, the impedance of the signal layer as a whole is balanced, the thickness uniformity of the dielectric layer on the signal layer is improved, and the signal integrity of the high-speed PCB is improved. Specifically, by adding the surrounding pattern between the target pattern and the surrounding pattern, the area of ​​the glue filling area around the target pattern is reduced, and the resin accumulation caused by the continuous low-pressure area formed near the target pattern during lamination is avoided, thereby improving the thickness uniformity of the dielectric layer formed after the PCB is pressed, avoiding the signal line from contacting the uneven dielectric layer, and improving the signal integrity of the high-speed PCB.

[0020] 3. By rotating the target pattern to adjust the propagation direction of the high-speed signal, the impedance mismatch caused by the signal line passing through the glass fiber layer in different directions is reduced, signal reflection and crosstalk are reduced, thereby reducing the signal delay difference (skew) and uneven propagation, and improving signal quality.

[0021] 4. By adopting the non-micro-etching mode to clean the high-speed PCB surface, the traditional roughening treatment is avoided, the mechanical damage to the PCB surface is effectively reduced, the roughness of the copper surface itself is retained, and the loss of high-speed PCB signal integrity is reduced.

[0022] 5. By using ultra-low roughness browning solution for etching in the browning process, and by accurately controlling the micro-etching rate of the browning solution at 7.5±2.5μinch, the erosion of the copper surface can be controllably reduced, thereby achieving the effect of controllably reducing the roughness, thereby reducing the loss caused by the skin effect and improving the signal integrity, thereby achieving the loss optimization of the signal integrity of the high-speed PCB produced by the browning process. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic flow chart of the method for optimizing high-speed PCB signal integrity provided by the present invention.

[0024] Figure 2 This is a schematic diagram of the graphic optimization of the high-speed PCB in Example 1.

[0025] Figure 3 This is a schematic diagram of the graphic optimization of the high-speed PCB in Example 2.

[0026] Figure 4 Schematic diagram of graphic optimization of high-speed PCB in Examples 3 and 4.

[0027] Figure 5 This is a SEM image of the copper surface after the browning process in the traditional high-speed PCB manufacturing process.

[0028] Figure 6 This is a SEM image of the copper surface after the browning process in the method for optimizing high-speed PCB signal integrity provided by the present invention.

[0029] Figure 7 This is a schematic diagram of the target graphic design of the high-speed PCB in Comparative Example 1.

[0030] Figure 8 This is the impedance test waveform of the high-speed PCB in comparative example 1.

[0031] Fig. 9 This is the impedance test waveform of the high-speed PCB in Example 1. DETAILED DESCRIPTION

[0032] The drawings of the present invention are only for illustrative purposes and should not be construed as limiting the present invention. In order to better illustrate the following embodiments, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; it is understandable to those skilled in the art that some well-known structures and their descriptions in the drawings may be omitted.

[0033] Example 1 like Figure 1 As shown, this embodiment provides a method for optimizing high-speed PCB signal integrity, comprising the following steps: S1. Cutting and chemical cleaning: Cut the PCB substrate according to the design requirements to ensure that the material size meets the requirements. Then, the chemical cleaning process is carried out. Compared with the traditional chemical cleaning process, the micro-etching process is omitted, including ultrasonic immersion, degreasing, pickling and drying; by adopting the non-micro-etching mode to clean the surface of each layer of the PCB substrate that makes up the high-speed PCB, the traditional roughening treatment is avoided, the mechanical damage to the surface of the PCB substrate is effectively reduced, the roughness of the copper surface itself is retained, and the loss of high-speed PCB signal integrity is reduced.

[0034] S2. Dry film covering and pattern etching: The surface of the PCB substrate after chemical cleaning is covered with a dry film, and then the pattern is transferred and etched. On the PCB substrate where the signal layer is located, during the etching process, the etched image includes not only the target pattern, but also the surrounding patterns outside the target pattern and the surrounding patterns added between the target pattern and the surrounding patterns.

[0035] like Figure 2As shown, preferably, it also includes a graphic optimization process: for the needs of impedance design, the surrounding graphics are continuously copper-plated, thereby increasing the residual copper rate of the entire board surface of the signal layer, providing a low-impedance return path for high-speed signals, reducing the electromagnetic radiation of the signal line, reducing signal crosstalk, enhancing signal integrity, and effectively controlling impedance. When the residual copper rate of the surrounding graphics is between 50% and 70%, the surrounding graphics added between the target graphics and the surrounding graphics are composed of a plurality of grooves and blocks continuously distributed at intervals, and the grooves connect the target graphics and the surrounding graphics; by setting continuous blocks and multiple grooves, it is beneficial for the resin in the semi-cured layer to fully flow between the target graphics and the surrounding graphics during lamination, thereby further improving the uneven thickness of the dielectric layer formed on the signal layer after lamination.

[0036] Preferably, the target pattern is distributed in an overall long strip shape, and the surrounding pattern is in an overall rectangular shape. A guide pattern is further provided on the outside of at least one short side of the rectangle; and the guide pattern is a circular array distribution structure, and the guide grooves of the guide pattern are formed in the gaps between the circles. In this case, the backflow gaps formed between the guide patterns are larger, thereby improving the resin fluidity around the target circuit area, promoting full filling of the resin gaps, and allowing excess resin to be discharged in time around the target circuit area, providing a thinner dielectric layer thickness on the signal layer while ensuring uniform dielectric layer thickness.

[0037] Preferably, the target pattern is set to rotate 1-5° relative to the surrounding patterns. The target pattern is rotated to adjust the propagation direction of the high-speed signal, thereby reducing the impedance mismatch caused by the signal line passing through the glass fiber layers in different directions, reducing signal reflection and crosstalk, thereby reducing signal delay differences (skew) and uneven propagation, and improving signal quality.

[0038] Preferably, the film lamination pressure of the dry film is maintained between 4.5-5.5 kg to ensure a close fit between the dry film and the PCB substrate, avoiding the generation and distribution of bubbles and uneven media, thereby improving the accuracy of the circuit on the PCB substrate, reducing impedance mismatch, and improving heat conduction and electromagnetic interference problems, thereby effectively ensuring the transmission quality and reliability of signals on high-speed PCBs.

[0039] S3. Browning: After the circuit patterns on the various layers of the PCB substrates constituting the high-speed PCB are etched, the PCB substrates are subjected to a browning treatment, wherein the browning adopts a low-roughness browning process, such as Figure 5-Figure 6As shown, by using ultra-low roughness browning solution for etching in the browning process, and controlling the micro-etching rate of the browning solution between 7.5±2.5μinch, the erosion of the copper surface can be controllably reduced, so as to controllably reduce the roughness, thereby reducing the loss caused by the skin effect and improving the signal integrity. Preferably, the browning solution is H with a concentration of 28±8 ml / L. 2 O 2 .

[0040] S4. Arrange and press the boards: Finally, all processed PCB substrates are arranged in the design order and pressed together to form the final high-speed PCB. The pressing process requires strict control of temperature and pressure to ensure good bonding of each layer in the high-speed PCB and to ensure the stability and reliability of the circuit on the high-speed PCB.

[0041] Example 2 like Figure 1 As shown, this embodiment provides a method for optimizing high-speed PCB signal integrity, comprising the following steps: S1. Cutting and chemical cleaning: Cut the PCB substrate according to the design requirements to ensure that the material size meets the requirements. Then, the chemical cleaning process is carried out. Compared with the traditional chemical cleaning process, the micro-etching process is omitted, including ultrasonic immersion, degreasing, pickling and drying; by adopting the non-micro-etching mode to clean the surface of each layer of the PCB substrate that makes up the high-speed PCB, the traditional roughening treatment is avoided, the mechanical damage to the surface of the PCB substrate is effectively reduced, the roughness of the copper surface itself is retained, and the loss of high-speed PCB signal integrity is reduced.

[0042] S2. Dry film covering and pattern etching: The surface of the PCB substrate after chemical cleaning is covered with a dry film, and then the pattern is transferred and etched. On the PCB substrate where the signal layer is located, during the etching process, the etched image includes not only the target pattern, but also the surrounding patterns outside the target pattern and the surrounding patterns added between the target pattern and the surrounding patterns.

[0043] like Figure 3As shown, preferably, it also includes a graphic optimization process: for the needs of impedance design, the surrounding graphics are continuously copper-plated, thereby increasing the residual copper rate of the entire signal layer board surface, providing a low-impedance return path for high-speed signals, reducing the electromagnetic radiation of the signal line, reducing signal crosstalk, enhancing signal integrity, and effectively controlling impedance. When the residual copper rate of the surrounding graphics is between 70% and 75%, a surrounding graphic is added between the target graphic and the surrounding graphics, and the surrounding graphic is composed of a continuous distribution of spaced single grooves and blocks, and the grooves connect the target graphic and the surrounding graphics; by setting continuous blocks and grooves, it is beneficial for the resin in the semi-cured layer to fully flow between the target graphic and the surrounding graphics during lamination, thereby further improving the uneven thickness of the dielectric layer formed on the signal layer after lamination.

[0044] Preferably, the target pattern is distributed in an overall long strip shape, and the surrounding pattern is in an overall rectangular shape. A guide pattern is further provided on the outside of at least one short side of the rectangle; the guide pattern is a square array distribution structure, and the guide grooves of the guide pattern are formed in the gaps between the squares. In this case, the backflow gaps formed between the guide patterns are smaller, thereby appropriately reducing the resin fluidity around the target circuit area and reducing the amount of resin discharged around the target circuit area, promoting the resin to flow and mix evenly on the signal layer after fully filling the gap to form a dielectric layer, thereby increasing the thickness of the dielectric layer while ensuring the uniformity of the dielectric layer thickness.

[0045] Preferably, the target pattern is set to rotate 1-5° relative to the surrounding patterns. The target pattern is rotated to adjust the propagation direction of the high-speed signal, thereby reducing the impedance mismatch caused by the signal line passing through the glass fiber layers in different directions, reducing signal reflection and crosstalk, thereby reducing signal delay differences (skew) and uneven propagation, and improving signal quality.

[0046] Preferably, the film lamination pressure of the dry film is maintained between 4.5-5.5 kg to ensure a close fit between the dry film and the PCB substrate, avoiding the generation and distribution of bubbles and uneven media, thereby improving the accuracy of the circuit on the PCB substrate, reducing impedance mismatch, and improving heat conduction and electromagnetic interference problems, thereby effectively ensuring the transmission quality and reliability of signals on high-speed PCBs.

[0047] S3. Browning: After the circuit patterns on the various layers of the PCB substrates constituting the high-speed PCB are etched, the PCB substrates are subjected to a browning treatment, wherein the browning adopts a low-roughness browning process, such as Figure 5-Figure 6As shown, by using ultra-low roughness browning solution for etching in the browning process, and controlling the micro-etching rate of the browning solution between 7.5±2.5μinch, the erosion of the copper surface can be controllably reduced, so as to controllably reduce the roughness, thereby reducing the loss caused by the skin effect and improving the signal integrity. Preferably, the browning solution is H with a concentration of 28±8 ml / L. 2 O 2 .

[0048] S4. Arrange and press the boards: Finally, all processed PCB substrates are arranged in the design order and pressed together to form the final high-speed PCB. The pressing process requires strict control of temperature and pressure to ensure good bonding of each layer in the high-speed PCB and to ensure the stability and reliability of the circuit on the high-speed PCB.

[0049] Example 3 like Figure 1 As shown, this embodiment provides a method for optimizing high-speed PCB signal integrity, comprising the following steps: S1. Cutting and chemical cleaning: Cut the PCB substrate according to the design requirements to ensure that the material size meets the requirements. Then, the chemical cleaning process is carried out. Compared with the traditional chemical cleaning process, the micro-etching process is omitted, including ultrasonic immersion, degreasing, pickling and drying; by adopting the non-micro-etching mode to clean the surface of each layer of the PCB substrate that makes up the high-speed PCB, the traditional roughening treatment is avoided, the mechanical damage to the surface of the PCB substrate is effectively reduced, the roughness of the copper surface itself is retained, and the loss of high-speed PCB signal integrity is reduced.

[0050] S2. Dry film covering and pattern etching: The surface of the PCB substrate after chemical cleaning is covered with a dry film, and then the pattern is transferred and etched. On the PCB substrate where the signal layer is located, during the etching process, the etched image includes not only the target pattern, but also the surrounding patterns outside the target pattern and the surrounding patterns added between the target pattern and the surrounding patterns.

[0051] like Figure 4As shown, preferably, it also includes a graphic optimization process: for the needs of impedance design, the surrounding graphics are continuously copper-plated, thereby increasing the residual copper rate of the entire signal layer board surface, providing a low-impedance return path for high-speed signals, reducing the electromagnetic radiation of the signal line, reducing signal crosstalk, enhancing signal integrity, and effectively controlling impedance. When the residual copper rate of the surrounding graphics exceeds 75%, a surrounding graphic is added between the target graphic and the surrounding graphics, and the surrounding graphic is composed of continuously distributed blocks, and the surrounding graphic separates the target graphic and the surrounding graphics. In this case, the overall residual copper rate of the signal layer is high, which greatly improves the thickness uniformity of the dielectric layer on the signal layer, but the resin filled around the target line area during the lamination process has poor fluidity, so it is not suitable for the situation where the resin fluidity in the semi-cured sheet set on the signal layer is poor.

[0052] Preferably, the target pattern is distributed in a long strip shape as a whole, and the surrounding pattern is a rectangle as a whole, and the line width of the short side of one side of the rectangle is greater than that of the other side, so that the setting of the surrounding pattern balances the impedance between the surrounding patterns adjacent to the two sides of the short side of the rectangle and the guide pattern adjacent to the board edge and the influence on the thickness of the dielectric layer. Preferably, the line width of the short side of one side of the rectangle is 3-5 times that of the other side.

[0053] Preferably, the target pattern is set to rotate 1-5° relative to the surrounding patterns. The target pattern is rotated to adjust the propagation direction of the high-speed signal, thereby reducing the impedance mismatch caused by the signal line passing through the glass fiber layers in different directions, reducing signal reflection and crosstalk, thereby reducing signal delay differences (skew) and uneven propagation, and improving signal quality.

[0054] Preferably, the film lamination pressure of the dry film is maintained between 4.5-5.5 kg to ensure a close fit between the dry film and the PCB substrate, avoiding the generation and distribution of bubbles and uneven media, thereby improving the accuracy of the circuit on the PCB substrate, reducing impedance mismatch, and improving heat conduction and electromagnetic interference problems, thereby effectively ensuring the transmission quality and reliability of signals on high-speed PCBs.

[0055] S3. Browning: After the circuit patterns on the various layers of the PCB substrates constituting the high-speed PCB are etched, the PCB substrates are subjected to a browning treatment, wherein the browning adopts a low-roughness browning process, such as Figure 5-Figure 6 As shown, by using ultra-low roughness browning solution for etching in the browning process, and controlling the micro-etching rate of the browning solution between 7.5±2.5μinch, the erosion of the copper surface can be controllably reduced, so as to controllably reduce the roughness, thereby reducing the loss caused by the skin effect and improving the signal integrity. Preferably, the browning solution is H with a concentration of 28±8 ml / L. 2 O 2 .

[0056] S4. Arrange and press the boards: Finally, all processed PCB substrates are arranged in the design order and pressed together to form the final high-speed PCB. The pressing process requires strict control of temperature and pressure to ensure good bonding of each layer in the high-speed PCB and to ensure the stability and reliability of the circuit on the high-speed PCB.

[0057] Example 4 like Figure 1 As shown, this embodiment provides a method for optimizing high-speed PCB signal integrity, comprising the following steps: S1. Cutting and chemical cleaning: Cut the PCB substrate according to the design requirements to ensure that the material size meets the requirements. Then, the chemical cleaning process is carried out. Compared with the traditional chemical cleaning process, the micro-etching process is omitted, including ultrasonic immersion, degreasing, pickling and drying; by adopting the non-micro-etching mode to clean the surface of each layer of the PCB substrate that makes up the high-speed PCB, the traditional roughening treatment is avoided, the mechanical damage to the surface of the PCB substrate is effectively reduced, the roughness of the copper surface itself is retained, and the loss of high-speed PCB signal integrity is reduced.

[0058] S2. Dry film covering and pattern etching: The surface of the PCB substrate after chemical cleaning is covered with a dry film, and then the pattern is transferred and etched. On the PCB substrate where the signal layer is located, during the etching process, the etched image includes not only the target pattern, but also the surrounding patterns outside the target pattern and the surrounding patterns added between the target pattern and the surrounding patterns.

[0059] like Figure 4As shown, preferably, it also includes a graphic optimization process: for the needs of impedance design, the surrounding graphics are continuously coppered, thereby increasing the residual copper rate of the entire board surface of the signal layer, providing a low-impedance return path for high-speed signals, reducing the electromagnetic radiation of the signal line, reducing signal crosstalk, enhancing signal integrity, and effectively controlling impedance. When the residual copper rate of the surrounding graphics is less than 50%, a surrounding graphic is added between the target graphic and the surrounding graphics, and the surrounding graphic is composed of a continuous distribution of blocks, and the surrounding graphic separates the target graphic and the surrounding graphic. In this case, the symmetry and uniformity of the graphic setting on the overall signal layer can still be conveniently balanced by setting the surrounding graphics, and the glue filling in the target line area is adjusted to match the glue filling uniformity of the entire board surface of the signal layer. The surrounding graphics are set to be composed of a continuous distribution of blocks, thereby increasing the local residual copper rate of the periphery of the target graphics, avoiding the lamination low-pressure area caused by retaining a continuous blank board surface between the target graphics and the surrounding graphics, thereby improving the overall glue filling uniformity on the board surface of the signal layer, and improving the uniformity of the thickness of the dielectric layer on the signal layer after lamination, and ensuring the signal integrity of the high-speed PCB.

[0060] Preferably, the target pattern is distributed in a long strip shape as a whole, and the surrounding pattern is a rectangle as a whole, and the line width of the short side of one side of the rectangle is greater than that of the other side, so that the setting of the surrounding pattern balances the impedance between the surrounding patterns adjacent to the two sides of the short side of the rectangle and the guide pattern adjacent to the board edge and the influence on the thickness of the dielectric layer. Preferably, the line width of the short side of one side of the rectangle is 3-5 times that of the other side.

[0061] Preferably, the target pattern is set to rotate 1-5° relative to the surrounding patterns. The target pattern is rotated to adjust the propagation direction of the high-speed signal, thereby reducing the impedance mismatch caused by the signal line passing through the glass fiber layers in different directions, reducing signal reflection and crosstalk, thereby reducing signal delay differences (skew) and uneven propagation, and improving signal quality.

[0062] Preferably, the film lamination pressure of the dry film is maintained between 4.5-5.5 kg to ensure a close fit between the dry film and the PCB substrate, avoiding the generation and distribution of bubbles and uneven media, thereby improving the accuracy of the circuit on the PCB substrate, reducing impedance mismatch, and improving heat conduction and electromagnetic interference problems, thereby effectively ensuring the transmission quality and reliability of signals on high-speed PCBs.

[0063] S3. Browning: After the circuit patterns on each layer of the PCB substrate constituting the high-speed PCB are etched, the PCB substrate is subjected to a browning treatment, wherein the browning adopts a low-roughness browning process, such as Figure 5-Figure 6As shown, by using ultra-low roughness browning solution for etching in the browning process, and controlling the micro-etching rate of the browning solution between 7.5±2.5μinch, the erosion of the copper surface can be controllably reduced, so as to controllably reduce the roughness, thereby reducing the loss caused by the skin effect and improving the signal integrity. Preferably, the browning solution is H with a concentration of 28±8 ml / L. 2 O 2 .

[0064] S4. Arrange and press the boards: Finally, all processed PCB substrates are arranged in the design order and pressed together to form the final high-speed PCB. The pressing process requires strict control of temperature and pressure to ensure good bonding of each layer in the high-speed PCB and to ensure the stability and reliability of the circuit on the high-speed PCB.

[0065] Comparative Example 1 like Figure 7 As shown, this comparative example provides a high-speed PCB, which is different from Examples 1-4 in that no continuous copper surface filling of surrounding patterns is performed around the target pattern on its signal layer, and no surrounding pattern is set, and the residual copper rate around the target pattern is 16%; and the target pattern is not rotated.

[0066] Depend on Figure 8 The high-speed PCB test results provided in Example 1 have a region with a large waveform change, that is, there are impedance abnormal points. After optimizing the target pattern on the high-speed PCB using the method for optimizing the signal integrity of the high-speed PCB provided in Example 1, as shown in FIG. Fig. 9 As shown, the test results of the high-speed PCB prepared by the manufacturing method of Example 1 show that the waveform changes little, and the impedance and signal integrity are both good.

[0067] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the technical solution of the present invention, and are not intended to limit the specific implementation methods of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the claims of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A method for optimizing high-speed PCB signal integrity, comprising the following steps: S1. Cut the material and perform chemical cleaning; S2. Dry film covering and pattern etching; S3. Browning; S4. Arrange the plates and press them together; It is characterized in that in the step S2, the etched image includes the optimized target pattern and the surrounding pattern outside the target pattern, and the optimization method is based on the following principles: When the residual copper rate of the surrounding pattern is between 50% and 70%, a surrounding pattern is added between the target pattern and the surrounding pattern, wherein the surrounding pattern is composed of a plurality of spaced grooves and blocks continuously distributed, and the grooves connect the target pattern and the surrounding pattern; When the residual copper rate of the surrounding pattern is between 70% and 75%, a surrounding pattern is added between the target pattern and the surrounding pattern, wherein the surrounding pattern is composed of spaced single grooves and blocks continuously distributed, and the grooves connect the target pattern and the surrounding pattern; When the residual copper rate of the surrounding pattern exceeds 75%, a surrounding pattern is added between the target pattern and the surrounding pattern, wherein the surrounding pattern is formed by continuously distributed stoppers, and the surrounding pattern separates the target pattern and the surrounding pattern.

2. The method for optimizing high-speed PCB signal integrity according to claim 1, characterized in that: The step S2 also includes the following principles: When the residual copper rate of the surrounding pattern is lower than 50%, a surrounding pattern is added between the target pattern and the surrounding pattern, wherein the surrounding pattern is formed by continuously distributed stoppers, and the surrounding pattern separates the target pattern and the surrounding pattern.

3. The method for optimizing high-speed PCB signal integrity according to claim 1, characterized in that: In the step S2, the target pattern is distributed in a long strip shape as a whole, the surrounding pattern is distributed in a rectangular shape as a whole, and a guide pattern is provided on the outside of at least one short side of the rectangle.

4. The method for optimizing high-speed PCB signal integrity according to claim 3, characterized in that: When the residual copper rate of the surrounding patterns is between 50% and 70%, the flow-guiding pattern is a circular array distribution structure, and the flow-guiding grooves of the flow-guiding pattern are formed in the gaps between the circles; When the residual copper rate of the surrounding patterns is between 70% and 75%, the flow guide pattern is a square array distribution structure, and the flow guide grooves of the flow guide pattern are formed in the gaps between the squares.

5. The method for optimizing high-speed PCB signal integrity according to claim 2, characterized in that: In step S2, the target pattern is distributed in a long strip shape as a whole, and the surrounding pattern is distributed in a rectangular shape as a whole. When the residual copper rate of the surrounding pattern exceeds 75% or is less than 50%, the line width of the short side of one side of the rectangle is greater than that of the other side.

6. The method for optimizing high-speed PCB signal integrity according to claim 5, characterized in that: The line width of the short side of one side of the rectangle is 3-5 times that of the other side.

7. The method for optimizing high-speed PCB signal integrity according to any one of claims 1 to 6, characterized in that: The target shape is rotated 1-5° relative to the surrounding shapes.

8. The method for optimizing high-speed PCB signal integrity according to any one of claims 1 to 6, characterized in that: Compared with the conventional chemical cleaning process, the chemical cleaning in step S1 omits the micro-etching process and includes ultrasonic immersion, degreasing, pickling and drying.

9. The method for optimizing high-speed PCB signal integrity according to claim 8, characterized in that: In step S3, the browning is performed using low roughness browning, and the micro-etching rate is controlled between 7.5±2.5 μinch.

10. The method for optimizing high-speed PCB signal integrity according to claim 8, characterized in that: The laminating pressure of the dry film in step S2 is between 4.5 kg and 5.5 kg.

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