A semiconductor device and its fabrication method, a memory and a storage system

Abstract

This disclosure provides a semiconductor device and its fabrication method, a memory, and a memory system. First, a first stacked layer including a first insulating layer and a sacrificial layer is formed. The first stacked layer includes a core region, a transition region, and a connection region adjacent in a first direction, with the transition region located between the core region and the connection region. Then, a first gate isolation structure located in the core region and a second gate isolation structure located in the transition region are formed. The first gate isolation structure includes a plurality of first air gaps arranged along the first direction and a first connection portion located between two adjacent first air gaps. The second gate isolation structure includes a plurality of second air gaps arranged along the first direction and a second connection portion located between two adjacent second air gaps. The dimension of the second connection portion along the first direction is larger than the dimension of the first connection portion along the first direction. Therefore, by increasing the dimension of the second connection portion in the transition region, the length of the filled portion in the transition region can be increased, thereby improving the performance of the semiconductor device.

Description

Technical Field

[0001] This disclosure generally relates to the field of electronic devices, and more specifically to a semiconductor device and a method for fabricating the same, a memory, and a storage system. Background Technology

[0002] NAND flash memory devices are non-volatile memory products with low power consumption, light weight, and high performance, and are widely used in electronic products. Planar NAND devices have reached their practical expansion limits. To further increase storage capacity and reduce the cost per bit, 3D NAND flash memory was proposed. In the 3D NAND flash memory structure, multiple layers of data storage cells are vertically stacked to achieve a stacked memory structure.

[0003] However, the performance of current 3D NAND devices needs improvement.

[0004] Public content

[0005] The purpose of this disclosure is to provide a semiconductor device and a method for fabricating the same, as well as a memory and a memory system, with the aim of improving the performance of the semiconductor device.

[0006] In a first aspect, this disclosure provides a method for fabricating a semiconductor device, the method comprising:

[0007] A first stacked layer is formed, the first stacked layer comprising alternating layers of a first insulating layer and a sacrificial layer, the first stacked layer comprising a core region, a transition region and a connection region adjacent in a first direction, the transition region being located between the core region and the connection region, the first direction intersecting the stacking direction of the first stacked layer;

[0008] A first gate line isolation structure is formed in the core region and a second gate line isolation structure is formed in the transition region. The first gate line isolation structure includes a plurality of first air gaps arranged along the first direction and a first connecting portion located between two adjacent first air gaps. The second gate line isolation structure includes a plurality of second air gaps arranged along the first direction and a second connecting portion located between two adjacent second air gaps. The dimension of the second connecting portion along the first direction is larger than the dimension of the first connecting portion along the first direction.

[0009] In some embodiments, the size of the second connecting portion along the first direction ranges from 25 to 55 nm.

[0010] In some embodiments, the step of forming a first gate line isolation structure located in the core region and a second gate line isolation structure located in the transition region includes:

[0011] A hole structure is formed that penetrates the first stacked layer along the stacking direction and is spaced apart along the first direction. The hole structure includes a first hole structure located in the core region and a second hole structure located in the transition region.

[0012] The hole structure is enlarged to form a first grid line slot located in the core region and a second grid line slot located in the transition region;

[0013] A filling layer is formed in the first gate line gap and the second gate line gap to form a first gate line isolation structure and a second gate line isolation structure.

[0014] In some embodiments, the step of forming a hole structure that penetrates the first stacked layer along the stacking direction and is spaced apart along the first direction includes:

[0015] The first stacked layer is etched along the stacking direction of the first stacked layer to form a first hole structure, a second hole structure and a third hole structure located in the core region, the transition region and the connection region respectively. The first hole structure and the second hole structure are arranged in a row along the first direction, and the third hole structure is arranged in multiple rows along the first direction.

[0016] The third hole structures in two adjacent rows are staggered along the first direction, and the spacing between three adjacent third hole structures is equal.

[0017] In some embodiments, the step of enlarging the hole structure includes:

[0018] The first stacked layer surrounding the first hole structure, the second hole structure, and the third hole structure is etched to form a first gate line slot, a second gate line slot, and a third gate line slot that extend along a first direction and are interconnected.

[0019] In some embodiments, the hole spacing between two adjacent second hole structures is greater than the hole spacing between two adjacent first hole structures; the hole spacing between adjacent first hole structures and second hole structures is greater than the hole spacing between two adjacent first hole structures; the hole spacing between adjacent third hole structures and second hole structures is greater than the hole spacing between two adjacent first hole structures.

[0020] In some embodiments, the method for fabricating the semiconductor device further includes:

[0021] During the formation of the hole structure, channel holes and virtual channel holes are formed that penetrate the first stacked layer along the stacking direction of the first stacked layer.

[0022] The channel hole is located in the core area and between two adjacent rows of first hole structures, and the virtual channel hole is located in the transition area and between two adjacent rows of second hole structures.

[0023] In some embodiments, the step of forming a hole structure that penetrates the first stacked layer along the stacking direction and is spaced apart along the first direction includes:

[0024] The first stacked layer is etched along the stacking direction to form a first hole structure located in the core region and a second hole structure located in the transition region. The second hole structure includes a first sub-hole structure and a second sub-hole structure arranged alternately along the first direction.

[0025] Wherein, the maximum dimension of the first sub-hole structure along the first direction is equal to the maximum dimension of the first hole structure along the first direction, and the maximum dimension of the second sub-hole structure along the first direction is less than the maximum dimension of the first sub-hole structure along the first direction.

[0026] In some embodiments, the method for fabricating the semiconductor device further includes:

[0027] A second stacked layer is formed on the first stacked layer, and a central hole structure is formed that penetrates the second stacked layer along the stacking direction and is arranged along the first direction. The central hole structure includes a first central hole structure located in the core region and a second central hole structure located in the transition region.

[0028] A third stacked layer is formed on the second stacked layer, and an upper hole structure is formed that penetrates the second stacked layer along the stacking direction and is arranged along the first direction. The upper hole structure includes a first upper hole structure located in the core region and a second upper hole structure located in the transition region.

[0029] Wherein, the middle hole structure is connected to the hole structure, and the upper hole structure is connected to the middle hole structure; the maximum dimension of the second hole structure along the first direction is smaller than the maximum dimension of the second middle hole structure along the first direction, and the maximum dimension of the second middle hole structure along the first direction is smaller than the maximum dimension of the second upper hole structure along the first direction.

[0030] In some embodiments, the maximum dimension of the first hole structure along the first direction, the maximum dimension of the first middle hole structure along the first direction, and the maximum dimension of the first upper hole structure along the first direction are all equal.

[0031] In some embodiments, the step of forming a filling layer in the first gate line gap and the second gate line gap includes:

[0032] A second insulating layer and a first conductive layer are formed in the first gate line gap, the second gate line gap, and the third gate line gap.

[0033] In some embodiments, prior to the step of forming a second insulating layer and a first conductive layer in the first gate line gap, the second gate line gap, and the third gate line gap, the method for fabricating the semiconductor device further includes:

[0034] The sacrificial layer in the first stacked layer of the core region is replaced with a gate layer.

[0035] In a second aspect, this disclosure provides a semiconductor device, the semiconductor device comprising:

[0036] A first stacked structure includes alternating layers of a first insulating layer and a gate layer. The first stacked structure includes a core region, a transition region, and a connection region adjacent in a first direction. The transition region is located between the core region and the connection region. The first direction intersects the stacking direction of the stacked structure.

[0037] A first gate isolation structure extends through the first stacked structure of the core region along the stacking direction and extends along the first direction;

[0038] The second gate line isolation structure extends through the first stacked structure in the transition region along the stacking direction, and the second gate line isolation structure extends along the first direction and is connected to the first gate line isolation structure.

[0039] The first grid isolation structure includes a plurality of first air gaps arranged along the first direction and a first connecting portion located between two adjacent first air gaps; the second grid isolation structure includes a plurality of second air gaps arranged along the first direction and a second connecting portion located between two adjacent second air gaps; the dimension of the second connecting portion along the first direction is larger than the dimension of the first connecting portion along the first direction.

[0040] In some embodiments, the semiconductor device further includes a third gate line isolation structure, the third gate line isolation structure extending through the first stacked structure of the connection region along the stacking direction, the third gate line isolation structure extending along the first direction and connected to the second gate line isolation structure;

[0041] The maximum dimension of the first gate isolation structure in the second direction is smaller than the minimum dimension of the third gate isolation structure in the second direction, and the second direction intersects the stacking direction and the first direction.

[0042] In some embodiments, the top view of the second grid isolation structure includes a plurality of first arcs connected along the first direction, wherein the plurality of first arcs have equal arc lengths.

[0043] In some embodiments, the top view of the second grid isolation structure further includes a second arc connected to the first arc, the second arc being located between two adjacent first arcs, and the arc length of the second arc being less than the arc length of the first arc.

[0044] In some embodiments, the semiconductor device further includes:

[0045] The second stacking structure is located on the first stacking structure;

[0046] A central gate line isolation structure extends through the second stacked layer along the stacking direction and extends along the first direction. The central gate line isolation structure includes a first central gate line isolation structure located in the core region and a second central gate line isolation structure located in the transition region.

[0047] The third stacking structure is located on the second stacking structure;

[0048] The upper gate line isolation structure extends through the third stacking layer along the stacking direction and extends along the first direction. The upper gate line isolation structure includes a first upper gate line isolation structure located in the core region and a second upper gate line isolation structure located in the transition region.

[0049] Wherein, the first gate line isolation structure, the first middle gate line isolation structure and the first upper gate line isolation structure are connected in the stacking direction, and the second gate line isolation structure, the second middle gate line isolation structure and the second upper gate line isolation structure are connected in the stacking direction;

[0050] The maximum dimension of the second upper gate line isolation structure along the second direction is greater than the maximum dimension of the second middle gate line isolation structure along the second direction; the maximum dimension of the second middle gate line isolation structure along the second direction is greater than the maximum dimension of the second gate line isolation structure along the second direction.

[0051] In some embodiments, the first central grid isolation structure includes a plurality of first central air gaps arranged along the first direction, and a first central connecting portion located between two adjacent first central air gaps;

[0052] The second central grid isolation structure includes a plurality of second central air gaps arranged along the first direction, and a second central connecting portion located between two adjacent second central air gaps;

[0053] The dimension of the second middle connecting portion along the first direction is greater than the dimension of the first middle connecting portion along the first direction.

[0054] In some embodiments, the first upper grid line isolation structure includes a plurality of first upper air gaps arranged along the first direction, and a first upper connecting portion located between two adjacent first upper air gaps;

[0055] The second upper grid line isolation structure includes a plurality of second upper air gaps arranged along the first direction, and a second upper connecting portion located between two adjacent second upper air gaps;

[0056] The dimension of the first upper connecting portion along the first direction is greater than or equal to the dimension of the second upper connecting portion along the first direction.

[0057] In some embodiments, the dimension of the second upper connecting portion along the first direction is smaller than the dimension of the second middle connecting portion along the first direction; the dimension of the second middle connecting portion along the first direction is smaller than the dimension of the second connecting portion along the first direction.

[0058] Thirdly, embodiments of this application provide a memory, including:

[0059] The semiconductor device provided in any of the above embodiments;

[0060] The peripheral circuit is electrically connected to the semiconductor device.

[0061] Fourthly, embodiments of this application provide a storage system, including:

[0062] The memory provided in any of the foregoing embodiments;

[0063] A controller, electrically connected to the memory, is used to control the memory to store data.

[0064] This disclosure provides a semiconductor device and its fabrication method, a memory, and a memory system. First, a first stacked layer including a first insulating layer and a sacrificial layer is formed. The first stacked layer includes a core region, a transition region, and a connection region adjacent in a first direction, with the transition region located between the core region and the connection region. Then, a first gate isolation structure located in the core region and a second gate isolation structure located in the transition region are formed. The first gate isolation structure includes a plurality of first air gaps arranged along the first direction and a first connection portion located between two adjacent first air gaps. The second gate isolation structure includes a plurality of second air gaps arranged along the first direction and a second connection portion located between two adjacent second air gaps. The dimension of the second connection portion along the first direction is larger than the dimension of the first connection portion along the first direction. Therefore, compared to the first connection portion in the core region, increasing the size of the second connection portion in the transition region increases the length of the filled portion in the transition region, thereby improving the performance of the semiconductor device. Attached Figure Description

[0065] The technical solution and other beneficial effects of this disclosure will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0066] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device provided in some embodiments of this disclosure;

[0067] Figures 2a-2g These are schematic diagrams illustrating the structure of semiconductor devices during fabrication according to some embodiments of this application;

[0068] Figures 3a-3e These are schematic diagrams illustrating the structure of semiconductor devices during fabrication according to some embodiments of this application;

[0069] Figures 4a-4c These are schematic diagrams illustrating the structure of semiconductor devices during fabrication according to some embodiments of this application;

[0070] Figure 5 This is a cross-sectional structural schematic diagram of the semiconductor device provided in some embodiments of this application during the fabrication process;

[0071] Figure 6 These are schematic diagrams of the structure of semiconductor devices provided in some embodiments of this application;

[0072] Figure 7 These are schematic diagrams of the memory structure provided in some embodiments of this application;

[0073] Figure 8 This is a schematic diagram of the structure of a storage system provided in some embodiments of this application. Detailed Implementation

[0074] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0075] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of this disclosure.

[0076] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0077] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a range smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0078] It should be noted that the illustrations provided in the embodiments of this disclosure are only schematic representations of the basic concept of this disclosure. Although the illustrations only show components related to this disclosure and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0079] This paper uses Cartesian coordinates to represent directions, where "X" represents the first direction, "Y" represents the second direction, and "Z" represents the stacking direction. The first, second, and third directions intersect each other, that is, X, Y, and Z intersect each other, for example, they can be perpendicular to each other or form a certain angle.

[0080] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating the fabrication method of a semiconductor device provided in some embodiments of this disclosure. Please also refer to... Figures 2a-2g , Figures 2a-2g This is a schematic diagram of the semiconductor device provided in some embodiments of this application during the fabrication process. The fabrication method of the semiconductor device includes the following steps S1-S2.

[0081] Step S1: Form a first stacked layer 10, the first stacked layer 10 including alternating layers of a first insulating layer and a sacrificial layer, the first stacked layer 10 including a core region 10a, a transition region 10b and a connecting region 10c adjacent in a first direction (X), the transition region 10b being located between the core region 10a and the connecting region 10c, the first direction (X) intersecting the stacking direction (Z) of the first stacked layer 10.

[0082] A substrate can be provided first, and then a first insulating layer and a sacrificial layer can be alternately deposited on the substrate to form a first stacked layer 10. For example... Figure 2a As shown, the first stacked layer 10 includes a core region 10a, a transition region 10b, and a connection region 10c arranged sequentially adjacent to each other in a first direction (X). The first stacked layer 10 of the core region 10a is used to form a memory channel structure, the first stacked layer 10 of the transition region 10b is used to form a virtual channel structure, and the first stacked layer 10 of the connection region 10c is used to form a conductive structure, such as word line contacts.

[0083] An exemplary material for the first insulating layer is silicon oxide, and an exemplary material for the sacrificial layer is silicon nitride. The deposition process for the first insulating layer and the sacrificial layer can employ, but is not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) methods such as thermal oxidation, evaporation, sputtering, and other methods.

[0084] Step S2: Form a first gate line isolation structure 11a located in the core region 10a and a second gate line isolation structure 11b located in the transition region 10b. The first gate line isolation structure 11a includes a plurality of first air gaps 111a arranged along the first direction (X) and a first connecting portion 112a located between two adjacent first air gaps 111a. The second gate line isolation structure 11b includes a plurality of second air gaps 111b arranged along the first direction (X) and a second connecting portion 112b located between two adjacent second air gaps 111b. The dimension of the second connecting portion 112b along the first direction (X) is larger than the dimension of the first connecting portion 112a along the first direction (X).

[0085] In some embodiments, the size of the second connecting portion 112b along the first direction (X) ranges from 25 to 55 nm.

[0086] Specifically, step S2 may include the following steps.

[0087] 1) A hole structure is formed that extends through the first stacked layer 10 along the stacking direction (Z) and is spaced apart along the first direction (X), the hole structure including a first hole structure 101a located in the core region 10a and a second hole structure 101b located in the transition region 10b.

[0088] like Figure 2a As shown, the first stacked layer 10 can be etched along the stacking direction (Z) to form multiple hole structures, wherein the first hole structure 101a is located in the core region 10a, the second hole structure 101b is located in the transition region 10b, and the third hole structure 101c is located in the connection region 10c. The first hole structure 101a and the second hole structure 101b are arranged in a row along the first direction (X), and the third hole structure 101c is arranged in multiple rows along the first direction (X).

[0089] In some embodiments, the third hole structures 101c in adjacent rows are staggered along the first direction (X). For example, the third hole structures 101c in the second row are not aligned with the third hole structures 101c in the first row, but rather the third hole structures 101c in the second row correspond to the area between the third hole structures 101c in the first row. Furthermore, in this staggered arrangement, the spacing between three adjacent third hole structures 101c is equal.

[0090] In some embodiments, during the etching process of the hole structure, channel holes and virtual channel holes (not shown in the figure) that penetrate the first stacked layer 10 along the stacking direction (Z) of the first stacked layer 10 can also be formed, that is, the hole structure, channel holes, and virtual channel holes are formed together. The channel holes are located in the core region 10a and between two adjacent rows of first hole structures 101a, while the virtual channel holes are located in the transition region 10b and between two adjacent rows of second hole structures 101b.

[0091] The method for fabricating this semiconductor device also includes forming a channel structure and a virtual channel structure in the channel hole and the virtual channel hole, respectively.

[0092] It should be noted that, Figure 2a Only one row of the first hole structure 101a and the second hole structure 101b is shown. In reality, multiple rows of the first hole structure 101a and multiple rows of the second hole structure 101b are formed in the first stacked layer 10, and there is a gap between adjacent rows. That is to say, Figure 2aThe displayed hole structure is a repeating unit, and multiple repeating units can be arranged at intervals along the second direction (Y). Therefore, channel holes are formed in... Figure 2a The virtual channel holes are formed on both sides of the first hole structure 101a along the second direction (Y). Figure 2a The second hole structure 101b is located on both sides of the second direction (Y).

[0093] 2) The hole structure is enlarged to form a first grid line slot 102a located in the core region 10a and a second grid line slot 102b located in the transition region 10b.

[0094] Specifically, the first stacked layer 10 surrounding the first hole structure 101a, the second hole structure 101b, and the third hole structure 101c can be etched to form a first gate line slot 102a, a second gate line slot 102b, and a third gate line slot 102c that extend along the first direction (X) and are interconnected. For a single hole structure ( Figure 2a The outline after enlarging the hole (solid line circle) is as follows: Figure 2a As shown by the dashed circle, multiple hole structures are connected after being enlarged, and the overall outline (grid gaps) is as follows. Figure 2b As shown by the dashed lines, the gate line slots include a first gate line slot 102a, a second gate line slot 102b, and a third gate line slot 102c. Since the first gate line slot 102a is obtained by enlarging the first hole structure 101a, the second gate line slot 102b is obtained by enlarging the second hole structure 101b, and the third gate line slot 102c is obtained by enlarging the third hole structure 101c, the first gate line slot 102a is located in the core region 10a, the second gate line slot 102b is located in the transition region 10b, and the third gate line slot 102c is located in the connecting region 10c. Because the third hole structure 101c has a larger number of rows, the maximum dimension of the third gate line slot 102c along the second direction (Y) is greater than the maximum dimension of the second gate line slot 102b along the second direction (Y), and the maximum dimension of the third gate line slot 102c along the second direction (Y) is greater than the maximum dimension of the first gate line slot 102a along the second direction (Y).

[0095] In some embodiments, with the third hole structures 101c arranged in an alternating pattern, the spacing between three adjacent third hole structures 101c is equal. Compared to the case where two rows of third hole structures 101c are arranged in an aligned manner, the density of the third hole structures 101c can be increased. In this way, the first stacked layer 10 between the third hole structures 101c is easier to remove during the hole enlargement process, which can increase the hole enlargement process window.

[0096] 3) A filling layer 103 is formed in the first gate line gap 102a and the second gate line gap 102b to form a first gate line isolation structure 11a and a second gate line isolation structure 11b.

[0097] It should be noted that before forming the fill layer 103 or after via drilling, the sacrificial layer in the first stacked layer 10 of the core region 10a and transition region 10b needs to be replaced with a gate layer (e.g., tungsten). Therefore, after via drilling, the first stacked layer 10 becomes the first stacked structure 10'. Between the formation of the fill layer 103, a conductive structure extending along the stacking direction (Z) also needs to be formed between the gaps 102c of the two adjacent third gate lines.

[0098] In some specific embodiments, such as Figure 2c As shown, a second insulating layer and a first conductive layer can be sequentially deposited in the first gate gap 102a, the second gate gap 102b, and the third gate gap 102c. The second insulating layer is, for example, silicon oxide, and the first conductive layer is, for example, polycrystalline silicon. The arrows in the figure indicate the direction of gas during material deposition. Because the third gate gap 102c has a larger dimension along the second direction (Y), the third gate gap 102c is not completely filled.

[0099] like Figure 2d As shown, the second insulating layer and the first conductive layer located in the third gate line gap 102c are then removed to allow for the connection of the conductive structure in the connection region 10c to the gate layer in the core region 10a. Specifically, after the third gate line gap 102c is hollowed out, the sacrificial layer around the third gate line gap 102c is replaced with a connection layer (e.g., tungsten), so that the connection layer can connect the gate layer and the conductive structure in the connection region 10c.

[0100] like Figure 2e As shown, a second insulating layer and a first conductive layer are then filled into the third gate line gap 102c, thereby forming a filling layer 103 in the gate line gap.

[0101] In some embodiments, Figure 2d In the process of removing the second insulating layer and the first conductive layer, part of the filler layer 103 in the second gate line gap 102b will be removed. Figure 2e During the filling process, both the second gate line gap 102b and the second gate line gap 102b will be filled.

[0102] The filling layer 103 can be formed using any of the above-mentioned deposition processes. Due to the limitations of the deposition process, air gaps will be formed in the gate line gaps. Therefore, the first gate line isolation structure 11a includes a first air gap 111a and a first connecting portion 112a, the second gate line isolation structure 11b includes a second air gap 111b and a second connecting portion 112b, and the third gate line isolation structure 11c includes a third air gap and a third connecting portion (not shown in the figure).

[0103] However, for the smaller first gate isolation structure 11a and second gate isolation structure 11b, in order to ensure the performance of the semiconductor device (e.g., support performance), the total length of the connection portion (including the first connection portion 112a and the second connection portion 112b) along the first direction (X) needs to reach a specific value to reduce the risk of adjacent air gap communication and improve support performance. Therefore, the length of the second connection portion 112b can be increased by increasing the hole spacing of the second hole structure 101b in the transition region 10b, such as... Figure 2a As shown, the hole spacing W1 between two adjacent second hole structures 101b is greater than the hole spacing between two adjacent first hole structures 101a, and after filling, it is as follows: Figure 2e As shown, the length L1 of the second connecting part 112b is greater than the length L2 of the first connecting part 112a.

[0104] It should be noted that, due to Figure 2a Only one first hole structure 101a is shown in the image, therefore the hole spacing between two adjacent first hole structures 101a is not shown.

[0105] In some embodiments, if the region between adjacent first hole structure 101a and second hole structure 101b is divided into core region 10a ( Figure 2a As shown in the figure, the hole spacing W2 between adjacent first hole structures 101a and second hole structures 101b is equal to the hole spacing between two adjacent first hole structures 101a.

[0106] If the area between adjacent first hole structures 101a and second hole structures 101b is divided into transition area 10b, then the hole spacing between adjacent first hole structures 101a and second hole structures 101b (equal to the hole spacing between two adjacent second hole structures 101b) is greater than the hole spacing between two adjacent first hole structures 101a.

[0107] In some embodiments, if the region between adjacent second hole structure 101b and third hole structure 101c is divided into connection region 10c ( Figure 2a As shown in the figure, the hole spacing between the adjacent third hole structure 101c and the second hole structure 101b is smaller than the hole spacing between the two adjacent first hole structures 101a.

[0108] If Figure 2a The second hole structure 101b, located near the connecting region 10c, is divided into the connecting region 10c to become the third hole structure 101c. That is, the dashed line between the transition region 10b and the connecting region 10c is shifted to the left to the left edge of the second hole structure 101b, making it the third hole structure 101c. Therefore, the hole spacing between adjacent third hole structures 101c and second hole structures 101b is greater than the hole spacing between two adjacent first hole structures 101a. In general, the hole spacing in the transition region is larger than the hole spacing in the core region.

[0109] In some embodiments, the maximum dimensions of the first hole structure 101a, the second hole structure 101b, and the third hole structure 101c along the first direction (X) are all equal.

[0110] It should be noted that there are multiple first air gaps 111a and second air gaps 111b, because... Figure 2c Only three second air gaps 111b are shown. However, during the etching process that removes the second insulating layer and the first conductive layer located in the third gate line gap 102c, the two second air gaps 111b near the connection region 10c may be removed, resulting in a structure as shown in the image. Figure 2f As shown. The structure after the third grid line gap 102c is filled is as follows. Figure 2g As shown, therefore Figure 2f and 2g The second connecting part is not shown. And because... Figure 2f The etching process removes a portion of the second air gap 111b in the transition region 10b. Therefore, the length of the filling layer 103 near the connection region 10c in the transition region 10b in the first direction (X) is greater than the length of the second connection portion in the transition region 10b. In fact, in Figure 2g In the structure, the transition zone 10b also has multiple second air gaps 111b and multiple second connecting parts, and the length of the second connecting part along the first direction (X) is greater than the length L2 of the first connecting part 112a along the first direction (X).

[0111] In some embodiments, the total length of the connection portion can be increased by increasing the number of second hole structures 101b. However, this would increase the size of the transition region 10b, thereby increasing the number of virtual channel structures in the transition region 10b and consequently compressing the storage space. In the semiconductor device fabrication method provided in this application, the total length of the connection portion is increased by increasing the length of the second connection portion 112b to ensure performance, without increasing the number of virtual channel structures or the space of the transition region 10b, thus improving the storage space.

[0112] Please see Figures 3a-3e , Figures 3a-3e This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this application during the fabrication process.

[0113] The fabrication method of this semiconductor device also includes the above steps S1 and S2, and... Figures 2a-2e The difference in the embodiment is that, in the step of forming the hole structure, the second hole structure 101b' includes a first sub-hole structure 1011b and a second sub-hole structure 1012b arranged alternately along the first direction (X).

[0114] In this configuration, the maximum dimension R1 of the first sub-hole structure 1011b along the first direction (X) is equal to the maximum dimension R2 of the first hole structure 101a along the first direction (X), and the maximum dimension R3 of the second sub-hole structure 1012b along the first direction (X) is smaller than the maximum dimension R1 of the first sub-hole structure 1011b along the first direction (X). In other words, by reducing the size of the second sub-hole structure 1012b within the second hole structure 101b', the hole spacing between adjacent second hole structures 101b' is increased, making the hole spacing of the second hole structures 101b' greater than the hole spacing of the first hole structure 101a, thereby allowing for a subsequent increase in the length of the second connecting portion 112b.

[0115] like Figure 3b As shown, after via enlargement, a first gate line slot 102a, a second gate line slot 102b', and a third gate line slot 102c are formed. The structure after depositing the second insulating layer and the first conductive layer is as follows. Figure 3c As shown, after removing the second insulating layer and the first conductive layer in the third gate line gap 102c, the structure is as follows: Figure 3d As shown. Figure 3e As shown, after filling the third gate line gap 102c, a first gate line isolation structure 11a, a second gate line isolation structure 11b', and a third gate line isolation structure 11c are formed. Among them, the second gate line isolation structure 11b' includes a second air gap 111b' and a second connecting portion 112b'.

[0116] It should be noted that the length L3 of the second connecting portion 112b' along the first direction (X) is greater than the length of the first connecting portion along the first direction (X). Figure 3e The first connecting part is not shown.

[0117] Please see Figures 4a-4c and Figure 5 , Figures 4a-4c These are schematic diagrams illustrating the fabrication process of semiconductor devices provided in some embodiments of this application. Figure 5 This is a cross-sectional structural diagram of a semiconductor device provided in some embodiments of this application during the fabrication process.

[0118] The method for fabricating the semiconductor device includes the steps S1-S2 described above. A plurality of first hole structures 11 and a plurality of second hole structures 12 are formed in the first stacked layer 10. The first hole structures 11 are located in the core region 10a, and the second hole structures 12 are located in the transition region 10b.

[0119] The method for fabricating the semiconductor device may further include: 1) forming a second stacked layer 20 on the first stacked layer 10, and forming a central hole structure that penetrates the second stacked layer 20 along the stacking direction (Z) and is arranged along the first direction (X), the central hole structure including a first central hole structure 21 located in the core region 10a and a second central hole structure 22 located in the transition region 10b; 2) forming a third stacked layer 30 on the second stacked layer 20, and forming an upper hole structure that penetrates the second stacked layer 20 along the stacking direction (Z) and is arranged along the first direction (X), the upper hole structure including a first upper hole structure 31 located in the core region 10a and a second upper hole structure 32 located in the transition region 10b.

[0120] in, Figure 4c The diagram shows the structure after the pore structure is formed in the first stacked layer 10. Figure 4b The diagram shows the structure after the central hole structure is formed in the second stacked layer 20. Figure 4a The diagram shows the structure after the upper hole structure is formed in the third stacked layer 30. The middle hole structure is connected to the corresponding hole structure, and the upper hole structure is connected to the corresponding middle hole structure. After hole enlargement... Figure 4a The outline connecting the dashed circle in the middle to the third stacked layer 30 is the outline of the upper gate line gap, after the via is enlarged. Figure 4b The outline connecting the dashed circle in the middle to the second stacked layer 20 is the outline of the central gate gap, after the via is enlarged. Figure 4c The outline of the dashed circle connected to the first stacked layer 10 is the outline of the gate line slots (including the connected first gate line slot, second gate line slot and third gate line slot).

[0121] like Figure 5As shown, the maximum dimensions of the first hole structure 11 along the first direction (X), the first middle hole structure 21 along the first direction (X), and the first upper hole structure 31 along the first direction (X) are all equal, all being D1. The maximum dimension D2 of the second hole structure 12 along the first direction (X) is smaller than the maximum dimension D3 of the second middle hole structure 22 along the first direction (X). The maximum dimension D3 of the second middle hole structure 22 along the first direction (X) is smaller than the maximum dimension D4 of the second upper hole structure 32 along the first direction (X). That is, from top to bottom, the dimensions of the hole structures in the transition region 10b gradually decrease. Therefore, compared to the first middle hole structure 21 and the first hole structure 11 in the core region 10a, the hole spacing between the second middle hole structures 22 and the hole spacing between the second hole structures 12 are increased, thereby increasing the length of the second middle connecting portion and the second connecting portion after filling. Furthermore, in the fabrication method of semiconductor devices with multiple stacked layers, the size of the second upper hole structure 32 is relatively large, which is beneficial to the filling process of the lower second middle hole structure 22 and the second hole structure 12, and can further increase the length of the filled part (connection part).

[0122] In some embodiments, the maximum dimension D4 of the second upper hole structure 32 along the first direction (X) is less than or equal to the maximum dimension D1 of the first upper hole structure 31 along the first direction (X). When the maximum dimension D4 of the second upper hole structure 32 is less than the maximum dimension D1 of the first upper hole structure 31, the length of the first upper connecting portion can be increased.

[0123] This disclosure also provides a semiconductor device, which can be a wafer. The wafer can be diced to form multiple chips, such as a three-dimensional memory. Three-dimensional memory can be applied to communication products, consumer electronics, automotive products, aerospace products, artificial intelligence products, or big data, etc. Consumer electronics include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses, or gaming products.

[0124] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this application. The semiconductor device is fabricated by the method described in any of the above embodiments, and therefore can be referred to... Figure 2e and Figure 3e It should be noted that, Figure 6 Examples and Figure 2e The difference lies in the number displayed in the first air gap 111a.

[0125] The semiconductor device includes a first stacked structure 10', a first gate isolation structure 11a, and a second gate isolation structure 11b. The first stacked structure 10' includes alternating layers of a first insulating layer and a gate layer. The first stacked structure 10' includes a core region 10a, a transition region 10b, and a connection region 10c adjacent in a first direction (X), with the transition region 10b located between the core region 10a and the connection region 10c. The first gate isolation structure 11a extends through the core region 10a of the first stacked structure 10' along the stacking direction (Z) and extends along the first direction (X). Second gate isolation structures 11b / 11b' extend through the transition region 10b of the first stacked structure 10' along the stacking direction (Z), and the second gate isolation structures 11b / 11b' extend along the first direction (X) and are connected to the first gate isolation structure 11a. The first gate isolation structure 11a includes a plurality of first air gaps 111a arranged along the first direction (X), and a first connecting portion 112a located between two adjacent first air gaps 111a. The second gate isolation structure 11b / 11b' includes a plurality of second air gaps 111b arranged along the first direction (X), and a second connecting portion 112b located between two adjacent second air gaps 111b. The dimension L1 of the second connecting portion 112b along the first direction (X) is larger than the dimension L2 of the first connecting portion 112a along the first direction (X).

[0126] In some embodiments, the semiconductor device further includes a third gate isolation structure 11c, which extends along the stacking direction (Z) through the first stacked structure 10' of the connection region 10c, and extends along the first direction (X) and connects to the second gate isolation structures 11b / 11b'. The maximum dimension of the first gate isolation structure 11a in the second direction (Y) is smaller than the minimum dimension of the third gate isolation structure 11c in the second direction (Y). The maximum dimension of the second gate isolation structures 11b / 11b' in the second direction (Y) is also smaller than the minimum dimension of the third gate isolation structure 11c in the second direction (Y).

[0127] In some embodiments, such as Figure 2e As shown, the top view of the second grid isolation structure 11b / 11b' includes a plurality of first arcs connected along the first direction (X), and the arc lengths of the plurality of first arcs are equal.

[0128] In some embodiments, such as Figure 3eAs shown, the top view of the second grid isolation structure 11b / 11b' also includes a second arc connected to the first arc. The second arc is located between two adjacent first arcs, and the arc length of the second arc is less than the arc length of the first arc.

[0129] In some embodiments, Figures 4a-4c After filling in the dashed outline, the semiconductor device further includes a second stacked structure, a middle gate isolation structure, a third stacked structure, and a top gate isolation structure. The second stacked structure is located on the first stacked structure 10', and the middle gate isolation structure penetrates the second stacked structure along the stacking direction (Z) and extends along the first direction (X). The middle gate isolation structure includes a first middle gate isolation structure located in the core region 10a and a second middle gate isolation structure located in the transition region 10b. The third stacked structure is located on the second stacked structure, and the top gate isolation structure penetrates the third stacked structure along the stacking direction (Z) and extends along the first direction (X). The top gate isolation structure includes a first top gate isolation structure located in the core region 10a and a second top gate isolation structure located in the transition region 10b. The first gate isolation structure 11a, the first middle gate isolation structure, and the first top gate isolation structure are connected along the stacking direction (Z). The second gate line isolation structure, the second middle gate line isolation structure, and the second upper gate line isolation structure are connected in the stacking direction (Z).

[0130] In some embodiments, the maximum dimension of the second upper gate line isolation structure along the second direction (Y) is greater than the maximum dimension of the second middle gate line isolation structure along the second direction (Y). The maximum dimension of the second middle gate line isolation structure along the second direction (Y) is also greater than the maximum dimension of the second gate line isolation structure along the second direction (Y). That is, the maximum dimensions of the second upper gate line isolation structure, the second middle gate line isolation structure, and the second gate line isolation structure gradually decrease from top to bottom.

[0131] The first central gate isolation structure includes a plurality of first central air gaps arranged along the first direction (X), and a first central connecting portion located between two adjacent first central air gaps. The second central gate isolation structure includes a plurality of second central air gaps arranged along the first direction (X), and a second central connecting portion located between two adjacent second central air gaps. The dimension of the second central connecting portion along the first direction (X) is larger than the dimension of the first central connecting portion along the first direction (X), thus increasing the length of the second central connecting portion in the transition region 10b of the second stacked structure.

[0132] The first upper gate isolation structure includes a plurality of first upper air gaps arranged along the first direction (X), and a first upper connection portion located between two adjacent first upper air gaps. The second upper gate isolation structure includes a plurality of second upper air gaps arranged along the first direction (X), and a second upper connection portion located between two adjacent second upper air gaps. The dimension of the first upper connection portion along the first direction (X) is larger than the dimension of the second upper connection portion along the first direction (X), thus increasing the length of the second upper connection portion in the transition region 10b of the third stacked structure.

[0133] Therefore, for a semiconductor device with multiple stacked structures, the dimension of the transition region 10b connection portion along the first direction (X) of each stacked structure can be greater than the dimension of the core region 10a connection portion along the first direction (X).

[0134] In some embodiments, since the maximum dimension D4 of the second upper hole structure 32 along the first direction (X) is less than or equal to the maximum dimension D1 of the first upper hole structure 31 along the first direction (X), the dimension of the first upper connecting portion along the first direction (X) can be less than or equal to the dimension of the second upper connecting portion along the first direction (X).

[0135] In some embodiments, since the maximum size of the hole structure in the transition zone 10b gradually decreases from top to bottom, the size of the second upper connecting portion along the first direction (X) is smaller than the size of the second middle connecting portion along the first direction (X); the size of the second middle connecting portion along the first direction (X) is smaller than the size of the second connecting portion 112b along the first direction (X), that is, the length of the connecting portion in the transition zone 10b gradually increases from top to bottom.

[0136] The semiconductor device provided in this embodiment has a size of the second connection portion 112b of the transition region 10b along the first direction (X) that is larger than the size of the first connection portion 112a of the core region 10a along the first direction (X). This ensures the support performance of the device and does not require increasing the size of the transition region 10b, thus increasing the storage space of the core region 10a.

[0137] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a memory provided in some embodiments of this application. The memory 100 can be a three-dimensional memory, such as a 3D NAND or 3D NOR memory.

[0138] The memory 100 includes a semiconductor device 101 and peripheral circuitry 102. The semiconductor device 101 can be any of the semiconductor devices described in the above embodiments, and the peripheral circuitry 102 can be a CMOS (Complementary Metal-Oxide-Semiconductor). The peripheral circuitry 102 is electrically connected to the semiconductor device 101 to transmit signals. The peripheral circuitry 102 can be used for logic operations and to control and detect the switching states of each memory cell in the semiconductor device 101 via metal interconnects, thereby enabling data storage and retrieval.

[0139] The semiconductor device 101 includes: a first stacked structure comprising alternating layers of a first insulating layer and a gate layer, the first stacked structure including a core region, a transition region, and a connection region adjacent in a first direction, the transition region being located between the core region and the connection region, the first direction intersecting the stacking direction of the stacked structure; a first gate line isolation structure extending through the core region of the first stacked structure along the stacking direction and extending along the first direction; a second gate line isolation structure extending through the transition region of the first stacked structure along the stacking direction and extending along the first direction and connected to the first gate line isolation structure; wherein the first gate line isolation structure includes a plurality of first air gaps arranged along the first direction and a first connection portion located between two adjacent first air gaps; the second gate line isolation structure includes a plurality of second air gaps arranged along the first direction and a second connection portion located between two adjacent second air gaps; the dimension of the second connection portion along the first direction is larger than the dimension of the first connection portion along the first direction.

[0140] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of a storage system provided in some embodiments of this application. The storage system 200 includes a memory 201 and a controller 202. The memory 201 can be the memory in any of the above embodiments, and the memory 201 can include any of the semiconductor devices in the above embodiments. The controller 202 is electrically connected to the memory 201 and is used to control the memory 201 to store data. The memory 201 can perform data storage operations based on the control of the controller 202.

[0141] In some implementations, the storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0142] The semiconductor device in the memory 201 includes: a first stacked structure comprising alternating layers of a first insulating layer and a gate layer, the first stacked structure including a core region, a transition region, and a connection region adjacent in a first direction, the transition region being located between the core region and the connection region, the first direction intersecting the stacking direction of the stacked structure; a first gate line isolation structure extending through the first stacked structure in the core region along the stacking direction and extending along the first direction; a second gate line isolation structure extending through the first stacked structure in the transition region along the stacking direction and extending along the first direction and connected to the first gate line isolation structure; wherein, the first gate line isolation structure includes a plurality of first air gaps arranged along the first direction and a first connection portion located between two adjacent first air gaps; the second gate line isolation structure includes a plurality of second air gaps arranged along the first direction and a second connection portion located between two adjacent second air gaps; the dimension of the second connection portion along the first direction is larger than the dimension of the first connection portion along the first direction.

[0143] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this disclosure; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The method for fabricating the semiconductor device includes: A first stacked layer is formed, the first stacked layer comprising alternating layers of a first insulating layer and a sacrificial layer, the first stacked layer comprising a core region, a transition region and a connection region adjacent in a first direction, the transition region being located between the core region and the connection region, the first direction intersecting the stacking direction of the first stacked layer; A first gate line isolation structure is formed in the core region and a second gate line isolation structure is formed in the transition region. The first gate line isolation structure includes a plurality of first air gaps arranged along the first direction and a first connecting portion located between two adjacent first air gaps. The second gate line isolation structure includes a plurality of second air gaps arranged along the first direction and a second connecting portion located between two adjacent second air gaps. The dimension of the second connecting portion along the first direction is larger than the dimension of the first connecting portion along the first direction. The step of forming a first gate line isolation structure located in the core region and a second gate line isolation structure located in the transition region includes: forming a hole structure that penetrates the first stacked layer along the stacking direction and is spaced apart along a first direction, the hole structure including a first hole structure located in the core region and a second hole structure located in the transition region, wherein the hole spacing between two adjacent second hole structures is greater than the hole spacing between two adjacent first hole structures.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The second connecting portion has a size range of 25~55nm along the first direction.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The steps of forming the first gate line isolation structure located in the core region and the second gate line isolation structure located in the transition region include: The hole structure is enlarged to form a first grid line slot located in the core region and a second grid line slot located in the transition region; A filling layer is formed in the first gate line gap and the second gate line gap to form a first gate line isolation structure and a second gate line isolation structure.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The step of forming a hole structure that penetrates the first stacked layer along the stacking direction and is spaced apart along the first direction includes: The first stacked layer is etched along the stacking direction of the first stacked layer to form a first hole structure, a second hole structure and a third hole structure located in the core region, the transition region and the connection region respectively. The first hole structure and the second hole structure are arranged in a row along the first direction, and the third hole structure is arranged in multiple rows along the first direction. The third hole structures in two adjacent rows are staggered along the first direction, and the spacing between three adjacent third hole structures is equal.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The step of enlarging the hole structure includes: The first stacked layer surrounding the first hole structure, the second hole structure, and the third hole structure is etched to form a first gate line slot, a second gate line slot, and a third gate line slot that extend along a first direction and are interconnected.

6. The method for fabricating a semiconductor device according to claim 4, characterized in that, The hole spacing between adjacent first hole structures and second hole structures is greater than the hole spacing between two adjacent first hole structures; the hole spacing between adjacent third hole structures and second hole structures is greater than the hole spacing between two adjacent first hole structures.

7. The method for fabricating a semiconductor device according to claim 3, characterized in that, The method for fabricating the semiconductor device further includes: During the formation of the hole structure, channel holes and virtual channel holes are formed that penetrate the first stacked layer along the stacking direction of the first stacked layer. The channel hole is located in the core area and between two adjacent rows of first hole structures, and the virtual channel hole is located in the transition area and between two adjacent rows of second hole structures.

8. The method for fabricating a semiconductor device according to claim 3, characterized in that, The step of forming a hole structure that penetrates the first stacked layer along the stacking direction and is spaced apart along the first direction includes: The first stacked layer is etched along the stacking direction to form a first hole structure located in the core region and a second hole structure located in the transition region. The second hole structure includes a first sub-hole structure and a second sub-hole structure arranged alternately along the first direction. Wherein, the maximum dimension of the first sub-hole structure along the first direction is equal to the maximum dimension of the first hole structure along the first direction, and the maximum dimension of the second sub-hole structure along the first direction is less than the maximum dimension of the first sub-hole structure along the first direction.

9. The method for fabricating a semiconductor device according to claim 3, characterized in that, The method for fabricating the semiconductor device further includes: A second stacked layer is formed on the first stacked layer, and a central hole structure is formed that penetrates the second stacked layer along the stacking direction and is arranged along the first direction. The central hole structure includes a first central hole structure located in the core region and a second central hole structure located in the transition region. A third stacked layer is formed on the second stacked layer, and an upper hole structure is formed that penetrates the second stacked layer along the stacking direction and is arranged along the first direction. The upper hole structure includes a first upper hole structure located in the core region and a second upper hole structure located in the transition region. Wherein, the middle hole structure is connected to the hole structure, and the upper hole structure is connected to the middle hole structure; the maximum dimension of the second hole structure along the first direction is smaller than the maximum dimension of the second middle hole structure along the first direction, and the maximum dimension of the second middle hole structure along the first direction is smaller than the maximum dimension of the second upper hole structure along the first direction.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The maximum dimensions of the first hole structure along the first direction, the maximum dimensions of the first middle hole structure along the first direction, and the maximum dimensions of the first upper hole structure along the first direction are all equal.

11. The method for fabricating a semiconductor device according to claim 5, characterized in that, The step of forming a filling layer in the first grid line gap and the second grid line gap includes: A second insulating layer and a first conductive layer are formed in the first gate line gap, the second gate line gap, and the third gate line gap.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, Prior to the step of forming a second insulating layer and a first conductive layer in the first gate line gap, the second gate line gap, and the third gate line gap, the method for fabricating the semiconductor device further includes: The sacrificial layer in the first stacked layer of the core region is replaced with a gate layer.

13. A semiconductor device, characterized in that, The semiconductor device includes: A first stacked structure includes alternating layers of a first insulating layer and a gate layer. The first stacked structure includes a core region, a transition region, and a connection region adjacent in a first direction. The transition region is located between the core region and the connection region. The first direction intersects the stacking direction of the stacked structure. A first gate isolation structure extends through the first stacked structure of the core region along the stacking direction and extends along the first direction; The second gate line isolation structure extends through the first stacked structure in the transition region along the stacking direction, and the second gate line isolation structure extends along the first direction and is connected to the first gate line isolation structure. The first grid isolation structure includes a plurality of first air gaps arranged along the first direction and a first connecting portion located between two adjacent first air gaps; the second grid isolation structure includes a plurality of second air gaps arranged along the first direction and a second connecting portion located between two adjacent second air gaps; the dimension of the second connecting portion along the first direction is larger than the dimension of the first connecting portion along the first direction.

14. The semiconductor device according to claim 13, characterized in that, The semiconductor device further includes a third gate line isolation structure, which penetrates the first stacked structure of the connection region along the stacking direction, and extends along the first direction and is connected to the second gate line isolation structure; The maximum dimension of the first gate isolation structure in the second direction is smaller than the minimum dimension of the third gate isolation structure in the second direction, and the second direction intersects the stacking direction and the first direction.

15. The semiconductor device according to claim 13, characterized in that, The top view of the second grid isolation structure includes a plurality of first arcs connected along the first direction, wherein the arc lengths of the plurality of first arcs are equal.

16. The semiconductor device according to claim 15, characterized in that, The top view of the second grid isolation structure also includes a second arc connected to the first arc. The second arc is located between two adjacent first arcs, and the arc length of the second arc is less than the arc length of the first arc.

17. The semiconductor device according to claim 13, characterized in that, The semiconductor device further includes: The second stacking structure is located on the first stacking structure; A central gate line isolation structure extends through the second stacking structure along the stacking direction and extends along the first direction. The central gate line isolation structure includes a first central gate line isolation structure located in the core region and a second central gate line isolation structure located in the transition region. The third stacking structure is located on the second stacking structure; The upper gate line isolation structure extends through the third stacking structure along the stacking direction and extends along the first direction. The upper gate line isolation structure includes a first upper gate line isolation structure located in the core region and a second upper gate line isolation structure located in the transition region. Wherein, the first gate line isolation structure, the first middle gate line isolation structure and the first upper gate line isolation structure are connected in the stacking direction, and the second gate line isolation structure, the second middle gate line isolation structure and the second upper gate line isolation structure are connected in the stacking direction; The maximum dimension of the second upper gate line isolation structure along the second direction is greater than the maximum dimension of the second middle gate line isolation structure along the second direction; the maximum dimension of the second middle gate line isolation structure along the second direction is greater than the maximum dimension of the second gate line isolation structure along the second direction.

18. The semiconductor device according to claim 17, characterized in that, The first central grid isolation structure includes a plurality of first central air gaps arranged along the first direction, and a first central connecting portion located between two adjacent first central air gaps; The second central grid isolation structure includes a plurality of second central air gaps arranged along the first direction, and a second central connecting portion located between two adjacent second central air gaps; The dimension of the second middle connecting portion along the first direction is greater than the dimension of the first middle connecting portion along the first direction.

19. The semiconductor device according to claim 18, characterized in that, The first upper grid line isolation structure includes a plurality of first upper air gaps arranged along the first direction, and a first upper connecting portion located between two adjacent first upper air gaps; The second upper grid line isolation structure includes a plurality of second upper air gaps arranged along the first direction, and a second upper connecting portion located between two adjacent second upper air gaps; The dimension of the first upper connecting portion along the first direction is greater than or equal to the dimension of the second upper connecting portion along the first direction.

20. The semiconductor device according to claim 19, characterized in that, The dimension of the second upper connecting portion along the first direction is smaller than the dimension of the second middle connecting portion along the first direction; the dimension of the second middle connecting portion along the first direction is smaller than the dimension of the second connecting portion along the first direction.

21. A memory, characterized in that, include: The semiconductor device as described in any one of claims 13-20; The peripheral circuit is electrically connected to the semiconductor device.

22. A storage system, characterized in that, include: The memory according to claim 21; A controller, electrically connected to the memory, is used to control the memory to store data.

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