IGBT device

Abstract

The invention discloses an IGBT (Insulated Gate Bipolar Translator) device, which comprises a plurality of gate trench structures and emitter trench structures, wherein the gate trench structures and the emitter trench structures are arranged in parallel and penetrate through a well region. The gate conductive material layer is connected to the gate. The emitter conductive material layer is connected with the emitter. A drift region is formed at the bottom of the well region, and a collector region is formed at the bottom of the drift region. An emitter region is formed in a surface region of a selected region of the well region. The emitter regions are located on the two sides of each gate trench structure and are self-aligned with the side faces of the gate trench structures. The emitter region is not in contact with the side surface of the emitter trench structure. The top of the emitter region is connected to the emitter through a first contact hole, and a contact injection region is formed at the bottom of the first contact hole. The width of the emitter trench is smaller than that of the gate trench, so that the width of the mesa region between the trench structures is increased, the distance from the first contact hole to the conductive channel is increased, and the influence of the contact injection region on the threshold voltage of the device is reduced. According to the invention, the uniformity of the threshold voltage of the device can be improved.

Description

Technical Field

[0001] The invention relates to a semiconductor power device, in particular to an IGBT device. Background Art

[0002] Compared with the planar gate structure, the trench gate technology eliminates the junction gate field-effect transistor (JEFT) area, has the characteristics of compact cells and small on-state voltage drop, and can achieve a higher current density. Therefore, it is widely used in the field of electric vehicle chips.

[0003] The carrier concentration of traditional IGBT chips decreases from the back collector to the front emitter, and the low carrier concentration of the front emitter limits the reduction of the on-state voltage drop. Therefore, to achieve the increase of IGBT chip current density and the reduction of power loss, it is also necessary to combine carrier storage technology to make the carrier distribution in the IGBT chip closer to the optimal state.

[0004] like Figure 1 FIG. 1 is a schematic diagram of the structure of an existing IGBT device; taking an N-type device as an example, the existing IGBT device includes:

[0005] A plurality of trench gates are arranged in parallel, wherein the trench gates include a gate trench, a gate dielectric layer 110 formed on the inner surface of the gate trench, and a gate conductive material layer 111 filled in the gate trench.

[0006] The gate conductive material layer 111 is connected to the gate formed by the front metal layer 109 .

[0007] Each trench gate passes through the P-type doped well region 105 .

[0008] An N-type doped drift region 103 is formed at the bottom of the well region 105 .

[0009] A P-type heavily doped collector region 101 is formed at the bottom of the drift region 103. A back metal layer is formed on the back side of the collector region 101 and the back metal layer forms a collector.

[0010] In the prior art, an N-type heavily doped buffer layer 102 is further included between the drift region 103 and the collector region 1011 .

[0011] N-type heavily doped emitter regions 106 are formed in the surface regions of the well regions 105 in the terrace regions on both sides of the trench gates, and the emitter regions 106 are self-aligned with the side surfaces of the corresponding trench gates.

[0012] An N-type heavily doped carrier stored (CS) layer 104 is also formed in the top region of the drift region 103 .

[0013] Each gate trench passes through the carrier storage layer 104 .

[0014] Figure 1 The IGBT device shown uses refined trench technology to increase the current density of the IGBT chip, and adds a carrier storage layer to prevent holes from entering the P base region, namely the well region 105, so as to increase the hole concentration near the emitter and reduce the on-state voltage by at least 20%.

[0015] IGBT is a bipolar device. There are electron current and hole current when it is turned on and off. Usually, B or BF2 is implanted (imp) through the CT after etching the contact hole (CT), so that the bottom of the CT is connected to the P-type well area to collect the hole current. At the same time, it can also effectively improve the anti-latch capability of the IGBT. However, as the cell pitch of the IGBT, that is, the step (pitch), becomes smaller and smaller, the pitch is the width of the spacer between the cells and the spacing between the CT and the channel. The impact of CT imp on the channel cannot be ignored. At the 1.6 micron / 1.2 micron node, CT imp will cause the threshold voltage (VTH) of the device to increase and the distribution to be discrete. And due to stress problems, the difference in VTH between the center and edge of the wafer will be more obvious, which is obviously not conducive to the promotion and application of IGBT. Summary of the invention

[0016] The technical problem to be solved by the present invention is to provide an IGBT device which can improve the uniformity of the threshold voltage of the device.

[0017] In order to solve the above technical problems, the IGBT device provided by the present invention comprises: a plurality of trench structures arranged in parallel; a part of the trench structures is used as a gate trench structure and another part of the trench structures is used as an emitter trench structure.

[0018] The gate trench structure includes a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench.

[0019] The emitter trench structure includes an emitter trench, an emitter dielectric layer formed on the inner surface of the emitter trench, and an emitter conductive material layer filled in the emitter trench.

[0020] The gate conductive material layer is connected to the gate composed of the front metal layer.

[0021] The emitter conductive material layer is connected to the emitter composed of the front metal layer.

[0022] Each of the gate trench structures and each of the emitter trench structures passes through a well region doped with the second conductivity type; a surface of the well region covered by a side surface of the gate conductive material layer is used to form a conductive channel of the first conductivity type.

[0023] A drift region doped with a first conductivity type is formed at the bottom of the well region.

[0024] A collector region heavily doped with a second conductivity type is formed at the bottom of the drift region.

[0025] An emitter region heavily doped with a first conductivity type is formed in a surface region of a selected region of the well region.

[0026] The emitter region is located at both sides of each of the gate trench structures and is self-aligned with the side surfaces of the corresponding gate trench structures; the emitter region does not contact the side surfaces of the emitter trench structures.

[0027] The top of the emitter region on both sides of each gate trench structure is connected to the emitter through a first contact hole, and a contact injection region is formed at the bottom of the first contact hole, and the contact injection region realizes the connection between the first contact hole and the well region.

[0028] The width of the emitter trench is smaller than that of the gate trench, and is used to increase the width of the mesa region between the trench structures and thereby increase the distance from the first contact hole to the conductive channel, thereby reducing the influence of the contact injection region on the threshold voltage of the device.

[0029] A further improvement is that a carrier storage layer heavily doped with the first conductivity type is also formed in the top region of the drift region.

[0030] A further improvement is that the gate trench passes through the carrier storage layer.

[0031] A further improvement is that the depth of the emitter trench is smaller than the depth of the gate trench to reduce the stress in the surface; the emitter trench and the gate trench are formed simultaneously using the same etching process, and the smaller the width of the emitter trench, the shallower the depth of the emitter trench.

[0032] A further improvement is that the bottom surface of the carrier storage layer is located below the bottom surface of the emitter trench to increase the carrier injection effect.

[0033] A further improvement is that the top of the well region on both sides of each emitter trench structure is connected to the emitter through a second contact hole; or, no contact hole is set on the top of the well region on both sides of each emitter trench structure to form a floating structure.

[0034] A further improvement is that the gate trench structure and the emitter trench structure are arranged periodically in a ratio of m:n, where m is the number of the gate trench structures in the arrangement period, and n is the number of the emitter trench structures in the arrangement period, m is greater than or equal to 1, and n is greater than or equal to 1.

[0035] A further improvement is that the values ​​of m:n include:

[0036] 1:1, 1:2, 1:3, 2:2, 3:3.

[0037] A further improvement is that a buffer layer heavily doped with the first conductivity type is further provided between the drift region and the collector region.

[0038] A further improvement is that the width of the emitter trench is 0.05 μm to 0.2 μm smaller than the width of the gate trench.

[0039] A further improvement is that the gate dielectric layer and the emitter dielectric layer are made of the same material and are formed simultaneously.

[0040] The gate conductive material layer and the emitter conductive material layer are made of the same material and are formed simultaneously.

[0041] A further improvement is that the material of the gate dielectric layer includes an oxide layer, and the material of the gate conductive material layer includes polysilicon.

[0042] A further improvement is that the step size of the parallel arranged trench structures is 1.6 microns or less than 1.2 microns.

[0043] A further improvement is that the IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the IGBT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0044] A further improvement is that when the IGBT device is an N-type device, the implanted impurities in the contact implantation region include boron or boron fluoride.

[0045] The present invention sets up an emitter trench structure arranged in parallel with the gate trench structure. By reducing the width of the emitter trench, i.e., the critical dimension (CD), the width of the platform region (mesa) between the trench structures can be increased while keeping the average step of the entire parallel trench structure unchanged. In this way, the spacing between the first contact holes arranged on both sides of the gate trench structure and the conductive channels corresponding to the side surfaces of the gate trench will increase, and the spacing between the contact injection region self-alignedly formed at the bottom of the first contact hole and the conductive channel will also increase, so that the impurities of the heavily doped contact injection region can be reduced or prevented from affecting the doping concentration and distribution of the well region at the conductive channel, thereby reducing the influence of the contact injection region on the threshold voltage of the device, and finally improving the uniformity of the threshold voltage of the device and the uniformity of the in-plane distribution.

[0046] The gate trench and emitter trench of the present invention can be formed simultaneously by the same etching process. By utilizing the etching effect, the width of the emitter trench can be reduced while the depth of the emitter trench can be reduced. The reduction in the depth of the emitter trench can reduce the stress within the wafer surface. The reduction in stress can also reduce the difference in threshold voltages between different regions of the wafer, such as the center and edge portions, thereby further improving the uniformity of the threshold voltage of the device.

[0047] In addition, the present invention can further reduce the depth of the emitter trench until the bottom surface of the emitter trench is located above the bottom surface of the carrier storage layer. This can reduce the leakage of minority carriers in the drift region into the well region relative to the increased area of ​​the carrier storage layer, thereby enhancing the carrier injection effect, thereby reducing the conduction loss of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0049] Figure 1 It is a schematic diagram of the structure of an existing IGBT device;

[0050] Figure 2 is a schematic structural diagram of an IGBT device according to a first embodiment of the present invention;

[0051] Figure 3 is a schematic structural diagram of an IGBT device according to a second embodiment of the present invention;

[0052] Figure 4 It is a schematic structural diagram of an IGBT device according to the third embodiment of the present invention. DETAILED DESCRIPTION

[0053] like Figure 2 FIG. 1 is a schematic diagram of the structure of an IGBT device according to a first embodiment of the present invention. The IGBT device according to the first embodiment of the present invention comprises:

[0054] A plurality of trench structures are arranged in parallel; a portion of the trench structures is used as a gate trench structure 201 and another portion of the trench structures is used as an emitter trench structure 202 .

[0055] The gate trench structure 201 includes a gate trench 203 (Gate TCH), a gate dielectric layer 10 a formed on the inner surface of the gate trench 203 , and a gate conductive material layer 11 a filled in the gate trench 203 .

[0056] The emitter trench structure 202 includes an emitter trench 204 (Emitter TCH), an emitter dielectric layer 10 b formed on the inner surface of the emitter trench 204 , and an emitter conductive material layer 11 b filled in the emitter trench 204 .

[0057] In the first embodiment of the present invention, the gate dielectric layer 10a and the emitter dielectric layer 10b are made of the same material and are formed simultaneously.

[0058] The gate conductive material layer 11 a and the emitter conductive material layer 11 b are made of the same material and are formed at the same time.

[0059] In some embodiments, the material of the gate dielectric layer 10 a includes an oxide layer, and the material of the gate conductive material layer 11 a includes polysilicon.

[0060] The gate conductive material layer 11 a is connected to the gate electrode composed of the front metal layer 9 . Figure 2 In FIG. 1 , the gate conductive material layer 11 a is also represented by G.

[0061] The emitter conductive material layer 11 b is connected to the emitter composed of the front metal layer 9 . Figure 2 The gate is not shown in the corresponding cross section, and the corresponding front metal layer 9 is an emitter. The emitter conductive material layer 11b is also represented by E.

[0062] Each gate trench structure 201 and each emitter trench structure 202 passes through the well region 5 doped with the second conductivity type; the surface of the well region 5 covered by the side surface of the gate conductive material layer 11 a is used to form a conductive channel of the first conductivity type.

[0063] A drift region 3 doped with the first conductivity type is formed at the bottom of the well region 5 .

[0064] A collector region 1 heavily doped with the second conductivity type is formed at the bottom of the drift region 3. A back metal layer is formed on the back of the collector region 1 and the back metal layer forms a collector electrode. Figure 2 In the diagram, the collector is also represented by Collector.

[0065] In the first embodiment of the present invention, a buffer layer 2 heavily doped with the first conductivity type is further provided between the drift region 3 and the collector region 11 .

[0066] An emitter region 6 heavily doped with the first conductivity type is formed in the surface region of a selected area of ​​the well region 5 .

[0067] The emitter regions 6 are located on both sides of each gate trench structure 201 and are self-aligned with the side surfaces of the corresponding gate trench structure 201 ; the emitter regions 6 do not contact the side surfaces of the emitter trench structure 202 .

[0068] The top of the emitter region 6 on both sides of each gate trench structure 201 is connected to the emitter through the first contact hole 7a. A contact injection region (not shown) is formed at the bottom of the first contact hole 7a to connect the first contact hole 7a and the well region 5.

[0069] The width of the emitter trench 204 is smaller than that of the gate trench 203, and is used to increase the width of the mesa region between the trench structures and thereby increase the distance from the first contact hole 7a to the conductive channel, thereby reducing the impact of the contact injection region on the threshold voltage of the device.

[0070] In the first embodiment of the present invention, a carrier storage layer 4 heavily doped with the first conductivity type is further formed in the top region of the drift region 3 .

[0071] The gate trench 203 passes through the carrier storage layer 4 .

[0072] The depth of the emitter trench 204 is smaller than that of the gate trench 203 to reduce the stress in the surface. The emitter trench 204 and the gate trench 203 are formed simultaneously by the same etching process. The smaller the width of the emitter trench 204 is, the shallower the depth of the emitter trench 204 is.

[0073] In some embodiments, the width of the emitter trench 204 is 0.05 μm to 0.2 μm smaller than the width of the gate trench 203. The width of the emitter trench 204 can be fine-tuned according to the actual size of the product pitch.

[0074] In some embodiments, the stepping of the parallel trench structures is 1.6 microns or less than 1.2 microns. The stepping of the parallel trench structures is the sum of the width of the trench structures and the width of the terraces between the trench structures.

[0075] The bottom surface of the carrier storage layer 4 is located below the bottom surface of the emitter trench 204, so that the area of ​​the carrier storage layer 4 will increase, which will enhance the blocking effect of minority carriers in the drift region 3, thereby increasing the carrier injection effect.

[0076] In the first embodiment of the present invention, the top of the well region 5 on both sides of each emitter trench structure 202 is connected to the emitter through the second contact hole 7b;

[0077] In the first embodiment of the present invention, the gate trench structure 201 and the emitter trench structure 202 are periodically arranged in a ratio of m:n, where m is the number of gate trench structures 201 in the arrangement period, and n is the number of emitter trench structures 202 in the arrangement period, m is greater than or equal to 1, and n is greater than or equal to 1. Further, in the first embodiment of the present invention, the value of m:n is 1:3.

[0078] In the first embodiment of the present invention, the IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. The implanted impurities in the contact implantation region include boron or boron fluoride.

[0079] In other embodiments, the IGBT device may be a P-type device, the first conductivity type may be a P-type device, and the second conductivity type may be an N-type device.

[0080] The first embodiment of the present invention provides an emitter trench structure 202 arranged in parallel with the gate trench structure 201. By reducing the width of the emitter trench 204, i.e., the critical dimension (CD), the width of the platform region (mesa) between the trench structures can be increased while keeping the average step of the entire parallel trench structure unchanged. In this way, the spacing between the first contact hole 7a provided on both sides of the gate trench structure 201 and the conductive channel corresponding to the side of the gate trench 203 will increase, and the spacing between the contact injection region self-alignedly formed at the bottom of the first contact hole 7a and the conductive channel will also increase. In this way, the impurities in the heavily doped contact injection region can be reduced or prevented from affecting the doping concentration and distribution of the well region 5 at the conductive channel, thereby reducing the influence of the contact injection region on the threshold voltage of the device, and finally improving the uniformity of the threshold voltage of the device and the uniformity of the in-plane distribution.

[0081] The gate groove 203 and the emitter groove 204 of the first embodiment of the present invention can be formed simultaneously by the same etching process. By utilizing the etching effect, the width of the emitter groove 204 can be reduced while the depth of the emitter groove 204 can be reduced. The reduction in the depth of the emitter groove 204 can reduce the stress within the wafer surface. The reduction in stress can also reduce the difference in threshold voltages between different regions of the wafer, such as the center and the edge, thereby further improving the uniformity of the threshold voltage of the device.

[0082] In addition, the first embodiment of the present invention can further reduce the depth of the emitter groove 204 until the bottom surface of the emitter groove 204 is located above the bottom surface of the carrier storage layer 4. In this way, relative to the increased area of ​​the carrier storage layer 4, the leakage of minority carriers in the drift region 3 into the well region 5 can be reduced, thereby enhancing the carrier injection effect, thereby reducing the conduction loss of the device.

[0083] The first embodiment of the present invention can effectively improve the uniformity of IGBT threshold voltage while retaining CT imp. Mainly, by reducing the CD of the emitter TCH, i.e., the emitter trench 204, under the same etching conditions, the depth of the emitter TCH will be shallower than the gate TCH, thus increasing the width of the mesa, i.e., the platform area, and reducing the stress in the wafer surface. Under the same conditions, the distance between the CT and the channel increases, which weakens the influence of the CT imp on the channel, and improves the uniformity of the VTH of the IGBT device and the uniformity of the in-plane distribution. Figure 2 As shown in the figure, Gate TCH and Emitter TCH are arranged periodically at a ratio of 1:3. The size of Emitter TCH is about 0.05-0.2μm smaller than that of Gate TCH, and is fine-tuned according to the product Pitch size. Under the same etching conditions, a small CD of Emitter TCH will lead to a decrease in TCH depth, which will increase the width of mesa and the alignment window of CT. At the same time, when the CS injection energy is increased, the area of ​​CS layer is increased, the carrier injection effect is enhanced, and the on-state loss of the device is reduced.

[0084] like Figure 3 , which is a schematic diagram of the structure of the IGBT device of the second embodiment of the present invention; the difference from the IGBT device of the first embodiment of the present invention is that in the IGBT device of the second embodiment of the present invention, no contact hole 7 is provided on the top of the well region 5 on both sides of each emitter trench structure 202, resulting in a floating structure.

[0085] like Figure 4 , which is a schematic diagram of the structure of an IGBT device according to a third embodiment of the present invention; the difference from the IGBT device according to the first embodiment of the present invention is that in the IGBT device according to the third embodiment of the present invention, the value of m:n is 1:1.

[0086] Other embodiments can be obtained by changing m:n. In some embodiments, the value of m:n can be 1:2, 2:2, 3:3.

[0087] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. An IGBT device, characterized in that: include: A plurality of parallel arranged groove structures; A portion of the trench structure is used as a gate trench structure and another portion of the trench structure is used as an emitter trench structure; The gate trench structure comprises a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench; The emitter trench structure comprises an emitter trench, an emitter dielectric layer formed on the inner surface of the emitter trench, and an emitter conductive material layer filled in the emitter trench; The gate conductive material layer is connected to the gate composed of the front metal layer; The emitter conductive material layer is connected to the emitter composed of the front metal layer; Each of the gate trench structures and each of the emitter trench structures passes through a well region doped with the second conductivity type; The surface of the well region covered by the side surface of the gate conductive material layer is used to form a conductive channel of the first conductive type; A drift region doped with a first conductivity type is formed at the bottom of the well region; A collector region heavily doped with a second conductivity type is formed at the bottom of the drift region; An emitter region heavily doped with a first conductivity type is formed in a surface region of a selected region of the well region; The emitter region is located at both sides of each of the gate trench structures and is self-aligned with the side surfaces of the corresponding gate trench structures; the emitter region does not contact the side surfaces of the emitter trench structures; The top of the emitter region on both sides of each gate trench structure is connected to the emitter through a first contact hole, and a contact injection region is formed at the bottom of the first contact hole, and the contact injection region realizes the connection between the first contact hole and the well region; The width of the emitter trench is smaller than that of the gate trench, and is used to increase the width of the mesa region between the trench structures and thereby increase the distance from the first contact hole to the conductive channel, thereby reducing the influence of the contact injection region on the threshold voltage of the device.

2. The IGBT device according to claim 1, characterized in that: A carrier storage layer heavily doped with the first conductivity type is also formed in the top region of the drift region.

3. The IGBT device according to claim 2, characterized in that: The gate trench passes through the carrier storage layer.

4. The IGBT device according to claim 3, characterized in that: The depth of the emitter trench is smaller than that of the gate trench to reduce the stress in the surface; the emitter trench and the gate trench are formed simultaneously by using the same etching process, and the smaller the width of the emitter trench, the shallower the depth of the emitter trench.

5. The IGBT device according to claim 4, characterized in that: The bottom surface of the carrier storage layer is located below the bottom surface of the emitter trench to increase the carrier injection effect.

6. The IGBT device according to claim 1, characterized in that: The top of the well region on both sides of each emitter trench structure is connected to the emitter through a second contact hole; or, no contact hole is set on the top of the well region on both sides of each emitter trench structure to form a floating structure.

7. The IGBT device according to claim 5, characterized in that: The gate trench structures and the emitter trench structures are periodically arranged in a ratio of m:n, where m is the number of the gate trench structures in the arrangement period, and n is the number of the emitter trench structures in the arrangement period, m is greater than or equal to 1, and n is greater than or equal to 1.

8. The IGBT device according to claim 7, characterized in that: The values ​​of m:n include: 1：1，1：2，1：3，2：2，3：3。 9. The IGBT device according to claim 1, characterized in that: A buffer layer heavily doped with the first conductivity type is further included between the drift region and the collector region.

10. The IGBT device according to claim 4, characterized in that: The width of the emitter trench is 0.05 μm to 0.2 μm smaller than the width of the gate trench.

11. The IGBT device according to claim 1, characterized in that: The gate dielectric layer and the emitter dielectric layer are made of the same material and are formed simultaneously; The gate conductive material layer and the emitter conductive material layer are made of the same material and are formed simultaneously.

12. The IGBT device according to claim 11, characterized in that: The material of the gate dielectric layer includes an oxide layer, and the material of the gate conductive material layer includes polysilicon.

13. The IGBT device according to claim 13, characterized in that: The step size of the parallel arranged trench structures is 1.6 microns or less than 1.2 microns.

14. The IGBT device according to any one of claims 1 to 13, characterized in that: The IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; Alternatively, the IGBT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

15. The IGBT device according to claim 14, characterized in that: When the IGBT device is an N-type device, the implanted impurities in the contact implantation region include boron or boron fluoride.

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