IGBT device

Abstract

The invention discloses an IGBT (Insulated Gate Bipolar Translator) device, which comprises a plurality of gate trench structures and emitter trench structures, wherein the gate trench structures and the emitter trench structures are arranged in parallel and penetrate through a well region. The gate conductive material layer is connected to the gate. The emitter conductive material layer is connected with the emitter. A drift region is formed at the bottom of the well region, and a collector region is formed at the bottom of the drift region. An emitter region is formed in a surface region of a selected region of the well region. The emitter regions are located on the two sides of each gate trench structure and are self-aligned with the side faces of the gate trench structures. The emitter region is not in contact with the side surface of the emitter trench structure. The emitter trench structure serves as a shielding structure of the gate trench structure to reduce Cgc, the depth of the emitter trench is larger than that of the gate trench, and the shielding effect on the gate trench structure is improved by increasing the depth of the emitter trench. According to the invention, Cgc can be reduced.

Description

Technical Field

[0001] The invention relates to a semiconductor power device, in particular to an IGBT device. Background Art

[0002] Compared with the planar gate structure, the trench gate technology eliminates the junction gate field-effect transistor (JEFT) area, has the characteristics of compact cells and small on-state voltage drop, and can achieve a higher current density. Therefore, it is widely used in the field of electric vehicle chips.

[0003] The carrier concentration of traditional IGBT chips decreases from the back collector to the front emitter, and the low carrier concentration of the front emitter limits the reduction of the on-state voltage drop. Therefore, to achieve the increase of IGBT chip current density and the reduction of power loss, it is also necessary to combine carrier storage technology to make the carrier distribution in the IGBT chip closer to the optimal state.

[0004] like Figure 1 , which is a schematic diagram of the structure of an existing IGBT device; taking an N-type device as an example, the existing IGBT device 201 includes:

[0005] A plurality of trench gates are arranged in parallel, wherein the trench gates include a gate trench, a gate dielectric layer 110 formed on the inner surface of the gate trench, and a gate conductive material layer 111 filled in the gate trench.

[0006] The gate conductive material layer 111 is connected to the gate formed by the front metal layer 109 .

[0007] Each trench gate passes through the P-type doped well region 105 .

[0008] An N-type doped drift region 103 is formed at the bottom of the well region 105 .

[0009] A P-type heavily doped collector region 101 is formed at the bottom of the drift region 103. A back metal layer is formed on the back side of the collector region 101 and the back metal layer forms a collector.

[0010] In the prior art, an N-type heavily doped buffer layer 102 is further included between the drift region 103 and the collector region 1011 .

[0011] N-type heavily doped emitter regions 106 are formed in the surface regions of the well regions 105 in the terrace regions on both sides of the trench gates, and the emitter regions 106 are self-aligned with the side surfaces of the corresponding trench gates.

[0012] An N-type heavily doped carrier stored (CS) layer 104 is also formed in the top region of the drift region 103 .

[0013] Each gate trench passes through the carrier storage layer 104 .

[0014] Figure 1 The IGBT device 201 shown uses refined trench technology to improve the current density of the IGBT chip, and adds a carrier storage layer to prevent holes from entering the P base region, namely the well region 105, so as to increase the hole concentration near the emitter and reduce the on-state voltage by at least 20%.

[0015] Due to the design structure, there are many parasitic capacitors inside the IGBT device 201. These equivalent capacitors can be simplified to the capacitance between the electrodes of the IGBT device 201, such as Figure 2 As shown, it is an equivalent circuit diagram of an existing IGBT device; the collector of the IGBT device 201 is represented by COLLECTOR, the emitter is represented by EMITTER, and the gate is represented by GATE, which includes three parasitic capacitors, namely:

[0016] The parasitic capacitance C between the gate and collector GC ;

[0017] The parasitic capacitance C between the gate and the emitter GE ;

[0018] The parasitic capacitance C between the collector and emitter CE .

[0019] In the half-bridge topology, when the upper IGBT, S1, is conducting, the changing voltage dv / dt is added to the CE of the lower IGBT, S2, where CE represents the collector and emitter. The current flows through the parasitic Miller capacitance Cgc, gate drive resistor Rg, and internal integrated gate drive resistor Rdrive of S2. The gate is the gate electrode, and the current can be roughly estimated using the following formula:

[0020] Icg = Ccg * (dvce / dt) (1);

[0021] This current generates a voltage difference across the gate resistor. If this voltage exceeds the gate drive threshold of the IGBT, it will cause parasitic conduction, which will cause the bridge arm to be directly connected and cause the module to short-circuit and fail. Therefore, reducing Cgc is an effective solution to reduce drive crosstalk. Summary of the invention

[0022] The technical problem to be solved by the present invention is to provide an IGBT device capable of reducing Cgc.

[0023] In order to solve the above technical problems, the IGBT device provided by the present invention comprises: a plurality of gate trench structures and emitter trench structures arranged in parallel.

[0024] The gate trench structure includes a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench.

[0025] The emitter trench structure includes an emitter trench, an emitter dielectric layer formed on the inner surface of the emitter trench, and an emitter conductive material layer filled in the emitter trench.

[0026] The gate conductive material layer is connected to the gate composed of the front metal layer.

[0027] The emitter conductive material layer is connected to the emitter composed of the front metal layer.

[0028] Each of the gate trench structures and each of the emitter trench structures passes through a well region doped with the second conductivity type.

[0029] A drift region doped with a first conductivity type is formed at the bottom of the well region.

[0030] A collector region heavily doped with a second conductivity type is formed at the bottom of the drift region.

[0031] An emitter region heavily doped with a first conductivity type is formed in a surface region of a selected region of the well region.

[0032] The emitter region is located at both sides of each of the gate trench structures and is self-aligned with the side surfaces of the corresponding gate trench structures; the emitter region does not contact the side surfaces of the emitter trench structures.

[0033] The emitter trench structure serves as a shielding structure of the gate trench structure to reduce Cgc, where Cgc is the gate collector capacitance. The depth of the emitter trench is greater than the depth of the gate trench. The shielding effect on the gate trench structure is increased by increasing the depth of the emitter trench.

[0034] A further improvement is that a carrier storage layer heavily doped with the first conductivity type is also formed in the top region of the drift region.

[0035] A further improvement is that both the gate trench and the emitter trench pass through the carrier storage layer.

[0036] A further improvement is that the width of the emitter trench is greater than the width of the gate trench, and the emitter trench and the gate trench are formed simultaneously using the same etching process; the greater the width of the emitter trench, the deeper the depth of the emitter trench.

[0037] A further improvement is that the spacing between the center positions of two adjacent gate trenches, the spacing between the center positions of two adjacent emitter trenches, or the spacing between the center positions of adjacent gate trenches and emitter trenches are equal.

[0038] The increase in the width of the emitter trenches makes the width of the mesa regions on both sides of each emitter trench smaller than the width of the mesa regions between each gate trench, thereby increasing the carrier injection effect.

[0039] A further improvement is that the top of the emitter region on both sides of each gate trench structure is connected to the emitter through a contact hole, and the contact hole at the top of the emitter region also passes through the emitter region and contacts the well region at the bottom of the emitter region.

[0040] The top of the well region on both sides of each emitter trench structure is connected to the emitter through a contact hole; or, no contact hole is provided on the top of the well region on both sides of each emitter trench structure to form a floating structure.

[0041] A further improvement is that the gate trench structure and the emitter trench structure are arranged periodically in a ratio of m:n, where m is the number of the gate trench structures in the arrangement period, and n is the number of the emitter trench structures in the arrangement period, m is greater than or equal to 1, and n is greater than or equal to 1.

[0042] A further improvement is that the values ​​of m:n include:

[0043] 1:1, 1:2, 1:3, 2:2, 3:3.

[0044] A further improvement is that a trench bottom injection region doped with a second conductive type is formed in the drift region at the bottom of the emitter trench, and the trench bottom injection region also extends laterally to the drift region on both sides of the emitter trench, and the trench bottom injection region is used to increase the shielding effect on the gate trench structure.

[0045] A further improvement is that, in the platform region between adjacent emitter trenches, the trench bottom implantation regions at the bottoms of two adjacent emitter trenches are laterally connected together.

[0046] At the bottom of each gate trench, there is a distance between adjacent trench bottom implantation regions.

[0047] A further improvement is that a buffer layer heavily doped with the first conductivity type is further provided between the drift region and the collector region 1 .

[0048] A further improvement is that the width of the emitter trench is 0.05 μm to 0.2 μm greater than the width of the gate trench.

[0049] A further improvement is that the gate dielectric layer and the emitter dielectric layer are made of the same material and are formed simultaneously.

[0050] The gate conductive material layer and the emitter conductive material layer are made of the same material and are formed simultaneously.

[0051] A further improvement is that the material of the gate dielectric layer includes an oxide layer, and the material of the gate conductive material layer includes polysilicon.

[0052] A further improvement is that the IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type;

[0053] Alternatively, the IGBT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0054] The present invention provides an emitter trench structure arranged in parallel with the gate trench structure, and sets the depth of the emitter trench to be greater than the depth of the gate trench. Thus, by increasing the depth of the emitter trench, the coupling effect between the gate conductive material layer and the drift region at the bottom can be reduced, that is, the gate trench structure can be shielded, thereby reducing Cgc, i.e., the gate collector capacitance. The deeper the depth of the emitter trench, the stronger the shielding effect, and the better the effect of reducing Cgc.

[0055] The gate trench and emitter trench of the present invention can be formed simultaneously by the same etching process. By utilizing the etching effect, the depth of the emitter trench can be increased and made deeper than the depth of the gate trench by only increasing the width of the emitter trench, i.e., the critical dimension (CD). Therefore, the present invention also has the advantages of simple process and low cost.

[0056] In addition, under the condition of keeping the pitch of each groove including the gate groove and the emitter groove and the platform area between the grooves unchanged or fine-tuning, after the width of the emitter groove increases, the width of the platform area on both sides of the emitter groove will inevitably decrease on the basis of the width of the platform area between the gate grooves. After the width of the platform area is reduced, the path for the minority carriers in the drift region to leak to the emitter region becomes narrower, which can enhance the carrier injection effect, thereby also reducing the on-state voltage drop of the device and thereby reducing the conduction loss.

[0057] In addition, when a carrier storage layer is formed, after the width of the platform region is reduced, under the same conditions, the injection dose of the carrier storage layer can be increased, which can also enhance the carrier injection effect, thereby reducing the conduction loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0059] Figure 1 It is a schematic diagram of the structure of an existing IGBT device;

[0060] Figure 2 It is the equivalent circuit diagram of the existing IGBT device;

[0061] Figure 3 is a schematic structural diagram of an IGBT device according to a first embodiment of the present invention;

[0062] Figure 4 is a schematic structural diagram of an IGBT device according to a second embodiment of the present invention;

[0063] Figure 5 is a schematic structural diagram of an IGBT device according to a third embodiment of the present invention;

[0064] Figure 6 is a schematic structural diagram of an IGBT device according to a fourth embodiment of the present invention;

[0065] Figure 7 It is a schematic structural diagram of an IGBT device according to a fifth embodiment of the present invention. DETAILED DESCRIPTION

[0066] like Figure 3 , which is a schematic structural diagram of an IGBT device according to the first embodiment of the present invention; the IGBT device according to the first embodiment of the present invention comprises: a plurality of gate trench structures 301 and emitter trench structures 302 arranged in parallel.

[0067] The gate trench structure 301 includes a gate trench 303 , a gate dielectric layer 10 a formed on the inner surface of the gate trench 303 (Gate TCH), and a gate conductive material layer 11 a filled in the gate trench 303 .

[0068] The emitter trench structure 302 includes an emitter trench 304 , an emitter dielectric layer 10 b formed on the inner surface of the emitter trench 304 (Emitter TCH), and an emitter conductive material layer 11 b filled in the emitter trench 304 .

[0069] The gate conductive material layer 11 a is connected to the gate electrode composed of the front metal layer 9 . Figure 3 In FIG. 1 , the gate conductive material layer 11 a is also represented by G.

[0070] The emitter conductive material layer 11 b is connected to the emitter composed of the front metal layer 9 . Figure 3 The gate is not shown in the corresponding cross section, and the corresponding front metal layer 9 is an emitter. The emitter conductive material layer 11b is also represented by E.

[0071] Each gate trench structure 301 and each emitter trench structure 302 passes through the well region 5 doped with the second conductivity type.

[0072] A drift region 3 doped with the first conductivity type is formed at the bottom of the well region 5 .

[0073] A collector region 1 heavily doped with the second conductivity type is formed at the bottom of the drift region 3. A back metal layer is formed on the back of the collector region 1 and the back metal layer forms a collector electrode. Figure 3 In the diagram, the collector is also represented by Collector.

[0074] In the first embodiment of the present invention, a buffer layer 2 heavily doped with the first conductivity type is further provided between the drift region 3 and the collector region 11 .

[0075] An emitter region 6 heavily doped with the first conductivity type is formed in the surface region of the selected region of the well region 5 .

[0076] The emitter regions 6 are located on both sides of each gate trench structure 301 and are self-aligned with the side surfaces of the corresponding gate trench structure 301 ; the emitter regions 6 do not contact the side surfaces of the emitter trench structure 302 .

[0077] The emitter trench structure 302 serves as a shielding structure for the gate trench structure 301 to reduce Cgc, where Cgc is the gate collector capacitance. The depth of the emitter trench 304 is greater than that of the gate trench 303 . The shielding effect on the gate trench structure 301 is increased by increasing the depth of the emitter trench 304 .

[0078] In the first embodiment of the present invention, a carrier storage layer 4 heavily doped with the first conductivity type is further formed in the top region of the drift region 3 .

[0079] Both the gate trench 303 and the emitter trench 304 pass through the carrier storage layer 4 .

[0080] The width of the emitter trench 304 is greater than that of the gate trench 303 , and the emitter trench 304 and the gate trench 303 are formed simultaneously using the same etching process; using the etching effect that the greater the trench width, the greater the etching depth, it can be seen that the greater the width of the emitter trench 304, the deeper the emitter trench 304.

[0081] In the first embodiment of the present invention, the gate dielectric layer 10a and the emitter dielectric layer 10b are made of the same material and are formed simultaneously.

[0082] The gate conductive material layer 11 a and the emitter conductive material layer 11 b are made of the same material and are formed at the same time.

[0083] In some embodiments, the width of the emitter trench 304 is 0.05 μm to 0.2 μm greater than the width of the gate trench 303 .

[0084] The material of the gate dielectric layer 10 a includes an oxide layer, and the material of the gate conductive material layer 11 a includes polysilicon.

[0085] In the first embodiment of the present invention, the spacing between the center positions of two adjacent gate trenches 303, the spacing between the center positions of two adjacent emitter trenches 304, or the spacing between the center positions of adjacent gate trenches 303 and emitter trenches 304 are equal. The spacing between the center positions of two adjacent gate trenches 303 is the sum of the width of a gate trench 303 and the width of the platform area between the gate trenches 303, corresponding to a step (pitch), and the step is the sum of the spacing between the trenches. The introduction of the emitter trench 304 does not change the step size, that is, the sum of the width of the emitter trench 304 and the adjacent platform area is equal to the sum of the width of the gate trench 303 and the width of the platform area between the gate trenches 303. In other implementations, it is also possible to fine-tune the step of the corresponding area of ​​the emitter trench 304 after the emitter trench 304 is introduced.

[0086] The width of the emitter trench 304 increases so that the width of the platform region on both sides of each emitter trench 304 is smaller than the width of the platform region between each gate trench 303. The width of the platform region decreases, and the number of minority carriers in the drift region 3 leaking into the well region 5 formed in the platform region decreases, so the number of minority carriers in the drift region 3 increases, thereby increasing the carrier injection effect. In addition, in the first embodiment of the present invention, the width of the platform region decreases, and under the same conditions, the injection dose of the carrier storage layer 4 can also be increased, which can also enhance the carrier injection effect, thereby reducing the on-state loss.

[0087] In the first embodiment of the present invention, the top of the emitter region 6 on both sides of each gate trench structure 301 is connected to the emitter through a contact hole 7 passing through the interlayer film 8. The contact hole 7 at the top of the emitter region 6 also passes through the emitter region 6 and contacts the well region 5 at the bottom of the emitter region 6.

[0088] The top of the well region 5 on both sides of each emitter trench structure 302 is connected to the emitter through a contact hole 7 .

[0089] In the first embodiment of the present invention, the gate trench structure 301 and the emitter trench structure 302 are periodically arranged in a ratio of m:n, where m is the number of gate trench structures 301 in the arrangement period, and n is the number of emitter trench structures 302 in the arrangement period, m is greater than or equal to 1, and n is greater than or equal to 1. Further in the first embodiment of the present invention, the value of m:n is 2:3.

[0090] In the first embodiment of the present invention, the IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the IGBT device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0091] The first embodiment of the present invention provides an emitter trench structure 302 arranged in parallel with the gate trench structure 301, and the depth of the emitter trench 304 is set to be greater than the depth of the gate trench 303. In this way, by increasing the depth of the emitter trench 304, the coupling effect between the gate conductive material layer 11a and the drift region 3 at the bottom can be reduced, that is, the gate trench structure 301 can be shielded, thereby reducing Cgc, that is, the gate collector capacitance. The deeper the depth of the emitter trench 304, the stronger the shielding effect, and the better the effect of reducing Cgc.

[0092] The gate trench 303 and the emitter trench 304 of the first embodiment of the present invention can be formed simultaneously by the same etching process. By utilizing the etching effect, it is only necessary to increase the width of the emitter trench 304, i.e., the critical dimension (CD), to increase the depth of the emitter trench 304 and make the depth of the emitter trench 304 deeper than the depth of the gate trench 303. Therefore, the first embodiment of the present invention also has the advantages of simple process and low cost.

[0093] In addition, under the condition of keeping the pitch of each groove including the gate groove 303 and the emitter groove 304 and the platform area between the grooves unchanged or fine-tuning, after the width of the emitter groove 304 increases, the width of the platform area on both sides of the emitter groove 304 will inevitably decrease on the basis of the width of the platform area between the gate grooves 303. After the width of the platform area is reduced, the path for the minority carriers in the drift region 3 to leak to the emitter region 6 becomes narrower, which can enhance the carrier injection effect, thereby also reducing the on-state voltage drop of the device and thereby reducing the conduction loss.

[0094] In addition, when the carrier storage layer 4 is formed, after the width of the platform region is reduced, under the same conditions, the injection dose of the carrier storage layer 4 can be increased, which can also enhance the carrier injection effect, thereby reducing the on-state loss.

[0095] In the first embodiment of the present invention, by increasing the CD of the emitter TCH, i.e., the emitter trench 304, under the same etching conditions, the depth of the emitter TCH will be deeper than the gate TCH, i.e., the gate trench 303, thereby strengthening the shielding effect of the emitter TCH on the gate TCH, thereby reducing Cgc. At the same time, after the CD of the emitter TCH is increased, the width of the mesa, i.e., the platform area, will be reduced, and the carrier injection effect will be stronger under the same conditions, thereby reducing the on-state voltage drop of the IGBT.

[0096] like Figure 4 , which is a schematic diagram of the structure of the IGBT device of the second embodiment of the present invention; the difference from the IGBT device of the first embodiment of the present invention is that in the IGBT device of the second embodiment of the present invention, the top of the well region 5 on both sides of each emitter trench structure 302 is not provided with a contact hole 7, so that a floating structure is formed. Figure 4 The contact hole 7 is not provided in the area corresponding to the dotted frame 305.

[0097] like Figure 5 , which is a schematic diagram of the structure of an IGBT device according to a third embodiment of the present invention; the difference from the IGBT device according to the first embodiment of the present invention is that in the IGBT device according to the third embodiment of the present invention, the value of m:n is 1:1.

[0098] like Figure 6 , which is a schematic diagram of the structure of an IGBT device according to a fourth embodiment of the present invention; the difference from the IGBT device according to the first embodiment of the present invention is that in the IGBT device according to the fourth embodiment of the present invention, the value of m:n is 1:3.

[0099] Other embodiments can be obtained by changing m:n. In some embodiments, the value of m:n can be 1:2, 2:2, 3:3.

[0100] like Figure 7 , which is a schematic diagram of the structure of an IGBT device according to a fifth embodiment of the present invention; the difference from the IGBT device according to the first embodiment of the present invention is that in the IGBT device according to the fifth embodiment of the present invention:

[0101] A trench bottom injection region 306 doped with the second conductive type is formed in the drift region 3 at the bottom of the emitter trench 304 . The trench bottom injection region 306 also extends laterally to the drift region 3 on both sides of the emitter trench 304 . The trench bottom injection region 306 is used to increase the shielding effect on the gate trench structure 301 .

[0102] In the terrace region between adjacent emitter trenches 304 , trench bottom implantation regions 306 at the bottoms of two adjacent emitter trenches 304 are laterally connected together.

[0103] At the bottom of each gate trench 303 , there is a gap between adjacent trench bottom implantation regions 306 .

[0104] Since the IGBT device in the fifth embodiment of the present invention is an N-type device, the second conductivity type is a P-type, Figure 7 In FIG. 3 , the trench bottom implantation region 306 is also represented by P-type implantation.

[0105] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. An IGBT device, characterized in that: include: A plurality of gate trench structures and emitter trench structures arranged in parallel; The gate trench structure comprises a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench; The emitter trench structure comprises an emitter trench, an emitter dielectric layer formed on the inner surface of the emitter trench, and an emitter conductive material layer filled in the emitter trench; The gate conductive material layer is connected to the gate composed of the front metal layer; The emitter conductive material layer is connected to the emitter composed of the front metal layer; Each of the gate trench structures and each of the emitter trench structures passes through a well region doped with the second conductivity type; A drift region doped with a first conductivity type is formed at the bottom of the well region; A collector region heavily doped with a second conductivity type is formed at the bottom of the drift region; An emitter region heavily doped with a first conductivity type is formed in a surface region of a selected region of the well region; The emitter region is located at both sides of each of the gate trench structures and is self-aligned with the side surfaces of the corresponding gate trench structures; the emitter region does not contact the side surfaces of the emitter trench structures; The emitter trench structure serves as a shielding structure of the gate trench structure to reduce Cgc, where Cgc is the gate collector capacitance. The depth of the emitter trench is greater than the depth of the gate trench. The shielding effect on the gate trench structure is increased by increasing the depth of the emitter trench.

2. The IGBT device according to claim 1, characterized in that: A carrier storage layer heavily doped with the first conductivity type is also formed in the top region of the drift region.

3. The IGBT device according to claim 2, characterized in that: The gate trench and the emitter trench both pass through the carrier storage layer.

4. The IGBT device according to claim 3, characterized in that: The width of the emitter trench is greater than the width of the gate trench, and the emitter trench and the gate trench are formed simultaneously by using the same etching process; the greater the width of the emitter trench, the deeper the depth of the emitter trench.

5. The IGBT device according to claim 4, characterized in that: The spacing between the center positions of two adjacent gate trenches, the spacing between the center positions of two adjacent emitter trenches, or the spacing between the center positions of adjacent gate trenches and emitter trenches are equal; The increase in the width of the emitter trenches makes the width of the platform regions on both sides of each emitter trench smaller than the width of the platform regions between each gate trench, thereby increasing the carrier injection effect.

6. The IGBT device according to claim 1, characterized in that: The top of the emitter region on both sides of each gate trench structure is connected to the emitter through a contact hole, and the contact hole at the top of the emitter region also passes through the emitter region and contacts the well region at the bottom of the emitter region; The top of the well region on both sides of each emitter trench structure is connected to the emitter through a contact hole; or, no contact hole is provided on the top of the well region on both sides of each emitter trench structure to form a floating structure.

7. The IGBT device according to claim 5, characterized in that: The gate trench structures and the emitter trench structures are periodically arranged in a ratio of m:n, where m is the number of the gate trench structures in the arrangement period, and n is the number of the emitter trench structures in the arrangement period, m is greater than or equal to 1, and n is greater than or equal to 1.

8. The IGBT device according to claim 7, characterized in that: The values ​​of m:n include: 1：1，1：2，1：3，2：2，3：3。 9. The IGBT device according to claim 3, characterized in that: A trench bottom injection region doped with a second conductive type is formed in the drift region at the bottom of the emitter trench. The trench bottom injection region also extends laterally to the drift regions on both sides of the emitter trench. The trench bottom injection region is used to increase the shielding effect on the gate trench structure.

10. The IGBT device according to claim 9, characterized in that: In the platform area between adjacent emitter trenches, the trench bottom injection areas at the bottoms of two adjacent emitter trenches are laterally connected together; At the bottom of each gate trench, there is a distance between adjacent trench bottom implantation regions.

11. The IGBT device according to claim 1, characterized in that: A buffer layer heavily doped with the first conductivity type is further included between the drift region and the collector region.

12. The IGBT device according to claim 4, characterized in that: The width of the emitter trench is 0.05 μm to 0.2 μm greater than the width of the gate trench.

13. The IGBT device according to claim 1, characterized in that: The gate dielectric layer and the emitter dielectric layer are made of the same material and are formed simultaneously; The gate conductive material layer and the emitter conductive material layer are made of the same material and are formed simultaneously.

14. The IGBT device according to claim 13, characterized in that: The material of the gate dielectric layer includes an oxide layer, and the material of the gate conductive material layer includes polysilicon.

15. The IGBT device according to any one of claims 1 to 14, characterized in that: The IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; Alternatively, the IGBT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

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