Semiconductor device with silicon carbide portion and glass structure and method of manufacture

Abstract

The invention relates to a semiconductor device having a silicon carbide portion and a glass structure and a method of manufacture. A semiconductor device (500) includes a single crystal silicon carbide portion (100) having a first surface (101), an opposing second surface (102), and a third surface (103) extending from the first surface (101) in a direction of the second surface (102). Along the third surface (103), hydrogen atoms and / or atoms of one or more non-metallic elements other than silicon and having an atomic number greater than six saturate dangling bonds of the silicon carbide portion (100), and / or the passivation coating (210) is in direct contact with the third surface (103). The semiconductor device (500) further includes a glass structure (250) and an interface layer structure (220) between the third surface (103) and the glass structure (250).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having a silicon carbide portion and a glass structure. More particularly, the present disclosure relates to a high voltage semiconductor device having an edge termination structure with a glass structure for high blocking voltage capability. Background Art

[0002] In a vertical power semiconductor device, in the conduction mode, the load current flows between the front and back sides of the semiconductor die in the vertical direction. In the blocking mode, the vertical power semiconductor device is subjected to a large terminal voltage. For example, a power semiconductor diode is forward biased in the conduction mode and reverse biased in the blocking mode, and a power semiconductor switch is in the conduction mode when turned on and in the blocking mode when turned off. The maximum terminal voltage that a power semiconductor device can withstand is the blocking voltage. The blocking voltage depends on the material properties and design of the power semiconductor device. Since the lateral surface of the semiconductor die is relatively rough and has low crystal quality, the rear side potential is usually brought to the front side along the edge of the semiconductor die to keep the lateral surface of the semiconductor die free of an electric field, and the lateral field termination structure in the termination area shapes the electric field to avoid field crowding and ensure a high blocking voltage.

[0003] There is a continuing need for area efficient power semiconductor devices with high blocking voltage capabilities. Summary of the invention

[0004] Instead of providing lateral field termination structures that consume area, embodiments of the present disclosure use vertical field termination structures.

[0005] According to the related disclosure, the semiconductor device includes a single crystal silicon carbide portion, which includes a first surface, an opposite second surface, and a third surface extending from the first surface in the direction of the second surface. Along the third surface, hydrogen atoms and / or atoms of one or more non-metallic elements other than silicon and having an atomic number greater than six saturate the dangling bonds of the silicon carbide portion, and / or the passivation coating is in direct contact with the third surface. The semiconductor device also includes a glass structure and an interface layer structure between the third surface and the glass structure.

[0006] The combination of the glass structure with passivated and / or saturated dangling bonds along the third surface voltage promotes a more vertical field termination with the blocking capability tuned to that in the central device region of the semiconductor device. The vertical field termination structure can be designed to occupy less horizontal chip area than comparable conventional lateral field termination, thereby saving material costs.

[0007] The present disclosure also relates to a method for manufacturing a semiconductor device, wherein the method includes: forming a separation trench in a main surface of a single-crystal silicon carbide layer, wherein the separation trench surrounds a core portion of the silicon carbide layer; processing at least a first sidewall of the separation trench of the silicon carbide layer during a conditioning process, wherein dangling bonds of the silicon carbide layer are passivated; forming an interface layer on the first sidewall of the separation trench; forming a glass-filling structure in the separation trench; and separating the silicon carbide layer along a vertical separation line parallel to the separation trench.

[0008] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are provided for further understanding of the embodiments and form an integral part of the present description. The accompanying drawings illustrate embodiments of semiconductor devices and methods of manufacture and together with the description explain the underlying principles of the embodiments. Further embodiments are described in the following detailed description and in the claims. The features of the various embodiments may be combined with each other.

[0010] Figure 1A is a schematic vertical cross-sectional view of a portion of a semiconductor device having a field termination structure based on passivated dangling bonds along a third surface at a chip edge, a glass structure, and an interface layer structure between the third surface and the glass structure according to an embodiment.

[0011] Figure 1B is a schematic vertical cross-sectional view of a portion of a semiconductor device having a field termination structure based on saturated dangling bonds along a third surface at a chip edge, a glass structure, and an interface layer structure between the third surface and the glass structure according to an embodiment.

[0012] Figure 2A is a schematic vertical cross-sectional view of a portion of a semiconductor device having a field termination structure based on passivated dangling bonds along a third surface in a termination trench, a glass structure in the termination trench, and an interface layer structure between the third surface and the glass structure according to an embodiment.

[0013] Figure 2B is a schematic vertical cross-sectional view of a portion of a semiconductor device having a field termination structure based on saturated dangling bonds along a third surface in a termination trench, a glass structure in the termination trench, and an interface layer structure between the glass structure and the third surface according to an embodiment.

[0014] FIG. 3A to FIG. 3D is a schematic vertical cross-sectional view of a portion of a semiconductor device having an edge structure according to further embodiments.

[0015] Figures 4 to 6 is a schematic vertical cross-sectional view of a portion of a semiconductor device having an edge structure including an interface layer structure terminating at a first metal structure according to an embodiment.

[0016] Figures 7 to 9 is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment, the semiconductor device having an edge structure including an interface layer structure having a vertical extent smaller than that of a first metal structure at a front side.

[0017] Figures 10 to 12 is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment, the semiconductor device having an edge structure including an interface layer structure partially covering a first metal structure at a front side.

[0018] Figure 13 to Figure 14 is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment, the semiconductor device having an edge structure including an interface layer structure partially covered by a first metal structure at a front side.

[0019] Fig.15 is a schematic vertical cross-sectional view of a portion of a semiconductor device having a body / anode region laterally separated from an edge structure in accordance with an embodiment.

[0020] Figure 16 to Figure 17 is a schematic vertical cross-sectional view of a portion of a semiconductor device having a field relaxation structure located between a bulk / anode region and an edge structure according to an embodiment.

[0021] Fig.18 is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment, the semiconductor device having a surface layer located between a first surface and a field relaxation structure.

[0022] Figures 19 to 20 is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment, the semiconductor device having a field relaxation structure including a weakly doped supplementary structure.

[0023] FIG. 21A to FIG. 21E is a schematic vertical cross-sectional view of a portion of a silicon carbide layer for illustrating a method of manufacturing a semiconductor device having an edge structure for a vertical field termination according to an embodiment, the method including slicing along separation lines in separation trenches.

[0024] Fig. 22is a schematic vertical cross-sectional view of a portion of a silicon carbide layer for illustrating a method of manufacturing a semiconductor device having an edge structure for a vertical field termination according to an embodiment, the method including slicing along a separation line between separation trenches.

[0025] Fig.23 is a schematic plan view of a portion of a silicon carbide layer for illustrating a method of manufacturing a semiconductor device having an edge structure for vertical field termination according to an embodiment, the method including slicing along separation lines in separation trenches.

[0026] Fig.24 is a schematic plan view of a portion of a silicon carbide layer for illustrating a method of manufacturing a semiconductor device having an edge structure for vertical field termination according to an embodiment, the method including slicing along separation lines between separation trenches.

[0027] FIG. 25A to FIG. 25F is a schematic vertical cross-sectional view of a portion of a silicon carbide layer for illustrating a method of manufacturing a semiconductor device according to an embodiment, the method including forming a separation trench after forming a gate electrode structure and a first metal structure on a front side.

[0028] FIG. 26A to FIG. 26F is a schematic vertical cross-sectional view of a portion of a silicon carbide layer for illustrating a method of manufacturing a semiconductor device according to an embodiment, the method including forming a separation trench after forming a gate electrode structure and before forming a first metal structure on a front side.

[0029] FIG. 27A to FIG. 27C is a schematic vertical cross-sectional view of a portion of a silicon carbide layer for illustrating a method of manufacturing a semiconductor device according to an embodiment, the method including forming a first metal structure covering a portion of an edge structure at a front side.

[0030] FIG. 28A to FIG. 28C is a schematic vertical cross-sectional view of a portion of a silicon carbide layer for illustrating a method of manufacturing a semiconductor device according to an embodiment, the method including forming an edge structure extending through the silicon carbide layer.

[0031] FIG. 29A to FIG. 29C is a schematic vertical cross-sectional view of a portion of a silicon carbide layer for illustrating a method of manufacturing a semiconductor device according to an embodiment, the method including forming a separation trench before forming a gate electrode structure in a gate trench. DETAILED DESCRIPTION

[0032] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, and in which certain embodiments of semiconductor devices and methods of manufacture are illustrated as illustrations. Structural or logical changes may be made to the illustrated embodiments without departing from the scope of the present disclosure. For example, features shown or described for one embodiment may be used on other embodiments or used in combination with other embodiments, resulting in another embodiment. The present disclosure is intended to include such modifications and variations. The embodiments are described in a manner that should not be interpreted as limiting the scope of the appended claims. The drawings are not drawn to scale and are for illustration purposes only. Unless otherwise indicated, corresponding elements are designated by the same reference numerals in the various drawings.

[0033] The terms "having", "containing", "including", "comprising", etc. are open ended and the terms indicate the presence of certain structures, elements, or features but do not exclude the presence of additional elements or features. The articles "a", "an", and "the" include both the plural and the singular unless the context clearly indicates otherwise.

[0034] The term “power semiconductor device” refers to a semiconductor device having a voltage blocking capability of at least 30 V (e.g., 48 V, 100 V, 600 V, 1.6 kV, 3.3 kV, or greater) and having a nominal on-state current or forward current of at least 200 mA (e.g., 1 A, 10 A, or greater).

[0035] A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a voltage controlled device and includes all types of IGFETs (Insulated Gate Field Effect Transistors) having a gate electrode based on doped semiconductor material and / or metal and having a gate dielectric made of oxide and / or dielectric material other than oxide.

[0036] An ohmic contact describes a non-rectifying electrical junction between two conductors (e.g., between a semiconductor material and a metal). An ohmic contact has a linear or nearly linear current-voltage (IV) curve in the first and third quadrants of the IV diagram as in Ohm's law.

[0037] Ranges given for physical dimensions include the boundary values. For example, the range of parameter y from a to b is read as a≤y≤b. The same applies to ranges with a boundary value (e.g., "at most" and "at least").

[0038] The term “on” should not be interpreted as meaning only “directly on.” On the contrary, if an element is disposed “on another element” (for example, a layer is “on another layer” or “on a substrate”), another component (for example, another layer) may be disposed between the two elements (for example, if a layer is “on a substrate,” another layer may be disposed between the layer and the substrate).

[0039] Two adjacent doped regions in a semiconductor layer may form a semiconductor junction. Two adjacent doped regions of the same conductivity type and having different dopant concentrations form a unipolar junction, for example, an n / n+ or p / p+ junction along the boundary surface between the two doped regions. At a unipolar junction, the dopant concentration profile orthogonal to the unipolar junction may show a step or turning point, at which the dopant concentration profile changes from concave to convex and vice versa. Two adjacent doped regions of complementary conductivity form a pn junction.

[0040] The accompanying drawings illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means a doping concentration that is lower than the doping concentration of an "n" doping region, while an "n+" doping region has a higher doping concentration than an "n" doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions may have the same or different absolute doping concentrations.

[0041] The present disclosure relates to a semiconductor device that may include a single-crystal silicon carbide portion having a first surface, an opposite second surface, and a third surface extending from the first surface in a direction of the second surface.

[0042] The first surface and the second surface may be parallel or at least approximately parallel to each other, wherein planes coplanar with the first surface and the second surface may intersect each other at an angle of no more than 4 degrees. The first surface may be planar or ribbed, and the groove may extend from the first surface into the silicon carbide portion. The plane of the first surface defines a horizontal (lateral) direction. A surface orthogonal to the first surface defines a vertical direction orthogonal to the horizontal direction.

[0043] The third surface may be tilted with respect to the first plane at an angle in the range of 70 to 110 degrees (e.g., in the range of 80 to 100 degrees). The third surface may connect the first surface and the second surface. Alternatively, the third surface ends at a distance from the second surface.

[0044] Along the third surface, hydrogen atoms and / or atoms of one or more non-metallic elements other than silicon and having an atomic number greater than six saturate dangling bonds of the silicon carbide portion, and / or the passivation coating is in direct contact with the third surface.

[0045] The dangling bonds along the third surface may include silicon-face dangling bonds and carbon-face dangling bonds. The auxiliary atoms of one or more non-metallic elements other than silicon and carbon may saturate the dangling bonds to a large extent. The non-metallic elements may include at least one of nitrogen, oxygen, phosphorus, sulfur, selenium, halogens (Group 17 elements) or rare gases (Group 18 elements). Along the third surface, metal atoms may not exist or almost completely do not exist. As an example, by Auger electron spectroscopy (AES), the presence of auxiliary atoms and the absence of metal atoms can be detected. For example, along the third surface, the density of metal atoms may be at most 10% of the density of non-metallic atoms other than carbon and silicon, for example, at most 1% or at most 0.1%.

[0046] The passivation coating may be a layer or layer stack of uniform thickness, which may be formed of at least one, two, ten or ten dense continuous atomic layers. The passivation coating may passivate dangling bonds and / or metal atoms so that when a blocking voltage less than the nominal maximum blocking voltage is applied between the front side and the back side of the semiconductor device, no voltage breakdown is formed along the third surface.

[0047] In both alternatives, dangling bonds and / or metal atoms are at least largely deactivated. For example, the interface state density (Dit) along the third surface is at most 5E121 / cm 2 eV, up to 2E121 / cm 2 eV or up to 1E121 / cm 2 eV.

[0048] The semiconductor device may further include a glass structure and an interface layer structure between the third surface and the glass structure.

[0049] The glass structure may provide sufficient dielectric strength to avoid voltage breakdown between the front side and the back side along a path parallel to the third surface outside the silicon carbide portion. The interface layer structure may allow processing of the glass structure to be decoupled from passivation / saturation of dangling bonds and / or may improve adhesion between the glass structure and the silicon carbide portion. The interface layer structure may provide sufficient dielectric strength to avoid voltage breakdown between the front side and the back side through the interface layer structure.

[0050] The interface layer structure, the glass structure and the passivation coating (if applicable) can form an edge structure, which provides an area-efficient field termination structure to block the electric field between the first conductive structure on the front side of the silicon carbide portion and the second conductive structure on the back side of the silicon carbide structure. In a blocking mode of the semiconductor device, the back side potential can be confined to the back side of the silicon carbide portion. The blocking mode can be a reverse bias mode of a power semiconductor diode or an off state of a power semiconductor switch. The edge structure can be combined with a lateral termination structure with a reduced width. Alternatively, the lateral termination structure can be omitted entirely.

[0051] According to an embodiment, the atoms of the non-metal element may include at least one of nitrogen atoms, oxygen atoms, or phosphorus atoms.

[0052] Nitrogen, oxygen and phosphorus atoms can be applied through proven and tested processes using recognized techniques.

[0053] According to an embodiment, the passivation coating may include a layer structure including at least one of an oxide layer, a nitride layer, an oxynitride layer, or a layer including carbon.

[0054] The oxide layer may be an oxide-based layer, such as a silicon oxide layer (Si x O y , such as SiO2) or silicon carbide layer (Si x C y O z The nitride layer may be a nitride-based layer, such as a silicon nitride layer (Si x N y , such as Si3N4) or silicon carbonitride layer (Si x C y N z The oxynitride layer may be a silicon oxynitride layer (Si x O y N z ) or silicon carbon nitride oxide layer (SiC x O y N z ).

[0055] For example, the passivation coating may be or may include a layer comprising oxygen formed by O2 flash, a silicon oxide layer formed by atomic layer deposition (ALD), or an annealed silicon oxide layer obtained in a deposition process using tetraethyl orthosilicate (TEOS) as a precursor. For example, the passivation coating is a layer stack comprising one or more deposited silicon dioxide layers comprising SiO2 and one or more deposited silicon nitride layers comprising Si3N4.

[0056] According to an embodiment, the third surface may include inner sidewalls of a trench structure laterally surrounding a central portion of the silicon carbide portion.

[0057] The trench structure may laterally separate the central portion from a peripheral portion between the trench structure and a lateral surface of the silicon carbide portion, wherein the lateral surface extends from an edge of the first surface to an edge of the second surface.

[0058] The groove structure may have a uniform vertical extent ("depth"), a uniform lateral width and / or a uniform lateral distance relative to the lateral edges of the silicon carbide portion. The groove structure may form a continuous frame around the central portion. The frame may be rectangular with four orthogonal straight sections. The following may be possible: the frame has rounded or flattened / sheared corners between the straight sections.

[0059] Atoms of hydrogen and / or one or more non-metallic elements other than silicon and having an atomic number greater than six saturate dangling bonds of the silicon carbide portion along the inner sidewall of the groove structure toward the central portion. In addition, atoms of hydrogen and / or one or more non-metallic elements other than silicon and having an atomic number greater than six may saturate dangling bonds of the silicon carbide portion along the outer sidewall of the groove structure toward the peripheral portion and / or along the bottom of the groove structure toward the second surface and connecting the inner sidewall and the outer sidewall. The interface layer structure may cover the inner sidewall, the outer sidewall and the bottom in a uniform thickness. The glass structure fills the space between the various sections of the interface layer structure.

[0060] Alternatively or in addition, the passivation coating may be in direct contact with the entire inner sidewall of the groove structure towards the central portion. In addition, the passivation coating may be in direct contact with the outer sidewall of the groove structure and / or in direct contact with the bottom of the groove structure. The interface layer structure may cover all sections of the passivation coating according to a uniform thickness. The glass structure fills the space between the various sections of the interface layer structure.

[0061] According to another embodiment, the third surface may form at least a portion of a lateral surface connecting an edge of the first surface and an edge of the second surface.

[0062] The lateral surface may include: a third surface extending from the first surface toward the second surface; a fourth surface extending from the second surface toward the first surface; and a fifth surface connecting the edges of the third surface and the fourth surface away from the first surface and the second surface. The combined third, fourth and fifth surfaces may form a stepped surface. The fourth surface may extend in a vertical direction and / or parallel to the third surface. The third surface may be oriented in a vertical direction or deflected by no more than 20 degrees relative to the vertical direction. The fifth surface may extend in a horizontal direction or deflected by no more than 20 degrees relative to the horizontal direction. Alternatively, the lateral surface may include more than one step extending outward from the silicon carbide portion at a distance from the first surface and at a distance from the second surface.

[0063] According to an embodiment, the third surface connects an edge of the first surface and an edge of the second surface.

[0064] The third surface forms a lateral surface connecting an edge of the first surface and an edge of the second surface. The third surface may be straight and extend in a vertical direction from an edge of the first surface to an edge of the second surface.

[0065] Auxiliary atoms of hydrogen and / or one or more nonmetallic elements other than silicon and having an atomic number greater than six saturate dangling bonds of the silicon carbide portion along the third surface (that is, along the entire lateral surface).The interface layer structure may be in direct contact with the third surface.

[0066] Alternatively or additionally, the passivation coating is formed in direct contact with the third surface, that is to say, along the entire lateral surface.The interface layer structure covers the passivation coating with a uniform thickness.

[0067] According to an embodiment, the silicon carbide portion may include a heavily doped base portion of the first conductivity type and a more lightly doped main layer of the first conductivity type between the first surface and the base portion, and wherein the third surface laterally exposes the main layer and the base portion.

[0068] The primary layer and the substrate portion may form a monopolar junction, wherein the interface between the primary layer and the substrate portion is at least approximately horizontal. Additional horizontal layers or horizontal layered structures may be formed between the first surface and the primary layer, between the primary layer and the substrate portion, and / or between the substrate portion and the second surface. The third surface may expose the entire lateral surface of the primary layer, and may expose a portion of the lateral surface of the substrate portion or the entire lateral surface of the substrate portion.

[0069] According to an embodiment, the interface layer structure may include a surface portion on the first surface.

[0070] In addition to the groove portion formed on the third surface, the interface layer structure may also include a surface portion. The groove portion and the surface portion may be connected to each other to form a continuous integral structure. The groove portion and the surface portion may be layered portions of the same layer thickness. The surface portion may directly cover the edge area of ​​the first surface along the edge between the first surface and the third surface or transition.

[0071] According to embodiments, the glass structure may include a horizontal portion formed on the interface layer structure.

[0072] In addition to the groove portion formed in the volume between the interface layer structure and the lateral surface of the semiconductor device, the glass structure may also include a horizontal portion. A first portion of the horizontal portion may be formed directly on the surface portion of the interface layer structure, and a second portion of the horizontal portion is formed directly on the groove portion of the glass structure. The horizontal portion and the groove portion may be connected to each other and form a continuous integral structure having an L-shaped or T-shaped vertical cross-section. The horizontal portion covers at least a section of the surface portion of the interface layer structure directly adjacent to the groove portion.

[0073] According to an embodiment, the first metal structure may be in direct contact with the first surface of the silicon carbide portion and the interface layer structure.

[0074] The first metal structure may be formed on the front side of the silicon carbide portion. The first metal structure and the doped regions in the silicon carbide portion may form an electrical contact, wherein the electrical contact may be a low resistance ohmic contact or a Schottky contact. For example, the first metal structure includes a contact layer and a main layer. The contact layer may contain metal atoms that form a stable, highly conductive phase with silicon and carbon and / or silicon carbide. Alternatively, the contact layer is based on a material that forms a Schottky contact with a suitable doped region in the silicon carbide portion. The main layer may contain aluminum and / or copper. The first metal structure and the interface layer structure form an interface that is inclined relative to the first surface.

[0075] According to an embodiment, the first vertical extent v1 of the surface portion of the interface layer structure may be at least 80% and at most 120% of the second vertical extent v2 of the first metal structure.For example, the first vertical extent v1 and the second vertical extent v2 can be equal.

[0076] The first vertical extent v1 and the second vertical extent v2 may have the same target value, and a difference between the first vertical extent v1 and the second vertical extent v2 may be process-dependent.

[0077] According to another embodiment, the first vertical extent v1 of the surface portion of the interface layer structure may be less than 80% of the second vertical extent v2 of the first metal structure.

[0078] For example, the first vertical extent v1 of the surface portion of the interface layer structure is at most 60% or 50% of the second vertical extent v2 of the first metal structure.

[0079] According to an embodiment, a total thickness v3 of the interface layer structure and the horizontal portion of the glass structure and the second vertical extent v2 of the first metal structure may be equal.

[0080] The total thickness v3 of the horizontal portion of the interface layer structure and the glass structure and the second vertical extent v2 of the first metal structure may have the same target value, and the difference between the total thickness v3 and the second vertical extent v2 may be process-related.

[0081] Top surfaces of the glass structure and the first metal structure distal from the silicon carbide portion may be substantially in the same plane. The glass structure and the first metal structure form an interface that is inclined relative to the first surface.

[0082] According to an embodiment, the first metal structure and the horizontal portion of the glass structure may be separated in a laterally direction.

[0083] The auxiliary gap exposing the top surface of the interface layer structure may separate the glass structure and the first metal structure in a laterally direction.

[0084] According to an embodiment, in a lateral direction, a surface portion of the interface layer structure may end at the first metal structure, and the first metal structure may end at a surface portion of the interface layer structure.

[0085] The first metal structure and the surface portions of the interface layer structure may form an interface having a single surface that is inclined relative to the first surface.

[0086] According to another embodiment, the surface portion of the interface layer structure and the first metal structure may overlap in a vertical direction.

[0087] For example, the surface portion of the interface layer structure may cover a portion of the first metal structure. The surface portion of the interface layer structure overlaps the first metal structure laterally, wherein the surface portion includes a step and directly covers the lateral surface of the first metal structure facing the interface layer structure and the peripheral portion of the first metal structure along the lateral surface of the first metal structure.

[0088] According to another example, the first metal structure may cover a portion of the surface portion of the interface layer structure. The first metal structure overlaps the surface portion of the interface layer structure laterally, wherein the first metal structure includes a step and directly covers the lateral surface of the surface portion facing the first metal structure and the peripheral portion of the surface portion along the lateral surface of the surface portion.

[0089] According to an embodiment, the semiconductor device may further include a body / anode region of a second conductivity type complementary to the first conductivity type, wherein the body / anode region is formed between the main layer and the first surface.

[0090] The bulk / anode region may be in direct contact with the edge structure, or may be separate from the edge structure. For example, a separate region of the first conductivity type may extend along the edge structure from the first surface to the main layer.

[0091] The body / anode region may form or include an anode region of a vertical power semiconductor diode having a forward current flowing in a vertical direction. Alternatively, the body / anode region may include a body region of a transistor cell of a vertical power semiconductor transistor having a drain current flowing in a vertical direction.

[0092] According to an embodiment, the bulk / anode region may be formed at a distance from the interface layer structure and the passivation coating.

[0093] For example, the bulk / anode region is formed at a lateral distance from an edge structure, the edge structure comprising a sandwich structure and a glass structure or a sandwich structure, a glass structure and a passivation coating.

[0094] According to an embodiment, the semiconductor device may further include a field relaxation structure of the second conductivity type, wherein the field relaxation structure laterally surrounds the body / anode region, and wherein a net doping of the field relaxation structure is lower than a net doping in the body / anode region.

[0095] In the vertical direction, the field relaxation structure may be formed between the lighter doped main layer and the first surface. In the lateral direction, the field relaxation structure may be formed between the bulk / anode region and the edge structure.

[0096] According to an embodiment, the field relaxation structure may be in direct contact with the interface layer structure or the passivation coating.

[0097] According to another embodiment, the field relaxation structure is formed to be spaced a distance from the interface layer structure and the passivation coating.

[0098] The field relaxation structure may be separated from the edge structure. For example, a separated region of the first conductivity type may extend along the edge structure from the first surface to the main layer.

[0099] According to an embodiment, the field relaxation structure may comprise one single field relaxation loop.The field relaxation loop may be laterally separated from the body / anode region.

[0100] According to another embodiment, the field relaxation structure may include a plurality of laterally separated field relaxation rings.

[0101] Separate regions of the first conductivity type may extend between adjacent field relaxation rings and between the innermost field relaxation ring and the bulk / anode region from the direction of the first surface to the main layer.

[0102] According to an embodiment, the semiconductor device may further include a surface layer of the first conductivity type between the first surface and the field relaxation structure.

[0103] According to an embodiment, the field relaxation structure may include a supplementary structure, wherein the supplementary structure is in direct contact with the field relaxation ring and has a lower net doping than the field relaxation ring. The supplementary structure has the second conductivity type.

[0104] The supplementary structure is formed between the first surface and the main layer, or between the surface layer and the main layer. The supplementary structure may form a connection layer extending parallel to the first surface. The field relaxation loop may extend into the connection layer and overlap with the connection layer.

[0105] According to an embodiment, the supplementary structure may include a plurality of supplementary rings, each supplementary ring being formed between adjacent field relaxation rings, or between an innermost field relaxation ring and the body / anode region. The supplementary rings have the second conductivity type.

[0106] The present disclosure also relates to a method for manufacturing a semiconductor device, wherein the method may include: forming a separation trench in a main surface of a single-crystal silicon carbide layer, wherein the separation trench surrounds a core portion of the silicon carbide layer; processing a first sidewall of the separation trench of the silicon carbide layer during a conditioning process, wherein dangling bonds of the silicon carbide layer are passivated; forming an interface layer on the first sidewall of the separation trench; forming a glass-filling structure in the separation trench; and separating the silicon carbide layer along a vertical separation line parallel to the separation trench.

[0107] The conditioning process may include terminating or passivating dangling bonds in another manner, for example, by means of a suitable dense passivation coating. Dangling bonds are at least largely ineffective. In addition, metal atoms may be removed or made highly inactive. After the conditioning process, the interface state density (Dit) along the third surface is at most 5E121 / cm 2 eV, up to 2E121 / cm 2 eV or up to 1E121 / cm 2 eV.

[0108] The conditioning process may be effective only for the first sidewall of the separation trench, or for any combination of the first and second sidewalls, the bottom of the separation trench, one or more sections of the main surface and the inner surface of the gate trench.

[0109] The interface layer may be formed only on the first sidewall of the separation trench, or on any combination of the first sidewall and the second sidewall, the bottom of the separation trench, and one or more sections of the major surface.

[0110] According to an embodiment, the vertical separation lines may extend through the separation trenches and along the separation trenches.

[0111] According to an embodiment, processing the first sidewall may include plasma based flash passivation.

[0112] Plasma-based flash passivation may include impinging a gas such as oxygen (O2), nitrogen (N2), or sulfur dioxide gas (SO2) to form a plasma of dissociated radicals to react with the exposed surface of the silicon carbide layer. A passivation layer of material (e.g., oxide or nitride) may be formed on the surface. Metal atoms may be removed or deactivated.

[0113] In some implementations, the gas is exposed to RF power delivery for a relatively short amount of time (such as between about 0.5 seconds and about 5 seconds) to form a plasma for plasma-based flash passivation. The dissociated radicals react with atoms along the exposed surface of the silicon carbide layer. The dissociated radicals can remove impurity atoms (e.g., metal atoms) trapped along the exposed surface of the silicon carbide layer, and / or oxidize silicon or carbon. For example, the dissociated radicals can form a thin, dense silicon oxide layer or dense layer that contains stoichiometric or non-stoichiometric silicon dioxide SiO2 and / or stoichiometric or non-stoichiometric silicon carbide oxide SiOC.

[0114] According to an embodiment, processing the first sidewall may include depositing a passivation coating using a precursor material including silicon as a main component.

[0115] The precursor material may be a silane such as monosilane SiH4 or TEOS. Forming the passivation coating may include depositing a conformal atomic layer having at least one, two, five or ten monoatomic layers using a precursor containing oxygen and a precursor containing silicon or a precursor containing oxygen and silicon. Alternatively, the passivation coating may be formed by chemical vapor deposition (CVD) using TEOS as a precursor material.

[0116] According to an embodiment, forming the glass-filled structure may include pressing a glass material into the separation trenches.

[0117] For example, forming the glass-filled structures may include a glass patterning process.

[0118] According to an embodiment, the method may also include: forming a contact layer in a contact section of the main surface, wherein the contact layer and the silicon carbide layer form an ohmic contact (e.g., a low resistance ohmic contact) and / or a Schottky contact; and forming a main layer on the contact layer, wherein the main layer includes at least one of aluminum Al or copper Cu.

[0119] According to embodiments, after forming the main layer, the separation trenches may be formed.

[0120] According to embodiments, after forming a contact layer, a separation trench may be formed, and after forming a glass filling structure, a main layer may be formed.

[0121] According to an embodiment, sections of the main layer may be formed on sections of the glass filling structure.

[0122] According to an embodiment, the method may further include thinning the silicon carbide layer from a side opposite to the main surface before the separation, wherein after the thinning, the glass filling structure (eg, a bottom of the glass filling structure) is exposed.

[0123] According to an embodiment, the method may further include: forming a gate electrode structure in the silicon carbide layer, wherein forming the gate electrode structure includes forming a gate trench extending from the main surface into the silicon carbide layer and forming a gate electrode in the gate trench, and wherein before forming the gate electrode, a separation trench is formed.

[0124] According to an embodiment, the method may further include: before forming the gate electrode, filling the separation trench with an auxiliary material, and after forming the contact layer, removing the auxiliary material.

[0125] Figure 1A and Figure 1B A semiconductor device 500 is shown having a single-crystal silicon carbide portion 100. The silicon carbide portion 100 has a first surface 101 and an opposing second surface 102. A third surface 103 extends from the first surface 101 in the direction of the second surface 102 without reaching the second surface 102.

[0126] The first surface 101 is located at the front side of the silicon carbide portion 100. The first surface 101 can be planar or can include first coplanar surface segments between grooves extending from a first plane defined by the first coplanar surface segments of the first surface 101 into the silicon carbide portion 100. The second surface 102 is located at the opposite back side of the silicon carbide portion 100 and can be planar or can include second coplanar surface segments separated by grooves extending from a second plane defined by the second coplanar surface segments into the silicon carbide portion 100. The first plane and the second plane can be inclined with respect to each other by up to 4 degrees. In the illustrated embodiment, the first surface 101 and the second surface 102 are parallel to each other.

[0127] The first surface 101 has lateral extents in two orthogonal horizontal directions defined by the x-axis and the y-axis. A surface orthogonal to the first surface 101 defines a vertical direction along the z-axis.

[0128] The third surface 103 is tilted with respect to the first plane at an angle in the range of 70 to 110 degrees. The third surface 103 ends at a distance from the second surface 102. The third surface 103 may be a part of a sidewall of a trench extending from the first surface 101 into the silicon carbide portion 100, or may be a part of a lateral surface of the silicon carbide portion 100, wherein the lateral surface connects an edge of the first surface 101 with an edge of the second surface 102.

[0129] Silicon carbide portion 100 comprises a heavily doped base portion 130 of a first conductivity type and a lighter doped main layer 140 of the first conductivity type between first surface 101 and base portion 130. A body / anode region 150 of a second conductivity type complementary to the first conductivity type is formed between main layer 140 and first surface 101.

[0130] In the illustrated embodiment, the first conductivity type is n-type and the second conductivity type is p-type. According to other embodiments, the first conductivity type is p-type and the second conductivity type is n-type.

[0131] The body / anode region 150 may form an anode region of a vertical power semiconductor diode with forward current flowing in a vertical direction. Alternatively, the body / anode region 150 may comprise a body region of a transistor cell of a vertical power semiconductor transistor with load current flowing in a vertical direction.

[0132] The third surface 103 forms the sidewalls of a recess or groove extending from the first surface 101 into the base portion 130. The recess or groove laterally exposes the body / anodic region 150, the main layer 140 and the upper section of the base portion 130. The body / anodic region 150, the main layer 140 and the base portion 130 are in direct contact with the edge structure 200.

[0133] The first metal structure formed on the first surface 101 may be in direct contact with the body / anode region 150. The second metal structure 320 formed directly on the second surface 102 is in direct contact with the base portion 130.

[0134] exist Figure 1A In the embodiment, the edge structure 200 includes a passivation coating 210, which is in direct contact with the third surface 103. The passivation coating 210 is a dense layer formed with a uniform thickness, and may be formed of a small number of continuous atomic layers.

[0135] The passivation coating at least largely inactivates dangling bonds of silicon carbide and / or metal atoms along the third surface 103. For example, the interface state density (Dit) along the third surface 103 is at most 5E121 / cm 2 eV, up to 2E121 / cm 2 eV or up to 1E121 / cm 2 eV.

[0136] exist Figure 1B In the embodiment of the present invention, the auxiliary atoms 110 saturate (terminate) the dangling bonds of the silicon carbide portion 100. The auxiliary atoms 110 include hydrogen atoms and / or atoms of one or more non-metallic elements other than silicon and having an atomic number greater than six. The dangling bonds along the third surface 103 include silicon-surface dangling bonds and carbon-surface dangling bonds. The auxiliary atoms 110 have one or more non-metallic elements other than silicon and carbon, and saturate the dangling bonds to a large extent. The non-metallic elements include hydrogen, nitrogen, oxygen, phosphorus, sulfur, selenium, halogens (17 group elements) and rare gases (18 group elements). According to the example, the non-metallic elements are selected from nitrogen, oxygen and phosphorus.

[0137] The auxiliary atoms 110 electrically inactivate the dangling bonds at least to a large extent, so that the dangling bonds affect the dielectric strength along the third surface 103 only to a negligible extent (if at all). For example, the auxiliary atoms 110 reduce the interface state density (Dit) along the third surface 103 to at most 5E121 / cm 2 eV, up to 2E121 / cm 2 eV or up to 1E121 / cm 2 eV.

[0138] The edge structure 200 extends from the first surface 101 into the silicon carbide portion 100 along the third surface 103. The edge structure 200 includes a glass structure 250 and an interface layer structure 220 formed between the silicon carbide portion 100 and the glass structure 250.

[0139] exist Figure 1A In the embodiment, the edge structure 200 further includes a passivation coating 210 between the silicon carbide portion 100 and the interface layer structure 220 .

[0140] exist Figure 1B In the embodiment, the interface layer structure 220 is in direct contact with the silicon carbide portion 100 , wherein the auxiliary atoms 110 are embedded along the interface between the silicon carbide portion 100 and the interface layer structure 220 .

[0141] In the blocking mode of the semiconductor device 500, the edge structure 200 limits the back side potential of the second metal structure 320 at the back side. The lateral extension of the lateral termination structure can be reduced, or such a lateral termination structure can be omitted completely. The dangling bonds along the third surface 103 are saturated and / or passivated to a sufficient extent, and / or metal atoms are not present to such an extent that the dielectric strength of the semiconductor device 500 is sufficiently high.

[0142] exist Figure 2A and Figure 2B , the third surface 103 is an inner sidewall of a trench structure 400 , which separates a central portion 195 from a peripheral portion 199 of the silicon carbide portion 100 .

[0143] The groove structure 400 surrounds the central portion 195 of the silicon carbide portion 100 laterally. The peripheral portion 199 separates the groove structure 400 from the lateral surface 109, which connects the edge of the first surface 101 to the edge of the second surface 102. The groove structure 400 has a uniform vertical extent ("depth") and a uniform lateral width between the central portion 195 and the peripheral portion 199. The groove structure 400 forms a continuous frame around the central portion 195. The frame can be rectangular with four orthogonal straight sections. Along each straight section of the lateral surface 109, the groove structure 400 has a uniform lateral distance relative to the lateral surface 109. The body / anode region 150 is formed in the central portion 195 and is not present in the peripheral portion 199. Alternatively, the main layer 140 extends from the first surface 101 to the base portion 130 in the peripheral region 199.

[0144] exist Figure 2A 195, the passivation coating 210 is in direct contact with the entire inner sidewall 401 of the groove structure 400 toward the center portion 195. In addition, the passivation coating 210 is in direct contact with the outer sidewall 402 of the groove structure 400, and is in direct contact with the bottom 403 of the groove structure 400. The interface layer structure 220 covers all sections of the passivation coating 210. In the illustrated example, the interface layer structure 220 covers all sections of the passivation coating 210 with a uniform thickness. The glass structure 250 completely fills the space between the various sections of the interface layer structure 220.

[0145] exist Figure 2B In the embodiment of the present invention, the auxiliary atoms 110 saturate the dangling bonds of the silicon carbide portion 100 along the inner sidewall 401 of the groove structure 400 toward the central portion 195. In addition, the auxiliary atoms 110 saturate the dangling bonds of the silicon carbide portion 100 along the outer sidewall 402 of the groove structure 400 toward the peripheral portion 199 and / or along the bottom 403 of the groove structure 400 toward the second surface 102 and connecting the inner sidewall 401 and the outer sidewall 402. The interface layer structure 220 covers the inner sidewall 401, the outer sidewall 402, and the bottom 403. In the illustrated example, the interface layer structure 220 covers the inner sidewall 401, the outer sidewall 402, and the bottom 403 with a uniform thickness. The glass structure 250 completely fills the space between the various sections of the interface layer structure 220.

[0146] exist Figure 3A , Figure 3B , Figure 3C and Figure 3D In the embodiment shown in FIG. 1 , the third surface 103 forms a lateral surface 109 or a part of the lateral surface 109 connecting an edge of the first surface 101 and an edge of the second surface 102 of the silicon carbide portion 100 .

[0147] exist Figure 3A and Figure 3C In the embodiment, the lateral surface 109 includes: a third surface 103 extending from the first surface 101 to the second surface 102; a fourth surface 104 extending from the second surface 102 to the first surface 101; and a fifth surface 105 connecting the adjacent edges of the third surface 103 and the fourth surface 104 at a distance from the first surface 101 and the second surface 102. The fourth surface 104 may extend in a vertical direction. The third surface 103 may extend in a vertical direction, or may be inclined by no more than 20 degrees relative to the vertical direction. The fifth surface 105 may extend in a horizontal direction, or may be inclined by no more than 20 degrees relative to the horizontal direction.

[0148] exist Figure 3A , a first section of the passivation coating 210 is in direct contact with the third surface 103. A second section of the passivation coating 210 is in direct contact with the fifth surface 105. The interface layer structure 220 covers the first section and the second section of the passivation coating 210 with a uniform thickness. The glass structure 250 is in direct contact with the interface layer structure 220. An outer lateral surface 254 of the glass structure 250 away from the third surface 103, the fourth surface 104 of the silicon carbide portion 100, and the lateral edges of the passivation coating 210 and the interface layer structure 220 are coplanar and form a smooth transition without bends and kinks.

[0149] exist Figure 3B , the third surface 103 forms a lateral surface 109, and the lateral surface 109 extends from the edge of the first surface 101 to the edge of the second surface 102 in the vertical direction. The passivation coating 210 extends from the first surface 101 to the second surface 102 in the vertical direction. The interface layer structure 220 extends from the plane of the first surface 101 to the plane of the second surface 102 in the vertical direction. The glass structure 250 extends from the plane of the first surface 101 to the plane of the second surface 102 in the vertical direction.

[0150] Figure 3C Auxiliary atoms 110 are shown, which largely saturate dangling bonds of the silicon carbide portion 100 along the third surface 103. In addition, auxiliary atoms 110 are present along the fifth surface 105. The interface layer structure 220 is formed directly on the third surface 103 and the fifth surface 105. The glass structure 250 is in direct contact with the interface layer structure 220. The outer lateral surface 254 of the glass structure 250, the lateral edge of the interface layer structure 220, and the fourth surface 104 of the silicon carbide portion 100 are coplanar.

[0151] exist Figure 3D, the third surface 103 forms a lateral surface 109 extending in the vertical direction from the edge of the first surface 101 to the edge of the second surface 102. The auxiliary atoms 110 largely saturate the dangling bonds of the silicon carbide portion 100 along the third surface 103. The interface layer structure 220 extends in the vertical direction from the plane of the first surface 101 to the plane of the second surface 102. The glass structure 250 extends in the vertical direction from the plane of the first surface 101 to the plane of the second surface 102.

[0152] In all the figures described so far, interface layer structure 220 includes a groove portion in the volume between first surface 101 and second surface 102. Interface layer structure 220 may include only a groove portion, wherein interface layer structure 220 is completely formed in the volume between first surface 101 and second surface 102.

[0153] exist Figure 4 In the embodiment of the present invention, the field relaxation structure 160 of the second conductivity type laterally surrounds the body / anode region 150. The net doping of the field relaxation structure 160 is lower than the net doping of the body / anode region 150. For example, the net doping in the field relaxation structure 160 is at most 50% or at most 10% of the net doping in the body / anode region 150.

[0154] In the vertical direction, the field relaxation structure 160 is formed between the lighter doped main layer 140 and the first surface 101. In the horizontal direction, the field relaxation structure 160 is formed between the body / anode region 150 and the groove portion 221 of the interface layer structure 220. In the illustrated example, the field relaxation structure 160 extends from the first surface 101 to the main layer 140, and from the body / anode region 150 to the groove portion 221 of the interface layer structure 220. In another example, the field relaxation structure 160 may be formed with the following example: Figure 1A The passivation coating 210 shown in FIG.

[0155] Figure 4 Also shown is an edge structure 200, the interface layer structure 220 of the edge structure 200 includes: a groove portion 221 formed between the first surface 101 and the second surface 102; and a surface portion 222 formed on the first surface 101. The groove portion 221 and the surface portion 222 are connected to each other and form a continuous integral structure. The groove portion 221 and the surface portion 222 are layered portions that can have the same thickness. At least the surface portion 222 directly along the edge between the first surface 101 and the third surface 103 or the transition covering the edge area 111 of the first surface 101 has a first vertical extent v1.

[0156] The field relaxation structure 160 is formed entirely in the edge region 111. The surface portion 222 of the interface layer structure 200 is in direct contact with the field relaxation structure 160 across the entire width of the field relaxation structure 160 and overlaps the body / anode region 150 laterally.

[0157] The first metal structure 310 is formed on a portion of the first surface 101 surrounded by the surface portion 222 of the interface layer structure 200 at the front side of the silicon carbide portion 100. In the lateral direction, the first metal structure 310 is in direct contact with the interface layer structure 220, wherein the surface portion 222 of the interface layer structure 200 ends at the first metal structure 310, and the first metal structure 310 ends at the surface portion 222.

[0158] The first metal structure 310 and the surface portion 222 of the interface layer structure 220 form an interface including a single surface that is inclined relative to the first surface 101. No lateral overlap exists between the surface portion 222 and the first metal structure 310.

[0159] The first vertical extent v1 of the surface portion 222 of the interface layer structure 220 is at least 80% and at most 120% of the second vertical extent v2 of the first metal structure 310. In the illustrated example, the first vertical extent v1 and the second vertical extent v2 are equal.

[0160] The first metal structure 310 may include: a contact layer 311 formed directly on the first surface 101 ; and a main layer 312 formed directly on the contact layer 311 .

[0161] The contact layer 311 and the doped regions in the silicon carbide portion 100 form an electrical contact, such as a low resistance ohmic contact and / or a Schottky contact. For example, the first metal structure 310 comprises metal atoms that form a stable, highly conductive phase with silicon and carbon. The main layer 312 comprises aluminum and / or copper, such as an aluminum-copper alloy.

[0162] In the edge region 111 of the first surface 101, auxiliary atoms of hydrogen and / or one or more non-metallic elements other than silicon and having an atomic number greater than six largely saturate the dangling bonds of the silicon carbide portion 100. Alternatively or additionally, the dense passivation coating may be in direct contact with the silicon carbide portion 100 in the edge region 111 of the first surface 101.

[0163] For the illustrated example, no passivation coating 210 is formed on the first surface 101 in the edge region 111 , and the interface layer structure 220 is in direct contact with the first surface 101 in the edge region 111 .

[0164] Glass structure 250 of edge structure 200 includes trench portion 251 in the volume between interface layer structure 220 and the lateral edge of the semiconductor device. In the illustrated example, glass structure 250 includes only trench portion 251 and is completely formed in the volume between interface layer structure 220 and the lateral edge of the semiconductor device.

[0165] Figure 5 The edge structure 200 is shown, and the glass structure 250 of the edge structure 200 includes a horizontal portion 252 formed on the interface layer structure 220.

[0166] In addition to the groove portion 251 formed in the volume between the interface layer structure 220 and the lateral edge of the semiconductor device, the glass structure 250 also includes a horizontal portion 252. More specifically, a first portion of the horizontal portion 252 is formed directly on the surface portion 222 of the interface layer structure 220, and a second portion of the horizontal portion 252 is formed directly on the groove portion 251 of the glass structure 250. The horizontal portion 252 and the groove portion 251 are connected to each other and form a continuous integral structure having an L-shaped vertical cross-section. The horizontal portion 252 covers at least a section of the surface portion 222 of the interface layer structure 220 that is directly adjacent to the groove portion 221.

[0167] exist Figure 5 , the horizontal portion 252 of the glass structure 250 completely covers the surface portion 222 of the interface layer structure 220 and laterally overlaps the outer portion of the body / anode region 150 .

[0168] exist Figure 6 , the horizontal portion 252 covers only the inner section of the surface portion 222 of the interface layer structure 220 directly adjacent to the groove portion 252 and does not exist on the outer section away from the groove portion 252. The horizontal portion 252 does not overlap the body / anode region 150.

[0169] Figure 7 A semiconductor device is shown in which a surface portion 222 of the interface layer structure 220 has a first vertical extent v1 that is less than 80% of a second vertical extent v2 of the first metal structure 310 .

[0170] According to another example, the first vertical extent v1 of the surface portion 222 of the interface layer structure 220 is at most 60% or 50% of the second vertical extent v2 of the first metal structure 310 .

[0171] The glass structure 250 includes only the groove portion 251 , wherein the upper surface of the groove portion 251 and the top surface of the surface portion 222 of the interface layer structure 220 are substantially coplanar.

[0172] exist Figure 8 , a surface portion 222 of the interface layer structure 220 has a first vertical extent v1, which is less than 80% of a second vertical extent v2 of the first metal structure 320. The glass structure 250 includes a horizontal portion 252, which is in lateral contact with the first metal structure 310. The total thickness v3 of the interface layer structure 220 and the horizontal portion 252 of the glass structure 250 is substantially equal to the second vertical extent v2 of the first metal structure 310. The top surfaces of the glass structure 250 and the first metal structure 310 away from the silicon carbide portion 100 are substantially in the same plane. The glass structure 250 and the first metal structure 310 form an interface that is inclined relative to the first surface 101.

[0173] Fig. 9 An auxiliary gap 259 is shown between the first metal structure 310 and the horizontal portion 252 of the glass structure 250. The auxiliary gap 259 exposes the top surface of the interface layer structure 220 and laterally separates the glass structure 250 from the first metal structure 310.

[0174] Fig.10 , Fig.11 and Fig.12 A surface portion 222 of the interface layer structure 220 is shown laterally overlapping the first metal structure 310 .

[0175] Each of the surface portions 222 includes a step, and covers both a lateral surface of the first metal structure 310 facing the interface layer structure 220 and a peripheral portion of the first metal structure 310 directly along a lateral edge of the first metal structure 310 .

[0176] A first portion of surface portion 222 of interface layer structure 220 is in direct contact with first surface 101 of silicon carbide portion 100 . A second portion of surface portion 222 of interface layer structure 220 is in direct contact with a section of the top surface of first metal structure 310 .

[0177] exist Fig.10 In the embodiment of the present invention, the top surface of the glass structure 250 and the top surface of the first portion of the surface portion 222 of the interface layer structure 220 are substantially coplanar.

[0178] exist Fig.11 and Fig.12 In the embodiment of the present invention, the top surface of the glass structure 250 and the top surface of the second portion of the surface portion 222 of the interface layer structure 220 are substantially coplanar.

[0179] exist Fig.11 In the embodiment, the lateral end surface of the horizontal portion 252 of the glass structure 250 is in direct contact with the vertical section of the surface portion 222 of the interface layer structure 220 along the step.

[0180] exist Fig.12 In the embodiment, the separation gap 258 exposes a section of the first portion of the surface portion 222 and laterally separates the horizontal portion 252 of the glass structure 250 from the second portion of the surface portion 222. The lateral end surface of the horizontal portion 252 of the glass structure 250 is laterally separated from the vertical section of the surface portion 222 of the interface layer structure 220.

[0181] Fig.13 and Fig.14 A first metal structure 310 is shown laterally overlapping the glass structure 250 .

[0182] The first metal structure 310 includes a step, and covers both a lateral surface of the glass structure 250 facing the first metal structure 310 and a peripheral portion of the glass structure 250 directly along an edge of the glass structure 250 .

[0183] exist Fig.13 In the embodiment of the present invention, the first metal structure 310 only partially overlaps the field relaxation structure 160 .

[0184] exist Fig.14 In the embodiment of the present invention, the first metal structure 310 completely overlaps the field relaxation structure 160 , and a lateral edge of the first metal structure 310 is directly located above the groove portion 251 of the glass structure 250 .

[0185] Fig.15 A separation region 145 of the first conductivity type is shown, extending from the first surface 101 to the main layer 140 along the edge structure 200. The separation region 145 separates the bulk / anode region 150 from the edge structure 200 laterally.

[0186] Fig.16 A field relaxation structure 160 is shown, which extends from the first surface 101 to the main layer 140 and extends between the body / anode region 150 and the groove portion 221 of the interface layer structure 220. The field relaxation structure 160 laterally surrounds the body / anode region 150. The field relaxation structure 160 may be laterally adjacent to the body / anode region 150, or may have a lateral end region in which the doping concentration profiles of the field relaxation structure 160 and the body / anode region 150 overlap. The net doping in the field relaxation structure 160 is lower than the net doping in the body / anode region 150. For example, the net doping in the field relaxation structure 160 is at most 50% of the net doping in the body / anode region 150. The field relaxation structure 160 and the body / anode region 150 form a unipolar junction. The separation region 145 of the first conductivity type extends from the first surface 101 to the main layer 140 along the edge structure 200 and separates the field relaxation structure 160 from the edge structure 200 in a laterally direction.

[0187] The field relaxation structure 160 includes a single field relaxation loop 161, wherein the field relaxation loop 161 and the body / anode region 150 form a unipolar junction. The net doping in the field relaxation loop 161 is between 5E16 and 5E18 cm -3 , 1E17 to 1E18 cm -3 or 1E17 to 5E17 cm -3 in the range of.

[0188] exist Fig.17 In the embodiment, the field relaxation structure 160 includes a plurality of laterally separated field relaxation rings 161. A separation region 145 of the first conductivity type extends from the first surface 101 to the main layer 140 between adjacent field relaxation rings 161 and between the innermost field relaxation ring 161 and the body / anode region 150.

[0189] Fig.18 A surface layer 170 of the first conductivity type is shown between the first surface 101 and the field relaxation structure 160. The surface layer 170 separates the field relaxation structure 160 from the first surface 101. The field relaxation structure 160 includes a single field relaxation ring 161 as shown in the figure or a plurality of laterally separated field relaxation rings 161. The field relaxation structure 160 may be laterally adjacent to the main body / anode region 150, or may have a lateral end region in which the doping concentration profiles of the field relaxation structure 160 and the main body / anode region 150 overlap.

[0190] exist Fig.19 and Fig. 20 In the embodiment, the field relaxation structure 160 includes a supplementary structure 162 having a second conductivity type and a lower net doping than the field relaxation ring 161. The net doping in the supplementary structure 162 is in the range of 1E17 to 5E17 cm -3 range, and can be compared with from 1E18 to 1E19 cm -3 The net doping combination in the field relaxation loop 161 in the range of .

[0191] exist Fig.19 In the embodiment, the supplementary structure 162 includes a plurality of supplementary rings 163, wherein each supplementary ring 163 is formed between two adjacent field relaxation rings 161, or between the innermost field relaxation ring 161 and the body / anode region 150. The supplementary rings 163 extend from the first surface 101 to the main layer 140 and separate the field relaxation rings 161 laterally.

[0192] exist Fig. 20In the embodiment, a surface layer 170 of the first conductivity type is formed between the first surface 101 and the single field relaxation ring 161, and a plurality of laterally separated supplementary rings 163 extend from the first surface 101 through the surface layer 170 into the field relaxation ring 161. The field relaxation ring 161 may be laterally adjacent to the body / anode region 150, or may have a lateral end region in which the doping concentration profiles of the field relaxation ring 161 and the body / anode region 150 overlap.

[0193] The field relaxation structure 160, the field relaxation ring 161, the supplementary structure 162, the supplementary ring 163 and the surface layer 170 form a lateral field termination structure, which shapes the electric field in the portion of the silicon carbide layer close to the edge structure 200 in such a way that the maximum electric field in the edge structure 200 is significantly reduced and the breakdown voltage is significantly increased. The width of the lateral field termination structure is less than 50% of the lateral width of a conventional lateral field termination structure without the edge structure 200, for example, less than 20% thereof.

[0194] Refer to below FIG. 21A to FIG. 29C The described method can be used to obtain reference Figures 1A to 20 The semiconductor device described herein and utilizing reference FIG. 21A to FIG. 29C Any suitable method described can be used to obtain the reference Figures 1A to 20 A semiconductor device is described.

[0195] FIG. 21A to FIG. 21E A vertical cross-sectional view of a portion of a silicon carbide layer 700 is shown for illustrating a method of manufacturing a semiconductor device.

[0196] according to Fig.21A , a separation trench 740 is formed in the main surface 701 of the single-crystal silicon carbide layer 700 , wherein the separation trench 740 surrounds the die portion 710 of the silicon carbide layer 700 .

[0197] The silicon carbide layer 700 may be a homogeneous silicon carbide wafer, or may be a layer formed on an underlying material different from single-crystal silicon carbide. The silicon carbide layer 700 may be uniformly doped. For example, the silicon carbide layer 700 is n-doped.

[0198] The major surface 701 is located at the front side of the silicon carbide layer 700. The major surface 701 has lateral extents in two orthogonal horizontal directions defined by the x-axis and the y-axis. A surface orthogonal to the major surface 701 defines a vertical direction along the z-axis.

[0199] Before forming the separation trenches 740 or after forming the separation trenches 740 , further trenches (eg gate trenches) may be formed, which extend from the first major surface 701 into the silicon carbide layer 700 .

[0200] The sidewalls of the separation trench 740 are inclined at an angle in the range from 70 degrees to 110 degrees with respect to the main surface 701 . The separation trench 740 ends in the silicon carbide layer 710 .

[0201] At least the first sidewall 741 of the separation trench 740 is processed in the conditioning process, wherein dangling bonds of the silicon carbide layer 700 along the first sidewall 741 are deactivated.

[0202] The dangling bonds along the third surface 103 include silicon-face dangling bonds and carbon-face dangling bonds. Passivating the dangling bonds may include a process that provides auxiliary atoms 110 of hydrogen and / or one or more additional non-metallic elements other than silicon and carbon to saturate (terminate) the dangling bonds to a large extent. Non-metals include hydrogen, nitrogen, oxygen, phosphorus, sulfur, selenium, halogens, and rare gases. For example, the process may include plasma-based flash passivation using oxygen O2. Alternatively or in addition, passivating the dangling bonds may include depositing a dense passivation coating. Depositing the passivation coating may include forming a stack of dense conformal atomic layers on the first sidewall 741.

[0203] In both alternatives, the dangling bonds are electrically deactivated at least to a large extent. After this treatment, the interface state density (Dit) along the third surface 103 is at most 5E121 / cm 2 eV, up to 2E121 / cm 2 eV or up to 1E121 / cm 2 eV.

[0204] In the illustrated example, the conditioning process is effective for the first sidewall 741 of the separation trench 740, the second sidewall 742 and the bottom 743 of the separation trench 740. The passivation electrically inactivates the dangling bonds.

[0205] Fig. 21B Passivated dangling bonds 749 along the first sidewall 741 , the second sidewall 742 , and the bottom 743 of the separation trench 740 are shown.

[0206] An interface layer 720 is deposited on the front side of the silicon carbide layer 700. The interface layer 720 may include at least one silicon oxide layer and / or one silicon nitride layer.

[0207] according to Fig. 21C The interface layer 720 covers the main surface 701 , the first sidewall 741 of the separation trench 740 , the second sidewall 742 of the separation trench 740 , and the bottom 743 of the separation trench 740 .

[0208] Glass material 753 is placed or deposited on interface layer 720. Initially, glass material 753 may be solid. Glass material 753 is heated to a high temperature (e.g., above 200°C or above 400°C or even above 500°C), and glass material 753 is subjected to pressure. Depending on the temperature, the pressure is selected so that at least a portion of glass material 753 is liquefied. The liquefied portion of the glass material gradually fills separation trench 740, as shown in FIG. Fig.21D as shown in .

[0209] After the separation trenches are filled (eg, completely filled), the temperature and pressure are reduced, and the glass material 753 resolidifies. The resolidified glass material obtained in the glass patterning process may be patterned, for example, by a polishing process, to form a glass filling structure.

[0210] Along vertical separation lines 705 forming a regular grid, the silicon carbide layer 700 is sliced ​​into a plurality of semiconductor dies 510. One separation trench 740 or a pair of separation trenches 740 runs parallel to each vertical separation line 705. As an example, the slicing may include mechanical sawing.

[0211] Fig.21E Slicing is shown along a vertical separation line 705 extending through Fig.21D The separation groove 740 is parallel to Fig.21D The separation groove 740 is formed. Fig.21D The silicon carbide layer 700 is divided into a plurality of silicon carbide portions 100 . Fig.21D The interface layer 720 and the glass filling structure are divided into edge structures 200, wherein each edge structure 200 includes Fig.21E The interface layer structure 220 is formed by a portion of the interface layer 720 and the glass structure 250 is formed by a portion of the glass filling structure.

[0212] Fig. 22 Slicing is shown along a vertical separation line 705, which is at Fig.21D Extending between two parallel separation trenches 740 .

[0213] Fig.23 Showing a plan view on the silicon carbide layer 700 , the separation trenches 740 form a regular orthogonal grid and the vertical separation lines 705 run along the lateral center lines of the separation trenches 740 .

[0214] Fig.24 Showing a plan view on the silicon carbide layer 700, each separation trench 740 forms a rectangular frame and the rectangular frames are arranged in rows and columns in a matrix shape. Vertical separation lines 705 extend between adjacent frames.

[0215] Refer to below FIG. 25A to FIG. 29CThe described method shows an integrated field relaxation structure 160 as an example of a lateral field termination structure. The described method can be combined with any other lateral field termination structure, for example Figures 1A to 20 Any combination of the lateral field termination structures shown in FIG.

[0216] Figures 25A to 25F Referring to one method, the method includes forming separation trenches 740 after forming a first metal structure 310 on a major surface 701 .

[0217] Gate trenches 450 extending from the major surface 701 into the silicon carbide layer 700 are formed. A gate dielectric 420 is formed on at least one sidewall of each gate trench 450. A gate electrode material (e.g., heavily doped polysilicon) is deposited and patterned to form gate electrodes 430 in the gate trenches 450. An interlayer dielectric 440 is formed that covers the gate electrodes 430 and exposes contact sections of the major surface 701 between the gate trenches 450. Source regions 180 of a first conductivity type are formed in the silicon carbide layer 700, wherein each source region 180 extends from the major surface 701 into the body / anode region 150 along at least one sidewall of the gate trenches 450.

[0218] The contact layer 311 is formed on the contact section of the major surface 701 and the interlayer dielectric 440. The contact layer 311 and the silicon carbide layer 700 form an ohmic contact. In an additional or alternative example, a Schottky contact may be formed between the contact layer 311 and the silicon carbide layer 700. The main layer 312 is formed on the contact layer 311. The main layer 312 includes at least one of aluminum Al or copper Cu.

[0219] The main layer 312 and the contact layer 311 are removed from the grid-shaped edge and kerf region of the major surface 701. The grid-shaped separation grooves 740 are formed in the edge-and-kerf region.

[0220] Fig.25A The first metal structure 310 is shown, and the first metal structure 310 includes a patterned contact layer 311 and a patterned main layer 312. The first metal structure 310 does not exist in the edge regions on both sides of the separation trench 740.

[0221] The sidewalls of the separation trench 740 are adjusted to saturate / passivate dangling bonds, and / or remove metal atoms. An interfacial layer is deposited, and a portion of the interfacial layer deposited on the first metal structure 310 is removed.

[0222] Fig.25B A patterned interface layer 725 is shown covering the exposed portions of the major surface 701 in the edge regions on both sides of the separation trench 740 .

[0223] Fig.25C A glass patterning process is shown which presses the glass material 753 into the separation trenches 740. A portion of the resulting glass structure is removed from over the first metal structure 310.

[0224] Fig.25D A glass-filled structure 755 is shown that is obtained by removing glass from over the first metal structure 310. The edges of the patterned glass structure may be rounded.

[0225] Fig.25E A glass filling structure 755 with rounded edges is shown. The silicon carbide layer 700 is thinned from the back side, for example, by grinding. The thinning stops at a vertical distance from the bottom of the separation trench 740. After thinning, a second metal structure 320 is formed on the back side. The silicon carbide layer is divided into semiconductor dies 510 along vertical separation lines, which extend along the horizontal longitudinal axis of the separation trench 740.

[0226] Fig.25F Two semiconductor dies 510 are shown, each of the semiconductor dies 510 having an edge structure 200 including Fig.25E A portion of the patterned interface layer 725 and a portion of the glass filling structure 755 having rounded edges.

[0227] Figures 26A to 26F A method is shown, which includes forming separation trenches 740 after forming the gate electrode 430 and before depositing the main layer 320 .

[0228] The gate electrode 430 is arranged in the gate trench 450. An interlayer dielectric 440 is formed, which covers the gate electrode 430 and exposes the contact section of the main surface 701 between the gate trenches 450. The contact layer 311 is formed on the contact section of the main surface 701 and the interlayer dielectric 440. The contact layer 311 and the silicon carbide layer 700 form an ohmic contact. Separately or in combination, the contact layer 311 and the silicon carbide layer 700 can form a Schottky contact. A portion of the contact layer 311 in the grid-shaped edge and saw-cut area of ​​the main surface 701 is removed. The grid-shaped separation groove 740 is formed in the edge and saw-cut area.

[0229] Fig.26A A patterned contact layer 311 is shown on the contact sections of the major surface between laterally separated sections of the interlayer dielectric 440. The contact layer 311 is absent in the edge regions on both sides of the separation trench 740 over the field relaxation structure 160.

[0230] The sidewalls of the separation trench 740 are tuned to saturate / passivate dangling bonds, and / or remove metal atoms. An interface layer 720 is deposited.

[0231] Fig.26B An interface layer 720 is shown, covering the exposed portions of the major surface 701 in the edge regions on both sides of the separation trench 740 , the interlayer dielectric 440 , and the contact layer 311 .

[0232] Fig.26C A glass embossing process is shown, which presses the glass material 753 into the separation trench 740. The resulting glass structure and a portion of the interface layer 720 are removed from above the interlayer dielectric 440 and the contact layer 311. The silicon carbide layer is thinned from the back side, such as grinding. The thinning stops at a vertical distance from the bottom of the separation trench 740. After thinning, a second metal structure 320 is formed on the back side.

[0233] Fig.26D A glass-filled structure 755 and a patterned interface layer 725 are shown, obtained by removing glass from above the interlayer dielectric 440 and the contact layer 311 .

[0234] The main layer 312 is formed on the contact layer 311 and the interlayer dielectric 440. The main layer 312 includes at least one of aluminum Al or copper Cu. The contact layer 311 and / or the main layer 312 may be formed before a thinning process (eg, a grinding process) or after the thinning process.

[0235] like Fig.26E As shown in FIG. , the top surfaces of the main layer 312 and the glass-filled structures 755 can be substantially coplanar.

[0236] The silicon carbide layer 700 is divided into semiconductor dies 510 along vertical separation lines, which extend along the horizontal longitudinal axes of the separation trenches 740 .

[0237] Fig.26F Two semiconductor dies 510 are shown, each of the semiconductor dies 510 having an edge structure 200 including Fig.25E A portion of the patterned interface layer 725 and a portion of the glass filling structure 755 having rounded edges.

[0238] Figures 27A to 27C The process sequence shown in the figure is similar to Figures 26D to 26F The process sequence illustrated in FIG. 7 differs in that the primary layer 312 is formed to cover the outer section of the glass filling structure 755. The primary layer 312 and the glass filling structure 755 overlap laterally.

[0239] Figures 28A to 28C The process sequence shown in the figure is similar to Figures 26D to 26FThe process sequence illustrated in FIG. 1 differs in that the thinning stops after the glass fill structure 755 is exposed. Figure 3B and Figure 3D The semiconductor device combination shown in FIG.

[0240] according to Fig.29A , the gate trench 450 and the separation trench 740 are formed simultaneously using the same mask or in a directly consecutive mask and etch process. The separation trench 740 may be formed before forming the gate trench 450. In other examples, the separation trench 740 may be formed after forming the gate trench 450. Sidewall conditioning for passivating dangling bonds and / or removing metal atoms is performed, which is effective for both the gate trench 450 and the separation trench.

[0241] Fig.29A The gate trench 450 and the separation trench 740 are shown extending from the main surface 701 into the silicon carbide layer 700. The separation trench 740 is filled with a sacrificial material 745.

[0242] Fig.29B 740 is shown filled with a sacrificial material 745. The process proceeds to form the gate dielectric 420, the gate electrode 430, and the interlayer dielectric 440. In a later process step ( Fig.29B ), the sacrificial material 745 is removed and thereafter, the interface layer 725 is deposited.

Claims

1. A semiconductor device (500), comprising: A single crystal silicon carbide portion (100) comprising a first surface (101), an opposite second surface (102) and a third surface (103) extending from the first surface (101) in the direction of the second surface (102), wherein a) along the third surface (103) hydrogen atoms and / or atoms of one or more non-metallic elements other than silicon and having an atomic number greater than six saturate dangling bonds of the silicon carbide portion (100), and / or b) a passivation coating (210) is in direct contact with the third surface (103); a glass structure (250); and An interface layer structure (220) is located between the third surface (103) and the glass structure (250).

2. A semiconductor device as claimed in claim 1, The non-metallic element includes at least one of nitrogen, oxygen or phosphorus.

3. A semiconductor device as claimed in any one of the preceding claims, The passivation coating (210) comprises a layer structure, the layer structure comprising at least one of an oxide layer, a nitride layer, an oxynitride layer or a layer containing carbon.

4. A semiconductor device as claimed in any one of the preceding claims, The third surface (103) includes an inner sidewall (401) of a trench structure (400) that laterally surrounds a central portion (195) of the silicon carbide portion (100).

5. The semiconductor device according to any one of claims 1 to 3, The third surface (103) forms at least a portion of a lateral surface (109) connecting an edge of the first surface (101) and an edge of the second surface (102).

6. A semiconductor device as claimed in the preceding claim, The third surface (103) connects the edge of the first surface (101) and the edge of the second surface (102).

7. A semiconductor device as claimed in any one of the preceding claims, The silicon carbide portion (100) comprises a heavily doped substrate portion (130) of a first conductivity type and a lighter doped main layer (140) of the first conductivity type between the first surface (101) and the substrate portion (130), and wherein the third surface (103) laterally exposes the main layer (140) and the substrate portion (130).

8. A semiconductor device as claimed in any one of the preceding claims, The interface layer structure (220) includes a surface portion (222) on the first surface (101).

9. A semiconductor device as claimed in the preceding claim, The glass structure (250) includes a horizontal portion (252) formed on the interface layer structure (220).

10. The semiconductor device according to the preceding claim, further comprising: A first metal structure (310) is in direct contact with the first surface (101) of the silicon carbide portion (100) and the interface layer structure (220).

11. A semiconductor device as claimed in the preceding claim, The first vertical extent v1 of the surface portion (222) of the interface layer structure (220) is at least 80% and at most 120% of the second vertical extent v2 of the first metal structure (310).

12. The semiconductor device according to claim 10, The first vertical extent v1 of the surface portion (222) of the interface layer structure (220) is less than 80% of the second vertical extent v2 of the first metal structure (310).

13. A semiconductor device as claimed in the preceding claim, The total thickness v3 of the interface layer structure (220) and the horizontal portion (252) of the glass structure (250) is equal to the second vertical extent v2 of the first metal structure (310).

14. A semiconductor device as claimed in the preceding claim, The first metal structure (310) and the horizontal portion (252) of the glass structure (250) are separated laterally.

15. The semiconductor device according to any one of claims 10 to 14, In the lateral direction, the surface portion (222) of the interface layer structure (220) ends at the first metal structure (310), and the first metal structure (310) ends at the surface portion (222) of the interface layer structure (220).

16. The semiconductor device according to any one of claims 10 to 14, The surface portion (222) of the interface layer structure (220) and the first metal structure (310) overlap in a vertical direction.

17. The semiconductor device according to the preceding claim and claim 7, further comprising: A body / anode region (150) of a second conductivity type complementary to the first conductivity type, wherein the body / anode region (150) is formed between the main layer (140) and the first surface (101).

18. A semiconductor device as claimed in the preceding claim, The main body / anode region (150) is formed to be spaced a certain distance from the interface layer structure (220) and the passivation coating (210).

19. The semiconductor device according to claim 17, further comprising: The field relaxation structure (160) of the second conductivity type laterally surrounds the body / anode region (150), wherein the net doping of the field relaxation structure (160) is lower than the net doping in the body / anode region (150).

20. The semiconductor device according to claim 19, The field relaxation structure (160) is in direct contact with the interface layer structure (220) or the passivation coating (210).

21. The semiconductor device according to claim 19, The field relaxation structure (160) is formed to be spaced a certain distance from the interface layer structure (220) and the passivation coating (210).

22. The semiconductor device according to any one of claims 19 to 21, The field relaxation structure (160) comprises a single field relaxation ring (161).

23. The semiconductor device according to any one of claims 19 to 21, The field relaxation structure (160) comprises a plurality of field relaxation rings (161) separated laterally.

24. The semiconductor device according to any one of claims 19 to 23, further comprising: The first conductive type surface layer (170) is located between the first surface (101) and the field relaxation structure (160).

25. The semiconductor device according to any one of claims 19 to 24, The field relaxation structure (160) comprises a supplementary structure (162), wherein the supplementary structure (162) is in direct contact with the field relaxation ring (161) and has a lower net doping than the field relaxation ring (161).

26. The semiconductor device according to claim 25, The supplementary structure (162) includes a plurality of supplementary rings (163), each supplementary ring (163) being formed between adjacent field relaxation rings (161) or between the innermost field relaxation ring (161) and the main body / anode region (150).

27. A method for manufacturing a semiconductor device, the method comprising: forming a separation trench (740) in a major surface (701) of a single-crystal silicon carbide layer (700), wherein the separation trench (740) surrounds a die portion (710) of the silicon carbide layer (700); treating a first sidewall (741) of the separation trench (740) of the silicon carbide layer (700) during a conditioning process, wherein dangling bonds of the silicon carbide layer (700) are passivated; forming an interface layer (720) on the first sidewall (741) of the separation trench (740); forming a glass filling structure (755) in the separation trench (740); and The silicon carbide layer (700) is separated along a vertical separation line (705) parallel to the separation trench (740).

28. The method according to the preceding claim, The vertical separation line (705) extends through the separation groove (740) and extends along the separation groove (740).

29. The method according to any one of the two preceding claims, Wherein processing the first sidewall (741) comprises plasma-based flash passivation.

30. The method according to any one of the three preceding claims, Wherein processing the first sidewall (741) includes depositing a passivation coating (210) using a precursor material including silicon as a main component.

31. A method according to any one of the preceding four claims, The forming of the glass filling structure (750) includes pressing a glass material into the separation trench (740).

32. The method of any one of the preceding five claims, further comprising: forming a contact layer (311) in a contact section of the major surface (701), wherein the contact layer (311) and the silicon carbide layer (700) form an ohmic contact or a Schottky contact; and A main layer (312) is formed on the contact layer (311), wherein the main layer (312) includes at least one of aluminum (Al) or copper (Cu).

33. The method of claim 32, After forming the main layer (312), the separation trench (740) is formed.

34. The method of claim 32, The separation trench (740) is formed after forming the contact layer (311), and the main layer (312) is formed after forming the glass filling structure (755).

35. The method of claim 34, Wherein a section of the main layer (312) is formed on a section of the glass filling structure (755).

36. The method of any one of claims 27 to 35, further comprising: Prior to separation, the silicon carbide layer (700) is thinned from a side opposite to the major surface (701), wherein the glass filling structure (755) is exposed.

37. The method of any one of claims 27 to 36, further comprising: A gate electrode structure (400) is formed in the silicon carbide layer (700), wherein forming the gate electrode structure (400) includes forming a gate trench (450) extending from the main surface (701) into the silicon carbide layer (700) and forming a gate electrode (430) in the gate trench (450), and wherein the separation trench (740) is formed before forming the gate electrode (430).

38. The method of the preceding claim, further comprising: Before forming the gate electrode (430), the separation trench (740) is filled with an auxiliary material (745), and after forming the contact layer (311), the auxiliary material (745) is removed.

Images