Semiconductor device and manufacturing method thereof
By setting isolation grooves and isolation doping regions on the silicon carbide semiconductor layer, deep junction doping and monolithic integration are achieved, which solves the problem of monolithic integration of silicon carbide devices and improves the performance of the device.
Patent Information
- Application Number
- CN202510003437.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-03-28
AI Technical Summary
Silicon carbide-based materials lack a good implementation solution to realize the monolithic integration of devices, and silicon-based chips have shortcomings in operating temperature, high voltage resistance and radiation resistance.
By setting an isolation groove on the silicon carbide semiconductor layer and the isolation doping region, deep junction doping is achieved and adjacent transistors are separated, thereby achieving monolithic integration of silicon carbide devices.
The monolithic integration of silicon carbide devices is realized, which improves the device's working temperature, high voltage resistance and radiation resistance, and solves the shortcomings of silicon-based chips.
Smart Images
Figure CN119730343A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor device manufacturing, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art
[0002] At present, in the semiconductor chip processing technology, the processing technology that uses single crystal silicon as the substrate material, namely the silicon-based technology, is the most mature. Its process node can be as small as a few nanometers, and the types of devices that can be processed are also the most, including analog circuits, digital circuits, silicon-based optoelectronic devices or circuits, etc.
[0003] However, compared with chips with other materials as substrates, silicon-based chips still have many shortcomings, such as low operating temperature (generally not higher than 150°C), difficulty in making high-voltage devices, and poor radiation resistance. As the third-generation semiconductor, silicon carbide devices have high operating temperatures (normally can work at 175°C or even higher), can withstand high voltages, and have excellent radiation resistance. However, silicon carbide-based materials lack a better solution for realizing monolithic integration of devices. Therefore, it is necessary to provide a new semiconductor device to improve the above problems. Summary of the invention
[0004] In view of this, the present disclosure provides a semiconductor device and a method for manufacturing the same, which realizes deep junction doping on a silicon carbide semiconductor layer by setting an isolation trench and an isolation doping region, thereby separating adjacent transistors and further realizing monolithic integration of silicon carbide devices.
[0005] According to one aspect of an embodiment of the present disclosure, there is provided a semiconductor device, including:
[0006] substrate;
[0007] an epitaxial layer, located on the substrate;
[0008] an isolation trench extending along a surface of the epitaxial layer toward the substrate; and
[0009] an isolation doped region, a portion of which extends from the sidewall of the isolation trench into the epitaxial layer, and another portion of which extends from the bottom of the isolation trench into the substrate,
[0010] Wherein, the material of the substrate includes silicon carbide,
[0011] The isolation doping region is used to separate at least part of the epitaxial layer into a plurality of epitaxial islands, including a first epitaxial island and a second epitaxial island, and corresponding transistors are formed based on the first epitaxial island and the second epitaxial island.
[0012] The substrate and the isolation doped region are of a first conductivity type, the epitaxial layer is of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.
[0013] Optionally, the opening width of the isolation trench is greater than the bottom width of the isolation trench, so that the side wall of the isolation trench is inclined.
[0014] Optionally, a PNP transistor is formed based on the first epitaxial island, and / or an NPN transistor is formed based on the second epitaxial island.
[0015] Optionally, it also includes:
[0016] A first collector region is located below the first epitaxial island and extends from the surface of the substrate into the substrate.
[0017] A collector region lead-out groove extending along the surface of the first epitaxial island toward the substrate;
[0018] A collector region lead-out groove doping region, a portion of which extends from the sidewall of the collector region lead-out groove into the first epitaxial island, and another portion of which extends from the bottom of the collector region lead-out groove into the first collector region;
[0019] A collector lead-out region, located in the first epitaxial island and connected to the collector region lead-out groove doping region;
[0020] a first base region, located in the first epitaxial island; and
[0021] a first emitter region, located in the first base region,
[0022] The first base region is of the first conductivity type, and the first collector region, the collector region lead-out groove doping region, the collector lead-out region and the first emitter region are of the second conductivity type.
[0023] Optionally, the opening width of the collector region lead-out groove is greater than the bottom width of the collector region lead-out groove, so that the side wall of the collector region lead-out groove is inclined.
[0024] Optionally, it also includes:
[0025] A second base region is located below the second epitaxial island and extends from the surface of the substrate into the substrate.
[0026] A base region lead-out groove extending along a surface of the second epitaxial island toward the substrate;
[0027] A base region lead-out groove doping region, a portion of which extends from the sidewall of the base region lead-out groove into the second epitaxial island, and another portion of which extends from the bottom of the base region lead-out groove into the second base region;
[0028] a base lead-out region, located in the second epitaxial island and connected to the base lead-out groove doping region; and
[0029] A second collector region and a second emitter region are located in the second epitaxial island,
[0030] The second collector region and the second emitter region are of the first conductivity type, and the second base region, the base region lead-out groove doping region and the base region lead-out region are of the second conductivity type.
[0031] Optionally, the opening width of the base region lead-out groove is greater than the bottom width of the base region lead-out groove, so that the side wall of the base region lead-out groove is inclined.
[0032] Optionally, it further includes a substrate lead-out region, which is located in the epitaxial layer and connected to the isolation doping region.
[0033] Wherein, the substrate lead-out region is of the first conductivity type.
[0034] Optionally, it also includes:
[0035] a dielectric layer covering the epitaxial layer and filling the isolation trench; and
[0036] A plurality of conductive pillars penetrate the dielectric layer and are used to electrically lead a plurality of ends of the transistor to the surface of the dielectric layer.
[0037] Optionally, it further includes a resistance layer located on the surface of the dielectric layer.
[0038] The resistor formed by the resistor layer is selectively electrically connected to multiple ends of the transistor.
[0039] According to another aspect of an embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising:
[0040] forming an epitaxial layer on a substrate;
[0041] forming an isolation trench in the epitaxial layer, wherein the isolation trench extends along a surface of the epitaxial layer toward the substrate; and
[0042] forming an isolation doped region, wherein a portion of the isolation doped region extends from the sidewall of the isolation trench into the epitaxial layer, and another portion of the isolation doped region extends from the bottom of the isolation trench into the substrate,
[0043] Wherein, the material of the substrate includes silicon carbide,
[0044] The isolation doping region is used to separate at least part of the epitaxial layer into a plurality of epitaxial islands, and corresponding transistors are formed based on at least part of the epitaxial islands.
[0045] The substrate and the isolation doped region are of a first conductivity type, the epitaxial layer is of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.
[0046] Optionally, the opening width of the isolation trench is greater than the bottom width of the isolation trench, so that the side wall of the isolation trench is inclined.
[0047] Optionally, the step of forming the isolation trench includes:
[0048] forming a hard mask layer on the epitaxial layer;
[0049] forming a patterned photoresist layer on the hard mask layer;
[0050] Forming an inverted trapezoidal opening on the hard mask layer through the photoresist layer using isotropic etching processes; and
[0051] etching the epitaxial layer through the opening to form the isolation trench,
[0052] The inclination angle of the sidewall of the isolation groove is controlled by controlling the slope angle of the inverted trapezoidal opening and the etching selection ratio.
[0053] Optionally, the isolation doping region is formed by a vertical implantation process.
[0054] Optionally, it also includes:
[0055] forming a first doped region in the substrate, the first doped region corresponding to below the corresponding epitaxial island;
[0056] forming an extraction groove, wherein the extraction groove extends along the surface of the corresponding epitaxial island toward the substrate; and
[0057] forming a second doped region, a portion of which extends from the sidewall of the lead-out groove into the epitaxial island, and another portion of which extends from the bottom of the lead-out groove into the first doped region,
[0058] The first doped region and the second doped region are of the second conductivity type.
[0059] Optionally, the opening width of the lead-out groove is greater than the bottom width of the lead-out groove, so that the side wall of the lead-out groove is inclined.
[0060] Optionally, the second doped region is formed by a vertical implantation process.
[0061] Optionally, the method further comprises forming a substrate lead-out region in the epitaxial layer,
[0062] The substrate lead-out region is of the first conductivity type and is connected to the isolation doping region.
[0063] One of the above technical solutions has the following beneficial effects:
[0064] The isolation groove is extended from the surface of the epitaxial layer to the vicinity of the surface of the substrate, and the inner surface of the isolation groove is doped to form an isolation doping region, wherein a portion of the isolation doping region extends from the sidewall of the isolation groove into the epitaxial layer, and another portion extends from the bottom of the isolation groove into the substrate. Since the conductivity type of the substrate and the epitaxial layer is opposite, and the conductivity type of the isolation doping region and the substrate is the same, the structure of the isolation groove + isolation doping region realizes deep junction doping on the silicon carbide semiconductor layer, and separates the epitaxial layer into multiple islands, so that transistors formed based on different islands can be isolated, thereby realizing monolithic integration of silicon carbide devices.
[0065] In some embodiments, a first collector region is provided in the substrate, and the first collector region corresponds to the bottom of the first epitaxial island, and the collector of the transistor is extended from the substrate (the bottom of the device) with low resistance and led to the front of the device through the structure of the collector region lead-out groove + the collector region lead-out groove doping region, thereby reducing the series resistance of the collector of the transistor and reducing the collector-emitter saturation voltage drop V CESAT . Compared with using the first epitaxial island directly as the collector region of the transistor, using the first collector region + the collector region lead-out groove doping region together as the collector region of the transistor has the advantages of high doping concentration, low resistance, and small saturation voltage drop. In addition, setting the first collector region in the substrate makes full use of the vertical space of the device, which not only saves space in the first epitaxial island, making the layout of the first base region and the first emitter region in the first epitaxial island more flexible, but also the first collector region located in the substrate can also have a larger design space.
[0066] Similarly, a second base region is set in the substrate, and the second base region corresponds to the bottom of the second epitaxial island, and the base of the transistor is extended from the bottom of the device with low resistance and led to the front of the device through the structure of the base lead-out groove + the base lead-out groove doping region, which also has similar advantages as mentioned above.
[0067] In some embodiments, a substrate lead-out region is provided in the epitaxial layer, and the substrate, the isolation doping region, and the substrate lead-out region have the same conductivity type and are sequentially connected, thereby realizing the substrate potential being led out from the front side of the device. Compared with the solution of providing a back electrode on the back side of the substrate, bonding the back electrode to the packaging frame, and then connecting the electrode to be connected to the front side of the device through wire bonding, the structure of the isolation doping region + substrate lead-out region can save the steps of forming the back electrode and wire bonding, guide all the electrodes in the device to the front side, and reduce the resistance during circuit connection.
[0068] In some embodiments, the opening width of the isolation trench is greater than the bottom width of the isolation trench, so that the sidewalls of the isolation trench are inclined. Therefore, only a vertical injection process is needed to dope the bottom and sidewalls of the isolation trench to form an isolation doping region. There is no need to adjust the injection angle, and the process is low in difficulty and cost.
[0069] Similarly, the side walls of the collector region lead-out groove and the base region lead-out groove are also inclined, and the collector region lead-out groove doping region and the base region lead-out groove doping region can both be formed by a vertical injection process.
[0070] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0071] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.
[0072] Figure 1a A schematic diagram of the top structure of a semiconductor device in an embodiment of the present disclosure is shown.
[0073] Figure 1b Shown along Figure 1a Cross-sectional view taken along line AA.
[0074] Figures 2 to 13 The invention shows cross-sectional views of some stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0075] The present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements or parts are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, a semiconductor structure obtained after several steps can be described in one figure.
[0076] In the related art, a dielectric isolation structure is used to laterally isolate the silicon carbide metal-oxide semiconductor field-effect transistor (MOSFET), thereby realizing the monolithic integration of silicon carbide MOSFET. However, dielectric isolation cannot achieve good lead-out between the substrate and the buried layer. Therefore, for bipolar silicon carbide transistors, it is difficult to obtain an integrated product with relatively ideal performance parameters by simply using dielectric isolation. Therefore, it is necessary to provide a new semiconductor device to improve the above problems.
[0077] Figure 1a FIG. 1 shows a schematic diagram of a top view of a semiconductor device in an embodiment of the present disclosure. Figure 1b Shown along Figure 1a The cross-sectional view taken along line AA, where: Figure 1a The dielectric layer and the metal interconnection structure in and on the surface of the dielectric layer are not shown. Figure 1b The wiring layers on the dielectric layer are not shown.
[0078] like Figure 1a and Figure 1b As shown, the semiconductor device in the embodiment of the present disclosure includes: a substrate 101, a first collector region 111, a second base region 112, an epitaxial layer 120, an isolation groove 102, a collector region lead-out groove 103, a base region lead-out groove 104, an isolation doped region 130, a collector region lead-out groove doped region 141, a base region lead-out groove doped region 142, a first base region 151, a second collector region 152, a second emitter region 153, a substrate lead-out region 154, a first emitter region 161, a collector lead-out region 162, a base region lead-out region 163, a dielectric layer 170, a plurality of conductive pillars 180 and a wiring layer.
[0079] The substrate 101, the isolation doping region 130, the first base region 151, the second collector region 152, the second emitter region 153 and the substrate lead-out region 154 are of the first conductivity type, and the first collector region 111, the second base region 112, the epitaxial layer 120, the collector lead-out groove doping region 141, the base lead-out groove doping region 142, the first emitter region 161, the collector lead-out region 162 and the base lead-out region 163 are of the second conductivity type. The first conductivity type is opposite to the second conductivity type. The first conductivity type is selected from one of the P type and the N type, and the second conductivity type is selected from the other of the P type and the N type. In the following, the first conductivity type is P type and the second conductivity type is N type for example.
[0080] In this embodiment, the materials of the substrate 101 and the epitaxial layer 120 both include silicon carbide. The epitaxial layer 120 is located on the substrate 101. The isolation trench 102 extends along the surface of the epitaxial layer 120 toward the substrate 101, and extends to the vicinity of the surface of the substrate 101. Preferably, the bottom of the isolation trench 102 is just located on the surface of the substrate 101 or is located in the substrate 101 near the surface of the substrate 101. Preferably, the opening width of the isolation trench 102 is greater than the bottom width, so that the sidewall of the isolation trench 102 is inclined.
[0081] A portion of the isolation doped region 130 extends from the sidewall of the isolation trench 102 into the epitaxial layer 120, and another portion extends from the bottom of the isolation trench 102 into the substrate 101. The isolation doped region 130 is used to separate at least a portion of the epitaxial layer 120 into a plurality of epitaxial islands. Figure 1a and Figure 1bOnly two epitaxial islands are shown, namely the first epitaxial island 121 and the second epitaxial island 122. A first transistor is formed based on the first epitaxial island 121, and a second transistor is formed based on the second epitaxial island 122, wherein the first transistor is a vertical NPN transistor and the second transistor is a lateral PNP transistor. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may make other settings for the number of epitaxial islands and the type of transistors formed based on the epitaxial islands as needed.
[0082] The first collector region 111 is located in the substrate 101 and corresponds to the first epitaxial island 121. The collector region lead-out groove 103 extends from the surface of the first epitaxial island 121 toward the substrate 101 and extends to the vicinity of the surface of the substrate 101. Preferably, the bottom of the collector region lead-out groove 103 is just located on the surface of the substrate 101 or located in the first collector region 111 near the surface of the substrate 101. Preferably, the opening width of the collector region lead-out groove 103 is greater than the bottom width, so that the side wall of the collector region lead-out groove 103 is inclined. A part of the collector region lead-out groove doping region 141 extends from the side wall of the collector region lead-out groove 103 to the first epitaxial island 121, and another part extends from the bottom of the collector region lead-out groove 103 to the first collector region 111. The collector lead-out region 162 is located in the first epitaxial island 121 and is connected to the collector region lead-out groove doping region 141. The first base region 151 is located in the first epitaxial island 121 and is separated from the collector lead-out region 162. The first emitter region 161 is located in the first base region 151.
[0083] In this embodiment, the first collector region 111, the first epitaxial island 121, the collector region lead-out groove doping region 141, the first base region 151, the first emitter region 161 and the collector lead-out region 162 are used to form a vertical NPN transistor. The first collector region 111 and the collector region lead-out groove doping region 141 together serve as the collector region of the NPN transistor, wherein, by increasing the doping concentration of the collector region lead-out groove doping region 141, the collector region of the NPN transistor is led from the bottom of the device to the front of the device with low resistance for collector lead-out, thereby reducing the collector-emitter saturation voltage drop V of the NPN transistor. CESAT .
[0084] The second base region 112 is located in the substrate 101 and corresponds to the position directly below the second epitaxial island 122. The base lead-out groove 104 extends from the surface of the second epitaxial island 122 toward the substrate 101 and extends to the vicinity of the surface of the substrate 101. Preferably, the bottom of the base lead-out groove 104 is just located on the surface of the substrate 101 or located in the second base region 112 near the surface of the substrate 101. Preferably, the opening width of the base lead-out groove 104 is greater than the bottom width, so that the side wall of the base lead-out groove 104 is inclined. A part of the base lead-out groove doping region 142 extends from the side wall of the base lead-out groove 104 to the second epitaxial island 122, and another part extends from the bottom of the base lead-out groove 104 to the second base region 112. The second collector region 152, the second emitter region 153 and the base lead-out region 163 are all located in the second epitaxial island 122 and are separated from each other. The base lead-out region 163 is connected to the base lead-out groove doping region 142 .
[0085] In this embodiment, the second base region 112, the second epitaxial island 122, the base extraction groove doping region 142, the second collector region 152, the second emitter region 153 and the base extraction region 163 are used to form a lateral PNP transistor. The second base region 112 and the base extraction groove doping region 142 together serve as the base region of the PNP transistor, wherein the base region of the PNP transistor is led from the bottom of the device to the front of the device with low resistance for base extraction by increasing the doping concentration of the base extraction groove doping region 142, thereby reducing the saturation voltage drop of the PNP transistor.
[0086] The substrate lead-out region 154 is located in the epitaxial layer 120 outside the first epitaxial island 121 and the second epitaxial island 122 and is connected to the isolation doping region 130. By increasing the doping concentration of the isolation doping region 130, the low-resistance ground of the substrate 101 is led to the front side of the device.
[0087] In this embodiment, a groove 10 is further provided in the epitaxial layer 120 outside the first epitaxial island 121 and the second epitaxial island 122 as an alignment mark, and the alignment mark may be located in a dicing path of the wafer, and after the dicing step, the actual device does not include the groove 10. If the alignment mark is provided in a dummy area inside the device, the actual device includes the groove 10 after the dicing step.
[0088] The dielectric layer 170 covers the epitaxial layer 120 and fills the isolation groove 102, the collector lead-out groove 103, the base lead-out groove 104 and the groove 10. A plurality of conductive pillars 180 penetrate the dielectric layer 170 and are respectively connected to the first emitter region 161, the first base region 151, the collector lead-out region 162, the base lead-out region 163, the second collector region 152, the second emitter region 153 and the substrate lead-out region 154, so as to electrically lead the multiple ends of the NPN transistor and the PNP transistor and the substrate 101 to the surface of the dielectric layer 170.
[0089] In some optional embodiments, a resistance layer may be provided on the surface of the dielectric layer 170. The material of the resistance layer may include, for example, doped polysilicon or a high-resistance metal film. The resistance layer is used to form a resistor, and may be selectively electrically connected to multiple ends of an NPN transistor or a PNP transistor, or connected to other devices to form a desired circuit.
[0090] Figures 2 to 13 The invention shows cross-sectional views of some stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0091] like Figure 2 As shown, a groove 10 is formed in the scribe line of the silicon carbide wafer (substrate 101) by etching or other methods. The groove 10 is used as an alignment mark for photolithography positioning in subsequent processes, including photolithography before epitaxy and photolithography after epitaxy. Since epitaxial growth is isotropic growth, in order to avoid the situation where the opening of the groove 10 is closed after the epitaxy step and cannot be identified, the size of the opening of the groove 10 can be set to be more than twice the thickness of the epitaxial layer 120. Among them, the conductivity type of the substrate 101 is P type.
[0092] Further, a first doping region is formed in the substrate 101. In this step, for example, a mask layer is first deposited on the substrate 101, and then the mask layer is patterned by photolithography and etching processes to form an injection mask. Afterwards, the substrate 101 is doped by a high-temperature injection process to form a first doping region, wherein the conductivity type of the first doping region is N-type. In this embodiment, the first doping region includes a first collector region 111 and a first base region 112.
[0093] In some preferred embodiments, after forming the first doped region, a high temperature annealing process is required to repair the lattice defects of the substrate 101, thereby improving the quality of the epitaxial layer 120 in subsequent steps.
[0094] Furthermore, an epitaxial layer 120 is formed on the substrate 101, such as Figure 3 In this step, the groove 10 is transferred to the surface of the epitaxial layer 120, wherein the conductivity type of the epitaxial layer 120 is N type.
[0095] Furthermore, a hard mask layer 11 is formed on the epitaxial layer 120, such as Figure 4As shown. In this step, the hard mask layer 11 is formed by, for example, a deposition process. In this embodiment, the selection of the hard mask layer 11 needs to consider, on the one hand, that it has good injection masking performance, and on the other hand, that it needs to have good isotropic corrosion performance, so as to form a good slope morphology in the next step. At the same time, it also needs to be able to adapt to the temperature requirements of subsequent injections, such as high-temperature injection. Therefore, the hard mask layer 11 needs to be able to withstand the corresponding temperature. Based on the above conditions, the material of the hard mask layer 11 is preferably silicon dioxide.
[0096] Furthermore, a photoresist layer 12 is formed on the hard mask layer 11 . In this step, a photolithography process is required to pattern the photoresist layer 12 , so as to open a groove 12 a in the photoresist layer 12 .
[0097] Further, an opening 11a is formed in the hard mask layer 11, such as Figure 5 In this step, for example, an isotropic etching process is used to form an inverted trapezoidal opening 11a on the hard mask layer 11 through the groove 12a of the photoresist layer 12. Further, the photoresist layer 12 is removed, as shown in FIG. Figure 6 shown.
[0098] Furthermore, the epitaxial layer 120 is etched through the opening 11a of the hard mask layer 11 to form an isolation trench 102, as shown in FIG. Figure 7 As shown. In this step, the etching depth can be selected to be greater than or equal to the thickness of the epitaxial layer 120, so that the bottom of the isolation groove 102 is located near the surface of the substrate 101. Among them, the opening width of the isolation groove 102 is greater than the bottom width. This is because the opening 11a of the hard mask layer 11 has an inverted trapezoidal morphology, and the thickness of the hard mask layer 11 changes from thick to thin from the place far away from the opening 11a to the opening 11a. The etching gas also has a certain etching ability on the hard mask layer 11, so that the morphology of the isolation groove 102 formed by etching the silicon carbide epitaxial layer 120 also presents an inverted trapezoidal shape with inclined side walls. The inclination angle of the side wall of the isolation groove 102 is determined by two aspects. One is the inclination angle of the side wall of the opening 11a of the hard mask layer 11, and the other is determined by the etching selectivity of the etching process to the hard mask layer 11 and the epitaxial layer 120. Therefore, the inclination angle of the sidewall of the isolation trench 102 can be controlled by controlling the slope angle of the opening 11 a of the hard mask layer 11 and the selection ratio of etching the epitaxial layer 120 .
[0099] Furthermore, an isolation doping region 130 is formed through the opening 11a of the hard mask layer 11, such as Figure 8 As shown. In this step, the isolation doping region 130 is formed by a vertical implantation process with a tilt angle of 0 degrees. The conductivity type of the isolation doping region 130 is the same as that of the substrate 101, a portion of which extends from the sidewall of the isolation trench 102 into the epitaxial layer 120, and another portion of which extends from the bottom of the isolation trench 102 into the substrate 101, thereby achieving the connection between the isolation doping region 130 and the substrate 101.
[0100] Since the materials of the substrate 101 and the epitaxial layer 120 are both silicon carbide, and the diffusion temperature of silicon carbide is extremely high, it is generally impossible to diffuse the doped ions to a long distance through high temperature annealing like silicon-based wafers, so the conventional solution cannot form deep junctions and lateral diffusion, that is, it is impossible to form Figure 8 The structure shown is that the P-type layer on the surface of the epitaxial layer 120 is connected to the P-type substrate at the bottom of the epitaxial layer 120 .
[0101] If the sidewalls of the isolation trench 102 are etched into a relatively steep shape, it is difficult to implant doping ions into the sidewalls by the implantation process. When the isolation trench 102 is deep, it is even more difficult to implant doping into the sidewalls by adjusting the implantation angle. In this embodiment, the sidewalls of the isolation trench 102 are set to be inclined, and implant doping into the sidewalls of the isolation trench 102 can be achieved by only using a vertical implantation process.
[0102] In this embodiment, the P-type isolation doping region 130 separates at least part of the epitaxial layer 120 into a plurality of N-type epitaxial islands, including a first epitaxial island 121 and a second epitaxial island 122, which can reduce the interference of external factors on the internal device. Fig. 9 shown.
[0103] Further, a lead-out groove and a second doping region are formed, such as Fig.10 As shown. The lead-out groove includes a collector region lead-out groove 103 and a base region lead-out groove 104. The conductivity type of the second doped region is N-type, including a collector region lead-out groove doping region 141 and a base region lead-out groove doping region 142. The steps for forming the lead-out groove and the second doped region are similar to the steps for forming the isolation groove 102 and the isolation doped region 130, and are not repeated here. The opening width of the lead-out groove is greater than the bottom width, so that the side wall of the lead-out groove is inclined, thereby forming the second doped region by a vertical injection process.
[0104] Furthermore, a third doping region is formed in the epitaxial layer 120, such as Fig.11 As shown. The conductivity type of the third doping region is P type, including a first base region 151, a second collector region 152, a second emitter region 153 and a substrate lead-out region 154. In this step, for example, the first base region 151 is formed in the first epitaxial island 121 by depositing an injection masking film, photolithography, etching the injection masking film, removing the photoresist, ion implantation, etc., the second collector region 152 and the second emitter region 153 are formed in the second epitaxial island 122, and the substrate lead-out region 154 is formed in the epitaxial layer 120 outside the first epitaxial island 121 and the second epitaxial island 122, and the substrate lead-out region 154 is connected to the isolation doping region 130. Then, the implanted ions are activated by processes such as high temperature annealing.
[0105] Furthermore, a fourth doping region is formed in the first epitaxial island 121 and the second epitaxial island 122, such as Fig.12 As shown. The conductivity type of the fourth doping region is N-type, including a first emitter region 161 located in the first base region 151, a collector lead region 162 located in the first epitaxial island 121, and a base lead region 163 located in the second epitaxial island 122. The collector lead region 162 is connected to the collector lead groove doping region 141, and the base lead region 163 is connected to the base lead groove doping region 142. In this step, the fourth doping region is formed, for example, by depositing an injection mask film, photolithography, etching the injection mask film, removing the photoresist, ion implantation, etc. Then, the implanted ions are activated by processes such as high temperature annealing.
[0106] Furthermore, a dielectric layer 170 is formed on the epitaxial layer 120, such as Fig.13 The dielectric layer 170 covers the surface of the epitaxial layer 120 and fills the groove 10 , the isolation groove 102 , the collector region lead-out groove 103 and the base region lead-out groove 104 .
[0107] Furthermore, a plurality of conductive pillars 180 are formed in the dielectric layer 170, thereby forming Figure 1a and Figure 1b In this step, for example, a plurality of through holes are first etched in the dielectric layer 170, and then metal is deposited in the through holes to form circuit connections. Optionally, polysilicon can be deposited and doped or a high-resistance metal film can be deposited on the surface of the dielectric layer 170 as required, and the required resistors can be formed by photolithography, etching and other processes, and these resistors are connected to other devices through metal connections to form the required circuit.
[0108] The semiconductor device and the manufacturing method thereof provided by the present disclosure have at least the following advantages:
[0109] The isotropic etching characteristics of the hard mask layer 11 form an opening 11a with an oblique angle morphology, and then the epitaxial layer 120 is etched to obtain a silicon carbide injection window (such as the isolation groove 102) with the same oblique angle morphology, and then vertical injection is performed through the window to obtain a deep groove with a well-doped sidewall. This structure and method realize deep junction doping on a silicon carbide wafer.
[0110] This scheme uses the method of bevel etching and implantation to first achieve PN junction isolation (see Fig. 9 The isolation doping region 130) is then used to allow the back electrode to be led out to the front side (see Fig.11 The substrate lead-out region 154 is provided to facilitate setting the ground end of the circuit to zero potential; at the same time, the collector region of the vertical NPN and the base region of the lateral PNP are extended from the bottom of the device with low resistance and led to the front side (see Fig.10The collector region lead-out groove doping region 141 and the base region lead-out groove doping region 142 reduce the collector region resistance of the vertical NPN transistor and the base region resistance of the lateral PNP transistor, thereby greatly improving the performance of the device.
[0111] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.
Claims
1. A semiconductor device, comprising: substrate; an epitaxial layer, located on the substrate; An isolation trench extending along a surface of the epitaxial layer toward the substrate; as well as an isolation doped region, a portion of which extends from the sidewall of the isolation trench into the epitaxial layer, and another portion of which extends from the bottom of the isolation trench into the substrate, Wherein, the material of the substrate includes silicon carbide, The isolation doping region is used to separate at least part of the epitaxial layer into a plurality of epitaxial islands, including a first epitaxial island and a second epitaxial island, and corresponding transistors are formed based on the first epitaxial island and the second epitaxial island. The substrate and the isolation doped region are of a first conductivity type, the epitaxial layer is of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.
2. The semiconductor device according to claim 1, wherein The opening width of the isolation groove is greater than the bottom width of the isolation groove, so that the side wall of the isolation groove is inclined.
3. The semiconductor device according to claim 1, wherein A PNP transistor is formed based on the first epitaxial island, and / or an NPN transistor is formed based on the second epitaxial island.
4. The semiconductor device according to claim 1, further comprising: A first collector region is located below the first epitaxial island and extends from the surface of the substrate into the substrate. A collector region lead-out groove extending along the surface of the first epitaxial island toward the substrate; A collector region lead-out groove doping region, a portion of which extends from the sidewall of the collector region lead-out groove into the first epitaxial island, and another portion of which extends from the bottom of the collector region lead-out groove into the first collector region; A collector lead-out region, located in the first epitaxial island and connected to the collector region lead-out groove doping region; A first base region, located in the first epitaxial island; as well as a first emitter region, located in the first base region, The first base region is of the first conductivity type, and the first collector region, the collector region lead-out groove doping region, the collector lead-out region and the first emitter region are of the second conductivity type.
5. The semiconductor device according to claim 4, wherein: The opening width of the collector region lead-out groove is greater than the bottom width of the collector region lead-out groove, so that the side wall of the collector region lead-out groove is inclined.
6. The semiconductor device according to any one of claims 1 to 5, further comprising: A second base region is located below the second epitaxial island and extends from the surface of the substrate into the substrate. A base region lead-out groove extending along a surface of the second epitaxial island toward the substrate; A base region lead-out groove doping region, a portion of which extends from the sidewall of the base region lead-out groove into the second epitaxial island, and another portion of which extends from the bottom of the base region lead-out groove into the second base region; A base region lead-out region, located in the second epitaxial island and connected to the base region lead-out groove doping region; as well as A second collector region and a second emitter region are located in the second epitaxial island, The second collector region and the second emitter region are of the first conductivity type, and the second base region, the base region lead-out groove doping region and the base region lead-out region are of the second conductivity type.
7. The semiconductor device according to claim 6, wherein: The opening width of the base region lead-out groove is greater than the bottom width of the base region lead-out groove, so that the side wall of the base region lead-out groove is inclined.
8. The semiconductor device according to claim 1 or 2, further comprising a substrate lead-out region located in the epitaxial layer and connected to the isolation doping region, in, The substrate lead-out region is of the first conductivity type.
9. The semiconductor device according to claim 1 or 2, further comprising: a dielectric layer covering the epitaxial layer and filling the isolation trench; as well as A plurality of conductive pillars penetrate the dielectric layer and are used to electrically lead a plurality of ends of the transistor to the surface of the dielectric layer.
10. The semiconductor device according to claim 9, further comprising a resistance layer located on the surface of the dielectric layer, in, The resistor formed by the resistor layer is selectively electrically connected to multiple ends of the transistor.
11. A method for manufacturing a semiconductor device, comprising: forming an epitaxial layer on a substrate; forming an isolation trench in the epitaxial layer, wherein the isolation trench extends along a surface of the epitaxial layer toward the substrate; as well as forming an isolation doped region, wherein a portion of the isolation doped region extends from the sidewall of the isolation trench into the epitaxial layer, and another portion of the isolation doped region extends from the bottom of the isolation trench into the substrate, Wherein, the material of the substrate includes silicon carbide, The isolation doping region is used to separate at least part of the epitaxial layer into a plurality of epitaxial islands, and corresponding transistors are formed based on at least part of the epitaxial islands. The substrate and the isolation doped region are of a first conductivity type, the epitaxial layer is of a second conductivity type, and the first conductivity type is opposite to the second conductivity type.
12. The manufacturing method according to claim 11, wherein: The opening width of the isolation groove is greater than the bottom width of the isolation groove, so that the side wall of the isolation groove is inclined.
13. The manufacturing method according to claim 12, wherein: The steps of forming the isolation trench include: forming a hard mask layer on the epitaxial layer; forming a patterned photoresist layer on the hard mask layer; Forming an inverted trapezoidal opening on the hard mask layer through the photoresist layer using isotropic etching processes; and etching the epitaxial layer through the opening to form the isolation trench, The inclination angle of the sidewall of the isolation groove is controlled by controlling the slope angle of the inverted trapezoidal opening and the etching selection ratio.
14. The manufacturing method according to claim 12, wherein: The isolation doping region is formed by a vertical implantation process.
15. The manufacturing method according to any one of claims 11 to 14, further comprising: forming a first doped region in the substrate, the first doped region corresponding to below the corresponding epitaxial island; forming an extraction groove, wherein the extraction groove extends along the surface of the corresponding epitaxial island toward the substrate; as well as forming a second doped region, a portion of which extends from the sidewall of the lead-out groove into the epitaxial island, and another portion of which extends from the bottom of the lead-out groove into the first doped region, The first doped region and the second doped region are of the second conductivity type.
16. The manufacturing method according to claim 15, wherein: The opening width of the lead-out groove is greater than the bottom width of the lead-out groove, so that the side wall of the lead-out groove is inclined.
17. The manufacturing method according to claim 16, wherein: The second doping region is formed by a vertical implantation process.
18. The manufacturing method according to any one of claims 11 to 14, further comprising forming a substrate lead-out region in the epitaxial layer, in, The substrate lead-out region is of the first conductivity type and is connected to the isolation doping region.