Semiconductor device including substrate structure

Abstract

A semiconductor device may include a first semiconductor structure including a first device layer on an upper surface of a first substrate structure, the first device layer including a first region of the semiconductor device; and a second semiconductor structure including a second device layer on a lower surface of the second substrate structure, the second device layer connected to the first device layer and including a second region of the semiconductor device. The first substrate structure may include a first wafer and a second wafer on the first wafer. The second wafer may be in contact with the first device layer. The second substrate structure may include a third wafer and a fourth wafer on a lower surface of the third wafer. The fourth wafer may be in contact with the second device layer. The upper surface of the second wafer may be a (100) crystal face.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0126183 filed in the Korean Intellectual Property Office on September 21, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure are directed to a semiconductor device including a substrate structure. Background Art

[0004] A wafer corresponding to a semiconductor substrate may be used in a semiconductor device. The wafer may have a disk shape by cutting an ingot, which is a single crystal column formed by growing silicon (Si), gallium arsenide (GaAs), etc. The surface of the wafer may have a specific crystal plane according to the growth direction of the ingot, the cutting direction of the ingot, etc. Depending on the crystal plane, the mechanical / chemical properties of the wafer may vary. Summary of the invention

[0005] Example embodiments of the present disclosure provide a semiconductor device including a substrate structure having improved uniformity of mechanical rigidity and / or chemical characteristics.

[0006] According to an example embodiment of the present disclosure, a semiconductor device may include: a first semiconductor structure including a first substrate structure and a first device layer on an upper surface of the first substrate structure, the first device layer including a first region of the semiconductor device; and a second semiconductor structure including a second substrate structure and a second device layer on a lower surface of the second substrate structure, the second device layer being connected to the first device layer and including a second region of the semiconductor device. The first substrate structure may include a first wafer and a second wafer on the first wafer. The second wafer may be in contact with the first device layer. The second substrate structure may include a third wafer and a fourth wafer on a lower surface of the third wafer. The fourth wafer may be in contact with the second device layer. The upper surface of the second wafer may be a (100) crystal plane.

[0007] According to an example embodiment of the present disclosure, a semiconductor device may include: a first semiconductor structure including a first substrate structure and a first device layer on an upper surface of the first substrate structure, the first device layer including a first region of the semiconductor device; and a second semiconductor structure including a second substrate structure and a second device layer on a lower surface of the second substrate structure, the second device layer being connected to the first device layer and including a second region of the semiconductor device. The first substrate structure may include a plurality of wafers stacked vertically. In the first substrate structure, the plurality of wafers may be stacked so that their upper surfaces may have the same crystal plane and the crystal directions may be tilted relative to each other, or a portion of the upper surfaces of the plurality of wafers may have different crystal planes.

[0008] According to an example embodiment of the present disclosure, a semiconductor device may include: a first semiconductor structure including a first substrate structure, a first region of the semiconductor device on an upper surface of the first substrate structure, and a first bonding metal layer on the first region; and a second semiconductor structure including a second substrate structure, a second region of the semiconductor device on a lower surface of the second substrate structure, and a second bonding metal layer below the second region and bonded to the first bonding metal layer. The first substrate structure and the second substrate structure may each include a plurality of wafers stacked vertically. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0011] Figure 2 is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0012] Figure 3A and Figure 3B are a cross-sectional view and an exploded perspective view showing a substrate structure according to an example embodiment of the present disclosure;

[0013] Figure 4A and Figure 4B are a cross-sectional view and an exploded perspective view showing a substrate structure according to an example embodiment of the present disclosure;

[0014] Figure 5 is a cross-sectional view showing a substrate structure according to an example embodiment of the present disclosure;

[0015] Figure 6 is an exploded perspective view showing a substrate structure according to an example embodiment of the present disclosure;

[0016] 7A to 7C are a cross-sectional view, an exploded perspective view, and a plan view, respectively, showing a substrate structure according to an example embodiment of the present disclosure;

[0017] Figure 8 is a cross-sectional view showing a substrate structure according to an example embodiment of the present disclosure;

[0018] Fig. 9 is an exploded perspective view showing a substrate structure according to an example embodiment of the present disclosure;

[0019] Fig.10 is a cross-sectional view showing a substrate structure according to an example embodiment of the present disclosure;

[0020] Fig.11 and Fig.12 is an exploded perspective view showing a substrate structure according to an example embodiment of the present disclosure;

[0021] Fig.13A and Fig. 13B is a flow chart illustrating a method of manufacturing a semiconductor device including a substrate structure according to an example embodiment of the present disclosure;

[0022] Fig.14 and Fig.15 is a diagram illustrating a method of manufacturing a semiconductor device including a substrate structure according to an example embodiment of the present disclosure; and

[0023] Fig.16A and Fig. 16B is a diagram illustrating characteristics of a semiconductor device including a substrate structure according to example embodiments of the present disclosure. DETAILED DESCRIPTION

[0024] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value includes a manufacturing tolerance or an operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "generally" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the freedom of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including a manufacturing tolerance or an operating tolerance (e.g., ±10%) around the numerical value or shape.

[0025] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0026] Figure 1 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0027] Reference Figure 1 , the semiconductor device 10 may include a first semiconductor structure S1 and a second semiconductor structure S2 bonded to each other. The first semiconductor structure S1 may include a first substrate structure 100L and a first device layer ER1 disposed on an upper surface of the first substrate structure 100L. The second semiconductor structure S2 may include a second substrate structure 100U and a second device layer ER2 disposed on a lower surface of the second substrate structure 100U.

[0028] Each of the first substrate structure 100L and the second substrate structure 100U may include at least one wafer. In an example embodiment, at least one of the first substrate structure 100L and the second substrate structure 100U may include a plurality of wafers. Each of the plurality of wafers may include a Group IV semiconductor or a Group II IV compound semiconductor. For example, the Group IV semiconductor may include silicon (Si), germanium (Ge), silicon carbide (SiC), or silicon germanium (SiGe). The crystal structure of each of the plurality of wafers may be, for example, a diamond structure or a sphalerite structure. For example, the first substrate structure 100L and / or the second substrate structure 100U may include a plurality of wafers, which may be stacked so that the upper surfaces may have the same crystal plane and their crystal directions may be tilted relative to each other. For example, the first substrate structure 100L and / or the second substrate structure 100U may include a plurality of wafers, and the upper surfaces of at least a portion of the wafers may have different crystal planes. The plurality of wafers may be directly bonded to each other by surface treatment such as plasma treatment, or may be bonded to each other using an adhesive layer. In the case where the plurality of wafers are bonded to each other using an adhesive layer, each of the first substrate structure 100L and the second substrate structure 100U may also include an adhesive layer disposed between the wafers. The following will refer to Figures 3A to 12 The specific structures of the first substrate structure 100L and the second substrate structure 100U are described in more detail.

[0029] The first device layer ER1 may include a first region of a semiconductor device, and the second device layer ER2 may include a second region of a semiconductor device. The semiconductor device may include, for example, a logic semiconductor device, a power semiconductor device, or a memory semiconductor device. The logic semiconductor device may include a microprocessor, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor, a cryptographic processor, a controller, or an application specific integrated circuit (ASIC). The power semiconductor device may include an ultra-small size power device, such as a diode, a thyristor, or a transistor based on a composite material such as SiC or GaN. The memory semiconductor device may include a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a non-volatile memory device such as a flash memory.

[0030] In some example embodiments, the first region may include a logic transistor device, and the second region may include an interconnect structure electrically connected to the logic transistor device, for example, a power line. In some example embodiments, the first region may include a memory cell, and the second region may include a circuit device driving the memory cell.

[0031] The first semiconductor structure S1 and the second semiconductor structure S2 may be bonded to each other by, for example, hybrid bonding including copper (Cu) to copper (Cu) bonding and dielectric to dielectric bonding. A bonding surface BS may be formed between the first semiconductor structure S1 and the second semiconductor structure S2. In the bonding surface BS, the first device layer ER1 may be opposite to the second device layer ER2 and may be bonded to each other so that one surface thereof may contact each other.

[0032] Figure 2 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0033] Reference Figure 2 , the semiconductor device 10a shows Figure 1 In the semiconductor device 10a, the first substrate structure 100L may include a first wafer WF1 and a second wafer WF2 stacked in the Z direction, and the second substrate structure 100U may include a third wafer WF3 and a fourth wafer WF4 stacked in the Z direction.

[0034] In example embodiments, the upper surface of the first wafer WF1 may be a (111) crystal plane, and the upper surface of the second wafer WF2 may be a (100) crystal plane. In this case, the first wafer WF1 and the second wafer WF2 may be referred to as a (111) wafer and a (100) wafer, respectively. The first wafer WF1 and the second wafer WF2 may be stacked so that their crystal directions may or may not be tilted relative to each other. The third wafer WF3 and the fourth wafer WF4 may be (100) wafers, and may be stacked so that their crystal directions may or may not be tilted relative to each other. In addition, the second wafer WF2 and the fourth wafer WF4, which may be bonded to each other, may be stacked so that their crystal directions may or may not be tilted relative to each other. In some example embodiments, the first substrate structure 100L may have the structure of the second substrate structure 100U described above, and the second substrate structure 100U may have the structure of the first substrate structure 100L described above. In some example embodiments, each of the first substrate structure 100L and the second substrate structure 100U may include a (100) wafer that may be stacked so that their crystal directions may be tilted relative to each other. In this case, the tilted wafer may or may not form a bonding surface. In some example embodiments, each of the first substrate structure 100L and the second substrate structure 100U may have a structure in which a (111) wafer and a (100) wafer may be stacked and tilted, and the bonding surface may be defined by the (100) wafer.

[0035] However, in some example embodiments, the first substrate structure 100L and the second substrate structure 100U may be formed from the bottom Figures 3A to 12Furthermore, in some example embodiments, at least one of the first substrate structure 100L and the second substrate structure 100U may include a single wafer.

[0036] The device isolation layer 110 may be formed in the first substrate structure 100L so that an active region may be defined. The device isolation layer 110 and the active region may be formed in the uppermost second wafer WF2, but example embodiments thereof are not limited thereto. A source / drain region 105 including impurities may be disposed in a portion of the active region.

[0037] The first device layer ER1 may be disposed on the upper surface of the second wafer WF2. The first device layer ER1 may include a circuit device 120, a first contact plug 170, a first interconnection line 180, and a first interlayer insulating layer 190 disposed on the first substrate structure 100L. The first device layer ER1 may also include a first bonding via 195 as a bonding structure, a first bonding metal layer 198, and a first bonding insulating layer 199.

[0038] The circuit device 120 may include a planar transistor. Each of the circuit devices 120 may include a gate dielectric layer 122, a spacer layer 124, and a gate electrode 125. The source / drain region 105 may be disposed in the first substrate structure 100L on both sides of the gate electrode 125. The interlayer insulating layer 190 may be disposed on the circuit device 120 on the first substrate structure 100L. The first contact plug 170 may penetrate the interlayer insulating layer 190 and may be connected to the source / drain region 105, and may connect the first interconnect lines 180 on different levels to each other. An electrical signal may be applied to the circuit device 120 through the first contact plug 170. In an area not shown, other contact plugs may also be connected to the gate electrode 125. The first interconnect line 180 may be connected to the first contact plug 170 and may be disposed in multiple layers.

[0039] The first bonding via 195 may be disposed on the upper portion of the uppermost first interconnect line 180 and may be connected to the first interconnect line 180. At least a portion of the first bonding metal layer 198 may be connected to the first bonding via 195 on the first bonding via 195. The first bonding metal layer 198 may be connected to the second bonding metal layer 298 of the second semiconductor structure S2. The first bonding metal layer 198 and the second bonding metal layer 298 together may provide an electrical connection path according to the bonding between the first semiconductor structure S1 and the second semiconductor structure S2. The first bonding via 195 and the first bonding metal layer 198 may include a conductive material, for example, copper (Cu). The first bonding insulating layer 199 may be disposed around the first bonding metal layer 198. The first bonding insulating layer 199 may include a dielectric layer, and for example, may include at least one of SiN, SiON, SiCN, SiOC, SiOCN, and SiO.

[0040] The second device layer ER2 may be disposed on the lower surface of the fourth wafer WF4. The second device layer ER2 may include a second contact plug 270, a second interconnect line 280, and a second interlayer insulating layer 290 disposed on the lower surface of the second substrate structure 100U. The second device layer ER2 may also include a second bonding via 295, a second bonding metal layer 298, and a second bonding insulating layer 299 as a bonding structure.

[0041] The second contact plug 270 and the second interconnection line 280 may be disposed in a plurality of layers in the second interlayer insulating layer 290. In some example embodiments, the second interconnection line 280 may be configured as a power line that supplies power to the circuit device 120.

[0042] The second bonding via 295 and the second bonding metal layer 298 may be disposed below the lowermost second interconnection line 280. The second bonding via 295 may connect the second interconnection line 280 to the second bonding metal layer 298, and the second bonding metal layer 298 may be bonded to the first bonding metal layer 198 of the first semiconductor structure S1. The second bonding insulating layer 299 may be bonded to and connected to the first bonding insulating layer 199 of the first semiconductor structure S1. The second bonding via 295 and the second bonding metal layer 298 may include a conductive material, for example, copper (Cu). The second bonding insulating layer 299 may include a dielectric layer, and for example, may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0043] The bonding surface BS may be formed between the first semiconductor structure S1 and the second semiconductor structure S2. The first semiconductor structure S1 and the second semiconductor structure S2 may be bonded by bonding between the first bonding metal layer 198 and the second bonding metal layer 298 and bonding between the first bonding insulating layer 199 and the second bonding insulating layer 299. The bonding between the first bonding metal layer 198 and the second bonding metal layer 298 may be, for example, copper (Cu) to copper (Cu) bonding, and the bonding between the first bonding insulating layer 199 and the second bonding insulating layer 299 may be, for example, dielectric to dielectric bonding, such as SiCN to SiCN bonding. The first semiconductor structure S1 and the second semiconductor structure S2 may be bonded by a hybrid bonding including copper (Cu) to copper (Cu) bonding and dielectric to dielectric bonding.

[0044] In example embodiments, the semiconductor device 10a is shown to include a transistor type circuit device 120, but the type of semiconductor device included in the semiconductor device 10a is not limited thereto. In some example embodiments, the semiconductor device may further include a memory cell. In some example embodiments, in the semiconductor device, the memory cell structure may be bonded to the peripheral circuit region.

[0045] In the following, reference will be made to Figures 3A to 12 Describe in more detail Figure 1 and Figure 2 The specific structure of the substrate structure including the first substrate structure 100L and the second substrate structure 100U.

[0046] Figure 3A and Figure 3B are a cross-sectional view and an exploded perspective view illustrating a substrate structure according to example embodiments.

[0047] Reference Figure 3A and Figure 3B , the substrate structure 100a may include a first wafer WF1 and a second wafer WF2. The second wafer WF2 may be stacked on an upper surface of the first wafer WF1. The first wafer WF1 and the second wafer WF2 may be formed of the same material, and their upper surfaces may have different crystal planes. For example, the second wafer WF2 may be a (100) wafer, and the first wafer WF1 may be a (111) wafer.

[0048] The first wafer WF1 and the second wafer WF2 may be stacked so that the

[100] direction of the second wafer WF2 and the

[110] direction of the first wafer WF1 may become the same direction, but example embodiments thereof are not limited thereto. In some example embodiments, the first wafer WF1 and the second wafer WF2 may be arranged to be tilted at a desired and / or alternatively predetermined angle (θ) relative to each other, which is different from Figure 3B For example, the angle (θ) may be in the range of 0°≤θ≤90°.

[0049] The second thickness T2a of the second wafer WF2 may be less than the first thickness T1a of the first wafer WF1. For example, the first thickness T1a may be in the range of about 400 μm to about 1000 μm, and the second thickness T2a may be in the range of about 10 μm or less, for example, in the range of about 1 μm to about 10 μm. However, during the process of manufacturing the semiconductor device, the thickness of the substrate structure 100a may be reduced, thereby reducing the thickness of the first wafer WF1. In this case, the relative size of the second thickness T2a of the second wafer WF2 and the first thickness T1a of the first wafer WF1 may vary.

[0050] Each of the first wafer WF1 and the second wafer WF2 may have inherent mechanical and chemical properties depending on the crystal plane of its upper surface. For example, in the case where the upper surface of the wafer is a (100) plane, mechanical properties such as hardness may vary depending on the direction. Therefore, when a single wafer is used to manufacture a product such as Figure 1 and Figure 2When the semiconductor device shown is formed, deformation or warping of the wafer may occur, and uneven distribution of internal residual stress and strain may be caused. In this case, during the photolithography process for manufacturing the semiconductor device, or before and after the wafer-to-wafer (W2W) bonding process (such as bonding with a support wafer for the process and bonding between semiconductor structures), misalignment of the pattern for forming the semiconductor device may occur, making it difficult to perform overlap management. However, in the case of the substrate structure 100a in the example embodiment, the first wafer WF1 and the second wafer WF2 having different crystal planes are bonded to each other, so that the above-mentioned mechanical properties can become uniform throughout the substrate structure 100a, so that when the semiconductor device is manufactured, the process difficulty can be reduced and defects can be reduced.

[0051] Specifically, the (100) wafer may exhibit a relatively large warpage characteristic due to anisotropy of mechanical properties, and the (111) wafer may exhibit a warpage characteristic smaller than that of the (100) wafer. The substrate structure 100a in which the (100) wafer and the (111) wafer are stacked may exhibit a warpage characteristic greater than (e.g., improved over) that of the (111) wafer and smaller than that of the (100) wafer. As a result of simulation, it was confirmed that the warpage in the substrate structure 100a was reduced by about 40% compared to that of the (100) wafer.

[0052] For example, when the substrate structure 100a is used as Figure 1 When the first substrate structure 100L of the semiconductor device 10 is formed, wafers having different crystal planes can be stacked so that the uniformity of mechanical properties can be improved, and since the second wafer WF2 arranged in the uppermost part and including the circuit device 120 formed thereon has a (100) plane, the etching rate can be ensured during the process of forming the circuit device 120.

[0053] Figure 4A and Figure 4B are a cross-sectional view and an exploded perspective view illustrating a substrate structure according to example embodiments.

[0054] Reference Figure 4A and Figure 4B, the substrate structure 100b may include a first wafer to a third wafer WF1, WF2 and WF3 stacked in a vertical direction (e.g., Z direction). The second wafer WF2 may be stacked on the upper surface of the first wafer WF1, and the third wafer WF3 may be stacked on the lower surface of the first wafer WF1. The first wafer to the third wafer WF1, WF2 and WF3 may be formed of materials having the same composition or different compositions. The upper surfaces of the second wafer WF2 and the third wafer WF3 may have the same crystal plane, and the upper surface of the first wafer WF1 may have a different crystal plane from the upper surfaces of the second wafer WF2 and the third wafer WF3. For example, each of the upper surfaces of the second wafer WF2 and the third wafer WF3 may be a (100) crystal plane, and the upper surface of the first wafer WF1 may be a (111) crystal plane.

[0055] The first to third wafers WF1, WF2, and WF3 may be stacked such that the

[100] directions of the second wafer WF2 and the third wafer WF3 align with the

[100] directions of the first wafer WF1. The direction may become the same direction. The second wafer WF2 and the third wafer WF3 may be stacked without being tilted with respect to each other, but example embodiments thereof are not limited thereto.

[0056] The first to third thicknesses T1b, T2b, and T3b of the first to third wafers WF1, WF2, and WF3 may be the same or different. For example, in some example embodiments, the second thickness T2b of the second wafer WF2 in the uppermost portion may be smaller than the first thickness T1b and the third thickness T3b, but example embodiments are not limited thereto.

[0057] The substrate structure 100b may have a structure including a second wafer WF2 and a third wafer WF3 having a relatively high chemical etching rate, and including a first wafer WF1 having isotropic mechanical properties interposed between the second wafer WF2 and the third wafer WF3. Therefore, the mechanical properties of the entire substrate structure 100b may be improved, and the etching rate may be ensured by the second wafer WF2 disposed in the uppermost portion and forming a semiconductor device.

[0058] Figure 5 is a cross-sectional view illustrating a substrate structure according to example embodiments.

[0059] Reference Figure 5 In the substrate structure 100c, the first to third thicknesses T1c, T2c, and T3c of the first to third wafers WF1, WF2, and WF3 may be different from Figure 4A and Figure 4BSpecifically, the first thickness T1c of the first wafer WF1 may be greater than the second thickness T2c and the third thickness T3c. However, in example embodiments, the relative sizes of the first to third thicknesses T1c, T2c, and T3c may vary.

[0060] Figure 6 is an exploded perspective view illustrating a substrate structure according to example embodiments.

[0061] Reference Figure 6 , in the substrate structure 100d, different from Figure 4A and Figure 4B In the example embodiment of the present invention, the second wafer WF2 and the third wafer WF3 may be stacked and tilted relative to each other. Therefore, the crystal orientation corresponding to one direction (for example, R

[100] and R

[100] ) in the first to third wafers WF1, WF2, and WF3 is The second wafer WF2 may be rotated by a first angle (θ) in a counterclockwise direction relative to the reference directions R

[100] and R

[010] . The reference direction may be understood as a direction when the wafer is set to be non-tilted. The third wafer WF3 may be rotated by a second angle (-θ) in a counterclockwise direction relative to the reference direction. The second angle (-θ) may be substantially the same as the first angle (θ).

[0062] 7A to 7C sectional view, exploded perspective view, and plan view respectively illustrate a substrate structure according to example embodiments.

[0063] Reference FIG. 7A to FIG. 7C , the substrate structure 100e may include first to fourth wafers WF1, WF2, WF3, and WF4 stacked in a vertical direction (e.g., Z direction). The first to fourth wafers WF1, WF2, WF3, and WF4 may be stacked upward in the order of the fourth wafer WF4, the third wafer WF3, the first wafer WF1, and the second wafer WF2. The second wafer WF2 may be stacked on the upper surface of the first wafer WF1, the third wafer WF3 may be stacked on the lower surface of the first wafer WF1, and the fourth wafer WF4 may be stacked on the lower surface of the third wafer WF3.

[0064] The first to fourth wafers WF1, WF2, WF3, and WF4 may be formed of the same material, and their upper surfaces may have the same crystal plane. For example, the upper surfaces of the first to fourth wafers WF1, WF2, WF3, and WF4 may be (100) crystal planes. In some example embodiments, at least one of the first to fourth wafers WF1, WF2, WF3, and WF4 may be formed of different materials, and their upper surfaces may have the same crystal plane. The first to fourth thicknesses T1e, T2e, T3e, and T4e of the first to fourth wafers WF1, WF2, WF3, and WF4 may be substantially the same. The concept of "substantially the same" of an element may indicate that the element may be exactly the same, and may also indicate that the element may be determined to be the same in consideration of errors or deviations occurring during the process. In example embodiments, the number of wafers forming the substrate structure 100e may vary.

[0065] The first to fourth wafers WF1, WF2, WF3, and WF4 may be stacked such that their crystal directions may be tilted relative to each other. The substrate structure 100e may have a structure in which the first to fourth wafers WF1, WF2, WF3, and WF4 are angle-ply stacked. Figure 7B and Figure 7C In the example in which the upper surfaces of the first to fourth wafers WF1, WF2, WF3, and WF4 are the (100) crystal planes, reference directions

[100] direction (R

[100] ) and

[010] direction (R

[010] ) may be indicated. The reference direction may be understood as a direction when the wafer is set to be non-tilted.

[0066] In the substrate structure 100e, the tilt angles of the upper and lower wafers may be symmetrical to each other about the center surface CP corresponding to the center in the Z direction, and the tilt directions may be opposite to each other. The first wafer WF1 may be rotated by a first angle (θ1) in a counterclockwise direction relative to the reference direction. The second wafer WF2 may be rotated by a second angle (θ2) greater than the first angle (θ1) in a counterclockwise direction relative to the reference direction. The third wafer WF3 may be rotated by a third angle (-θ1) in a counterclockwise direction relative to the reference direction. The third angle (-θ1) may be substantially the same as the first angle (θ1). That is, the third wafer WF3 may be rotated by an angle substantially the same as the first angle (θ1) in a clockwise direction relative to the reference direction. For example, the third wafer WF3 may be described as being rotated 360°-first angle (θ1) in a counterclockwise direction relative to the reference direction. The fourth wafer WF4 may be rotated by a fourth angle (-θ2) in a counterclockwise direction relative to the reference direction. The fourth angle (-θ2) may be substantially the same as the second angle (θ2). That is, the fourth wafer WF4 may be rotated clockwise relative to the reference direction by an angle substantially the same as the second angle (θ2). For example, the fourth wafer WF4 may be described as being rotated counterclockwise relative to the reference direction by 360°-the second angle (θ2).

[0067] The first angle (θ1) and the large second angle (θ2) may be different from each other and may be within the range of 0°≤θ1 and θ2≤360°. When the first to fourth wafers WF1, WF2, WF3, and WF4 have a diamond crystal structure and a sphalerite crystal structure, the first angle (θ1) and the large second angle (θ2) may be within the range of 0°≤θ1, θ2≤90°, which may be configured as described above in consideration of the fact that when the diamond crystal structure and the sphalerite crystal structure are rotated 180°, the diamond crystal structure and the sphalerite crystal structure may become the same structure, so that the results when rotated 120° and -60° may be the same, and the results when rotated 240° and 60° may be the same. Considering the error in the process, the difference between the first angle (θ1) and the third angle (-θ1) and the difference between the second angle (θ2) and the fourth angle (-θ2) may be, for example, within the range of ±5°.

[0068] Therefore, in the substrate structure 100e, the specific crystal orientations of the first to fourth wafers WF1, WF2, WF3, and WF4 may be different. Figure 7B and Figure 7C As shown, the

[100] directions may be different. The first to fourth wafers WF1, WF2, WF3, and WF4 may have different crystal orientations in the R

[100] direction as a reference direction, for example.

[0069] In the substrate structure 100e in the example embodiment, a plurality of wafers may be bonded by being tilted at different angles, and thus mechanical properties may be uniform throughout the substrate structure 100e compared to a case where a single wafer is used, so that when a semiconductor device is manufactured, process difficulty may be reduced and defects may be reduced.

[0070] Figure 8 is a cross-sectional view illustrating a substrate structure according to example embodiments.

[0071] Reference Figure 8 In the substrate structure 100f, the thicknesses of the first to fourth wafers WF1, WF2, WF3, and WF4 may be different from FIG. 7A to FIG. 7C The thickness in the example embodiment of . Among the first to fourth wafers WF1, WF2, WF3, and WF4, the wafers tilted at substantially the same angle may have substantially the same thickness. The wafers symmetrically disposed with respect to the center surface CP may have substantially the same thickness.

[0072] The first thickness T1f of the first wafer WF1 and the third thickness T3f of the third wafer WF3 may be substantially the same, and the second thickness T2f of the second wafer WF2 and the fourth thickness T4f of the fourth wafer WF4 may be substantially the same. For example, the first thickness T1f and the third thickness T3f may be greater than the second thickness T2f and the fourth thickness T4f, but the relative sizes of the first thickness T1f and the third thickness T3f and the second thickness T2f and the fourth thickness T4f are not limited thereto.

[0073] Fig. 9 is an exploded perspective view illustrating a substrate structure according to example embodiments.

[0074] Reference Fig. 9 The substrate structure 100g may include first to sixth wafers WF1, WF2, WF3, WF4, WF5, and WF6. The substrate structure 100g may also include different FIG. 7A to FIG. 7C The fifth wafer WF5 and the sixth wafer WF6 of the exemplary embodiment of the present invention are stacked on the upper surface of the second wafer WF2, and the sixth wafer WF6 is stacked on the lower surface of the fourth wafer WF4. FIG. 7A to FIG. 7C The description described is applicable to the first to fourth wafers WF1 , WF2 , WF3 , and WF4 .

[0075] The upper surfaces of the first to sixth wafers WF1, WF2, WF3, WF4, WF5 and WF6 may be the same crystal plane, for example, (100) plane. The fifth wafer WF5 and the sixth wafer WF6 may be arranged so that the tilt angles may be symmetrical and their tilt directions may be opposite to each other with respect to the center surface CP.

[0076] The fifth wafer WF5 may be rotated in a counterclockwise direction relative to the reference direction by a fifth angle (θ3) different from the first angle (θ1) and the second angle (θ2). The sixth wafer WF6 may be rotated in a counterclockwise direction relative to the reference direction by a sixth angle (-θ3). The sixth angle (-θ3) may be substantially the same as the fifth angle (θ3). That is, the sixth wafer WF6 may be rotated in a clockwise direction relative to the reference direction by an angle substantially the same as the fifth angle (θ3). For example, the sixth wafer WF6 may be described as being rotated 360°-fifth angle (θ3) in a counterclockwise direction relative to the reference direction. The thickness of the fifth wafer WF5 may be substantially the same as the thickness of the sixth wafer WF6.

[0077] In example embodiments, the number of wafers included in the substrate structure 100g may vary under the condition that the tilt angles are symmetrical and the tilt directions are opposite to each other with respect to the central surface CP.

[0078] Fig.10 is a cross-sectional view illustrating a substrate structure according to example embodiments.

[0079] Reference Fig.10 , the substrate structure 100h may include a first wafer WF1 and a second wafer WF2. The substrate structure 100h may include only two wafers. The first wafer WF1 and the second wafer WF2 may be tilted relative to each other or may not be tilted relative to each other. For example, by selecting Fig. 9 The first wafer WF1 and the second wafer WF2 may be stacked by using two arbitrary wafers in the exemplary embodiment of the present invention. The thickness T2h of the second wafer WF2 may be greater than the thickness T1h of the first wafer WF1, but the exemplary embodiment thereof is not limited thereto.

[0080] Fig.11 and Fig.12 is an exploded perspective view illustrating a substrate structure according to example embodiments.

[0081] Reference Fig.11 , the substrate structure 100i may include first to third wafers WF1, WF2, and WF3. The second wafer WF2 may be stacked on the upper surface of the first wafer WF1, and the third wafer WF3 may be stacked on the lower surface of the first wafer WF1. The upper surfaces of the first to third wafers WF1, WF2, and WF3 may be the same crystal plane, for example, a (100) plane.

[0082] The first wafer WF1 may be stacked without being rotated or tilted. Therefore, the first angle (θ1) (which is the rotation angle of the first wafer WF1) may be 0°, and the

[100] direction of the first wafer WF1 may match the reference direction R

[100] . The second wafer WF2 may be rotated in a counterclockwise direction relative to the reference direction by a second angle (θ2) greater than the first angle (θ1). The third wafer WF3 may be rotated in a counterclockwise direction relative to the reference direction by a third angle (-θ2). The third angle (-θ2) may be substantially the same as the second angle (θ2). That is, the third wafer WF3 may be rotated in a clockwise direction relative to the reference direction by an angle substantially the same as the second angle (θ2). For example, the third wafer WF3 may be described as being rotated 360°-the second angle (θ2) in a counterclockwise direction relative to the reference direction.

[0083] The thickness of the second wafer WF2 may be substantially the same as the thickness of the third wafer WF3 , and may be the same as or different from the thickness of the first wafer WF1 .

[0084] Reference Fig.12 , the substrate structure 100j may include first to fifth wafers WF1, WF2, WF3, WF4, and WF5. The second wafer WF2 may be stacked on the upper surface of the first wafer WF1, the third wafer WF3 may be stacked on the lower surface of the first wafer WF1, the fourth wafer WF4 may be stacked on the upper surface of the second wafer WF2, and the fifth wafer WF5 may be stacked on the lower surface of the third wafer WF3. The first to fifth wafers WF1, WF2, WF3, WF4, and WF5 may be formed of the same material, and their upper surfaces may be the same crystal plane, for example, the (100) plane.

[0085] The first wafer WF1 may be stacked without being rotated or tilted. Therefore, the first angle (θ1) (which is the rotation angle of the first wafer WF1) may be 0°, and the

[100] direction of the first wafer WF1 may match the reference direction R

[100] . The second wafer WF2 may be rotated in a counterclockwise direction relative to the reference direction by a second angle (θ2) greater than the first angle (θ1). The third wafer WF3 may be rotated in a counterclockwise direction relative to the reference direction by a third angle (-θ2). The third angle (-θ2) may be substantially the same as the second angle (θ2). The fourth wafer WF4 may be rotated in a counterclockwise direction relative to the reference direction by a fourth angle (θ3) different from the first angle (θ1) and the second angle (θ2). The fifth wafer WF5 may be rotated in a counterclockwise direction relative to the reference direction by a fifth angle (-θ3). The fifth angle (-θ3) may be substantially the same as the fourth angle (θ3).

[0086] The thickness of the second wafer WF2 may be substantially the same as the thickness of the third wafer WF3 , and the thickness of the fourth wafer WF4 may be substantially the same as the thickness of the fifth wafer WF5 .

[0087] As in Fig.11 and Fig.12 In the example embodiment of the present invention, at least one of the wafers in the substrate structure may not be tilted relative to the reference direction. However, even in this case, the wafers may be arranged so that the tilt angles are symmetrical and the tilt directions are opposite to each other with respect to the center in the stacking direction.

[0088] Fig.13A and Fig. 13B is a flowchart illustrating a method of manufacturing a semiconductor device including a substrate structure according to example embodiments.

[0089] Fig.14 and Fig.15 is a diagram illustrating a method of manufacturing a semiconductor device including a substrate structure according to example embodiments.

[0090] First, refer to Fig.13A , a method for manufacturing a semiconductor device may include preparing a first substrate structure (S110), forming a first region of the semiconductor device on the first substrate structure (S120), preparing a second substrate structure (S130), bonding the first substrate structure and the second substrate structure to each other (S140), forming a second region of the semiconductor device on the first substrate structure in the first substrate structure and the second substrate structure bonded to each other (S150), and removing the second substrate structure from the first substrate structure and the second substrate structure bonded to each other (S160).

[0091] In the step of preparing the first substrate structure (S110), the first substrate structure may be a structure in which a semiconductor device is formed. The first substrate structure may include Figures 3A to 12 The substrate structure of one of the described example embodiments. Alternatively, in some example embodiments, the first substrate structure may be a single wafer.

[0092] In the step of forming a first region of a semiconductor device on a first substrate structure (S120), the semiconductor device formed on the first substrate structure may be, for example, a transistor, a memory cell, an interconnect structure, and in this process, at least a portion of the semiconductor device may be formed.

[0093] In the step of preparing the second substrate structure (S130), the second substrate structure may be a supporting substrate structure for supporting the first substrate structure during a process of forming a semiconductor device on the first substrate structure. The second substrate structure may include the semiconductor device according to the above reference Figures 3A to 12Alternatively, in some example embodiments, the second substrate structure may be a single wafer. At least one of the first substrate structure and the second substrate structure may include a substrate structure according to the above reference Figures 3A to 12 A substrate structure of an example embodiment is described.

[0094] The step of bonding the first substrate structure and the second substrate structure to each other (S140) may include attaching the first semiconductor structure S1 and the second semiconductor structure S2 including the first substrate structure and the second substrate structure to the first bonding chuck BC1 and the second bonding chuck BC2, respectively, and bonding the first semiconductor structure S1 and the second semiconductor structure S2 to each other, such as Fig.14 As shown. The first semiconductor structure S1 may be attached to a first bonding chuck BC1 disposed below, and the second semiconductor structure S2 may be attached to a second bonding chuck BC2 disposed above. In some example embodiments, the first semiconductor structure S1 may be attached to the second bonding chuck BC2, and the second semiconductor structure S2 may be attached to the first bonding chuck BC1. In this process, the second substrate structure may be bonded to the rear surface of the first substrate structure, that is, the surface on which the first region is not formed. The second substrate structure may be bonded to the first substrate structure using an adhesive layer, or may be directly bonded without an adhesive layer.

[0095] The step of forming a second region of the semiconductor device on the first substrate structure of the first substrate structure and the second substrate structure bonded to each other (S150) may include: performing a semiconductor process on the first substrate structure while being supported by the second substrate structure as a supporting structure. For example, the semiconductor process may need to support the first substrate structure. The second region may be formed on the first region. In some example embodiments, when the semiconductor process is a first process for manufacturing a semiconductor device, process S120 may not be performed.

[0096] The step of removing the second substrate structure (S160) from the first substrate structure and the second substrate structure bonded to each other may include removing the second substrate structure after performing the semiconductor process. Thereafter, a process of forming at least a portion of a semiconductor device on the first substrate structure may also be performed. If necessary, processes S130 to S160 may also be performed during the process of manufacturing the semiconductor device.

[0097] Reference Fig. 13B , a method for manufacturing a semiconductor device may include: preparing a first substrate structure (S210), forming a first region of the semiconductor device on the first substrate structure (S220), preparing a second substrate structure (S230), forming a second region of the semiconductor device on the second substrate structure (S240), and bonding the first substrate structure and the second substrate structure to each other (S250).

[0098] As for preparing the first substrate structure (S210) and forming the first region of the semiconductor device on the first substrate structure (S220), the above reference numerals may be applied. Fig.13A Description of processes S110 and S120 are described.

[0099] In the step of preparing the second substrate structure (S230), the second substrate structure may be a structure similar to the first substrate structure in which a semiconductor device is formed. The second substrate structure may include the structure described above with reference to Figures 3A to 12 At least one of the first substrate structure and the second substrate structure may include the substrate structure according to the above reference Figures 3A to 12 A substrate structure of an example embodiment is described.

[0100] The step of forming a second region of the semiconductor device on the second substrate structure (S240) may include: forming a portion of the semiconductor device on the second substrate structure separately from the first substrate structure. The second region of the semiconductor device may be electrically connected to the first region formed on the first substrate structure. Fig.15 As shown, a first device layer ER1 corresponding to the first region of the semiconductor device may be formed on the first substrate structure 100L, and a second device layer ER2 corresponding to the second region of the semiconductor device may be formed on the second substrate structure 100U.

[0101] The step of bonding the first substrate structure and the second substrate structure (S250) may include bonding the first region and the second region to face each other. The process may include bonding the first semiconductor structure S1 and the second semiconductor structure S2, which include the first substrate structure 100L and the second substrate structure 100U, respectively, to each other. Fig.15 As shown. The first device layer ER1 may include a first bonding structure including a first bonding metal layer 198, the second device layer ER2 may include a second bonding structure including a second bonding metal layer 298, and the first device layer ER1 and the second device layer ER2 may be bonded to each other through the first bonding structure and the second bonding structure. Thereafter, the first wafer WF1 of the first substrate structure 100L and / or the third wafer WF3 of the second substrate structure 100U may be thinned. However, the thinning process may not be performed. Therefore, it may be manufactured Figure 2 The semiconductor device 10a in FIG.

[0102] Fig.16A and Fig. 16B is a diagram illustrating characteristics of a semiconductor device including a substrate structure according to example embodiments.

[0103] Fig.16A and Fig. 16B The first substrate structure and the second substrate structure are shown as follows Fig.14Simulation results of misalignment and overlap of example embodiments shown bonded to each other. Misalignment may refer to distortion caused by bonding between a first substrate structure and a second substrate structure, and overlap may refer to alignment between patterns when a photolithography process is performed on the entire bonded structure.

[0104] The comparative example may correspond to a structure in which each of the first substrate structure and the second substrate structure may be a single wafer having a (100) plane. The first to seventh exemplary embodiments may have a wafer stacking structure having a first substrate structure in a lower portion and a second substrate structure in an upper portion, such as Fig.16A and Fig. 16B shown.

[0105] Specifically, in the first exemplary embodiment, each of the first substrate structure and the second substrate structure may have a structure in which two (100) wafers are stacked and tilted relative to each other, the tilt angle may be 45°, and the (100) wafers bonded to each other may also be bonded in a tilted state. In the second exemplary embodiment, the lower first substrate structure may have a structure in which a (111) wafer and a (100) wafer are stacked without tilting, such as Figure 3A and Figure 3B In the third example embodiment, the lower first substrate structure may have a structure in which the (111) wafer and the (100) wafer are stacked and the (100) wafer is stacked at an angle of 45° relative to the (111) wafer. In other example embodiments, each of the first substrate structure and the second substrate structure may also be understood from the illustrated example as described above.

[0106] As a result of the simulation, the misalignment was reduced in the second and third example embodiments, and the overlap was reduced in all example embodiments except the fourth example embodiment, compared to the comparative example. For example, in the third example embodiment, the overlap was reduced by about 44%, and the misalignment due to the bonding was also reduced by about 56%. Therefore, it can be indicated that when Fig.15 When semiconductor structures each including a substrate structure are bonded as shown, overlay characteristics may be improved, and in some example embodiments, misalignment may also be improved.

[0107] According to the above exemplary embodiments, by stacking a plurality of wafers by optimizing the composition or tilt angle of the crystal planes of the plurality of wafers, a substrate structure having improved uniformity of mechanical rigidity and ensured chemical properties can be provided. By bonding a semiconductor structure including the substrate structure, a semiconductor device having improved reliability and mass production can be provided.

[0108] One or more elements disclosed above may include or be implemented in a processing circuit, such as hardware including logic circuits, a hardware / software combination (such as a processor that executes software), or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0109] While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A first semiconductor structure comprising a first substrate structure and a first device layer on an upper surface of the first substrate structure, the first device layer comprising a first region of the semiconductor device; as well as a second semiconductor structure comprising a second substrate structure and a second device layer on a lower surface of the second substrate structure, the second device layer being connected to the first device layer and comprising a second region of the semiconductor device, wherein The first substrate structure includes a first wafer and a second wafer on the first wafer, The second wafer is in contact with the first device layer, The second substrate structure includes a third wafer and a fourth wafer on a lower surface of the third wafer, The fourth wafer is in contact with the second device layer, and The upper surface of the second wafer is a (100) crystal plane.

2. The semiconductor device according to claim 1, wherein: The bottom surface of the fourth wafer is a (100) crystal plane.

3. The semiconductor device according to claim 2, wherein: The crystal orientation of the second wafer and the crystal orientation of the fourth wafer are inclined relative to each other.

4. The semiconductor device according to claim 1, wherein: The upper surface of the first wafer is a (111) crystal plane.

5. The semiconductor device according to claim 1, wherein: The upper surface of the first wafer is a (100) crystal plane, and The first wafer and the second wafer are stacked such that a crystal orientation of the first wafer and a crystal orientation of the second wafer are inclined with respect to each other by a first angle θ1.

6. The semiconductor device according to claim 5, wherein: The first angle θ1 is in the range of 0°≤θ1≤90°.

7. The semiconductor device according to claim 1, wherein: The lower surface of the third wafer is a (111) crystal plane.

8. The semiconductor device according to claim 1, wherein: The lower surface of the third wafer is a (100) crystal plane.

9. The semiconductor device according to claim 8, wherein: The lower surface of the fourth wafer is a (100) crystal plane, and The third wafer and the fourth wafer are stacked such that a crystal orientation of the third wafer and a crystal orientation of the fourth wafer are inclined relative to each other.

10. The semiconductor device according to claim 1, wherein The first region includes a transistor, and The second region includes an interconnect structure electrically connected to the transistor.

11. The semiconductor device according to claim 1, wherein: The first device layer further includes a first bonding metal layer on the first region, and The second device layer also includes a second bonding metal layer below the second region, and The second bonding metal layer is bonded to the first bonding metal layer.

12. The semiconductor device according to claim 1, wherein: The second wafer has a thickness ranging from 1 μm to 5 μm.

13. A semiconductor device comprising: A first semiconductor structure comprising a first substrate structure and a first device layer on an upper surface of the first substrate structure, the first device layer comprising a first region of the semiconductor device; as well as a second semiconductor structure comprising a second substrate structure and a second device layer on a lower surface of the second substrate structure, the second device layer being connected to the first device layer and comprising a second region of the semiconductor device, wherein The first substrate structure includes a plurality of wafers stacked vertically, and In the first substrate structure, the plurality of wafers are stacked such that upper surfaces of the plurality of wafers have the same crystal plane and crystal directions are inclined relative to each other, or parts of upper surfaces of the plurality of wafers have different crystal planes.

14. The semiconductor device according to claim 13, wherein: The first substrate structure includes a first wafer and a second wafer on the first wafer, the second wafer is in contact with the first device layer, and The upper surface of the second wafer is a (100) crystal plane.

15. The semiconductor device according to claim 14, wherein: The upper surface of the first wafer is a (111) crystal plane.

16. The semiconductor device according to claim 13, wherein: The plurality of wafers include a first wafer tilted at a first angle in a counterclockwise direction from a reference direction and a second wafer tilted at the first angle in a clockwise direction from the reference direction, and The reference direction is parallel to an upper surface of the first substrate structure.

17. The semiconductor device according to claim 13, wherein: The plurality of wafers include a first wafer, a second wafer and a third wafer, The reference direction is parallel to the upper surface of the first substrate structure, The first wafer has a first crystal orientation in a direction rotated by a first angle in a counterclockwise direction from the reference direction, The second wafer has the first crystal orientation in a direction rotated by a second angle in a counterclockwise direction from the reference direction, and The third wafer has the first crystal orientation in a direction rotated by a third angle in a counterclockwise direction from the reference direction.

18. A semiconductor device comprising: A first semiconductor structure comprising a first substrate structure, a first region of the semiconductor device on an upper surface of the first substrate structure, and a first bonding metal layer on the first region; as well as a second semiconductor structure comprising a second substrate structure, a second region of the semiconductor device on a lower surface of the second substrate structure, and a second bonding metal layer below the second region and bonded to the first bonding metal layer, wherein The first substrate structure and the second substrate structure each include a plurality of wafers stacked vertically.

19. The semiconductor device according to claim 18, wherein: The first substrate structure includes a first wafer and a second wafer, and A crystal plane of an upper surface of the first wafer is different from a crystal plane of an upper surface of the second wafer.

20. The semiconductor device according to claim 18, wherein The first substrate structure comprises a first wafer, The upper surface of the first substrate structure is the upper surface of the first wafer, The second substrate structure comprises a second wafer, The lower surface of the second substrate structure is the lower surface of the second wafer, The upper surface of the first wafer and the upper surface of the second wafer have the same crystal plane, and The crystal orientation of the first wafer and the crystal orientation of the second wafer are inclined relative to each other.

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