Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a first logic cell and a second logic cell adjacent to each other on a substrate, and a hybrid separation structure extending in a first direction between the first logic cell and the second logic cell. Each logic cell includes: a first active pattern and a second active pattern extending in a second direction intersecting the first direction, and spaced apart from each other in the first direction; and gate electrodes extending in the first direction and spanning the first active pattern and the second active pattern, and the plurality of gate electrodes being spaced apart by a gate pitch. The hybrid separation structure includes a first separation structure that separates the first active pattern of the first logic cell from the first active pattern of the second logic cell; and a second separation structure on the first separation structure. The width of the first separation structure is greater than the gate pitch.

Description

[0001] This application is a divisional application of the Chinese invention patent application (application number: 201910135780.3) with a filing date of February 21, 2019 and entitled “Semiconductor Device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This patent application claims the priority benefit of Korean Patent Application No. 10-2018-0024411 filed in the Korean Intellectual Property Office on February 28, 2018, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0004] Apparatus, devices, and articles of manufacture according to the present disclosure relate to semiconductor devices, and more particularly, to semiconductor devices including field effect transistors. Background Art

[0005] Semiconductor devices are beneficial in the electronics industry due to their small size, versatility and / or low manufacturing cost. Semiconductor devices may include semiconductor memory devices that store logic data, semiconductor logic devices that process operations of logic data, and hybrid semiconductor devices having both storage elements and logic elements. With the advanced development of the electronics industry, semiconductor devices are increasingly in need of high integration. For example, semiconductor devices are increasingly required to have characteristics including high reliability, high speed and / or versatility. Semiconductor devices are gradually becoming more complex and more highly integrated to meet these required characteristics. Summary of the invention

[0006] One aspect is to provide a semiconductor device including a field effect transistor with enhanced electrical characteristics. According to one aspect of an exemplary embodiment, a semiconductor device is provided, including: a first logic unit and a second logic unit, the first logic unit and the second logic unit being adjacent to each other on a substrate; and a hybrid separation structure extending in a first direction between the first logic unit and the second logic unit, wherein each of the first logic unit and the second logic unit includes: a first active pattern and a second active pattern, the first active pattern and the second active pattern extending in a second direction intersecting the first direction and spaced apart from each other in the first direction; and a plurality of gate electrodes extending in the first direction and crossing the first active pattern and the second active pattern, and the plurality of gate electrodes are spaced apart by a gate pitch, and wherein the hybrid separation structure includes: a first separation structure separating a first active pattern of the first logic unit from a first active pattern of the second logic unit; and a second separation structure on the first separation structure, wherein a width of the first separation structure is greater than the gate pitch.

[0007] According to another aspect of the exemplary embodiment, a semiconductor device is provided, comprising a substrate, the substrate comprising a first active region and a second active region, the first active region and the second active region being spaced apart from each other in a first direction and extending in a second direction intersecting the first direction; a device isolation layer, disposed on the substrate and defining a first active pattern and a second active pattern, the first active pattern and the second active pattern extending in the second direction on the first active region and the second active region, respectively; and a hybrid separation structure, spanning the first active region and the second active region and extending in the first direction, wherein the hybrid separation structure comprises: a first separation structure, the first separation structure selectively spanning the first active pattern except for the second active pattern; and a second separation structure spanning the first active pattern and the second active pattern, wherein a first horizontal plane of a first bottom surface of the first separation structure is lower than a second horizontal plane of a second bottom surface of the second separation structure.

[0008] According to another aspect of the exemplary embodiment, a semiconductor device is provided, including: a first logic unit and a second logic unit, the first logic unit and the second logic unit being adjacent to each other on a substrate; and a hybrid separation structure extending in a first direction between the first logic unit and the second logic unit, wherein each of the first logic unit and the second logic unit includes: a first active area, in which a plurality of first transistors having a first conductivity are provided; and a second active area, in which a plurality of second transistors having a second conductivity different from the first conductivity are provided, and wherein the hybrid separation structure includes: a first separation structure, separating the first active area of ​​the first logic unit from the first active area of ​​the second logic unit; and a second separation structure, extending in the first direction on the first separation structure and separating the second active area of ​​the first logic unit from the second active area of ​​the second logic unit, wherein the second separation structure includes a second insulating material different from the first insulating material of the first separation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A block diagram illustrating a computer system for designing a semiconductor device according to an exemplary embodiment is shown;

[0010] Figure 2 A flow chart illustrating a method of designing and manufacturing a semiconductor device according to an exemplary embodiment is shown;

[0011] Figure 3 A detailed description is shown in Figure 2 A flowchart of step S30 of arranging and routing standard cells in the method;

[0012] Figure 4 and Figure 5 Shows the description Figure 3 A layout according to an exemplary embodiment of the steps of arranging and routing standard cells;

[0013] Figure 6 shows a plan view illustrating a semiconductor device according to an exemplary embodiment;

[0014] 7A to 7E Shown are Figure 6 sectional views taken along lines II', II-II', III-III', IV-IV' and V-V';

[0015] Figure 8 , Fig.10 and Fig.12 shows a plan view illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment;

[0016] 9A to 9D Shown are Figure 8 sectional views taken along lines II', II-II', III-III' and IV-IV';

[0017] FIG. 11A to FIG. 11E Shown are Fig.10 sectional views taken along lines II', II-II', III-III', IV-IV' and V-V';

[0018] FIG. 13A to FIG. 13E Shown are Fig.12 sectional views taken along lines II', II-II', III-III', IV-IV' and V-V';

[0019] Fig.14 shows a layout according to an exemplary embodiment;

[0020] Fig.15 shows a plan view illustrating a semiconductor device according to an exemplary embodiment;

[0021] FIG. 16A to FIG. 16C Shown are Fig.15 sectional views taken along lines II-I', II-II' and III-III';

[0022] Fig.17A and Fig. 17B 1 and 2 show the respective steps of illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment. Fig.15 A cross-sectional view taken along lines II-I' and II-II';

[0023] Fig.18 shows a layout according to an exemplary embodiment;

[0024] Fig.19 shows a plan view illustrating a semiconductor device according to an exemplary embodiment;

[0025] FIG. 20A to FIG. 20C Shown are Fig.19 sectional views taken along lines II-I', II-II' and III-III';

[0026] Fig.21 shows a layout according to an exemplary embodiment;

[0027] Fig. 22 shows a plan view illustrating a semiconductor device according to an exemplary embodiment;

[0028] Fig.23 Shown along Fig. 22 A cross-sectional view taken along line II';

[0029] Fig.24 shows a layout according to an exemplary embodiment;

[0030] Fig.25 shows a plan view illustrating a semiconductor device according to an exemplary embodiment;

[0031] Fig.26 Shown along Fig.25 A cross-sectional view taken along line II';

[0032] Fig. 27 shows a layout according to an exemplary embodiment;

[0033] Fig.28 shows a plan view illustrating a semiconductor device according to an exemplary embodiment;

[0034] FIG. 29A to FIG. 29C Shown are Fig.28 sectional views taken along lines II-I', II-II' and III-III';

[0035] Fig.30 shows a layout according to an exemplary embodiment;

[0036] Fig.31 shows a plan view illustrating a semiconductor device according to an exemplary embodiment;

[0037] Fig.32A and Fig.32B Shown are Fig.25 A cross-sectional view taken along lines II-I' and II-II';

[0038] Fig.33 shows a layout according to an exemplary embodiment;

[0039] Fig.34 shows a plan view illustrating a semiconductor device according to an exemplary embodiment; and

[0040] Fig.35A and Fig.35B Shown are Fig.34 Cross-sectional views taken along lines II' and II-II'. DETAILED DESCRIPTION

[0041] Figure 1 A block diagram illustrating a computer system for designing a semiconductor device according to an exemplary embodiment is shown. Figure 1 The computer system may include a central processing unit (CPU) 10, a working memory 30, an input / output (I / O) device 50, and an auxiliary storage device 70. The computer system may be provided as a dedicated device for designing a layout according to an exemplary embodiment. The computer system may be configured to drive various programs for designing and verifying simulations.

[0042] The CPU 10 may allow the computer system to execute software (e.g., application programs, operating systems, and device drivers). The CPU 10 may process the operating system loaded in the working memory 30. The CPU 10 may execute various application programs driven by the operating system. For example, the CPU 10 may process the layout design tool 32, the placement and routing tool 34, and / or the optical proximity correction (OPC) tool 36 loaded in the working memory 30.

[0043] An operating system or an application program may be loaded in the working memory 30. When the computer system is started, based on a startup sequence, an operating system image (not shown) stored in the auxiliary storage device 70 may be loaded into the working memory 30. The overall input / output operation of the computer system may be supported by the operating system. Likewise, the working memory 30 may be loaded with an application program selected by a user or provided for basic services.

[0044] A layout design tool 32 for layout design may be loaded from the auxiliary storage device 70 to the working memory 30. A placement and routing tool 34 may be loaded from the auxiliary storage device 70 to the working memory 30, and the placement and routing tool 34 places the designed standard cells and routes the arranged standard cells. An OPC tool 36 may be loaded from the auxiliary storage device 70 to the working memory 30, and the OPC tool 36 performs optical proximity correction (OPC) on the designed layout data.

[0045] The layout design tool 32 may include a deviation function by which a specific layout pattern is changed in terms of shape and position defined by the design rule. In addition, the layout design tool 32 may perform a design rule check (DRC) under the changed deviation data condition. The working memory 30 may be a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), or a non-volatile memory such as a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FRAM), or a NOR flash memory.

[0046] The I / O device 50 may control the user input / output operation of the user interface. For example, the I / O device 50 may include a keyboard or a monitor, thereby allowing the designer to input relevant information.

[0047] The auxiliary storage device 70 can be used as a storage medium for the computer system. The auxiliary storage device 70 can store application programs, operating system images, and various data. The auxiliary storage device 70 can be provided in the form of a memory card (e.g., MMC, eMMC, SD, or micro SD) and / or in the form of a hard disk drive (HDD). The auxiliary storage device 70 may include a NAND flash memory with a large storage capacity. Alternatively, the auxiliary storage device 70 may include a NOR flash memory, or a next-generation volatile memory (e.g., PRAM, MRAM, ReRAM, and FRAM).

[0048] The system interconnector 90 may be provided to function as a system bus for providing a network in the computer system. The CPU 10, the working memory 30, the I / O device 50, and the auxiliary storage device 70 may be electrically connected through the system interconnector 90, and may exchange data with each other. The system interconnector 90 may not be limited to the above description, and may also include an intermediate device for effective management.

[0049] Figure 2 A flow chart illustrating a method of designing and manufacturing a semiconductor device according to an exemplary embodiment is shown.

[0050] refer to Figure 2 , you can use reference Figure 1The computer system discussed is used to perform high-level design (S10) of a semiconductor integrated circuit. High-level design may mean describing an integrated circuit corresponding to a design target in a high-level language of a hardware description language. For example, a high-level language such as a C language may be used in the high-level design. Register transfer level (RTL) coding or simulation may be used to express in detail the circuit designed by the high-level design. In addition, the code created by the RTL coding may be converted into a netlist, which may be synthesized to describe the entire semiconductor device. The synthesized schematic circuit may be verified by a simulation tool, and an adjustment process may be performed based on the result of the verification.

[0051] Layout design may be performed to implement a logically completed semiconductor integrated circuit on a silicon substrate ( S20 ). For example, layout design may be performed based on a schematic circuit synthesized in a high-level design or a netlist corresponding to the schematic circuit.

[0052] The cell library used for layout design can include information related to the operation, speed, and power consumption of standard cells. A cell library for representing the layout of a specific gate-level circuit as a layout can be defined in most tools for designing layouts. The layout can be prepared to define the shape or size of the patterns that make up the transistors and metal lines, which will actually be formed on the silicon substrate. For example, in order to actually form an inverter circuit on a silicon substrate, it may be necessary to appropriately arrange or describe layout patterns such as PMOS, NMOS, N-well, gate electrodes, and metal lines on the silicon substrate. To this end, a search can first be performed to select a suitable inverter from the inverters predefined in the cell library.

[0053] The designed standard cells may be arranged and wired (S30). For example, advanced wires may be provided on the arranged standard cells. The arranged standard cells may be carefully connected to each other through a wiring step. The arrangement and wiring of the standard cells may be performed by Figure 1 The placement and routing tool 34 is automatically executed.

[0054] After the routing step, a verification step may be performed on the layout to check whether any part of the schematic circuit violates a given design rule. The verification step may include: a design rule check (DRC) for verifying whether the layout satisfies the given design rule, an electrical rule check (ERC) for verifying whether there is an electrical disconnection problem in the layout, and a layout comparison schematic (LVS) for verifying whether the layout is consistent with the gate-level netlist.

[0055] An optical proximity correction (OPC) step (S40) may be performed. A layout pattern obtained by the layout design may be implemented on a silicon substrate using a photolithography process. Optical proximity correction may be a technique for correcting unintended optical effects occurring in a photolithography process. For example, optical proximity correction may correct unintended phenomena such as refraction or process side effects caused by the characteristics of light in an exposure process using the layout pattern. When optical proximity correction is performed, the designed layout pattern may be slightly changed (or deviated) in shape and position.

[0056] A photomask may be generated based on the layout changed by the optical proximity correction (S50). The photomask may generally be manufactured by describing a layout pattern using a chrome layer coated on a glass substrate.

[0057] The generated photomask can be used to manufacture a semiconductor device (S60). Various exposure processes and etching processes can be repeatedly performed when using the photomask to manufacture a semiconductor device. Through these processes discussed above, a pattern defined in the layout design can be sequentially formed on a silicon substrate.

[0058] Figure 3 Shows detailed description Figure 2 Flow chart of step S30 of arranging and wiring standard cells. Figure 4 and Figure 5 Shows the description Figure 3 The steps of arranging and routing standard cells are arranged according to a layout of an exemplary embodiment.

[0059] refer to Figure 3 and Figure 4 , a first standard cell STD1, a second standard cell STD2, and a third standard cell STD3 may be arranged (S110). The first standard cell STD1, the second standard cell STD2, and the third standard cell STD3 may be arranged linearly in the second direction D2. The first standard cell STD1, the second standard cell STD2, and the third standard cell STD3 may be standard cells different from each other. The first standard cell STD1, the second standard cell STD2, and the third standard cell STD3 may respectively constitute a first logic circuit, a second logic circuit, and a third logic circuit different from each other.

[0060] Each of the first standard cell STD1, the second standard cell STD2, and the third standard cell STD3 may include a first active area pattern RXP, a second active area pattern RXN, and a gate pattern GP. Each of the first standard cell STD1, the second standard cell STD2, and the third standard cell STD3 may also include additional layout patterns (e.g., active fin patterns, active contact patterns, gate contact patterns, through hole patterns, and line patterns). In order to simplify the drawings and their descriptions, the following may not be included in the drawings. Figure 4and Figure 5 Additional layout patterns are shown in the first standard cell STD1 , the second standard cell STD2 , and the third standard cell STD3 shown in .

[0061] The first active area pattern RXP and the second active area pattern RXN may extend in the second direction D2. The first active area pattern RXP and the second active area pattern RXN may be spaced apart from each other in the first direction D1. The first active area pattern RXP may define a first active area, and the second active area pattern RXN may define a second active area.

[0062] The gate pattern GP may extend in a first direction D1 and may be arranged in a second direction D2 intersecting (eg, perpendicular to) the first direction D1. The gate patterns GP may be arranged to have the same spacing. The spacing may be the distance between the center of a first pattern and the center of a second pattern adjacent to the first pattern. The gate pattern GP may define a gate electrode.

[0063] The first diffusion interruption pattern FC may be disposed on a boundary of each of the first standard cell STD1, the second standard cell STD2, and the third standard cell STD3. For example, the first diffusion interruption pattern FC may be disposed between adjacent standard cells. The first diffusion interruption pattern FC may extend in the first direction D1. The first diffusion interruption pattern FC may separate adjacent standard cells from each other. The first diffusion interruption pattern FC may define a first separation structure.

[0064] For example, a first cell boundary BD1 may be defined between the first standard cell STD1 and the second standard cell STD2, and a second cell boundary BD2 may be defined between the second standard cell STD2 and the third standard cell STD3. A first diffusion interrupt pattern FC may be disposed on each of the first cell boundary BD1 and the second cell boundary BD2. The first diffusion interrupt pattern FC may separate the first active area pattern RXP of the first standard cell STD1 from the first active area pattern RXP of the second standard cell STD2. The first diffusion interrupt pattern FC may separate the second active area pattern RXN of the first standard cell STD1 from the second active area pattern RXN of the second standard cell STD2.

[0065] The first diffusion interruption pattern FC may overlap a pair of adjacent gate patterns GP. The first diffusion interruption pattern FC may have a first width W1 in the second direction D2. A first distance L1 may be provided between opposite sidewalls of the pair of adjacent gate patterns GP. The first width W1 and the first distance L1 may be substantially the same.

[0066] refer to Figure 3 and Figure 5, a hybrid diffusion interrupt pattern CSC may be provided on each of the first cell boundary BD1 and the second cell boundary BD2 (S120). For example, the hybrid diffusion interrupt pattern CSC may replace the first diffusion interrupt pattern FC on each of the first cell boundary BD1 and the second cell boundary BD2. The hybrid diffusion interrupt pattern CSC may include a first diffusion interrupt pattern FC and a second diffusion interrupt pattern RC. The first diffusion interrupt pattern FC and the second diffusion interrupt pattern RC may have substantially the same width in the second direction D2.

[0067] The second diffusion interruption pattern RC may extend in the first direction D1. The second diffusion interruption pattern RC may extend from the second active area pattern RXN toward the first active area pattern RXP. The size and shape of the second diffusion interruption pattern RC may be the same as those described above with reference to Figure 4 The size and shape of the first diffusion interruption pattern FC discussed are substantially the same. Figure 4 The discussed first diffusion interruption pattern FC, the second diffusion interruption pattern RC may separate adjacent standard cells from each other.

[0068] The first diffusion interrupt pattern FC of the hybrid diffusion interrupt pattern CSC may be limitedly disposed on the second active area pattern RXN. The size of the first diffusion interrupt pattern FC of the hybrid diffusion interrupt pattern CSC may be about half of the second diffusion interrupt pattern RC. For example, the first diffusion interrupt pattern FC of the hybrid diffusion interrupt pattern CSC may separate the second active area pattern RXN of the first standard cell STD1 from the second active area pattern RXN of the second standard cell STD2. The hybrid diffusion interrupt pattern CSC may define a hybrid separation structure.

[0069] Thereafter, a wiring step (S130) may be performed on the arranged first standard cell STD1, second standard cell STD2, and third standard cell STD3. Wiring the first standard cell STD1, second standard cell STD2, and third standard cell STD3 may include: arranging an advanced line pattern (not shown) that electrically connects the first standard cell STD1, second standard cell STD2, and third standard cell STD3 to each other. When the advanced line pattern is arranged, the first standard cell STD1, second standard cell STD2, and third standard cell STD3 may be connected to each other according to a designed circuit.

[0070] Figure 6 A plan view illustrating a semiconductor device according to an exemplary embodiment is shown. 7A to 7E Shown are Figure 6 Cross-sectional views taken along lines II', II-II', III-III', IV-IV' and V-V'. Figure 6 and 7A to 7E An example is shown when using Figure 5 The layout is the semiconductor device actually implemented on the substrate.

[0071] refer to Figure 5 , Figure 6 and 7A to 7E , a first logic cell LC1, a second logic cell LC2, and a third logic cell LC3 may be provided. The first logic cell LC1, the second logic cell LC2, and the third logic cell LC3 may be arranged along the second direction D2. The first logic cell LC1, the second logic cell LC2, and the third logic cell LC3 may correspond to Figure 5 The first standard cell STD1, the second standard cell STD2 and the third standard cell STD3. Each of the first logic cell LC1, the second logic cell LC2 and the third logic cell LC3 can constitute a logic circuit. For example, a logic transistor constituting a logic circuit can be provided on each of the first logic cell LC1, the second logic cell LC2 and the third logic cell LC3. In some exemplary embodiments, the first logic cell LC1, the second logic cell LC2 and the third logic cell LC3 may include logic circuits different from each other. The logic transistors and wires constituting the first logic cell LC1, the second logic cell LC2 and the third logic cell LC3 are described in detail below.

[0072] A substrate 100 may be provided. For example, the substrate 100 may be or include a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate. A device isolation layer ST may be provided on the substrate 100, and the device isolation layer ST defines a first active region PR and a second active region NR. For example, the first active region PR may be a PMOSFET region, and the second active region NR may be an NMOSFET region. The first active region PR and the second active region NR may be defined by a second trench TR2 on an upper portion of the substrate 100, and the device isolation layer ST may fill the second trench TR2. For example, the device isolation layer ST may include a silicon oxide layer.

[0073] The first active region PR and the second active region NR may be spaced apart from each other in the first direction D1 across the device isolation layer ST. The first active region PR and the second active region NR may extend in the second direction D2 and cross the first, second, and third logic cells LC1, LC2, and LC3.

[0074] A plurality of first active patterns FN1 extending in the second direction D2 may be disposed on the first active region PR. A plurality of second active patterns FN2 extending in the second direction D2 may be disposed on the second active region NR. The first active patterns FN1 and the second active patterns FN2 may be vertical protrusions of the substrate 100. The first active patterns FN1 and the second active patterns FN2 may be arranged along the first direction D1.

[0075] For example, three first active patterns FN1 extending in parallel along the second direction D2 may be disposed on the first active region PR. For example, three second active patterns FN2 extending in parallel along the second direction D2 may be disposed on the second active region NR. The number and shape of the first active pattern FN1 and the second active pattern FN2 on the first active region PR and the second active region NR, respectively, are exemplary and are not limited to the number and shape shown.

[0076] The first trench TR1 may be defined between a pair of active patterns FN1 and FN2 adjacent to each other in the first direction D1. The device isolation layer ST may also fill the first trench TR1.

[0077] The upper portions of the first active pattern FN1 and the second active pattern FN2 may be higher than the top surface of the device isolation layer ST. The upper portions of the first active pattern FN1 and the second active pattern FN2 may vertically protrude from the device isolation layer ST. The upper portion of each of the first active pattern FN1 and the second active pattern FN2 may be shaped like a fin protruding from the device isolation layer ST.

[0078] The upper portion of each of the first active patterns FN1 may include a first channel region CH1 and a first source / drain region SD1. The first source / drain region SD1 may be a p-type impurity region. Each of the first channel regions CH1 may be inserted between a pair of first source / drain regions SD1. The upper portion of each of the second active patterns FN2 may include a second channel region CH2 and a second source / drain region SD2. The second source / drain region SD2 may be an n-type impurity region. Each of the second channel regions CH2 may be inserted between a pair of second source / drain regions SD2.

[0079] The first source / drain region SD1 and the second source / drain region SD2 may be epitaxial patterns formed by a selective epitaxial growth process. Top surfaces of the first source / drain region SD1 and the second source / drain region SD2 may be higher than top surfaces of the first channel region CH1 and the second channel region CH2.

[0080] For example, the first source / drain region SD1 may include a semiconductor element whose lattice constant is greater than that of the semiconductor element of the substrate 100. Therefore, the first source / drain region SD1 may provide compressive stress to the first channel region CH1. Alternatively, the second source / drain region SD2 may include the same semiconductor element as the semiconductor element of the substrate 100. For example, the first source / drain region SD1 may include silicon germanium, and the second source / drain region SD2 may include silicon.

[0081] When viewed in a cross section along the first direction D1, a cross section of each of the first source / drain regions SD1 may be different from a cross section of each of the second source / drain regions SD2 (see FIG. 2 ). Fig. 7E ).

[0082] The gate electrode GE may be disposed to cross the first active pattern FN1 and the second active pattern FN2 and extend in the first direction D1. The gate electrodes GE may be spaced apart from each other in the second direction D2. A first pitch P1 may be provided between a pair of adjacent gate electrodes GE. The gate electrodes GE may be equally spaced apart at the first pitch P1.

[0083] The gate electrode GE may vertically overlap the first channel region CH1 and the second channel region CH2. Each gate electrode GE may be disposed on a top surface and opposite side walls of each of the first channel region CH1 and the second channel region CH2 (see Fig.7D For example, the gate electrode GE may include one or more of a conductive metal nitride (eg, titanium nitride or tantalum nitride) and a metal (eg, titanium, tantalum, tungsten, copper, or aluminum).

[0084] A pair of gate spacers GS may be provided on opposite side walls of each gate electrode GE. The gate spacers GS may extend in a first direction D1 along the gate electrode GE. The top surface of the gate spacer GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacer GS may be coplanar with the top surface of the gate cap layer CP to be discussed below. For example, the gate spacer GS may include one or more of SiCN, SiCON, and SiN. Alternatively, the gate spacer GS may include a multilayer consisting of two or more of SiCN, SiCON, and SiN.

[0085] The gate dielectric layer GI may be inserted between the gate electrode GE and the first channel region CH1 and the second channel region CH2. Each gate dielectric layer GI may extend along the bottom surface of the corresponding gate electrode in the gate electrode GE. Each gate dielectric layer GI may cover the top surface and the opposite sidewalls of each of the first channel region CH1 and the second channel region CH2. The gate dielectric layer GI may include a high-k dielectric material having a dielectric constant higher than that of the silicon oxide layer. For example, the high-k dielectric material may include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0086] A gate capping layer CP may be disposed on each gate electrode GE. The gate capping layer CP may extend in the first direction D1 along the gate electrode GE. The gate capping layer CP may include a material exhibiting etching selectivity to the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 to be discussed below. For example, the gate capping layer CP may include one or more of SiON, SiCN, SiCON, and SiN.

[0087] A hybrid separation structure CDB may be provided on a cell boundary between the first logic cell LC1 and the second logic cell LC2 and a cell boundary between the second logic cell LC2 and the third logic cell LC3. The hybrid separation structure CDB may extend in the first direction D1 and separate adjacent logic cells from each other. The hybrid separation structure CDB may include a first separation structure DB1 and a second separation structure DB2. The first separation structure DB1 may be provided on other cell boundaries of the first logic cell LC1 and on other cell boundaries of the third logic cell LC3.

[0088] The first separation structure DB1 may fill a third trench TR3 extending in the first direction D1. The third trench TR3 may separate a pair of active patterns FN1 and FN2 adjacent to each other in the second direction D2 from each other. For example, the depth of the third trench TR3 may be substantially the same as the depth of the second trench TR2. The third trench TR3 may be deeper than the first trench TR1. For another example, the depth of the third trench TR3 may be different from the depth of the second trench TR2. The first separation structure DB1 may be a device isolation layer ST filling the third trench TR3.

[0089] Therefore, the first separation structure DB1 may include the same silicon oxide layer as that of the device isolation layer ST. The first separation structure DB1 may have a width in the second direction D2 that may be substantially the same as a distance between opposing sidewalls of a pair of adjacent gate electrodes GE.

[0090] The first separation structure DB1 of the hybrid separation structure CDB may selectively cross the second active region NR except for the first active region PR. The first separation structure DB1 of the hybrid separation structure CDB may separate the second active pattern FN2 of the first logic cell LC1 from the second active pattern FN2 of the second logic cell LC2. The first separation structure DB1 of the hybrid separation structure CDB may separate the second active pattern FN2 of the second logic cell LC2 from the second active pattern FN2 of the third logic cell LC3.

[0091] The second separation structure DB2 may extend in the first direction D1 and cross the first active region PR and the second active region NR. On the first active region PR, the second separation structure DB2 may extend in the first direction D1 and cross the upper portion of the first active pattern FN1. On the second active region NR, the second separation structure DB2 may be disposed on the first separation structure DB1. For example, the first separation structure DB1 may have a bottom surface whose level is lower than that of the bottom surface of the second separation structure DB2.

[0092] The second separation structure DB2 may include a first segment DB2a and a second segment DB2b at opposite sides thereof. The first segment DB2a and the second segment DB2b may be parallel in the first direction D1 and extend in the first direction D1. The width of each of the first segment DB2a and the second segment DB2b may be substantially the same as the width of the gate electrode GE. The first segment DB2a and the second segment DB2b may have a second spacing P2 therebetween. The second spacing P2 may be substantially the same as the first spacing P1 between the gate electrodes GE.

[0093] The level of the bottom surface of the second separation structure DB2 may decrease and then increase as approaching the second segment DB2b from the first segment DB2a. The level of the bottom surface of the second separation structure DB2 may become minimum at a position between the first segment DB2a and the second segment DB2b. For example, when viewed in a cross section along the second direction D2, the second separation structure DB2 may have a U-shaped profile (see, for example, Fig. 7A and Figure 7B ).

[0094] The lowest level LV1 of the bottom surface of the second separation structure DB2 on the first active pattern FN1 may be higher than the lowest level LV2 of the bottom surface of the second separation structure DB2 on the first separation structure DB1 .

[0095] A pair of gate spacers GS may be disposed on opposite sidewalls of the second separation structure DB2. The second separation structure DB2 may have a top surface whose level is higher than that of the top surface of the gate electrode GE. The top surface of the second separation structure DB2 may be coplanar with the top surface of the first interlayer dielectric layer 110 to be discussed below.

[0096] The second separation structure DB2 may include an insulating material that is the same as or different from the insulating material of the first separation structure DB1. For example, the second separation structure DB2 may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0097] The hybrid separation structure CDB may have a width W1' in the second direction D2, which may be greater than the first pitch P1 between the gate electrodes GE. The width W1' of the hybrid separation structure CDB may be substantially the same as a width of each of the first and second separation structures DB1 and DB2.

[0098] The first separation structure DB1 of the hybrid separation structure CDB may increase the breakdown voltage between the second source / drain regions SD2 disposed on opposite sides of the first separation structure DB1. The second separation structure DB2 of the hybrid separation structure CDB may provide stress to the gate electrode GE adjacent to the second separation structure DB2. The semiconductor device according to some exemplary embodiments may be configured such that the first separation structure DB1 and the second separation structure DB2 are combined to form the hybrid separation structure CDB. The hybrid separation structure CDB may affect the performance of the semiconductor device. When the first separation structure DB1 and the second separation structure DB2 are appropriately arranged in the hybrid separation structure CDB, the semiconductor device may improve electrical characteristics.

[0099] A first interlayer dielectric layer 110, a second interlayer dielectric layer 120, and a third interlayer dielectric layer 130 sequentially stacked may be disposed on the substrate 100. Each of the first interlayer dielectric layer 110, the second interlayer dielectric layer 120, and the third interlayer dielectric layer 130 may include a silicon oxide layer or a silicon oxynitride layer.

[0100] One or more active contacts AC may be provided between a pair of gate electrodes GE, the one or more active contacts AC penetrating the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 to be electrically connected to the first source / drain region SD1 and the second source / drain region SD2. The active contact AC may have a strip shape extending in the first direction D1. For example, the one or more active contacts AC may be connected to a plurality of first source / drain regions SD1. For example, the one or more active contacts AC may be connected to a plurality of second source / drain regions SD2.

[0101] At least one gate contact GC may be provided on at least one gate electrode GE, the gate contact GC penetrating the second interlayer dielectric layer 120 and the gate cap layer CP to be electrically connected to at least one gate electrode GE. The gate contact AC may have a strip shape extending in the second direction D2. When viewed in a plan view, the gate contact GC may be provided between the first active region PR and the second active region NR. The gate contact GC may vertically overlap the device isolation layer ST filling the second trench TR2 between the first active region PR and the second active region NR.

[0102] The active contact AC and the gate contact GC may include the same conductive material. The active contact AC and the gate contact GC may include at least one metal material selected from, for example, aluminum, copper, tungsten, molybdenum, and cobalt.

[0103] Interconnection lines IL and vias VI may be provided in the third interlayer dielectric layer 130. For example, the interconnection lines IL and vias VI may constitute a first metal layer. The interconnection lines IL may include power lines VDD and VSS, which cross the first logic cell LC1, the second logic cell LC2, and the third logic cell LC3 and extend in the second direction D2.

[0104] The via VI may be inserted between the interconnection line IL and the active contact AC and between the interconnection line IL and the gate contact GC, thereby electrically connecting the interconnection line IL to the active contact AC and also electrically connecting the interconnection line IL to the gate contact GC. The interconnection line IL and the via VI may include the same conductive material. For example, the interconnection line IL and the via VI may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, and cobalt.

[0105] The interconnection line IL and the via VI thereunder may be integrally connected to form a conductive structure. For example, the interconnection line IL and the via VI may be formed simultaneously with each other. In some exemplary embodiments, a dual damascene process may be performed so that the interconnection line IL and the via VI are formed into a conductive structure.

[0106] Although not shown, one or more additional metal layers may be disposed on the first metal layer. Through the first metal layer and the additional metal layers, the first logic cell LC1, the second logic cell LC2, and the third logic cell LC3 may be connected to each other according to a designed circuit.

[0107] Figure 8 , Fig.10 and Fig.12 A plan view illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment is shown. 9A to 9D Shown are Figure 8 Cross-sectional views taken along lines II', II-II', III-III' and IV-IV'. FIG. 11A to FIG. 11E Shown are Fig.10 Cross-sectional views taken along lines II', II-II', III-III', IV-IV' and V-V'. FIG. 13A to FIG. 13E Shown are Fig.12 According to some exemplary embodiments, a method for manufacturing a semiconductor device includes using Figure 5 The layout is used to actually form the pattern on the substrate.

[0108] Reference Figure 5 , Figure 8 and 9A to 9D, a substrate 100 may be provided. For example, the substrate 100 may be or include a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate.

[0109] The upper portion of the substrate 100 may be patterned to form first trenches TR1 extending in the second direction D2. The first trenches TR1 may define first and second active patterns FN1 and FN2 on the upper portion of the substrate 100. The first and second active patterns FN1 and FN2 may be arranged along the first direction D1.

[0110] The upper portion of the substrate 100 may be patterned to form a second trench TR2, which defines a first active region PR and a second active region NR. When forming the second trench TR2, the active patterns FN1 and FN2 may be removed from the region where the second trench TR2 is formed. Forming the second trench TR2 may include performing a process based on Figure 5 The first active area pattern RXP and the second active area pattern RXN are manufactured by an etching process of a photomask.

[0111] The upper portion of the substrate 100 may be patterned to form a third trench TR3 on a boundary between the first logic cell LC1, the second logic cell LC2, and the third logic cell LC3. When the third trench TR3 is formed, the active patterns FN1 and FN2 may be removed from a region where the third trench TR3 is formed. Forming the third trench TR3 may include performing a Figure 5 The first diffusion interrupt pattern FC is manufactured by an etching process of a photomask.

[0112] For example, the second trench TR2 and the third trench TR3 may be formed to have the same depth as each other. For example, the second trench TR2 and the third trench TR3 may be simultaneously formed by the same etching process. The second trench TR2 and the third trench TR3 may be deeper than the first trench TR1.

[0113] A device isolation layer ST may be formed to fill the first trench TR1, the second trench TR2, and the third trench TR3. The device isolation layer ST may be formed using silicon oxide. For example, forming the device isolation layer ST may include forming an insulating layer filling the first trench TR1, the second trench TR2, and the third trench TR3 on the substrate 100, and then recessing the insulating layer until the first active pattern FN1 and the second active pattern FN2 are exposed at their upper portions. The device isolation layer ST filling the third trench TR3 may be defined as a first separation structure DB1.

[0114] Reference Figure 5 , Fig.10 and FIG. 11A to FIG. 11EThe gate electrode GE may be formed to extend in the first direction D1 and to cross the first active pattern FN1 and the second active pattern FN2. The gate dielectric layer GI may be formed under the gate electrode GE. A gate spacer GS may be formed on opposite sides of each gate electrode GE. A gate cap layer CP may be formed on the gate electrode GE. For example, a pair of gate electrodes GE may be formed on the first separation structure DB1 (see Fig. 11B ).

[0115] In some exemplary embodiments, forming the gate electrode GE may include forming a sacrificial pattern to cross the first and second active patterns FN1 and FN2 , forming a gate spacer GS on opposite sides of each sacrificial pattern, and replacing the sacrificial pattern with the gate electrode GE.

[0116] The gate electrode GE may include one or more of a metal and a conductive metal nitride. The gate dielectric layer GI may include a high-k dielectric material having a dielectric constant higher than that of the silicon oxide layer. The gate sidewall GS may include one or more of SiCN, SiCON, and SiN. The gate cap layer CP may include one or more of SiON, SiCN, SiCON, and SiN.

[0117] The first source / drain region SD1 may be formed on an upper portion of the first active pattern FN1. The second source / drain region SD2 may be formed on an upper portion of the second active pattern FN2. The first source / drain region SD1 and the second source / drain region SD2 may be formed on opposite sides of each gate electrode GE. The first source / drain region SD1 may be doped with p-type impurities, and the second source / drain region SD2 may be doped with n-type impurities.

[0118] The first source / drain region SD1 and the second source / drain region SD2 may be epitaxial patterns formed by a selective epitaxial growth process. For example, a partial recess process may be performed on the first active pattern FN1 and the second active pattern FN2 formed on opposite sides of each gate electrode GE, and then an epitaxial growth process may be performed on the recessed portions of the first active pattern FN1 and the second active pattern FN2.

[0119] The first interlayer dielectric layer 110 may be formed on the entire surface of the substrate 100. The first interlayer dielectric layer 110 may be formed of a silicon oxide layer or a silicon oxynitride layer. The top surface of the first interlayer dielectric layer 110 may be substantially coplanar with the top surface of the gate spacer GS and the top surface of the gate cap layer CP.

[0120] Reference Figure 5 , Fig.12 and FIG. 13A to FIG. 13E , the second separation structure DB2 may be formed on a cell boundary between the first logic cell LC1 and the second logic cell LC2 and a cell boundary between the second logic cell LC2 and the third logic cell LC3.

[0121] The second separation structure DB2 between the first logic cell LC1 and the second logic cell LC2 may be formed on the first separation structure DB1 between the first logic cell LC1 and the second logic cell LC2. The hybrid separation structure CDB may be composed of the first separation structure DB1 and the second separation structure DB2 formed between the first logic cell LC1 and the second logic cell LC2. The second separation structure DB2 between the second logic cell LC2 and the third logic cell LC3 may be formed on the first separation structure DB1 between the second logic cell LC2 and the third logic cell LC3. The hybrid separation structure CDB may be composed of the first separation structure DB1 and the second separation structure DB2 formed between the second logic cell LC2 and the third logic cell LC3.

[0122] For example, the mask layer HM may be formed on the first interlayer dielectric layer 110. The mask layer HM may include an opening OP exposing a cell boundary between the first logic cell LC1 and the second logic cell LC2, and further includes an opening OP exposing a cell boundary between the second logic cell LC2 and the third logic cell LC3. Figure 5 The openings OP of the mask layer HM are formed by an etching process using a photomask fabricated using the second diffusion interrupt pattern RC.

[0123] An anisotropic etching process may be performed to etch the gate cap layer CP, the gate spacer GS, the gate electrode GE, the gate dielectric layer GI, the first active pattern FN1, and the device isolation layer ST exposed to the opening OP of the mask layer HM, and the mask layer HM is used as an etching mask for the anisotropic etching process. The first active pattern FN1 may be removed on the upper portion of the first active pattern FN1 exposed to the opening OP, and the removal may separate the first active patterns FN1 of adjacent logic cells from each other.

[0124] After the anisotropic etching process, the opening OP may be filled with an insulating material to form the second separation structure DB2. The insulating material may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0125] During the anisotropic etching process, the region where the first interlayer dielectric layer 110 is located may be etched more than the region where the gate cap layer CP, the gate electrode GE, and the gate spacer SG are located. As a result, each of the second separation structures DB2 may be formed to have a U-shaped cross-section in the second direction D2.

[0126] Return to reference Figure 5 , Figure 6 and 7A to 7E The planarization process may be performed until the top surface of the first interlayer dielectric layer 110 is exposed. The second interlayer dielectric layer 120 may be formed on the first interlayer dielectric layer 110.

[0127] The active contact AC and the gate contact GC may be formed to penetrate the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120. The active contact AC may be formed on the first source / drain region SD1 and the second source / drain region SD2. The active contact AC may have a line shape extending in the first direction D1. The gate contact GC may be formed on the gate electrode GE. The gate contact GC may have a strip shape extending in the second direction D2.

[0128] A third interlayer dielectric layer 130 may be formed on the second interlayer dielectric layer 120. Interconnection lines IL and vias VI may be formed in the third interlayer dielectric layer 130. The vias VI may be formed between the interconnection lines IL and the active contacts AC and between the interconnection lines IL and the gate contacts GC.

[0129] Fig.14 1 shows a layout according to an exemplary embodiment. In the following exemplary embodiments, the above reference will be omitted. Figure 4 and Figure 5 The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0130] Reference Figure 3 and Fig.14 , the hybrid diffusion interrupt pattern CSC may be disposed on each of the first cell boundary BD1 and the second cell boundary BD2 (S120). The hybrid diffusion interrupt pattern CSC may include a first diffusion interrupt pattern FC and a pair of second diffusion interrupt patterns RC.

[0131] The pair of second diffusion interruption patterns RC may extend in parallel in the first direction D1. The pair of second diffusion interruption patterns RC may be disposed to overlap with the pair of gate patterns GP. Similar to the first diffusion interruption patterns FC, the pair of second diffusion interruption patterns RC may separate adjacent standard cells from each other.

[0132] Fig.15 A plan view illustrating a semiconductor device according to an exemplary embodiment is shown. FIG. 16A to FIG. 16C Shown are Fig.15 Cross-sectional views taken along lines II', II-II' and III-III'. Fig.15 and FIG. 16A to FIG. 16C An example is shown when using Fig.14 The layout of the semiconductor device is actually implemented on the substrate. In the following exemplary embodiments, the above reference will be omitted. Figure 6 and 7A to 7E The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0133] Reference Fig.14 , Fig.15 and FIG. 16A to FIG. 16C The hybrid separation structure CDB may be disposed on each of a cell boundary between the first logic cell LC1 and the second logic cell LC2 and a cell boundary between the second logic cell LC2 and the third logic cell LC3. The hybrid separation structure CDB may include a first separation structure DB1 and a pair of second separation structures DB2.

[0134] The pair of second separation structures DB2 may extend in the first direction D1 and span the first active region PR and the second active region NR. A pair of gate spacers GS may be provided on opposite sidewalls of each of the pair of second separation structures DB2. On the first active region PR, the first source / drain region SD1 may be interposed between the pair of second separation structures DB2.

[0135] The width of each of the pair of second separation structures DB2 may be substantially the same as the width of the gate electrode GE. A third spacing P3 may be provided between the pair of second separation structures DB2. A fourth spacing P4 may be provided between the second separation structure DB2 and the adjacent gate electrode GE. The third spacing P3 may be substantially the same as the first spacing P1 between the gate electrodes GE. The fourth spacing P4 may be substantially the same as the first spacing P1 between the gate electrodes GE.

[0136] Fig.17A and Fig. 17B Shown are Fig.15 A method for manufacturing a semiconductor device according to an exemplary embodiment is shown in a cross-sectional view taken along lines II' and II-II'. According to some exemplary embodiments, the method for manufacturing a semiconductor device includes using Fig.14 The layout is used to actually form the pattern on the substrate.

[0137] Reference Fig.14 , Fig.15 as well as Fig.17A and Fig. 17B , the mask layer HM may be formed on Fig.10 and FIG. 11A to FIG. 11E The mask layer HM may include a pair of openings OP that expose the cell boundary between the first logic cell LC1 and the second logic cell LC2. The mask layer HM may include a pair of openings OP that expose the cell boundary between the second logic cell LC2 and the third logic cell LC3. Fig.14 The pair of openings OP of the mask layer HM is formed by an etching process using a photomask manufactured using the second diffusion interrupt pattern RC.

[0138] When the anisotropic etching process is performed using the mask layer HM as an etching mask, the first active pattern FN1 may be removed on the upper portion of the first active pattern FN1 exposed to the opening OP. After the anisotropic etching process, the opening OP may be filled with an insulating material to form a second separation structure DB2.

[0139] Fig.18 1 shows a layout according to an exemplary embodiment. In the following exemplary embodiments, the above reference will be omitted. Figure 4 and Figure 5 The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0140] Reference Figure 3 and Fig.18 , the hybrid diffusion interrupt pattern CSC may be disposed on each of the first cell boundary BD1 and the second cell boundary BD2 (S120). The hybrid diffusion interrupt pattern CSC may include a first diffusion interrupt pattern FC (see Fig.18 solid line in the figure) and the second diffusion interruption pattern RC (see Fig.18 The first diffusion interrupt pattern FC and the second diffusion interrupt pattern RC may have substantially the same width in the second direction D2.

[0141] The first diffusion interrupt pattern FC of the hybrid diffusion interrupt pattern CSC may extend in the first direction D1. The first diffusion interrupt pattern FC of the hybrid diffusion interrupt pattern CSC may extend from the second active area pattern RXN toward the first active area pattern RXP. The size and shape of the first diffusion interrupt pattern FC of the hybrid diffusion interrupt pattern CSC may be the same as Figure 4 The sizes and shapes of the first diffusion interruption patterns FC are substantially the same.

[0142] The second diffusion interruption pattern RC may be limitedly disposed on the first active area pattern RXP. The size of the second diffusion interruption pattern RC may be about half the size of the first diffusion interruption pattern FC. That is, the second diffusion interruption pattern RC may extend to a boundary of the gate cutting pattern CT, as described below.

[0143] The gate cutting pattern CT may be disposed on a pair of gate patterns GP overlapping the hybrid diffusion interruption pattern CSC. The gate cutting pattern CT may be disposed between the first active area pattern RXP and the second active area pattern RXN. The gate cutting pattern CT may define a gate separation structure.

[0144] Fig.19 A plan view illustrating a semiconductor device according to an exemplary embodiment is shown. FIG. 20A to FIG. 20C Shown are Fig.19Cross-sectional views taken along lines II', II-II' and III-III'. Fig.19 and FIG. 20A to FIG. 20C An example is shown when using Fig.18 The layout of the semiconductor device is actually implemented on the substrate. In the following exemplary embodiments, the above reference will be omitted. Figure 6 and 7A to 7E The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0145] Reference Fig.18 , Fig.19 and FIG. 20A to FIG. 20C The hybrid separation structure CDB may be disposed on each of a cell boundary between the first logic cell LC1 and the second logic cell LC2 and a cell boundary between the second logic cell LC2 and the third logic cell LC3. The hybrid separation structure CDB may include a first separation structure DB1 and a second separation structure DB2.

[0146] The first separation structure DB1 may extend in the first direction D1 and cross the first active region PR and the second active region NR. The first separation structure DB1 may separate a pair of active patterns FN1 and FN2 adjacent to each other in the second direction D2 from each other.

[0147] The second separation structure DB2 may selectively cross the first active region PR except the second active region NR. On the first active region PR, the second separation structure DB2 may be disposed on the first separation structure DB1.

[0148] On the second active region NR, a pair of gate electrodes GE may be disposed on the first separation structure DB1 of the hybrid separation structure CDB. A pair of gate separation structures GSP may be interposed between the second separation structure DB2 and the pair of gate electrodes GE (see Fig. 20C The pair of gate separation structures GSP may be disposed on the first separation structure DB1 between the first active region PR and the second active region NR. The pair of gate separation structures GSP may include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0149] The pair of gate electrodes GE on the first separation structure DB1 of the hybrid separation structure CDB may be dummy gate electrodes and may be used as conductive lines.

[0150] Fig.21 1 shows a layout according to an exemplary embodiment. In the following exemplary embodiments, the above reference will be omitted. Fig.18 The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0151] Reference Figure 3 and Fig.21 The hybrid diffusion interruption pattern CSC may be disposed on each of the first cell boundary BD1 and the second cell boundary BD2 (S120). The hybrid diffusion interruption pattern CSC may include a first diffusion interruption pattern FC and a pair of second diffusion interruption patterns RC. The pair of second diffusion interruption patterns RC may each extend to a boundary of the gate cutting pattern CT.

[0152] The pair of second diffusion interruption patterns RC may extend in parallel in the first direction D1. The pair of second diffusion interruption patterns RC may be disposed to overlap with the pair of gate patterns GP.

[0153] Fig. 22 A plan view illustrating a semiconductor device according to an exemplary embodiment is shown. Fig.23 Shown along Fig. 22 A cross-sectional view taken along line II'. Fig. 22 and Fig.23 An example is shown when using Fig.21 The layout of the semiconductor device is actually implemented on the substrate. In the following exemplary embodiments, the above reference will be omitted. Fig.19 and FIG. 20A to FIG. 20C The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0154] Reference Fig.21 , Fig. 22 and Fig.23 The hybrid separation structure CDB may be disposed on each of a cell boundary between the first logic cell LC1 and the second logic cell LC2 and a cell boundary between the second logic cell LC2 and the third logic cell LC3. The hybrid separation structure CDB may include a first separation structure DB1 and a pair of second separation structures DB2.

[0155] The pair of second separation structures DB2 may extend in the first direction D1 and selectively cross the first active region PR. A pair of gate spacers GS may be disposed on opposite sidewalls of each of the pair of second separation structures DB2.

[0156] A pair of gate separation structures GSP may be inserted between a pair of gate electrodes GE on the first separation structure DB1 of the hybrid separation structure CDB and a pair of second separation structures DB2 of the hybrid separation structure CDB. For example, on the first separation structure DB1 of the hybrid separation structure CDB, the gate electrode GE, the gate separation structure GSP, and the second separation structure DB2 may be sequentially arranged along the first direction D1. The gate electrode GE, the gate separation structure GSP, and the second separation structure DB2 may be aligned along the first direction D1.

[0157] Fig.24 1 shows a layout according to an exemplary embodiment. In the following exemplary embodiments, the above reference will be omitted. Figure 4 and Figure 5 The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0158] Reference Fig.24 , the hybrid diffusion interrupt pattern CSC may be disposed on each of the first cell boundary BD1 between the first standard cell STD1 and the second standard cell STD2 and the second cell boundary BD2 between the second standard cell STD2 and the third standard cell STD3. The hybrid diffusion interrupt pattern CSC may include a first diffusion interrupt pattern FC and a second diffusion interrupt pattern RC. The second diffusion interrupt pattern RC may be disposed on each of the other cell boundaries of the first standard cell STD1 and the other cell boundaries of the third standard cell STD3.

[0159] The second diffusion interruption pattern RC may include a wide diffusion interruption pattern RCw and a narrow diffusion interruption pattern RCn. The wide diffusion interruption pattern RCw may correspond to the second diffusion interruption pattern RC of the mixed diffusion interruption pattern CSC, and the narrow diffusion interruption pattern RCn may correspond to the second diffusion interruption pattern RC disposed on the other cell boundary of each of the first standard cell STD1 and the third standard cell STD3. The detailed description of the wide diffusion interruption pattern RCw may be the same as that described above with reference to Figure 5 The detailed description of the second diffusion interruption pattern RC discussed is substantially the same.

[0160] The narrow diffusion interruption pattern RCn may extend in the first direction D1. The narrow diffusion interruption pattern RCn may separate adjacent standard cells from each other. The narrow diffusion interruption pattern RCn may define a narrow separation structure. The narrow diffusion interruption pattern RCn may overlap the gate pattern GP adjacent to the cell boundary. The width of the narrow diffusion interruption pattern RCn may be substantially the same as the width of the gate pattern GP.

[0161] Fig.25 A plan view illustrating a semiconductor device according to an exemplary embodiment is shown. Fig.26 Shown along Fig.25 A cross-sectional view taken along line II'. Fig.25 and Fig.26 An example is shown when using Fig.24 The layout of the semiconductor device is actually implemented on the substrate. In the following exemplary embodiments, the above reference will be omitted. Figure 6 and 7A to 7E The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0162] Reference Fig.24 , Fig.25 and Fig.26 The hybrid separation structure CDB may be disposed on each of a cell boundary between the first logic cell LC1 and the second logic cell LC2 and a cell boundary between the second logic cell LC2 and the third logic cell LC3. The hybrid separation structure CDB may include a first separation structure DB1 and a second separation structure DB2. The detailed description of the hybrid separation structure CDB may be referred to above. Figure 6 and 7A to 7E The detailed description of the hybrid separation structure CDB discussed is basically the same.

[0163] The second separation structure DB2 may be disposed on each of the other cell boundaries of the first logic cell LC1 and the other cell boundaries of the third logic cell LC3. The second separation structure DB2 may include a wide separation structure DB2w and a narrow separation structure DB2n. The wide separation structure DB2w may correspond to the second separation structure DB2 of the hybrid separation structure CDB, and the narrow separation structure DB2n may correspond to the second separation structure DB2 disposed on the other cell boundary of each of the first logic cell LC1 and the third logic cell LC3.

[0164] The narrow separation structure DB2n may extend in the first direction D1 and span the first active region PR and the second active region NR. A pair of gate spacers GS may be provided on opposite sidewalls of the narrow separation structure DB2n. The width of the narrow separation structure DB2n may be substantially the same as the width of the gate electrode GE. A fifth spacing P5 may be provided between the narrow separation structure DB2n and its adjacent gate electrode GE. The fifth spacing P5 may be substantially the same as the first spacing P1 between the gate electrodes GE.

[0165] Fig. 27 1 shows a layout according to an exemplary embodiment. In the following exemplary embodiments, the above reference will be omitted. Figure 4 and Figure 5 The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0166] Reference Fig. 27 The first diffusion interrupt pattern FC of the hybrid diffusion interrupt pattern CSC may be limitedly disposed on the first active area pattern RXP. For example, the first diffusion interrupt pattern FC of the hybrid diffusion interrupt pattern CSC may separate the first active area pattern RXP of the first standard cell STD1 from the first active area pattern RXP of the second standard cell STD2.

[0167] Fig.28 A plan view illustrating a semiconductor device according to an exemplary embodiment is shown. FIG. 29A to FIG. 29C Shown are Fig.28Cross-sectional views taken along lines II', II-II' and III-III'. Fig.28 and FIG. 29A to FIG. 29C An example is shown when using Fig. 27 The layout of the semiconductor device is actually implemented on the substrate. In the following exemplary embodiments, the above reference will be omitted. Figure 6 and 7A to 7E The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0168] Reference Fig. 27 , Fig.28 and FIG. 29A to FIG. 29C , except for the second active region NR, the first separation structure DB1 of the hybrid separation structure CDB may selectively cross the first active region PR. The first separation structure DB1 of the hybrid separation structure CDB may separate the first active pattern FN1 of the first logic cell LC1 from the first active pattern FN1 of the second logic cell LC2. The first separation structure DB1 of the hybrid separation structure CDB may separate the first active pattern FN1 of the second logic cell LC2 from the first active pattern FN1 of the third logic cell LC3.

[0169] Fig.30 1 shows a layout according to an exemplary embodiment. In the following exemplary embodiments, the above reference will be omitted. Figure 4 and Figure 5 The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0170] Reference Fig.30 , the first diffusion interrupt pattern FC and the second diffusion interrupt pattern RC of the hybrid diffusion interrupt pattern CSC may substantially overlap each other. For example, the first diffusion interrupt pattern FC and the second diffusion interrupt pattern RC of the hybrid diffusion interrupt pattern CSC may have substantially the same size and shape. The first diffusion interrupt pattern FC of the hybrid diffusion interrupt pattern CSC may extend from the second active area pattern RXN toward the first active area pattern RXP. The second diffusion interrupt pattern RC of the hybrid diffusion interrupt pattern CSC may extend from the second active area pattern RXN toward the first active area pattern RXP.

[0171] Fig.31 A plan view illustrating a semiconductor device according to an exemplary embodiment is shown. Fig.32A and Fig.32B Shown are Fig.25 Cross-sectional views taken along lines II' and II-II'. Fig.31 , Fig.32A and Fig.32B An example is shown when using Fig.30The layout of the semiconductor device is actually implemented on the substrate. In the following exemplary embodiments, the above reference will be omitted. Figure 6 and 7A to 7E The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0172] Reference Fig.30 , Fig.31 , Fig.32A and Fig.32B , the hybrid split structure CDB may be disposed on each of a cell boundary between the first logic cell LC1 and the second logic cell LC2 and a cell boundary between the second logic cell LC2 and the third logic cell LC3.

[0173] The hybrid separation structure CDB may be configured such that the second separation structure DB2 is disposed on the first separation structure DB1. The hybrid separation structure CDB may have a structure in which the second separation structure DB2 vertically overlaps the first separation structure DB1. The first active patterns FN1 in adjacent logic cells may be separated from each other by the hybrid separation structure CDB having a structure in which the first separation structure DB1 and the second separation structure DB2 are stacked. The second active patterns FN2 in adjacent logic cells may be separated from each other by the hybrid separation structure CDB having a structure in which the first separation structure DB1 and the second separation structure DB2 are stacked.

[0174] Fig.33 1 shows a layout according to an exemplary embodiment. In the following exemplary embodiments, the above reference will be omitted. Figure 4 and Figure 5 The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0175] refer to Fig.33 , the first active area pattern RXP may have a variable width in the first direction D1. For example, the first active area pattern RXP of the first standard cell STD1 may have a second width W2 in the first direction D1. The first active area pattern RXP of the second standard cell STD2 may have a third width W3 in the first direction D1. The first active area pattern RXP of the third standard cell STD3 may have a fourth width W4 in the first direction D1. The second width W2, the third width W3, and the fourth width W4 may be different from each other. The third width W3 may be greater than the second width W2, and the fourth width W4 may be greater than the third width W3.

[0176] The second active area pattern RXN may have a variable width in the first direction D1. For example, the second active area pattern RXN of the first standard cell STD1 may have a fifth width W5 in the first direction D1. The second active area pattern RXN of the second standard cell STD2 may have a sixth width W6 in the first direction D1. The second active area pattern RXN of the third standard cell STD3 may have a seventh width W7 in the first direction D1. The fifth width W5, the sixth width W6, and the seventh width W7 may be different from each other. The sixth width W6 may be greater than the fifth width W5, and the fifth width W5 and the seventh width W7 may be substantially the same as each other.

[0177] In the hybrid diffusion interrupt pattern CSC on the first cell boundary BD1, the first active area pattern RXP and the second active area pattern RXN may have variable widths thereof. For example, in the hybrid diffusion interrupt pattern CSC on the first cell boundary BD1, the width of the first active area pattern RXP may be changed from the second width W2 to the third width W3. In the hybrid diffusion interrupt pattern CSC on the first cell boundary BD1, the width of the second active area pattern RXN may be changed from the fifth width W5 to the sixth width W6.

[0178] In the hybrid diffusion interrupt pattern CSC on the second cell boundary BD2, the first active area pattern RXP and the second active area pattern RXN may have variable widths thereof. For example, in the hybrid diffusion interrupt pattern CSC on the second cell boundary BD2, the width of the first active area pattern RXP may be changed from the third width W3 to the fourth width W4. In the hybrid diffusion interrupt pattern CSC on the second cell boundary BD2, the width of the second active area pattern RXN may be changed from the sixth width W6 to the seventh width W7.

[0179] Fig.34 A plan view illustrating a semiconductor device according to an exemplary embodiment is shown. Fig.35A and Fig.35B Shown are Fig.34 Cross-sectional views taken along lines II' and II-II'. Fig.34 , Fig.35A and Fig.35B An example is shown when using Fig.33 The layout of the semiconductor device is actually implemented on the substrate. In the following exemplary embodiments, the above reference will be omitted. Figure 6 and 7A to 7E The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0180] refer to Fig.33 , Fig.34 , Fig.35A and Fig.35B, the first active region PR may have a variable width in the first direction D1. The width variation of the first active region PR may be similar to that described above with reference to Fig.33 The width variation of the first active region pattern RXP discussed above. The second active region NR may have a variable width in the first direction D1. The width variation of the second active region NR may be similar to that described in the above reference. Fig.33 The width of the second active area pattern RXN discussed varies.

[0181] The first logic cell LC1 may include one first active pattern FN1, the second logic cell LC2 may include two first active patterns FN1, and the third logic cell LC3 may include three first active patterns FN1. The first logic cell LC1 may include two second active patterns FN2, the second logic cell LC2 may include three second active patterns FN2, and the third logic cell LC3 may include two second active patterns FN2.

[0182] The number of the first active patterns FN1 on one side of the hybrid separation structure CDB may be different from the number of the first active patterns FN1 on the opposite side of the hybrid separation structure CDB. The number of the second active patterns FN2 on one side of the hybrid separation structure CDB may be different from the number of the second active patterns FN2 on the opposite side of the hybrid separation structure CDB. For example, the second logic cell LC2 may include two first active patterns FN1 and three second active patterns FN2 (see Fig.35A The third logic cell LC3 may include three first active patterns FN1 and two second active patterns FN2 (see Fig.35B ). The hybrid separation structure CDB may be located between the second logic cell LC2 and the third logic cell LC3, and the number of active patterns on one side of the hybrid separation structure CDB may be different from the number of active patterns on the opposite side of the hybrid separation structure CDB. The hybrid separation structure CDB may be located on a region where the number of active patterns changes, and this configuration may prevent the occurrence of various changes caused by the change in the number of active patterns.

[0183] According to an exemplary embodiment, a semiconductor device may be configured such that a hybrid separation structure is provided on a boundary between adjacent logic cells. By appropriately arranging the first separation structure and the second separation structure in the hybrid separation structure, electrical characteristics of the semiconductor device may be improved.

[0184] Although the exemplary embodiments have been discussed with reference to the accompanying drawings, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the exemplary embodiments. Therefore, it will be understood that the above exemplary embodiments are only illustrative and not restrictive in all aspects, and the scope is limited by the appended claims.

Claims

1. A semiconductor device, comprising: a first active pattern and a second active pattern adjacent to each other on a substrate; a plurality of gate electrodes, the plurality of gate electrodes being on the first active pattern and extending in a first direction, the plurality of gate electrodes having a gate pitch; as well as a hybrid separation structure extending in the first direction between the first active pattern and the second active pattern, wherein the first active pattern and the second active pattern extend in a second direction intersecting the first direction and are arranged along the second direction, Wherein, the hybrid separation structure comprises: a first separation structure separating the first active pattern from the second active pattern; and A second separation structure vertically overlaps the first separation structure and contacts at least a portion of an upper surface of the first separation structure.

2. The semiconductor device according to claim 1, wherein The width of the hybrid separation structure is greater than the gate pitch.

3. The semiconductor device according to claim 1, wherein The first separation structure includes a flat bottom surface, and Wherein, the second separation structure comprises a circular bottom surface.

4. The semiconductor device according to claim 1, wherein: A bottom surface of the first separation structure is lower than a bottom surface of the second separation structure.

5. The semiconductor device according to claim 1, wherein The second separation structure includes a pair of second separation structures.

6. The semiconductor device according to claim 5, wherein: The distance between the pair of second separation structures is substantially the same as the gate distance.

7. The semiconductor device according to claim 5, wherein: The plurality of gate electrodes include a pair of adjacent gate electrodes, and Wherein, a first distance between opposite side walls of the pair of second separation structures is substantially the same as a second distance between opposite side walls of the pair of adjacent gate electrodes.

8. The semiconductor device according to claim 1, wherein A spacing between the second separation structure and an adjacent gate electrode of the plurality of gate electrodes is substantially the same as the gate spacing.

9. The semiconductor device according to claim 1, wherein: The first active pattern includes a source / drain region, and Wherein, a bottom surface of the second separation structure is lower than a bottom surface of the source / drain region.

10. The semiconductor device according to claim 1, further comprising: an interlayer dielectric layer on the first active pattern and the second active pattern, Wherein, a top surface of the second separation structure is coplanar with a top surface of the interlayer dielectric layer.

11. The semiconductor device according to claim 1, further comprising: a gate capping layer on each of the plurality of gate electrodes, Wherein, a top surface of the second separation structure is coplanar with a top surface of the gate covering layer.

12. The semiconductor device according to claim 1, wherein The second separation structure includes an insulating material different from that of the first separation structure.

13. The semiconductor device according to claim 12, wherein: The second separation structure includes a silicon nitride layer or a silicon oxynitride layer.

14. The semiconductor device according to claim 1, further comprising: A gate separation structure is provided on the hybrid separation structure.

15. The semiconductor device according to claim 14, wherein: The gate separation structure includes a silicon nitride layer or a silicon nitride oxide layer.

16. The semiconductor device according to claim 1, further comprising: an active contact on the first active pattern and adjacent to the second separation structure, Wherein, the top surface of the active contact is higher than the top surface of the second separation structure.

17. The semiconductor device according to claim 1, wherein Each of the first active pattern and the second active pattern includes an active fin.

18. The semiconductor device according to claim 1, wherein Each of the first active pattern and the second active pattern includes a vertical protrusion of the substrate.

19. The semiconductor device according to claim 1, further comprising: an interlayer dielectric layer on the plurality of gate electrodes; as well as a metal layer on the interlayer dielectric layer, The metal layer includes a pair of power lines, and the pair of power lines extend along unit boundaries opposite to each other.

20. The semiconductor device according to claim 1, wherein The first active pattern and the second active pattern are disposed on the first active area and the second active area, respectively. wherein the hybrid separation structure is located between the first active region and the second active region, and A first width of the first active region is different from a second width of the second active region.

21. The semiconductor device according to claim 1, further comprising: a third active pattern on the substrate, wherein the substrate comprises a PMOSFET region and an NMOSFET region spaced apart from each other in the first direction, wherein the first active pattern and the second active pattern are disposed on one of the PMOSFET region and the NMOSFET region, and Wherein, the third active pattern is disposed on the other of the PMOSFET region and the NMOSFET region.

22. The semiconductor device according to claim 1, further comprising: a third active pattern on the substrate and adjacent to the second active pattern in the second direction; as well as a third separation structure extending in the first direction between the second active pattern and the third active pattern, Wherein, the width of the third separation structure is substantially the same as the width of the second separation structure.

23. The semiconductor device according to claim 1, further comprising: a third active pattern on the substrate and adjacent to the second active pattern in the second direction; as well as a third separation structure extending in the first direction between the second active pattern and the third active pattern, Wherein, the spacing between the third separation structure and an adjacent gate electrode among the plurality of gate electrodes is substantially the same as the gate spacing.

24. The semiconductor device according to claim 1, further comprising: a third active pattern on the substrate and adjacent to the second active pattern in the second direction; as well as An additional hybrid separation structure is provided, the additional hybrid separation structure extending along the first direction between the second active pattern and the third active pattern.

25. A semiconductor device comprising: a first logic cell and a second logic cell adjacent to each other on a substrate; as well as a first active pattern on the first logic unit and a second active pattern on the second logic unit, the first active pattern and the second active pattern extending along a first direction; a plurality of gate electrodes extending in a second direction intersecting the first direction; as well as a hybrid separation structure between the first active pattern and the second active pattern, Wherein, the hybrid separation structure comprises: a first separation structure separating the first active pattern from the second active pattern; and A second separation structure vertically overlaps with the first separation structure and contacts the first separation structure.

26. The semiconductor device according to claim 25, wherein: The plurality of gate electrodes have a gate pitch, and Wherein, the width of the hybrid separation structure is greater than the gate spacing.

27. The semiconductor device according to claim 25, wherein: The first separation structure includes a flat bottom surface, and Wherein, the second separation structure comprises a circular bottom surface.

28. The semiconductor device according to claim 25, wherein: The second separation structure includes a pair of second separation structures.

29. The semiconductor device according to claim 28, wherein: The plurality of gate electrodes have a gate pitch, and Wherein, the spacing between the pair of second separation structures is substantially the same as the gate spacing.

30. The semiconductor device according to claim 28, wherein The plurality of gate electrodes include a pair of adjacent gate electrodes, and Wherein, a first distance between opposite side walls of the pair of second separation structures is substantially the same as a second distance between opposite side walls of the pair of adjacent gate electrodes.

31. The semiconductor device according to claim 25, wherein: The first active pattern and the second active pattern are disposed on the first active area and the second active area, respectively. wherein the hybrid separation structure is located between the first active region and the second active region, and The first width of the first active region is different from the second width of the second active region.

32. The semiconductor device according to claim 25, further comprising: a third active pattern on the substrate and adjacent to the second active pattern in the first direction; as well as a third separation structure between the second active pattern and the third active pattern, wherein the plurality of gate electrodes have a gate spacing, and A spacing between the third separation structure and an adjacent gate electrode among the plurality of gate electrodes is substantially the same as the gate spacing.

33. The semiconductor device according to claim 25, further comprising: a third active pattern on the substrate and adjacent to the second active pattern in the first direction; as well as An additional hybrid separation structure is extended along the second direction between the second active pattern and the third active pattern.

34. A semiconductor device comprising: a first active pattern and a second active pattern adjacent to each other on a substrate; a plurality of gate electrodes, the plurality of gate electrodes extending on the first active pattern and in a first direction and having a gate pitch; as well as a separation structure extending in the first direction between the first active pattern and the second active pattern, wherein the first active pattern and the second active pattern extend in a second direction intersecting the first direction and are arranged along the second direction, Wherein, the separation structure comprises: a first separation structure separating the first active pattern from the second active pattern; and A second separation structure vertically overlaps with the first separation structure and contacts the first separation structure.

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